Ultra SeriesTM Crystal Oscillator Si541 Data Sheet Ultra Low Jitter Dual Any-Frequency XO (125 fs), 0.2 to 1500 MHz The Si541 Ultra SeriesTM oscillator utilizes Silicon Laboratories' advanced 4th generation DSPLL(R) technology to provide an ultra-low jitter, low phase noise clock at two selectable frequencies. The device is factory-programmed to provide any two selectable frequencies from 0.2 to 1500 MHz with <1 ppb resolution and maintains exceptionally low jitter for both integer and fractional frequencies across its operating range. The Si541 offers excellent reliability and frequency stability as well as guaranteed aging performance. On-chip power supply filtering provides industry-leading power supply noise rejection, simplifying the task of generating low jitter clocks in noisy systems that use switched-mode power supplies. Offered in a small, industry-standard 3.2x5 mm footprint, the Si541 has a dramatically simplified supply chain that enables Silicon Labs to ship custom frequency samples 1-2 weeks after receipt of order. Unlike a traditional XO, where a different crystal is required for each output frequency, the Si541 uses one simple crystal and a DSPLL IC-based approach to provide the desired output frequencies. This process also guarantees 100% electrical testing of every device. The Si541 is factory-configurable for a wide variety of user specifications, including frequency, output format, and OE pin location/polarity. Specific configurations are factoryprogrammed at time of shipment, eliminating the long lead times associated with custom oscillators. KEY FEATURES * Available with any two selectable frequencies from 0.2 MHz to 1500 MHz * Very low jitter: 125 fs Typ RMS (12 kHz - 20 MHz) * Excellent PSRR and supply noise immunity: -80 dBc Typ * 3x tighter stability than SAW oscillators * 3.3 V, 2.5 V and 1.8 V VDD supply operation from the same part number * LVPECL, LVDS, CML, HCSL, CMOS, and Dual CMOS output options * 3.2x5 mm package footprint * Any custom frequency available with 1-2 week lead times APPLICATIONS Pin Assignments OE/FS 1 6 * 100G/200G/400G OTN, coherent optics * 10G/40G/100G optical ethernet VDD FS/OE 2 5 CLK- GND 3 4 CLK+ * 3G-SDI/12G-SDI/24G-SDI broadcast video * Servers, switches, storage, NICs, search acceleration * Test and measurement * Clock and data recovery * FPGA/ASIC clocking (Top View) Pin # 1, 2 Fixed Frequency Crystal Descriptions Selectable via ordering option OE = Output enable; FS = Frequency Select DCO OSC 3 GND = Ground 4 CLK+ = Clock output 5 CLK- = Complementary clock output. Not used for CMOS. 6 VDD = Power supply silabs.com | Building a more connected world. Frequency Flexible DSPLL Digital Phase Detector Low Noise Driver Digital Loop Filter Phase Error Cancellation Phase Error Fractional Divider Flexible Formats, 1.8V - 3.3V Operation NVM Control Power Supply Regulation OE, Frequency Select (Pin Control) Built-in Power Supply Noise Rejection Rev. 0.7 Si541 Data Sheet Ordering Guide 1. Ordering Guide The Si541 XO supports a variety of options including frequency, output format, and OE pin location/polarity, as shown in the chart below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks. Silicon Laboratories provides an online part number configuration utility to simplify this process. Refer to www.silabs.com/oscillators to access this tool and for further ordering instructions. XO Series Description 541 Dual Frequency A 541 Signal Format LVPECL LVDS Total Stability 2 Temp Stability A Order VDD Range Option 2.5, 3.3 V A 1.8, 2.5, 3.3 V B CMOS 1.8, 2.5, 3.3 V C CML 1.8, 2.5, 3.3 V D HCSL Dual CMOS (In-Phase) Dual CMOS (Complementary) Custom 1 1.8, 2.5, 3.3 V E 1.8, 2.5, 3.3 V F 1.8, 2.5, 3.3 V G 1.8, 2.5, 3.3 V H 50 ppm 20 ppm A A OE Pin A Pin 1 B Pin 1 Package B - - OE Polarity Active High Active Low C Pin 2 Active High D Pin 2 Active Low - - 3.2x5 mm - - B Temperature Grade G -40 to 85 C A G R Device Revision FS Pin Pin 2 Pin 2 Pin 1 Pin 1 Reel R Tape and Reel <Blank> Coil Tape Frequency Code3 Description xxxxxx Two unique frequencies can be specified within the supported range of the selected signal format. Either frequency can be assigned to FS=0 or FS=1. A six digit numeric code will be assigned for the specific combination of frequencies. Notes: 1. Contact Silicon Labs for non-standard configurations. 2. Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 C. 3. Create custom part numbers at www.silabs.com/oscillators. 1.1 Technical Support Frequently Asked Questions (FAQ) www.silabs.com/Si541-FAQ Oscillator Phase Noise Lookup Utility www.silabs.com/oscillator-phase-noise-lookup Quality and Reliability www.silabs.com/quality Development Kits www.silabs.com/oscillator-tools silabs.com | Building a more connected world. Rev. 0.7 | 2 Si541 Data Sheet Electrical Specifications 2. Electrical Specifications Table 2.1. Electrical Specifications VDD = 1.8 V, 2.5 or 3.3 V 5%, TA = -40 to 85 C Parameter Temperature Range Frequency Range Supply Voltage Supply Current Symbol Test Condition/Comment Min Typ Max Unit -40 -- 85 C LVPECL, LVDS, CML 0.2 -- 1500 MHz HCSL 0.2 -- 400 MHz CMOS, Dual CMOS 0.2 -- 250 MHz 3.3 V 3.135 3.3 3.465 V 2.5 V 2.375 2.5 2.625 V 1.8 V 1.71 1.8 1.89 V LVPECL (output enabled) -- 100 132 mA LVDS/CML (output enabled) -- 75 111 mA HCSL (output enabled) -- 80 125 mA CMOS (output enabled) -- 74 108 mA Dual CMOS (output enabled) -- 80 125 mA Tristate Hi-Z (output disabled) -- 64 100 mA Frequency stability Grade A -20 -- 20 ppm TA FCLK VDD IDD Temperature Stability Total Stability1 FSTAB Frequency stability Grade A -50 -- 50 ppm Rise/Fall Time (20% to 80% VPP) TR/TF LVPECL/LVDS/CML -- -- 350 ps CMOS / Dual CMOS, (CL = 5 pF) -- 0.5 1.5 ns HCSL, FCLK >50 MHz -- -- 450 ps All formats 45 -- 55 % Duty Cycle DC Output Enable (OE) Frequency Select (FS)2 VIH 0.7 x VDD -- -- V VIL -- -- 0.3 x VDD V TD Output Disable Time, FCLK >10 MHz -- -- 3 s TE Output Enable Time, FCLK > 10 MHz -- -- 20 s TFS Settling Time after FS Change -- -- 10 ms Powerup Time tOSC Time from 0.9 x VDD until output frequency (FCLK) within spec -- -- 10 ms LVPECL Output Option3 VOC Mid-level VDD - 1.42 -- VDD - 1.25 V VO Swing (diff) 1.1 -- 1.9 VPP VOC Mid-level (2.5 V, 3.3 V VDD) 1.125 1.20 1.275 V Mid-level (1.8 V VDD) 0.8 0.9 1.0 V Swing (diff) 0.5 0.7 0.9 VPP LVDS Output Option4 VO silabs.com | Building a more connected world. Rev. 0.7 | 3 Si541 Data Sheet Electrical Specifications Parameter Symbol Test Condition/Comment Min Typ Max Unit VOH Output voltage high 660 750 850 mV VOL Output voltage low -150 0 150 mV VC Crossing voltage 250 350 550 mV CML Output Option (AC-Coupled) VO Swing (diff) 0.6 0.8 1.0 VPP CMOS Output Option VOH IOH = 8/6/4 mA for 3.3/2.5/1.8 V VDD 0.85 x VDD -- -- V VOL IOL = 8/6/4 mA for 3.3/2.5/1.8 V VDD -- -- 0.15 x VDD V HCSL Output Option5 Notes: 1. Total Stability includes 20 ppm temperature stability, initial accuracy, load pulling, VDD variation, and aging for 20 yrs at 70 C. 2. OE includes a 50 k pull-up to VDD for OE active high. Includes a 50 k pull-down to GND for OE active low. FS includes a 50 k pull-up to VDD. 3. 50 to VDD - 2.0 V. 4. Rterm = 100 (differential). 5. 50 to GND. Table 2.2. Clock Output Phase Jitter and PSRR VDD = 1.8 V, 2.5 or 3.3 V 5%, TA = -40 to 85 C Parameter Phase Jitter (RMS, 12kHz - 20MHz)1 FCLK 100 MHz Spurs Induced by External Power Supply Noise, 50 mVpp Ripple. LVDS 156.25 MHz Output Symbol Test Condition/Comment Min Typ Max Unit J Differential Formats -- 125 200 fs CMOS, Dual CMOS -- 250 -- fs 100 kHz sine wave -- -83 -- 200 kHz sine wave -- -83 -- 500 kHz sine wave -- -82 -- 1 MHz sine wave -- -85 -- PSRR dBc Note: 1. Guaranteed by characterization. Jitter inclusive of any spurs. Table 2.3. Clock Output Phase Noise (Typical) Offset Frequency (f) 156.25 MHz LVDS 200 MHz LVDS 644.53125 MHz LVDS 100 Hz -110 -107 -99 1 kHz -121 -120 -109 10 kHz -132 -130 -121 100 kHz -139 -137 -127 1 MHz -151 -149 -138 10 MHz -160 -161 -155 20 MHz -161 -162 -157 Phase Jitter (RMS, 12kHz - 20MHz) 121 114 108 silabs.com | Building a more connected world. Unit dBc/Hz fs Rev. 0.7 | 4 Si541 Data Sheet Electrical Specifications Offset Frequency (f) 156.25 MHz LVPECL 200 MHz LVPECL 644.53125 MHz LVPECL 100 Hz -113 -110 -100 1 kHz -123 -120 -110 10 kHz -133 -130 -119 100 kHz -139 -137 -127 1 MHz -151 -149 -138 10 MHz -162 -166 -156 20 MHz -163 -167 -157 Phase Jitter (RMS, 12kHz - 20MHz) 120 113 113 Unit dBc/Hz fs Phase jitter measured with Agilent E5052 using a differential-to-single ended converter (balun or buffer). Measurements collected for >700 commonly used frequencies. Phase noise plots for specific frequencies are available using our free, online Oscillator Phase Noise Lookup Tool at www.silabs.com/oscillators. Figure 2.1. Phase Jitter vs. Output Frequency silabs.com | Building a more connected world. Rev. 0.7 | 5 Si541 Data Sheet Electrical Specifications Table 2.4. Environmental Compliance and Package Information Parameter Test Condition Mechanical Shock MIL-STD-883, Method 2002 Mechanical Vibration MIL-STD-883, Method 2007 Solderability MIL-STD-883, Method 2003 Gross and Fine Leak MIL-STD-883, Method 1014 Resistance to Solder Heat MIL-STD-883, Method 2036 Moisture Sensitivity Level (MSL) 1 Contact Pads Gold over Nickel Note: 1. For additional product information not listed in the data sheet (e.g. RoHS Certifications, MDDS data, qualification data, REACH Declarations, ECCN codes, etc.), refer to our "Corporate Request For Information" portal found here: www.silabs.com/support/ quality/Pages/RoHSInformation.aspx. Table 2.5. Thermal Conditions Package 3.2x5 mm 6-pin CLCC Parameter Symbol Test Condition Value Unit Thermal Resistance Junction to Ambient JA Still Air, 85 C 80.3 C/W Thermal Resistance Junction to Board JB Still Air, 85 C 50.8 C/W Max Junction Temperature TJ Still Air, 85 C 125 C Table 2.6. Absolute Maximum Ratings1 Parameter Symbol Rating Unit TAMAX 95 C TS -55 to 125 C Supply Voltage VDD -0.5 to 3.8 C Input Voltage VIN -0.5 to VDD + 0.3 V ESD HBM (JESD22-A114) HBM 2.0 kV Solder Temperature2 TPEAK 260 C TP 20-40 sec Maximum Operating Temp. Storage Temperature Solder Time at TPEAK2 Notes: 1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. The device is compliant with JEDEC J-STD-020. silabs.com | Building a more connected world. Rev. 0.7 | 6 Si541 Data Sheet Dual CMOS Buffer 3. Dual CMOS Buffer Dual CMOS output format ordering options support either complementary or in-phase signals for two identical frequency outputs. This feature enables replacement of multiple XOs with a single Si541 device. ~ Complementary Outputs ~ In-Phase Outputs Figure 3.1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs silabs.com | Building a more connected world. Rev. 0.7 | 7 Si541 Data Sheet Recommended Output Terminations 4. Recommended Output Terminations The output drivers support both AC-coupled and DC-coupled terminations as shown in figures below. VDD VDD (3.3V, 2.5V) CLK+ Rp R1 R1 CLK+ 50 CLK- Si54x VDD VDD (3.3V, 2.5V) Rp R2 R2 LVPECL Receiver VDD (3.3V, 2.5V) CLK+ VDD Si54x Rp Rp 50 R2 VDD (3.3V, 2.5V) R1 VTT CLK+ 50 LVPECL Receiver 50 VDD CLK- 50 R2 R2 DC-Coupled LVPECL - Thevenin Termination 50 CLK- 50 Si54x AC-Coupled LVPECL - Thevenin Termination R1 50 CLK- 50 R1 LVPECL Receiver AC-Coupled LVPECL - 50 w/VTT Bias 50 Si54x R1 VTT R2 50 50 LVPECL Receiver DC-Coupled LVPECL - 50 w/VTT Bias Figure 4.1. LVPECL Output Terminations AC Coupled LVPECL Termination Resistor Values DC Coupled LVPECL Termination Resistor Values VDD R1 R2 Rp VDD R1 R2 3.3 V 127 82.5 130 3.3 V 127 82.5 2.5 V 250 62.5 90 2.5 V 250 62.5 silabs.com | Building a more connected world. Rev. 0.7 | 8 Si541 Data Sheet Recommended Output Terminations (3.3V, 2.5V, 1.8V) VDD CLK+ (3.3V, 2.5V, 1.8V) VDD 50 CLK+ 33 100 CLK50 Si54x LVDS Receiver CLK+ 50 HCSL Receiver Source Terminated HCSL (3.3V, 2.5V, 1.8V) VDD 50 CLK+ 100 CLK50 Si54x 50 50 Si54x DC-Coupled LVDS (3.3V, 2.5V, 1.8V) VDD 50 CLK- 33 50 CLK- LVDS Receiver 50 50 Si54x AC-Coupled LVDS 50 HCSL Receiver Destination Terminated HCSL Figure 4.2. LVDS and HCSL Output Terminations (3.3V, 2.5V, 1.8V) VDD CLK+ VDD (3.3V, 2.5V, 1.8V) 50 CLK 10 100 CLK- NC 50 Si54x CML Receiver CLK+ Single CMOS Termination VDD (3.3V, 2.5V, 1.8V) 50 50 CLK+ 50 CLK- VCM CLK- Si54x CMOS Receiver Si54x CML Termination without VCM (3.3V, 2.5V, 1.8V) VDD 50 50 CML Receiver CML Termination with VCM 10 10 Si54x 50 50 CMOS Receivers Dual CMOS Termination Figure 4.3. CML and CMOS Output Terminations silabs.com | Building a more connected world. Rev. 0.7 | 9 Si541 Data Sheet Package Outline 5. Package Outline The figure below illustrates the package details for the 3.2 x 5 mm Si541. The table below lists the values for the dimensions shown in the illustration. Figure 5.1. Si541 Outline Diagram Table 5.1. Package Diagram Dimensions (mm) Dimension Min Nom Max A 1.06 1.17 1.28 b 0.54 0.64 0.74 c 0.35 0.45 0.55 D D1 3.20 BSC 2.55 2.60 e 1.27 BSC E 5.00 BSC 2.65 E1 4.35 4.40 4.45 H 0.45 0.55 0.65 L 0.90 1.00 1.10 L1 0.05 0.10 0.15 p 1.17 1.27 1.37 R 0.32 REF aaa 0.15 bbb 0.15 ccc 0.10 ddd 0.10 eee 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. silabs.com | Building a more connected world. Rev. 0.7 | 10 Si541 Data Sheet PCB Land Pattern 6. PCB Land Pattern The figure below illustrates the 3.2 x 5.0 mm PCB land pattern for the Si541. The table below lists the values for the dimensions shown in the illustration. Figure 6.1. Si541 PCB Land Pattern Table 6.1. PCB Land Pattern Dimensions (mm) Dimension (mm) C1 2.60 E 1.27 X1 0.80 Y1 1.70 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. silabs.com | Building a more connected world. Rev. 0.7 | 11 Si541 Data Sheet Top Marking 7. Top Marking The figure below illustrates the mark specification for the Si541. The table below lists the line information. Figure 7.1. Mark Specification Table 7.1. Si541 Top Mark Description Line Position Description 1 1-8 "Si541", xxx = Ordering Option 1, Option 2, Option 3 (e.g. Si541AAA) 2 1-6 Frequency Code (6-digit custom code as described in the Ordering Guide) 3 Trace Code Position 1 Pin 1 orientation mark (dot) Position 2 Product Revision (A) Position 3-5 Tiny Trace Code (3 alphanumeric characters per assembly release instructions) Position 6-7 Year (last two digits of the year), to be assigned by assembly site (ex: 2017 = 17) Position 8-9 Calendar Work Week number (1-53), to be assigned by assembly site silabs.com | Building a more connected world. Rev. 0.7 | 12 Si541 Data Sheet Revision History 8. Revision History 8.1 Revision 0.7 June 27, 2017 * Initial release. silabs.com | Building a more connected world. Rev. 0.7 | 13 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW www.silabs.com/CBPro Quality www.silabs.com/quality Support and Community community.silabs.com Disclaimer Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. 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