Ultra Series™ Crystal Oscillator
Si541 Data Sheet
Ultra Low Jitter Dual Any-Frequency XO (125 fs), 0.2 to 1500 MHz
The Si541 Ultra Series™ oscillator utilizes Silicon Laboratories’ advanced 4th
generation DSPLL® technology to provide an ultra-low jitter, low phase noise clock
at two selectable frequencies. The device is factory-programmed to provide any
two selectable frequencies from 0.2 to 1500 MHz with <1 ppb resolution and
maintains exceptionally low jitter for both integer and fractional frequencies across
its operating range. The Si541 offers excellent reliability and frequency stability as
well as guaranteed aging performance. On-chip power supply filtering provides
industry-leading power supply noise rejection, simplifying the task of generating
low jitter clocks in noisy systems that use switched-mode power supplies. Offered
in a small, industry-standard 3.2×5 mm footprint, the Si541 has a dramatically
simplified supply chain that enables Silicon Labs to ship custom frequency
samples 1-2 weeks after receipt of order. Unlike a traditional XO, where a different
crystal is required for each output frequency, the Si541 uses one simple crystal
and a DSPLL IC-based approach to provide the desired output frequencies. This
process also guarantees 100% electrical testing of every device. The Si541 is
factory-configurable for a wide variety of user specifications, including frequency,
output format, and OE pin location/polarity. Specific configurations are factory-
programmed at time of shipment, eliminating the long lead times associated with
custom oscillators.
KEY FEATURES
• Available with any two selectable frequencies
from 0.2 MHz to 1500 MHz
• Very low jitter: 125 fs Typ RMS
(12 kHz – 20 MHz)
•Excellent PSRR and supply noise immunity:
–80 dBc Typ
• 3x tighter stability than SAW oscillators
• 3.3 V, 2.5 V and 1.8 V VDD supply operation
from the same part number
• LVPECL, LVDS, CML, HCSL, CMOS, and
Dual CMOS output options
• 3.2×5 mm package footprint
• Any custom frequency available with 1-2
week lead times
APPLICATIONS
• 100G/200G/400G OTN, coherent optics
• 10G/40G/100G optical ethernet
•3G-SDI/12G-SDI/24G-SDI broadcast video
• Servers, switches, storage, NICs, search
acceleration
• Test and measurement
• Clock and data recovery
• FPGA/ASIC clocking
Pin Assignments
1
2
3
6
5
4
GND
FS/OE
VDD
CLK+
CLK-
OE/FS
(Top View)
Pin # Descriptions
1, 2 Selectable via ordering option
OE = Output enable; FS = Frequency Select
3 GND = Ground
4 CLK+ = Clock output
5 CLK- = Complementary clock output. Not used
for CMOS.
6 VDD = Power supply
Phase Error
Cancellation
Fixed
Frequency
Crystal
Frequency
Flexible
DSPLL Low
Noise
Driver
Digital
Loop
Filter
DCO
Digital
Phase
Detector
Fractional
Divider
Phase Error
OSC
Power Supply Regulation
NVM
Built-in Power Supply
Noise Rejection
Control
OE, Frequency Select
(Pin Control)
Flexible
Formats,
1.8V – 3.3V
Operation
silabs.com | Building a more connected world. Rev. 0.7
1. Ordering Guide
The Si541 XO supports a variety of options including frequency, output format, and OE pin location/polarity, as shown in the chart
below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks. Silicon
Laboratories provides an online part number configuration utility to simplify this process. Refer to www.silabs.com/oscillators to access
this tool and for further ordering instructions.
FS
Pin
Pin 2
Pin 2
Pin 1
Pin 1
- - - - - B A G-AAA541 R
Dual Frequency
DescriptionXO Series
541 20 ppm
Temp Stability
A 3.2x5 mm
Package
B -40 to 85 °C
Temperature Grade
G
Device Revision
Tape and Reel
Reel
R
Coil Tape<Blank>
OE Polarity
OE
Pin
Active HighPin 1A
Active LowPin 1B
Active HighPin 2C
Active LowPin 2D
Frequency Code Description
xxxxxx
Two unique frequencies can be specified
within the supported range of the selected
signal format. Either frequency can be
assigned to FS=0 or FS=1. A six digit numeric
code will be assigned for the specific
combination of frequencies.
Order
Option
VDD RangeSignal Format
A2.5, 3.3 V LVPECL
B1.8, 2.5, 3.3 V LVDS
C1.8, 2.5, 3.3 V CMOS
D1.8, 2.5, 3.3 V CML
E1.8, 2.5, 3.3 V HCSL
F1.8, 2.5, 3.3 V
Dual CMOS
(In-Phase)
G1.8, 2.5, 3.3 V
Dual CMOS
(Complementary)
3
50 ppm
Total Stability2
H1.8, 2.5, 3.3 V Custom1
Notes:
1. Contact Silicon Labs for non-standard configurations.
2. Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 °C.
3. Create custom part numbers at www.silabs.com/oscillators.
1.1 Technical Support
Frequently Asked Questions (FAQ) www.silabs.com/Si541-FAQ
Oscillator Phase Noise Lookup Utility www.silabs.com/oscillator-phase-noise-lookup
Quality and Reliability www.silabs.com/quality
Development Kits www.silabs.com/oscillator-tools
Si541 Data Sheet
Ordering Guide
silabs.com | Building a more connected world. Rev. 0.7 | 2
2. Electrical Specifications
Table 2.1. Electrical Specifications
VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC
Parameter Symbol Test Condition/Comment Min Typ Max Unit
Temperature Range TA–40 — 85 ºC
Frequency Range FCLK LVPECL, LVDS, CML 0.2 — 1500 MHz
HCSL 0.2 — 400 MHz
CMOS, Dual CMOS 0.2 — 250 MHz
Supply Voltage VDD 3.3 V 3.135 3.3 3.465 V
2.5 V 2.375 2.5 2.625 V
1.8 V 1.71 1.8 1.89 V
Supply Current IDD LVPECL (output enabled) — 100 132 mA
LVDS/CML (output enabled) — 75 111 mA
HCSL (output enabled) — 80 125 mA
CMOS (output enabled) — 74 108 mA
Dual CMOS (output enabled) — 80 125 mA
Tristate Hi-Z (output disabled) — 64 100 mA
Temperature Stability Frequency stability Grade A –20 — 20 ppm
Total Stability1FSTAB Frequency stability Grade A –50 — 50 ppm
Rise/Fall Time
(20% to 80% VPP)
TR/TFLVPECL/LVDS/CML — — 350 ps
CMOS / Dual CMOS, (CL = 5 pF) — 0.5 1.5 ns
HCSL, FCLK >50 MHz — — 450 ps
Duty Cycle DCAll formats 45 — 55 %
Output Enable (OE)
Frequency Select (FS)2
VIH 0.7 × VDD — — V
VIL — — 0.3 × VDD V
TDOutput Disable Time, FCLK >10 MHz — — 3 µs
TEOutput Enable Time, FCLK > 10 MHz — — 20 µs
TFS Settling Time after FS Change — — 10 ms
Powerup Time tOSC Time from 0.9 × VDD until output fre-
quency (FCLK) within spec
— — 10 ms
LVPECL Output Option3VOC Mid-level VDD – 1.42 — VDD – 1.25 V
VOSwing (diff) 1.1 — 1.9 VPP
LVDS Output Option4VOC Mid-level (2.5 V, 3.3 V VDD) 1.125 1.20 1.275 V
Mid-level (1.8 V VDD) 0.8 0.9 1.0 V
VOSwing (diff) 0.5 0.7 0.9 VPP
Si541 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 0.7 | 3
Parameter Symbol Test Condition/Comment Min Typ Max Unit
HCSL Output Option5VOH Output voltage high 660 750 850 mV
VOL Output voltage low –150 0 150 mV
VCCrossing voltage 250 350 550 mV
CML Output Option
(AC-Coupled)
VOSwing (diff) 0.6 0.8 1.0 VPP
CMOS Output Option VOH IOH = 8/6/4 mA for 3.3/2.5/1.8 V VDD 0.85 × VDD — — V
VOL IOL = 8/6/4 mA for 3.3/2.5/1.8 V VDD — — 0.15 × VDD V
Notes:
1. Total Stability includes ±20 ppm temperature stability, initial accuracy, load pulling, VDD variation, and aging for 20 yrs at 70 ºC.
2. OE includes a 50 kΩ pull-up to VDD for OE active high. Includes a 50 kΩ pull-down to GND for OE active low. FS includes a 50
kΩ pull-up to VDD.
3. 50 Ω to VDD – 2.0 V.
4. Rterm = 100 Ω (differential).
5. 50 Ω to GND.
Table 2.2. Clock Output Phase Jitter and PSRR
VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC
Parameter Symbol Test Condition/Comment Min Typ Max Unit
Phase Jitter (RMS, 12kHz - 20MHz)1
FCLK ≥ 100 MHz
ϕJDifferential Formats — 125 200 fs
CMOS, Dual CMOS — 250 — fs
Spurs Induced by External Power Supply
Noise, 50 mVpp Ripple. LVDS 156.25 MHz
Output
PSRR 100 kHz sine wave — -83 —
dBc
200 kHz sine wave — -83 —
500 kHz sine wave — -82 —
1 MHz sine wave — -85 —
Note:
1. Guaranteed by characterization. Jitter inclusive of any spurs.
Table 2.3. Clock Output Phase Noise (Typical)
Offset Frequency (f) 156.25 MHz LVDS 200 MHz LVDS 644.53125 MHz LVDS Unit
100 Hz –110 –107 –99
dBc/Hz
1 kHz –121 –120 –109
10 kHz –132 –130 –121
100 kHz –139 –137 –127
1 MHz –151 –149 –138
10 MHz –160 –161 –155
20 MHz –161 –162 –157
Phase Jitter (RMS, 12kHz - 20MHz) 121 114 108 fs
Si541 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 0.7 | 4
Offset Frequency (f) 156.25 MHz
LVPECL
200 MHz
LVPECL
644.53125 MHz
LVPECL
Unit
100 Hz –113 –110 –100
dBc/Hz
1 kHz –123 –120 –110
10 kHz –133 –130 –119
100 kHz –139 –137 –127
1 MHz –151 –149 –138
10 MHz –162 –166 –156
20 MHz –163 –167 –157
Phase Jitter (RMS, 12kHz - 20MHz) 120 113 113 fs
Phase jitter measured with Agilent E5052 using a differential-to-single ended converter (balun or buffer). Measurements collected for
>700 commonly used frequencies. Phase noise plots for specific frequencies are available using our free, online Oscillator Phase Noise
Lookup Tool at www.silabs.com/oscillators.
Figure 2.1. Phase Jitter vs. Output Frequency
Si541 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 0.7 | 5
Table 2.4. Environmental Compliance and Package Information
Parameter Test Condition
Mechanical Shock MIL-STD-883, Method 2002
Mechanical Vibration MIL-STD-883, Method 2007
Solderability MIL-STD-883, Method 2003
Gross and Fine Leak MIL-STD-883, Method 1014
Resistance to Solder Heat MIL-STD-883, Method 2036
Moisture Sensitivity Level (MSL) 1
Contact Pads Gold over Nickel
Note:
1. For additional product information not listed in the data sheet (e.g. RoHS Certifications, MDDS data, qualification data, REACH
Declarations, ECCN codes, etc.), refer to our "Corporate Request For Information" portal found here: www.silabs.com/support/
quality/Pages/RoHSInformation.aspx.
Table 2.5. Thermal Conditions
Package Parameter Symbol Test Condition Value Unit
3.2×5 mm
6-pin CLCC
Thermal Resistance Junction to Ambient ΘJA Still Air, 85 ºC 80.3 ºC/W
Thermal Resistance Junction to Board ΘJB Still Air, 85 ºC 50.8 ºC/W
Max Junction Temperature TJStill Air, 85 ºC 125 ºC
Table 2.6. Absolute Maximum Ratings1
Parameter Symbol Rating Unit
Maximum Operating Temp. TAMAX 95 ºC
Storage Temperature TS–55 to 125 ºC
Supply Voltage VDD –0.5 to 3.8 ºC
Input Voltage VIN –0.5 to VDD + 0.3 V
ESD HBM (JESD22-A114) HBM 2.0 kV
Solder Temperature2TPEAK 260 ºC
Solder Time at TPEAK2TP20–40 sec
Notes:
1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification
compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device
reliability.
2. The device is compliant with JEDEC J-STD-020.
Si541 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 0.7 | 6
3. Dual CMOS Buffer
Dual CMOS output format ordering options support either complementary or in-phase signals for two identical frequency outputs. This
feature enables replacement of multiple XOs with a single Si541 device.
~
~
Complementary
Outputs
In-Phase
Outputs
Figure 3.1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs
Si541 Data Sheet
Dual CMOS Buffer
silabs.com | Building a more connected world. Rev. 0.7 | 7
4. Recommended Output Terminations
The output drivers support both AC-coupled and DC-coupled terminations as shown in figures below.
CLK-
LVPECL
Receiver
(3.3V, 2.5V)
VDD
Si54x
50 Ω
CLK+ 50 Ω
Rp Rp
VDD
R1 R1
R2 R2
CLK-
LVPECL
Receiver
(3.3V, 2.5V)
VDD
Si54x
50 Ω
CLK+ 50 Ω
VDD
R1 R1
R2 R2
AC-Coupled LVPECL – Thevenin Termination DC-Coupled LVPECL – Thevenin Termination
CLK-
LVPECL
Receiver
50 Ω
CLK+
50 Ω
Rp Rp
50 Ω
R1
R2 50 Ω
VDD VTT
Si54x
(3.3V, 2.5V)
VDD
CLK-
LVPECL
Receiver
50 Ω
CLK+
50 Ω
50 Ω
R1
R2 50 Ω
VDD VTT
Si54x
(3.3V, 2.5V)
VDD
AC-Coupled LVPECL - 50 Ω w/VTT Bias DC-Coupled LVPECL - 50 Ω w/VTT Bias
Figure 4.1. LVPECL Output Terminations
AC Coupled LVPECL
Termination Resistor Values
VDD R1 R2 Rp
3.3 V 127 Ω 82.5 Ω 130 Ω
2.5 V 250 Ω 62.5 Ω 90 Ω
DC Coupled LVPECL
Termination Resistor Values
VDD R1 R2
3.3 V 127 Ω 82.5 Ω
2.5 V 250 Ω 62.5 Ω
Si541 Data Sheet
Recommended Output Terminations
silabs.com | Building a more connected world. Rev. 0.7 | 8
DC-Coupled LVDS Source Terminated HCSL
AC-Coupled LVDS Destination Terminated HCSL
CLK-
LVDS
Receiver
50 Ω
CLK+
50 Ω
100 Ω
Si54x
(3.3V, 2.5V, 1.8V)
VDD
CLK-
LVDS
Receiver
50 Ω
CLK+
50 Ω
100 Ω
Si54x
(3.3V, 2.5V, 1.8V)
VDD
CLK-
HCSL
Receiver
50 Ω
CLK+ 50 Ω
Si54x
(3.3V, 2.5V, 1.8V)
VDD
33 Ω
33 Ω
50 Ω 50 Ω
CLK-
HCSL
Receiver
50 Ω
CLK+ 50 Ω
Si54x
(3.3V, 2.5V, 1.8V)
VDD
50 Ω 50 Ω
Figure 4.2. LVDS and HCSL Output Terminations
CML Termination without VCM Single CMOS Termination
CML Termination with VCM Dual CMOS Termination
CLK-
CML
Receiver
50 Ω
CLK+
50 Ω
100 Ω
Si54x
(3.3V, 2.5V, 1.8V)
VDD
50 Ω
50 Ω
VCM
CLK-
CML
Receiver
50 Ω
CLK+
50 Ω
Si54x
(3.3V, 2.5V, 1.8V)
VDD
50 Ω
10 Ω
CLK
NC CMOS
Receiver
(3.3V, 2.5V, 1.8V)
VDD
Si54x
50 Ω
10 Ω
CLK+
(3.3V, 2.5V, 1.8V)
VDD
Si54x
50 Ω
10 Ω
CLK-
CMOS
Receivers
Figure 4.3. CML and CMOS Output Terminations
Si541 Data Sheet
Recommended Output Terminations
silabs.com | Building a more connected world. Rev. 0.7 | 9
5. Package Outline
The figure below illustrates the package details for the 3.2 × 5 mm Si541. The table below lists the values for the dimensions shown in
the illustration.
Figure 5.1. Si541 Outline Diagram
Table 5.1. Package Diagram Dimensions (mm)
Dimension Min Nom Max
A 1.06 1.17 1.28
b 0.54 0.64 0.74
c 0.35 0.45 0.55
D 3.20 BSC
D1 2.55 2.60 2.65
e 1.27 BSC
E 5.00 BSC
E1 4.35 4.40 4.45
H 0.45 0.55 0.65
L 0.90 1.00 1.10
L1 0.05 0.10 0.15
p 1.17 1.27 1.37
R 0.32 REF
aaa 0.15
bbb 0.15
ccc 0.10
ddd 0.10
eee 0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Si541 Data Sheet
Package Outline
silabs.com | Building a more connected world. Rev. 0.7 | 10
6. PCB Land Pattern
The figure below illustrates the 3.2 × 5.0 mm PCB land pattern for the Si541. The table below lists the values for the dimensions shown
in the illustration.
Figure 6.1. Si541 PCB Land Pattern
Table 6.1. PCB Land Pattern Dimensions (mm)
Dimension (mm)
C1 2.60
E 1.27
X1 0.80
Y1 1.70
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
Si541 Data Sheet
PCB Land Pattern
silabs.com | Building a more connected world. Rev. 0.7 | 11
7. Top Marking
The figure below illustrates the mark specification for the Si541. The table below lists the line information.
Figure 7.1. Mark Specification
Table 7.1. Si541 Top Mark Description
Line Position Description
1 1–8 "Si541", xxx = Ordering Option 1, Option 2, Option 3 (e.g. Si541AAA)
2 1–6 Frequency Code
(6-digit custom code as described in the Ordering Guide)
3Trace Code
Position 1 Pin 1 orientation mark (dot)
Position 2 Product Revision (A)
Position 3–5 Tiny Trace Code (3 alphanumeric characters per assembly release instructions)
Position 6–7 Year (last two digits of the year), to be assigned by assembly site (ex: 2017 = 17)
Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site
Si541 Data Sheet
Top Marking
silabs.com | Building a more connected world. Rev. 0.7 | 12
8. Revision History
8.1 Revision 0.7
June 27, 2017
• Initial release.
Si541 Data Sheet
Revision History
silabs.com | Building a more connected world. Rev. 0.7 | 13
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intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
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