REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD711
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
Precision, Low Cost,
High Speed, BiFET Op Amp
FEATURES
Enhanced Replacement for LF411 and TL081
AC PERFORMANCE
Settles to ⴞ0.01% in 1.0 s
16 V/s min Slew Rate (AD711J)
3 MHz min Unity Gain Bandwidth (AD711J)
DC PERFORMANCE
0.25 mV max Offset Voltage: (AD711C)
3 V/ⴗC max Drift: (AD711C)
200 V/mV min Open-Loop Gain (AD711K)
4 V p-p max Noise, 0.1 Hz to 10 Hz (AD711C)
Available in Plastic Mini-DIP, Plastic SOIC, Hermetic
Cerdip, and Hermetic Metal Can Packages
MIL-STD-883B Parts Available
Available in Tape and Reel in Accordance with
EIA-481A Standard
Surface Mount (SOIC)
Dual Version: AD712
PRODUCT DESCRIPTION
The AD711 is a high speed, precision monolithic operational
amplifier offering high performance at very modest prices. Its
very low offset voltage and offset voltage drift are the results of
advanced laser wafer trimming technology. These performance
benefits allow the user to easily upgrade existing designs that use
older precision BiFETs and, in many cases, bipolar op amps.
The superior ac and dc performance of this op amp makes it
suitable for active filter applications. With a slew rate of 16 V/ms
and a settling time of 1 ms to ±0.01%, the AD711 is ideal as a
buffer for 12-bit D/A and A/D Converters and as a high-speed
integrator. The settling time is unmatched by any similar IC
amplifier.
The combination of excellent noise performance and low input
current also make the AD711 useful for photo diode preamps.
Common-mode rejection of 88 dB and open loop gain of
400 V/mV ensure 12-bit performance even in high-speed unity
gain buffer circuits.
The AD711 is pinned out in a standard op amp configuration
and is available in seven performance grades. The AD711J and
AD711K are rated over the commercial temperature range of
0∞C to 70∞C. The AD711A, AD711B and AD711C are rated
over the industrial temperature range of –40∞C to +85∞C. The
AD711S and AD711T are rated over the military temperature
range of –40∞C to +125∞C and are available processed to MIL-
STD-883B, REV. E.
Extended reliability PLUS screening is available, specified over
the commercial and industrial temperature ranges. PLUS
screening includes 168 hour burn-in, as well as other environ-
mental and physical tests.
The AD711 is available in an 8-pin plastic mini-DIP, small
outline, cerdip, TO-99 metal can, or in chip form.
PRODUCT HIGHLIGHTS
1. The AD711 offers excellent overall performance at very
competitive prices.
2. Analog Devices’ advanced processing technology and 100%
testing guarantee a low input offset voltage (0.25 mV max,
C grade, 2 mV max, J grade). Input offset voltage is specified
in the warmed-up condition. Analog Devices’ laser wafer
drift trimming process reduces input offset voltage drifts to
3 mV/∞C
max on the AD711C.
3. Along with precision dc performance, the AD711 offers
excellent dynamic response. It settles to ±0.01% in 1 ms and
has a 100% tested minimum slew rate of 16 V/ms. Thus this
device is ideal for applications such as DAC and ADC
buffers which require a combination of superior ac and dc
performance.
4. The AD711 has a guaranteed and tested maximum voltage
noise of 4 mV p-p, 0.1 to 10 Hz (AD711C).
5. Analog Devices’ well-matched, ion-implanted JFETs ensure
a guaranteed input bias current (at either input) of 25 pA
max (AD711C) and an input offset current of 10 pA max
(AD711C). Both input bias current and input offset current
are guaranteed in the warmed-up condition.
CONNECTION DIAGRAMS
10k⍀
V
OS
TRIM
–15V
NC
OFFSET
NULL
INVERTING
INPUT
NON
INVERTING
INPUT
OFFSET
NULL
OUTPUT
–V
S
+V
S
NC = NO CONNECT
AD711
NOTE
PIN 4 CONNECTED TO CASE
8
7
6
5
1
2
3
4
NC = NO CONNECT
OFFSET
NULL NC
OUTPUT
AD711
INVERTING
INPUT
NONINVERTING
INPUT
–VS
+VS
OFFSET
NULL
REV. E
–2–
AD711–SPECIFICATIONS
(VS = 15 V @ TA = 25C, unless otherwise noted.)
J/A/S K/B/T C
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
INPUT OFFSET VOLTAGE
1
Initial Offset 0.3 2/1/1 0.2 0.5 0.10 0.25 mV
T
MIN
to T
MAX
3/2/2 1.0 0.45 mV
vs. Temp 7 20/20/20 5 10 2 5 mV/∞C
vs. Supply 76 95 80 100 86 110 dB
T
MIN
to T
MAX
76/76/76 80 86 dB
Long-Term Stability 15 15 15 mV/Month
INPUT BIAS CURRENT
2
V
CM
= 0 V 15 50 15 50 15 25 pA
V
CM
= 0 V @ T
MAX
1.1/3.2/51 1.1/3.2/51 1.6 nA
V
CM
= ±10 V 20 100 20 100 20 50 pA
INPUT OFFSET CURRENT
V
CM
= 0 V 10 25 5 25 5 10 pA
V
CM
= 0 V @ T
MAX
0.6/1.6/26 0.6/1.6/26 0.65 nA
FREQUENCY RESPONSE
Small Signal Bandwidth 3.0 4.0 3.4 4.0 3.4 4.0 MHz
Full Power Response 200 200 200 kHz
Slew Rate 16 20 18 20 18 20 V/ms
Settling Time to 0.01% 1.0 1.2 1.0 1.2 1.0 1.2 ms
Total Harmonic Distortion 0.0003 0.0003 0.0003 %
INPUT IMPEDANCE
Differential 3 ¥ 10
12
储5.5 3 ¥ 10
12
储5.5 3 ¥ 10
12
储5.5 W储pF
Common Mode 3 ¥ 10
12
储5.5 3 ¥ 10
12
储5.5 3 ¥ 10
12
储5.5 W储pF
INPUT VOLTAGE RANGE
Differential
3
±20 ±20 ±20 V
Common-Mode Voltage
4
+14.5, –11.5 +14.5, –11.5 +14.5, –11.5
T
MIN
to T
MAX
–V
S
+ 4 +V
S
– 2 –V
S
+ 4 +V
S
– 2 –V
S
+ 4 +V
– 2 V
Common-Mode
Rejection Ratio
V
CM
= ±10 V 76 88 80 888694dB
T
MIN
to T
MAX
76/76/76 84 80 84 86 90 dB
V
CM
= ±11 V 70 84 76 847690dB
T
MIN
to T
MAX
70/70/70 80 74 80 74 84 dB
INPUT VOLTAGE NOISE 2 2 2 4 mV p-p
45 45 45 nV/÷Hz
22 22 22 nV/÷Hz
18 18 18 nV/÷Hz
16 16 16 nV/÷Hz
INPUT CURRENT NOISE 0.01 0.01 0.01 pA/÷Hz
OPEN-LOOP GAIN 150 400 200 400 200 400 V/mV
100/100/100 100 100 V/mV
OUTPUT
CHARACTERISTICS
Voltage +13, –12.5 +13.9, –13.3 +13, –12.5 +13.9, –13.3 +13, –12.5 +13.9, –13.3 V
±12/±12/±12 +13.8, –13.1 ±12 +13.8, –13.1 ±12 +13.8, –13.1 V
Current 25 25 25 mA
POWER SUPPLY
Rated Performance ±15 ±15 ±15 V
Operating Range ±4.5 ±18 ±4.5 ±18 ±4.5 ±18 V
Quiescent Current 2.5 3.4 2.5 3.0 2.5 2.8 mA
NOTES
1
Input Offset Voltage specifications are guaranteed after 5 minutes of operation at T
A
= 25∞C.
2
Bias Current specifications are guaranteed maximum at either input after 5 minutes of operation at T
A
= 25∞C. For higher temperatures, the current doubles every 10∞C.
3
Defined as voltage between inputs, such that neither exceeds ±10 V from ground.
4
Typically exceeding –14.1 V negative common-mode voltage on either input results in an output phase reversal.
Specifications subject to change without notice.
REV. E
AD711
–3–
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation
2
. . . . . . . . . . . . . . . . . . . . . 500 mW
Input Voltage
3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . +V
S
and –V
S
Storage Temperature Range (Q, H) . . . . . . . –65∞C to +150∞C
Storage Temperature Range (N) . . . . . . . . . . –65∞C to +125∞C
Operating Temperature Range
AD711J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0∞C to +70∞C
AD711A/B/C . . . . . . . . . . . . . . . . . . . . . . . . –40∞C to +85∞C
AD711S/T . . . . . . . . . . . . . . . . . . . . . . . . . –55∞C to +125∞C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300∞C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Thermal Characteristics:
8-Pin Plastic Package: q
JC
= 33∞C/Watt; q
JA
= 100∞C/Watt
8-Pin Cerdip Package: q
JC
= 22∞C/Watt; q
JA
= 110∞C/Watt
8-Pin Metal Can Package: q
JC
= 65∞C/Watt; q
JA
= 150∞C/Watt
8-Pin SOIC Package: q
JC
= 43∞C/Watt; q
JA
= 160∞C/Watt
3
For supply voltages less than ±18 V, the absolute maximum input voltage is equal
to the supply voltage.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option*
*AD711AH –40∞C to +85∞C8-Pin Metal Can H-08A
AD711AQ –40∞C to +85∞C8-Pin Ceramic DIP Q-8
*AD711BQ –40∞C to +85∞C8-Pin Ceramic DIP Q-8
*AD711CH –40∞C to +85∞C8-Pin Metal Can H-08A
AD711JN 0∞C to 70∞C8-Pin Plastic DIP N-8
AD711JR 0∞C to 70∞C8-Pin Plastic SOIC RN-8
AD711JR-REEL 0∞C to 70∞C8-Pin Plastic SOIC RN-8
AD711JR-REEL7 0∞C to 70∞C8-Pin Plastic SOIC RN-8
AD711KN 0∞C to 70∞C8-Pin Plastic DIP N-8
AD711KR 0∞C to 70∞C8-Pin Plastic SOIC RN-8
AD711KR-REEL 0∞C to 70∞C8-Pin Plastic SOIC RN-8
AD711KR-REEL7 0∞C to 70∞C8-Pin Plastic SOIC RN-8
*AD711SQ/883B –55∞C to +125∞C8-Pin Ceramic DIP Q-8
*AD711TQ/883B –55∞C to +125∞C8-Pin Ceramic DIP Q-8
*Not for new design, obsolete April 2002
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD711 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. E
AD711–Typical Performance Characteristics
–4–
SUPPLY VOLTAGE – Vo l t s
OUTPUT VOLTAGE SWING – Volts
005
10
10
5
15
20
15 20
RL = 2k
25C
+VOUT
–VOUT
TPC 2. Output Voltage Swing vs.
Supply Voltage
TEMPERATURE – C
INPUT BIAS CURRENT (V
CM
= 0) – Amps
10
–12
–60 –40 –20 0 20 40 60 80 100 120 140
10
–11
10
–10
10
–9
10
–8
10
–7
10
–6
TPC 5. Input Bias Current vs. Tem-
perature
AMBIENT TEMPERATURE – C
SHORT CIRCUIT CURRENT LIMIT – mA
–60
10
–40 –20 0 20 40 60 80 100 120 140
12
14
16
18
20
22
24
26
–OUTPUT CURRENT
+OUTPUT CURRENT
TPC 8. Short Circuit Current Limit
vs. Temperature
SUPPLY VOLTAGE – Vo l t s
INPUT VOLTAGE SWING – Volts
005
10
10
5
15
20
15 20
RL = 2k
25C
TPC 1. Input Voltage Swing vs.
Supply Voltage
SUPPLY VOLTAGE – Vo l t s
QUIESCENT CURRENT – mA
1.75 05
10 15 20
2.00
2.25
2.50
2.75
TPC 4. Quiescent Current vs. Sup-
ply Voltage
COMMON MODE VOLTAGE – Volts
INPUT BIAS CURRENT – pA
0
–10
50
25
75
100
MAX J GRADE LIMIT
–5 0 5 10
VS = 15V
25C
TPC 7. Input Bias Current vs. Com-
mon Mode Voltage
LOAD RESISTANCE –
OUTPUT VOLTAGE SWING – Volts p-p
0
10
15
100 1k 10k
20
25
30
10
5
15V SUPPLIES
TPC 3. Output Voltage Swing vs.
Load Resistance
FREQUENCY – Hz
OUTPUT IMPEDANCE –
0.01
1k
A
VCL
= 1
10k 100k 1M 10M
0.01
1
10
100
TPC 6. Output Impedance vs. Fre-
quency
TEMPERATURE – C
UNITY GAIN BANDWIDTHT – MHz
–60
3.0
–40 –20 0 20 40 60 80 100 120 140
3.5
4.0
4.5
5.0
TPC 9. Unity Gain Bandwidth vs.
Temperature
REV. E –5–
AD711
SUPPLY MODULATION FREQUENCY – Hz
POWER SUPPLY REJECTION – dB
0
10
20
40
60
80
100
110
100 1k 10k 10k1
–SUPPLY
+SUPPLY
V
S
= 15 SUPPLIES
WITH 1V p-p SINE
WAVE 25 C
TPC 12. Power Supply Rejection
vs. Frequency
SETTLING TIME – s
OUTPUT SWING FRIM 0V TO Vo l t s
0.5
–10
–8
–6
–4
–2
0
2
2
4
6
8
0.6 0.7 0.8 0.9 1.0
ERROR 1% 0.1% 0.01%
1% 0.1% 0.01%
TPC 15. Output Swing and Error
vs. Settling Time
INPUT ERROR SIGNAL – mV
(AT SUMMING JUNCTION)
SLEW RATE – Vs
0
0
100 200 300 400
5
10
15
20
25
500 600 700 800 900
TPC 18. Slew Rate vs. Input
Error Signal
SUPPLY VOLTAGE – Vo l t s
OPEN-LOOP GAIN – dB
0
95
5101520
100
105
110
115
120
125
R
L
= 2k
25C
TPC 11. Open-Loop Gain vs.
Supply Voltage
INPUT FREQUENCY – Hz
0
5
10
30
10M100k 1M
15
20
25
OUTPUT VOLTAGE – Volts p-p
R
L
= 2k
25 C
V
S
= 15V
TPC 14. Large Signal Frequency
Response
FREQUENCY – Hz
1
1
10
10
INPUT NOISE VOLTAGE – nV/ Hz
100
1k
100 1k 10k 100k
TPC 17. Input Noise Voltage
Spectral Density
FREQUENCY – Hz
OPEN LOOP GAIN – dB
10
–20
100 1k 10k 100k 1M
0
20
40
60
10M
80
100
GAIN
RL = 2k
C = 100pF
PHASE
–20
0
20
40
60
80
100
PHASE MARGIN – Degrees
TPC 10. Open-Loop Gain and
Phase Margin vs. Frequency
FREQUENCY – Hz
CMR – dB
100
0
10
20
100
V
S
= 15V
V
CM
= 1V p-p
25 C
40
60
80
1k 10k 100k 1M
TPC 13. Common Mode Rejection
vs. Frequency
FREQUENCY – Hz
THD – dB
–130
100
–120
–110
–100
–90
–80
–70
1k 10k 100k
3V RMS
R
L
= 2k
C
L
= 100pF
TPC 16. Total Harmonic Distor-
tion vs. Frequency
REV. E
AD711
–6–
TPC 21. Offset Null Configurations
TPC 22c. Unity Gain Follower
Pulse Response (Small Signal)
TPC 23c. Unity Gain Inverter Pulse
Response (Small Signal)
TPC 20. T.H.D. Test Circuit
TPC 22b. Unity Gain Follower
Pulse Response (Large Signal)
TPC 23b. Unity Gain Inverter
Pulse Response (Large Signal)
TEMPERATURE – C
SLEW RATE – V/s
–60 –40 –20 0 20 40 60 80 100 120 140
20
25
15
16
17
18
19
21
22
23
24
TPC 19. Slew Rate vs. Temperature
RL
2k
VOUT
VIN
+VS
–VS
0.1F
CL
100pF
0.1F
SQUARE WAVE
INPUT
AD711
TPC 22a. Unity Gain Follower
R
L
2k
V
OUT
V
IN
+V
S
–V
S
0.1F
C
L
100pF
0.1F
SQUARE WAVE
INPUT
5k
AD711
5k
TPC 23a. Unity Gain Inverter
2k
OUTPUT
+V
S
–V
S
0.1F
100pF
0.1F
AD711
INPUT
+V
S
–V
S
0.1F
AD711
10k
0.1F1.3Mk
+V
S
–V
S
0.1F
AD711
10k
0.1F
REV. E
AD711
–7–
OPTIMIZING SETTLING TIME
Most bipolar high-speed D/A converters have current outputs;
therefore, for most applications, an external op amp is required
for current-to-voltage conversion. The settling time of the
converter/op amp combination depends on the settling time of
the DAC and output amplifier. A good approximation is:
tSTotal =(tSDAC )2+(tSAMP )2
(1)
The settling time of an op amp DAC buffer will vary with the
noise gain of the circuit, the DAC output capacitance, and with
the amount of external compensation capacitance across the
DAC output scaling resistor.
Settling time for a bipolar DAC is typically 100 ns to 500 ns.
Previously, conventional op amps have required much longer
settling times than have typical state-of-the-art DACs; therefore,
the amplifier settling time has been the major limitation to a
high-speed voltage-output D-to-A function. The introduction
of the AD711/712 family of op amps with their 1 ms (to ±0.01%
of final value) settling time now permits the full high-speed
capabilities of most modern DACs to be realized.
In addition to a significant improvement in settling time, the
low offset voltage, low offset voltage drift, and high open-loop
gain of the AD711 family assures 12-bit accuracy over the full
operating temperature range.
The excellent high-speed performance of the AD711 is shown
in the oscilloscope photos of Figure 2. Measurements were taken
using a low input capacitance amplifier connected directly to the
summing junction of the AD711 – both photos show the worst
case situation: a full-scale input transition. The DAC’s 4 kW
[10 kW储8 kW = 4.4 kW] output impedance together with a 10 kW
feedback resistor produce an op amp noise gain of 3.25. The
current output from the DAC produces a 10 V step at the op
amp output (0 to –10 V Figure 2a, –10 V to 0 V Figure 2b.)
Therefore, with an ideal op amp, settling to ±1/2 LSB (±0.01%)
requires that 375 mV or less appears at the summing junction.
This means that the error between the input and output (that
voltage which appears at the AD711 summing junction) must
be less than 375 mV. As shown in Figure 2, the total settling time
for the AD711/AD565 combination is 1.2 microseconds.
OUTPUT
–10V TO +10V
+15V
0.1F
10pF
0.1F
AD711K
DAC
I
OUT
= 4
I
REF
CODE
0.5mA
I
REF
20k
19.95k
R1
100
BIPOLAR
OFFSET ADJUST
I
O
DAC
OUT
10V
SPAN
–15V
20V
SPAN
5k
5k
5k
10V
MSB LSB
REF
OUT V
CC
REF
IN
REF
GND
R2
100
GAIN
ADJUST
0.1F
AD565A
BIPOLAR
OFF
9.95k
–V
EE
0.1F
POWER
GND
Figure 1.
±
10 V Voltage Output Bipolar DAC
Figure 2. Settling Characteristics for AD711 with AD565A
a. (Full-Scale Negative Transition) b. (Full-Scale Positive Transition)
REV. E
AD711
–8–
OP AMP SETTLING TIME—A MATHEMATICAL MODEL
The design of the AD711 gives careful attention to optimizing
individual circuit components; in addition, a careful tradeoff was
made: the gain bandwidth product (4 MHz) and slew rate
(20 V/ms) were chosen to be high enough to provide very fast
settling time but not too high to cause a significant reduction in
phase margin (and therefore stability). Thus designed, the AD711
settles to ±0.01%, with a 10 V output step, in under 1 ms, while
retaining the ability to drive a 100 pF load capacitance when
operating as a unity gain follower.
If an op amp is modeled as an ideal integrator with a unity gain
crossover frequency of w
o
/2p, Equation 1 will accurately describe
the small signal behavior of the circuit of Figure 3a, consisting of
an op amp connected as an I-to-V converter at the output of a
bipolar or CMOS DAC. This equation would completely describe
the output of the system if not for the op amp’s finite slew rate
and other nonlinear effects.
V
O
I
IN
=–R
R(C
f
=C
X
)
w
o
s
2
+G
N
w
o
+RC
f
Ê
Ë
Áˆ
¯
˜s+1
(3)
where:
w
o
2
p
=op amp’s unity gain frequency
G
N
= “noise” gain of circuit
1+R
R
O
Ê
Ë
Áˆ
¯
˜
This equation may then be solved for C
f
:
Cf=2-GN
Rwo+2RCXwo+(1 -GN)
Rwo
(3)
In these equations, capacitor C
X
is the total capacitor appearing
the inverting terminal of the op amp. When modeling a DAC
buffer application, the Norton equivalent circuit of Figure 3a
can be used directly; capacitance C
X
is the total capacitance of
the output of the DAC plus the input capacitance of the op amp
(since the two are in parallel).
AD711
C
X
R
O
I
O
C
F
R
R
L
C
L
V
OUT
Figure 3a. Simplified Model of the AD711 Used as a
Current-Out DAC Buffer
When R
O
and I
O
are replaced with their Thevenin V
IN
and R
IN
equivalents, the general purpose inverting amplifier of Figure 26b
is created. Note that when using this general model, capacitance
C
X
is either the input capacitance of the op amp if a simple inverting
op amp is being simulated or it is the combined capacitance of
the DAC output and the op amp input if the DAC buffer is
being modeled.
AD711
C
X
R
IN
C
F
R
R
L
C
L
V
OUT
V
IN
Figure 3b. Simplified Model of the AD711
Used as an Inverter
In either case, the capacitance C
X
causes the system to go from
a one-pole to a two-pole response; this additional pole increases
settling time by introducing peaking or ringing in the op amp
output. Since the value of C
X
can be estimated with reasonable
accuracy, Equation 2 can be used to choose a small capacitor,
C
F
, to cancel the input pole and optimize amplifier response.
Figure 4 is a graphical solution of Equation 2 for the AD711
with R = 4 kW.
C
F
0010
C
X
10
20
30
40
50
60
20 30 40 50 60
G
N
= 4.0
G
N
= 1.0
G
N
= 1.5
G
N
= 2.0
G
N
= 3.0
Figure 4. Value of Capacitor C
F
vs. Value of C
X
The photos of Figures 5a and 5b show the dynamic response of
the AD711 in the settling test circuit of Figure 6.
The input of the settling time fixture is driven by a flat-top pulse
generator. The error signal output from the false summing node
of A1 is clamped, amplified by A2 and then clamped again. The
error signal is thus clamped twice: once to prevent overloading
amplifier A2 and then a second time to avoid overloading the
oscilloscope preamp. The Tektronix oscilloscope preamp type
7A26 was carefully chosen because it does not overload with
these input levels. Amplifier A2 needs to be a very high speed
FET-input op amp; it provides a gain of 10, amplifying the error
signal output of A1.
REV. E
AD711
–9–
Figure 5a. Settling Characteristics 0 to +10 V Step
Upper Trace: Output of AD711 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)
Figure 5b. Settling Characteristics 0 to –10 V Step
Upper Trace: Output of AD711 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)
GUARDING
The low input bias current (15 pA) and low noise characteristics
of the AD711 BiFET op amp make it suitable for electrometer
applications such as photo diode preamplifiers and picoampere
5pF
AD3554
VERROR
5
+15V
5k
–15V
0.47F
HP2835
TEXTRONIX 7A26
OSCILLOSCOPE
PREAMP
INPUT SELECTION
1M20pF
0.1F
AD711
+15V
–15V
0.1F
VOUT
10pF
HP2835
10k
0.2-0.0pF
1.1k
10k
5-18pF
10k
200k
4.99k4.99k
VIN
DATA
DYNAMICS
5109
(OR
EQUIVALENT
FLAT TOP
PULSE
GENERATOR)
0.47F
205
Figure 6. Settling Time Test Circuit
current-to-voltage converters. The use of a guarding technique
such as that shown in Figure 7, in printed circuit board layout
and construction is critical to minimize leakage currents. The
guard ring is connected to a low impedance potential at the
same level as the inputs. High impedance signal lines should
not be extended for any unnecessary length on the printed
circuit board.
1
8
7
6
5
4
3
26
5
7
8
2
3
1
4
Figure 7. Board Layout for Guarding Inputs
D/A CONVERTER APPLICATIONS
The AD711 is an excellent output amplifier for CMOS DACs.
It can be used to perform both 2-quadrant and 4-quadrant
operation. The output impedance of a DAC using an inverted
R-2R ladder approaches R for codes containing many 1s, 3R
for codes containing a single 1, and for codes containing all
zero, the output impedance is infinite.
For example, the output resistance of the AD7545 will modu-
late between 11 kW and 33 kW. Therefore, with the DAC’s
internal feedback resistance of 11 kW, the noise gain will vary
from 2 to 4/3. This changing noise gain modulates the effect of
the input offset voltage of the amplifier, resulting in nonlinear
DAC amplifier performance.
The AD711K with guaranteed 500 mV offset voltage minimizes
this effect to achieve 12-bit performance.
REV. E
AD711
–10–
AD711K
CF
VOUT
0.1F
0.1F
–15
+15
C1
33pF
R2*
OUT1
RFB
VDD
VREF
DGND AGND
R1*
VIN
ANALOG
COMMON
GAIN
ADJUST
DB11-DB0
VDD
AD7545
*FOR VALUES R1 AND R2,
REFER TO TABLE 1
Figure 8. Unipolar Binary Operation
R1 and R2 calibrate the zero offset and gain error of the DAC.
Specific values for these resistors depend upon the grade of
AD7545 and are shown below.
Table I. Recommended Trim Resistor Values vs. Grades
of the AD7545 for V
DD
= 5 V
TRIM
RESISTOR JN/AQ/SD KN/BQ/TD LN/CQ/UD GLN/GCQ/GUD
R1 500 W200 W100 W20 W
R2 150 W68 W33 W6.8 W
NOISE CHARACTERISTICS
The random nature of noise, particularly in the 1/f region, makes
it difficult to specify in practical terms. At the same time,
designers of precision instrumentation require certain guaranteed
maximum noise levels to realize the full accuracy of their equipment.
The AD711C grade is specified at a maximum level of 4.0 mV p-p,
in a 0.1 Hz to 10 Hz bandwidth. Each AD711C receives a 100%
noise test for two 10-second intervals; devices with any excursion
in excess of 4.0 mV are rejected. The screened lot is then submitted
to Quality Control for verification on an AQL basis.
All other grades of the AD711 are sample-tested on an AQL
basis to a limit of 6 mV p-p, 0.1 to 10 Hz.
DRIVING THE ANALOG INPUT OF AN A/D CONVERTER
An op amp driving the analog input of an A/D converter, such
as that shown in Figure 11, must be capable of maintaining a
constant output voltage under dynamically changing load conditions.
In successive-approximation converters, the input current is
compared to a series of switched trial currents. The comparison
point is diode clamped but may deviate several hundred millivolts
resulting in high frequency modulation of A/D input current.
Figures 10a and 10b show the settling time characteristics of the
AD711 when used as a DAC output buffer for the AD7545.
a. Full-Scale Positive b. Full-Scale Negative
Transition Transition
Figure 10. Settling Characteristics for AD711 with AD7545
compared to a series of switched trial currents. The comparison
point is diode clamped but may deviate several hundred milli-
volts resulting in high frequency modulation of A/D input
current. The output impedance of a feedback amplifier is made
artificially low by the loop gain. At high frequencies, where the
loop gain is low, the amplifier output impedance can approach
its open loop value. Most IC amplifiers exhibit a minimum open
loop output impedance of 25 W due to current limiting resistors.
A few hundred microamps reflected from the change in con-
verter loading can introduce errors in instantaneous input
Figures 8 and 9 show the AD711 and AD7545 (12-bit CMOS
DAC) configured for unipolar binary (2-quadrant multiplication)
or bipolar (4-quadrant multiplication) operation. Capacitor C1
provides phase compensation to reduce overshoot and ringing.
+15V
0.1F
0.1F
AD711K
–15V
R3
10k
1%
+15V
0.1F
0.1F
AD711K
–15V
R5
20k
1%
R4
20k
1%
R2*
C1
33pF
OUT1
R
FB
V
DD
V
REF
DGND AGND
R1*
V
IN
GAIN
ADJUST
DB11-DB0
V
DD
V
OUT
AD7545
12
DATA INPUT ANALOG
COMMON
*FOR VALUES R1 AND R2,
REFER TO TABLE 1
Figure 9. Bipolar Operation
+15V
0.1F
0.1F
AD711
–15V
R2
100
GAIN
ADJUST
12/8
R1
100
OFFSET
ADJUST
CS
AO
R/C
CE
REF IN
REF OUT
BIP OFF
10VIN
20VIN
ANA COM
STS
HIGH
BITS
MIDDLE
BITS
LOW
BITS
+5V
+15V
–15V
DIG COM
AD574
10V
ANALOG
INPUT
ANALOG COM
Figure 11. AD711 as ADC Unity Gain Buffer
REV. E
AD711
–11–
DRIVING A LARGE CAPACITIVE LOAD
The circuit in Figure 13 employs a 100 W isolation resistor which
enables the amplifier to drive capacitive loads exceeding 1500 pF;
the resistor effectively isolates the high frequency feedback from
the load and stabilizes the circuit. Low frequency feedback is
returned to the amplifier summing junction via the low pass
filter formed by the 100 W series resistor and the load capaci-
tance, C
L
. Figure 14 shows a typical transient response for
this connection.
R
L
INPUT
+V
S
–V
S
0.1F
C
L
0.1F
TYPICAL CAPACITANCE
LIMIT FOR VARIOUS
LOAD RESISTORS
R
L
C
L
UP TO
2k1500pF
10k1500pF
20k1000pF
4.99kAD711 100
30pF
4.99k
OUTPUT
Figure 13. Circuit for Driving a Large Capacitive Load
Figure 14. Transient Response R
L
= 2 k
W
, C
L
= 500 pF
ACTIVE FILTER APPLICATIONS
In active filter applications using op amps, the dc accuracy of the
amplifier is critical to optimal filter performance. The amplifier’s
offset voltage and bias current contribute to output error. Offset
voltage will be passed by the filter and may be amplified to produce
excessive output offset. For low frequency applications requiring
large value input resistors, bias currents flowing through these
resistors will also generate an offset voltage.
In addition, at higher frequencies, an op amp’s dynamics must
be carefully considered. Here, slew rate, bandwidth, and open-loop
gain play a major role in op amp selection. The slew rate must
be fast as well as symmetrical to minimize distortion. The amplifier’s
bandwidth in conjunction with the filter’s gain will dictate the
frequency response of the filter.
The use of a high performance amplifier such a s the AD711
will minimize both dc and ac errors in all active filter applica-
tions.
SECOND ORDER LOW PASS FILTER
Figure 15 depicts the AD711 configured as a second order
Butterworth low pass filter. With the values as shown, the corner
frequency will be 20 kHz; however, the wide bandwidth of the
AD711 permits a corner frequency as high as several hundred
kilohertz. Equations for component selection are shown below.
R1 = R2 = user selected (typical values: 10 kW – 100 kW)(4)
C1=1. 414
(2 p)( f
cutoff
)(R1) ,C2=0.707
(2 p)( f
cutoff
)(R1)
(5)
Where:
C1 and C2 are in farads.
V
OUT
+15V
–15V
0.1F
0.1F
AD711
V
IN
C2
280pF
R2
20k
R1
20k
C1
560pF
Figure 15. Second Order Low Pass Filter
An important property of filters is their out-of-band rejection.
The simple 20 kHz low pass filter shown in Figure 15, might be
used to condition a signal contaminated with clock pulses or
sampling glitches which have considerable energy content at
high frequencies.
The low output impedance and high bandwidth of the AD711
minimize high frequency feedthrough as shown in Figure 16.
The upper trace is that of another low-cost BiFET op amp
showing 17 dB more feedthrough at 5 MHz.
Figure 16.
voltage. If the A/D conversion speed is not excessive and the
bandwidth of the amplifier is sufficient, the amplifier’s output
will return to the nominal value before the converter makes its
comparison. However, many amplifiers have relatively narrow
bandwidth yielding slow recovery from output transients. The
AD711 is ideally suited to drive high speed A/D converters since
it offers both wide bandwidth and high open-loop gain.
a. Source Current = 2 mA b. Sink Current = 1 mA
Figure 12. ADC Input Unity Gain Buffer Recovery Times
REV. E
AD711
–12–
+15V
–15V
0.1F
0.1F
A1
AD711
VIN
VOUT
+15V
–15V
0.1F
0.1F
A2
AD711
A
*
B
*
C
*
D
*
0.001F
4.9395E–15 5.9276E–15 5.9276E–15 4.9395E–15
2800619064906190
0.001
F
100k124k
2800
*SEE TEXT
4.99k
4.99k
Figure 17. 9-Pole Chebychev Filter
+15V
–15V
0.1F
0.1F
1/2
AD712
1/2
AD712
0.001F
0.001F
R
1k
4.99k
R: 24.9k FOR 4.9395E–15
29.4k FOR 5.9276E–15
Figure 18. FDNR for 9-Pole Chebychev Filter Figure 19. High Frequency Response for 9-Pole
Chebychev Filter
9-POLE CHEBYCHEV FILTER
Figure 17 shows the AD711 and its dual counterpart, the AD712,
as a 9-pole Chebychev filter using active frequency dependent
negative resistors (FDNR). With a cutoff frequency of 50 kHz
and better than 90 dB rejection, it may be used as an anti-aliasing
filter for a 12-bit data acquisition system with 100 kHz throughput.
As shown in Figure 17, the filter is comprised of four FDNRs (A,
B, C, D) having values of 4.9395 ⫻ 10
–15
and 5.9276 ⫻
10
–15
farad-seconds. Each FDNR active network provides a
2-pole response; for a total of 8 poles. The 9th pole consists of a
0.001 mF capacitor and a 124 kW resistor at Pin 3 of amplifier A2.
Figure 18 depicts the circuits for each FDNR with the proper
selection of R. To achieve optimal performance, the 0.001 mF
capacitors must be selected for 1% or better matching and all
resistors should have 1% or better tolerance.
REV. E
AD711
–13–
OUTLINE DIMENSIONS
8-Lead Metal Can [TO-99]
(H-8)
Dimensions shown in inches and (millimeters)
0.2500 (6.35) MIN
0.5000 (12.70)
MIN
0.1850 (4.70)
0.1650 (4.19)
REFERENCE PLANE
0.0500 (1.27) MAX
0.0190 (0.48)
0.0160 (0.41)
0.0210 (0.53)
0.0160 (0.41)
0.0400 (1.02)
0.0100 (0.25)
0.0400 (1.02) MAX
BASE & SEATING PLANE
0.0340 (0.86)
0.0280 (0.71)
0.0450 (1.14)
0.0270 (0.69)
0.1600 (4.06)
0.1400 (3.56)
0.1000 (2.54) BSC
6
28
7
5
4
3
1
0.2000
(5.08)
BSC
0.1000
(2.54)
BSC
45 BSC
0.3700 (9.40)
0.3350 (8.51)
0.3350 (8.51)
0.3050 (7.75)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-002AK
8-Lead Ceramic Dip – Glass Hermetic Seal [CERDIP]
(Q-8)
Dimensions shown in inches and (millimeters)
14
85
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13)
MIN
0.055 (1.40)
MAX
0.100 (2.54) BSC
15
0
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
0.405 (10.29) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36) 0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
CONTROLLING DIMENSIONS ARE IN INCH; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8-Lead Plastic Dual-in-Line Package [PDIP]
(N-8)
Dimensions shown in inches and (millimeters)
SEATING
PLANE
0.015
(0.38)
MIN
0.180
(4.57)
MAX
0.150 (3.81)
0.130 (3.30)
0.110 (2.79) 0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
8
14
5
0.295 (7.49)
0.285 (7.24)
0.275 (6.98)
0.100 (2.54)
BSC
0.375 (9.53)
0.365 (9.27)
0.355 (9.02)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES)
COMPLIANT TO JEDEC STANDARDS MO-095AA
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(RN-8)
Dimensions shown in millimeters and (inches)
0.25 (0.0098)
0.19 (0.0075)
1.27 (0.0500)
0.41 (0.0160)
0.50 (0.0196)
0.25 (0.0099) ⴛ 45ⴗ
8ⴗ
0ⴗ
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
85
41
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.33 (0.0130)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
REV. E
AD711
–14–
Revision History
Location Page
10/02—Data Sheet changed from REV. D to REV. E.
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
10/02—Data Sheet changed from REV. C to REV. D.
Edits to CONNECTION DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5/02—Data Sheet changed from REV. B to REV. C.
Change from Small Outline Package (R-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Deleted METALLIZATION PHOTOGRAPH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
–15–
–16–
C00832–0–10/02(E)
PRINTED IN U.S.A.
