HD44231P, HD44232P, HD44233P, HD44234P Single Chip CODEC with Filters (COMBO) Features Single Chip CMOS CODEC with Filter In 16-pins DIL Package Power Supply Voltage +5 V+5%, Low Power Dissipation (50 mW Typ) Follows A-Law (HD44231P, HD44233P) Follows pi-Law (HD44232P, HD44234P) Exceeds CCITT Specifications & D4 Synchronous (All Devices)/Asynchronous (HD44233P, HD44234P Only) Operation for 2048/1544/1536 kHz PCM Rate Internal Clock Generator Anti-Aliasing Filter (2nd order CR Active Filter) Voltage Reference (Internal-Trimmed) Input Amplifier Auto-Zero Cancel Circuit Without External Component Pin Configuration arn \ [6] vss An || 16] Ves GAL & iis] yvCMOUT 5 cai[ 2 | 15] PCMour GA2 Ce [is] PD Gaz a tl Pb acnp [4] fia] DGND acnn [7] 13] DGND aout [5] fz] vcs Aout [5 | iz] Tx. sync wc [eo] fin] sNC wc) [6 | 11] RCV. SYNC veo [7 fio) CLOCK Voe [ 7} 10 | TX. CLOCK wco fe] Ta} pene Pom [8 is) RCV. CLOCK HD44231P, HD44232P HD44233P, HD44234P (Top View) Figure 1 Pin Assignment Packaging Information Part No. Package HD44231P DP-16A HD44232P DP-16A HD44233P DP-16A HD44234P DP-16A Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 441HD44231P/HD44232P/HD44233P/HD44234P AOUT FILTER Voc (SV) RCV. SYNC PCMIN 4 fh 6th VoD ~ * only for HD44231P, HD44232P Figure 2 Block Diagram Table 1. Pin Descriptions HD4423iP HD44233P HD44232P HD44234P Function Remarks No. Symbol No. Symbol 1 AIN 1 AIN Analog Input 2 GAIL 2 GAI Gain Adjust 1 Feed-Back Input 3. GA2 3 GA2 Gain Adjust 2 10 kQ < Ri Ct < 100 pF 4 AGND 4 AGND Analog Ground 5 AOUT 5 AOUT Analog Output Ri 2 600 W, Ci < 100 pF 6 NC. 6 NC. Open 7 VDD 7 VDD Positive Pow.Sup. 5V+5% 9 _PCMIN 8 PCMIN PCM Data Input (TTL) 10 CLOCK 9 RCV.CLK PCM Bit Clock (TTL) 2048/1544/1536 kHz 10 TX.CLK 11. SYNC 11. RCV. SYNC Synchronization (TTL) 8 kHz 12 TX.SYNC 13. DGND 13. DGND Digital Ground 14. PD 14. PD Power Down (TTL) 0 = down 15 PCMOUT 15 PCMOUT PCM Data Output Open Drain 16 VSS 16 VSS Negative POW.SUP. 5 V+5% 8 NC Open 12, NC Open HITACHI 442 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300HD44231P/HD44232P/HD44233P/HD44234P General Description The HD44231P, HD44232P, HD44233P, HD44234P are monolithic silicon gate CMOS Companding Encoder/ Decoder chips designed to implement the per channel voice frequency Codecs used in PCM systems. The chips contain the band limiting filters and the analog/digital conversion circuits that conform to the A-law or p-Law companding characteristic. HD44231P and HD44233P are A-Law. HD44232P and HD44234P are p-Law. These circuits provide the interface between the analog signals of the subscriber loop and digital signals of the PCM highway in a digital telephone switching system. The devices operate from dual power supplies of + 5 V. For a sampling rate of 8 kHz, PCM input/output data tate can be selected from 1536/1544/2048 kHz in synchronous or asynchronous (HD44233, HD44234 only) operation. Functional Description Figure 2 shows the simplified block diagram of the HD44231P, HD44232P, HD44233P and HD44234P. The dotted lines are connected internally to get the synchronous devices (HD44231P, HD44232P). The devices contain independent circuitry for processing transmit and receive signais. Switched capacitor filters provide the necessary bandwidth limiting of voice signals in both directions. Circuitry for coding and decoding operates on the principle of successive approximation, using charge redistribution in a binary weighted capacitor array to define segments and a resistor chain to define steps. The relationship between the PCM data word and the audio signal is defined justsame as CCITT G711 Table 1 for HD44231P and HD44233P, Table 2 for HD44232P and HD44234P respectively. A band-gap voltage generator supplies the reference level for the conversion process. 2nd Order CR Active Filter is implemented on chip to avoid the aliasing noise which is caused by the clock of transmit filter. Transmit Section Input analog signals first enter the chip at the uncommitted amplifier terminals. This op amp aliows gain trim to be used if desired to set the 0 dB or 0 level in the system. This amplifier also operates as the 2 nd order analog anti-aliasing filter. This filter eliminates the need for any off-chip filtering as it provides attenuation of 32 dB (typ) at 256 kHz and 40 dB (typ) at 512 kHz, the effective clock frequency of the following switched-capacitor Cosine Filter. From the Cosine Filter the signal enters a 5th Order Low-Pass Filter clocked at 128 kHz, followed by a 3rd Order High-Pass Filter clocked at 8 kHz. The resulting band-pass characteristics meet the CCITT, G.712 specifications. The output of the high pass filter is sampled by a capacitor array at the sampling rate of 8 kHz. The 8-bit PCM data is clocked out by the shift clock at one of 1536/1544/2048 kHz. A auto-zero loop (without any external capacitor) provides DC offset cancellation by integrating the sign bit of the PCM data and feeding it back to the non-inverting input of the comparator. An additional feature of the HD44231P and HD44233P is a signbit fixation circuit to reduce the idle channel noise during quiet periods. It is of particular importance because the A-Law transfer characteristic has mid-riser bias which enhances low level signals from crosstalk. Receive Section A shift clock, at one of 1536/1544/2048 kHz, clock the PCM data into the input buffer register once every sampling period. A charge proportional to the received PCM data word appears on the decoder capacitor array. A sample and hold initialized to zero by a narrow pulse at the beginning of each sampling period integrates the charge and holds for the rest of the sampling period. A switched-capacitor 5th Order Low-Pass Filter clocked at 128 kHz smooths the sampled and held signal. It also performs the loss equalization to compensate for the sin x/ x distortion due to the sample and hold operation. The filter output is available for driving electronic hybrids directly as long as the impedance is greater than 600 Q. Companding Law The encoding and decoding characteristics of the Codecs comply with the requirements of CCITT G711 table HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 443HD44231P/HD44232P/HD44233P/HD44234P 1 or Table 2, corresponding to their comparing law. The even bits of PCM words are inverted for A-Law devices. Positive logic is used (the High level corresponds to 1). Power Down Logic Powering down the CODEC can be done in several ways. The most direct method is to drive the PD pin toa low level. Stopping SYNC input will also put the chip into the stand-by mode. The input can be held high, low or disconnected. After the chip being activated by these functions, the PCMOUT is in high impedance state and the AOUT is connected to AGND for about 1 ms to avoid the power-on noise. Voltage Reference Circuit A temperature compensated band-gap voltage generator provides a stable reference for the coder and decoder. Two amplifiers buffer the reference and supply it to the coder and decoder independently to minimize crosstalk. This reference voltage is trimmed to ensure a minimum gain error of + 0.1 dB at the nominal power supply voltage and the room temperature. Timing Requirements The CODECs do not require that the 8 kHz transmit and receive sampling strobes shouldbe exactly 8 bit periods wide. The device has an internal bit counter that counts the number of data bits shifted. It is reset on the leading (+) edges of the strobe, forcing the PCM output in a high impedance state after the 8th bit is shifted out. This allows the strobe signal to have any duty cycle as long as its repetition rate is 8 KHz and shift clock is synchronized to it. The clock rate can be selected from 1536/1544/2048 kHz. System Clock The basic timing of the Codecs is provided by the shift clock. This 1.536/1.544/2.048 MHz clock is divided down internally to provide the various filter clocks and the timing for the conversions. No external control signal for the selection is required. HITACHI 444 Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD44231P/HD44232P/HD44233P/HD44234P Pin/Function Descriptions Pin No Descriptions * CLOCK 10 One of 1.536, 1.544, 2.048 MHz clock can be accepted with the pins. And they are automatically divided down to provide the internal clocks. **TX.CLOCK 9 These TTL compatible inputs shift PCM data out of the coder on the positive going edges RCV.CLOCK 10 and PCM data into the decoder on the negative going edges after receiving a positive edge on the SYNC, TX.SYNC/RCV.SYNC respectively. * SYNC li These TTL compatible pulse inputs (Typ 8 kHz) are used for analog sampling and for initiating the PCM output from the coder and initiate clocking of PCM input data into the **TX.SYNC li decoder. They must be synchronized with the CLOCK, TX.CLOCK/RCV.CLOCK with RCV.SYNC 12 these positive going edges occurring after the falling edge of the CLOCK, TX.CLOCK/ RCV.CLOCK respectively. The width of these signals are not critical. An internal bit counter generates the necessary timing for PCM output and input. PCMOUT 15 This is a LS-TTL compatible open-drain output. It is active only during transmission of PCM output for 8 bit periods of CLOCK, TX.CLOCK/RCV.CLOCK signal following a positive edge on the SYNC, TX.SYNC/RCV.SYNC input. Data is clocked out by the positive edge of the CLOCK. One 500 Q pull-up per 8 Codecs is required. * PCMIN 9 This is a TTL compatible input for supplying PCM input data to the decoder. Data is **PCMIN 8 clocked in by the negative edge of CLOCK, RCV.CLOCK. AIN 1 These three pins are provided for connecting analog signals in the range of Vrer to GAI1 2 +VreF to the device. The input stage can be connected as a unity gain amplifier, GA2 3 amplifier with gain or amplifier with adjustable gain. The adjustable gain configuration will facilitate calibration of the transmit channel. AIN is the input of analog signal of the amplifier. GA2 is the output of the amplifier. GA2 shall be loaded by the resistor above 10 kQ or directly connected to GA1. GA1 is the negative feed back input of the amplifier. Cx should be less than 100 pF. AOUT 5 This is the buffered output of the recreated analog signal from the received PCM data words. It can drive the impedance of 600 ohms. Ci should be less than 100 pF. Vopp 7 These are power supply pins. Vpp and Vss are positive and negative supply pins Vss 16 respectively (Typ +5 V,5 V). Analog and digital ground pins are separate for minimiz- AGND 4 ing crosstalk. DGND 13 PD 14 When this TTL compatible input is held low, the chip is put into the powered down mode * : for HD44231P, HD44232P ** : for HD44233P, HD44234P Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 regardless of strobes. The chip will also power down if the strobes stop. The strobes can be high, low or floating, but as long as they are static, the powered down mode is in effect. This pin should be pulled-up to Vpp to keep the device active or to control On/Off with strobes. HITACHI 445HD44231P/HD44232P/HD44233P/HD44234P Absolute Maximum Ratings Item Rating Vpp 0.3 t0+7 V Vss 40.3 to~7 V Storage Temperature 55C to +125C Power Dissipation 0.5 W Digital Input/Output Voltage ~0.3 V < Vin < Von + 0.3 Analog Input/Output Voltage Electrical Characteristics Static Characteristics (Vpp = 5 + 0.25 V, Vss = 5 0.25 V, Vec=5+0.25 V, Ta = 0-70C) Vss -0.3 V < Vin < Von + 0.3 Symbol Pin Pin Descriptions Min Typ Max Unit Note/Conditions HD44231P HD44233P HD44232P HD44234P Tpp 7 7 Vpp Current (OPE.) 5.5 10 mA Noe Iss 16 16 Vss Current (OPE.) -10 -45 AIN=0V Ippst 7 7 Vpp Current (St.By.) 0.3 1 PCMIN = +0 CODE Issst 16 16 Vss Current (St.By.) 0.2 Ri(GA2) = 10kQ Ri(AOUT) = 600 kQ IL 1, 2,9, 1, 2, 8, Leak Current -10.0 10.0 pA VmM=08V 10, 14 9, 10, 14 -10.0 10.0 pA VmM=2.0V 10.0 pA Vop=VmM=5.25V Tet. 11 11, 12 Pull Up Current -100 O pA Ipu 15 15 Leak Current 10.0 pA Vpop=VM=5.25V Cainz 1,2 1,2 Analog Input Cap. 10 pF at | MHz Vbias=0V Coin 9, 10, 8, 9, 10, Input Capacitance 10 pF at 1 MHz Vbias=0V 11, 14 11, 12, 14 Rovuta 5 5 AOUT Resistance 1 10) 6 Q Route 3 3 GA2 Resistance 30 Q Note} Vosw 3 3 GA2 Output Swing -3.0 3.0 Vi Rir=10kQ VOoFFIN 1 1 Analog Offset Input 500 500 mV_ Note! VOFFG 3 3 GA2 Offset Output -50 50 mV_ Notel VOFFA 5 AOUT Offset Output -50 50 mV PCMIN=+0-Code Cpout 15 15 PCMOUT Capacitance 15.0 pF at 1 MHz Vbias=0V Voi 15 15 PCMOUT Low Voltage 04 VV Rir=5002 +lot = 0.8 mA Vou 15 15 PCMOUT High Vec-0.3 VY Ton =-150 mA Voltage Vin 10, 11, 8, 10, 11, Digital Input High 2.0 Vv 9,14 9, 12, 14 Voltage Vit 10,11 8, 10, 11, Digital Input Low 08 = =V 9,14 9, 12, 14 Voltage Note 1) Analog Input Amplifier Gain = 0 dB (Gal is connected to GA2) 446 HITACHI Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD44231P/HD44232P/HD44233P/HD44234P Dynamic-Characteristics (Vpp = 5 + 0.25 V, Vss = -5 + 0.25 V, Vcc = 5 0.25 V, Ta = 0 to +70C) Sym. Descriptions Min Typ Max Unit Note FS Synchronization Rate 8 kHz FC PCM Bit Clock Rate 1536/ kHz 1544/ 2048 twe Clock Pulse Width 200 ns twsH SYNC Pulse High Width 200 ns twsL SYNC Pulse Low Width 8 ps tr Logic Input Rise Time 5 50 ns tf Logic Input Fall Time 5 50 ns tBcs Previous Clock To SYNC Delay 40 ns Now | tes Clock To SYNC Delay 100s ns Note 1.3 ted Clock To PCM MSB Delay 170 ns Nowe 1.2, 4 tsd SYNC To PCM MSB Delay 170 ns Nowe 1. 2. 4 tcd Clock To PCMOUT Delay 180 _ns Note 1,2. 5 tsu PCMIN Setup Time 65 ns Note | thd PCMIN Hold Time 120 ns Note Notes 1) tr, tf of digital input or clock is assumed 5ns for timing measurement. 2) PCMOUT Load Condition: 500 Q + 165 pF + two LS-TTL Equivalent (Ii. = 0.8 mA, Iti = -150 pA) Threshold Level (Von = 2.4 V, VoL = 0.4 V) 3) Positive value shows SYNC delay from CLOCK. 4) tcdl, tsd are specified by CLOCK or SYNC which has slower rise time. 5) ted specification is valid for the data except MSB. System Related Characteristics (Von =5 + 0.25 V, Vss=-5+0.25 V, Vec=50,25 V, Ta=0 to +70C, Input Amplifier Gain = 0 dB, GA2 Load = 10 kQ, Aout Load = 600 Q, Synchronous operation. FC (PCM Bit Clock) = 2048 kHz) For HD44231P, HD44233P Sym Descriptions Test Conditions Min Typ Max Unit Note SDA Signal to Dist 820 Hz tone 45 dBm0 25 dB sop-wegt (A to A) 40 30 dB 30 to +3 35 dB SNA Signal to Dist Noise -55 dBm0 14 dB (A to A) 40 29 dB -34 34 dB -27 to -6 36 dB -3 28 dB SDX Signal to Dist 820 Hz tone 45 dBm0 26 dB sp-wgt (A to D) 40 31 dB 30 to +3 _ 36 dB SNX Signal to Dist Noise -55 dBm0 15 dB (A to D) ~40 30 dB -34 35 dB -27 to -6 37 dB SDR Signal to Dist 820 Hz tone ~45 dBm0 26 dB sp-wgt (D to A) 40 31 dB -30 to +3 36 dB HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 447HD44231P/HD44232P/HD44233P/HD44234P (con'd) Sym. Descriptions Test Conditions Min Typ Max = Unit SNR Signal to Dist Noise -55 dBm0 15 dB (D to A) -40 30 dB 34 35 dB 27 to -6 37 dB GTA Gain Track 820 Hz tone -55 to -50 ~1.0 1.0 dB (A to A) Relative to dBm0 ~-10 dBm0 ~50 to -40 -0.5 0.5 dB 40 to +3 0.3 0.3 GNA Gain Track Noise Relative 60 to -0.8 08 dB (A to A) to -10 dBm0 -55 dBm0 -55 to -10 0.4 0.4 dB GTX Gain Track 820 Hz tone 55 to -50 0.8 0.8 dB (A to D) Relative to 50 to -40 -0.4 0.4 dB 10 dBm0 -40 to 0.2 0.2 dB +3 dBm0 GNX Gain Track Noise 60 to 0.6 0.6 dB (A to D) Relative to -55 dBm0 -10 dBm0 ~55 to 40 0.4 0.4 dB 40 to -10 0.2 0.2 dB GTR Gain Track 820 Hz tone -55 to -50 0.8 0.8 dB (D to A) Relative to ~50 to -40 -0.4 0.4 dB -10 dBm0 40 to 0.2 0.2 dB +3 dBm0 GNR Gain Track Noise -60 to 0.4 0.4 dB (D to A) Relative to -55 dBm0 10 dBm0 -55 to -10 ~0.2 0.2 dB FRX Freq.Response Relative to 0.06 kHz 24 dB (A to D) 820 Hz 0.2 0 2.0 (Loss) 0dBm0 0.3 to 3 0.15 0.15 3.18 0.15 0.65 3.4 0 0.8 3.78 6.5 FRR Freq. Response _ Relative 0 to 3 kHz 0.15 0.15 dB (D to A) to 820 Hz 3.18 0.15 0.65 (Loss) 0dBm0 3.4 0 0.8 3.78 6.5 AIL Analog Input 820 Hz 25C 1.217 1.231. 1.246 =Vrms Level 0dBm0 nom.P.S. AOL Analog Output 820 Hz 25C 1.217 1.231 1.246 Vrms Level 0dBmO nom. P.S. ICNA Idle Ch. Noise AtoA AIN = AGND -78 dBmOP ICNX Idle Ch. Noise AtoD AIN = AGND -80 dBmOP ICNR Idle Ch. Noise DtoA PCMIN = -81 dBmOP +0-CODE XTKA AIN to AOUT 820 Hz 0 dBm0 -65 dB Crosstalk XTKD PCMIN to 820 Hz 0 dBm0 -65 dB PCMOUT HITACHI 448 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300HD44231P/HD44232P/HD44233P/HD44234P For HD44232P, HD44234P Sym. Descriptions Test Conditions Min Typ Max Unit Note SDA Signal to Dist 1020 Hz tone 45 dBm0 25 dB sc-wegt (A to A) 40 30 dB -30 to +3 35 dB SDX Signal to Dist 1020Hz tone 45 dBm0 26 dB sc-wgt (A to D) 40 31 dB -30 to +3 36 dB SDR Signal to Dist 1020 Hz tone 45 dBm0 26 dB c-wegt (D to A) ~40 31 dB -30 to +3 36 dB GTA Gain Tracking 1020 Hz tone -55 to -50 dBm0 ~1.0 1.0 dB (A to A) Relative to -50 to -40 -0.5 0.5 dB -10 dBm0 40 to +3 -0.3 0.3 dB GTX Gain Tracking 1020 Hz tone ~55 to -50 0.8 0.8 dB (A to D) Relative to -50 to 40 -0.4 0.4 dB -10 dBm0 -40 to +3 dBm0 -0.2 0.2 dB GTR Gain Tracking 1020 Hz tone -55 to -50 -0.8 0.8 dB (Dto A) Relative to -50 to -40 -0.4 0.4 dB -10 dBmO -40 to +3 dBm0_ -0.2 0.2 dB FRX Freq.Response Relative to 0.06 kHz 24 (A to D)(Loss) 1020 Hz 0.2 0 2.0 0 dBm0 0.3 to 3 0.15 0.15 3.18 0.15 065 3.4 0 0.8 3.78 6.5 FRR Freq.Response Relative to 1020Hz 0Oto3kHz 0.15 0.15 (D to A) (Loss) 0 dBm0 3.18 -0.15 0.65 4B 3.4 0 0.8 3.78 6.5 AIL Analog Input 1020 Hz 25C nom. P.S, 1.213. 1.227 1.241 Vrms Level 0 dBm0 AOL Analog Output 1020 Hz 25C nom. P.S. 1.213. 1.227 1.241 Vrms Level 0dBm0 ICNA Idle Ch. Noise AtoA AIN = AGND 15 dBmCO ICNX Idle Ch. Noise AtoD AIN = AGND 15 dBmCO ICNR Idle Ch. Noise DtoA PCMIN = 9 dBmCO a +0Code XTKA AIN to AOUT 1020Hz 0 dBm0 -65 dB Crosstalk XTKD PCMIN to 1020 Hz 0 dBm0 -65 dB PCMOUT HITACHI Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 449HD44231P/HD44232P/HD44233P/HD44234P For HD44231P, HD44232P, HD44233P, HD44234P Sym. Descriptions Test Conditions Min Typ Max _Unit__Note AT AIL, AOL Variation _ Relative to 25C +20 ppm/C with temp. nominal P.S. AP AIL,AOL Variation 25C, 0.01 dB with P.S. Supplies + 5% ALS Gain Variation over AtoD Initial 0.2 0.2 dB Note 1) Temp. P.S. DtoA AIP Peak Analog Input 3.0 Vv AOP __ Peak Analog Output 2.5 Vv PDL __ Propagation Delay AtoA 0dBmO 450 480 ps DD Delay Distortion AtoA 0.5 to 1.4 0dBmO 0.6 kHz 0.6 to 1.0 0.7 ms rel. to min. 1.0 to 2.6 0.2 delay 2.6 to 2.8 1.4 PSRR PSRR AtoA Vopp Mod. = 30 dB AIN = +5 V + 100 mVop AGND Vss Mod. = 0.3- -5V+100mVop 30 50 kHz IM? Intermodulation A to A(2a-b) a; 0.47 kHz, -4 dBmO -38 dB b; 0.32, 4 IM2 Intermodulation A to A(a-b) a; 1.02 kHz, -4 dBmO 52 dB b; 0.05, -23 Ics Single Freq.Noise AtoA 8,16,24, AIN = 32,40 kHz -50 dBmO AGND DIS Discrimination AtoA 4.6 to 0dBmO 200 kHz 30 dB Note 450 1) Total variation of GAIN including the initial fluctuation temperature variation and power supply dependence (0 to 70C, Vop/Vss = + 5 V + 5%) HITACHI Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300For HD44231P, HD44232P HD44231P/HD44232P/HD44233P/HD44234P Timing Chart t tweet twsi - H 2.0" {4 OY --------;P---d4------------- 4h --------lf- SYNC 08 --------F- jroo hb ----------- Henna eee --- { | aiheiieetaed Ll tee te te ete ed pe ba t ot ti ' 20 - mc cife nn n-\eree re -- CLOCK ' 08 --);--- cryin ' tecs I tt ( | iy 11 ~-( od l ts 1 ! ti \ 1d i t 2 PCMOUT PCMIN For HD44233P, HD44234P Timing Chart XSYNC XCLOCK RSYNC PCMIN HITACHI Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 * (415) 589-8300 451