1 GSPS
Direct Digital Synthesizer
AD9858
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
FEATURES
1 GSPS internal clock speed
Up to 2 GHz input clock (selectable divide-by-2)
Integrated 10-bit D/A converter
Phase noise < 145 dBc/Hz @ 1 kHz offset
Output frequency = 100 MHz (DAC output)
32-bit programmable frequency register
Simplified 8-bit parallel and SPI® serial control interface
Automatic frequency sweeping capability
4 frequency profiles
3.3 V power supply
Power dissipation 2 W typical
Integrated programmable charge pump and phase
frequency detector with fast lock circuit
Isolated charge pump supply up to 5 V
Integrated 2 GHz mixer
APPLICATIONS
VHF/UHF LO synthesis
Tuners
Instrumentation
Agile clock synthesis
Cellular base station hopping synthesizer
Radar
Sonet/SDH clock synthesis
GENERAL DESCRIPTION
The AD9858 is a direct digital synthesizer (DDS) featuring a
10-bit DAC operating up to 1GSPS. The AD9858 uses advanced
DDS technology, coupled with an internal high speed, high
performance D/A converter to form a digitally programmable,
complete high frequency synthesizer capable of generating a
frequency-agile analog output sine wave at up to 400+ MHz.
The AD9858 is designed to provide fast frequency hopping and
fine tuning resolution (32-bit frequency tuning word). The
frequency tuning and control words are loaded into the AD9858
via parallel (8-bit) or serial loading formats. The AD9858
contains an integrated charge pump (CP) and phase frequency
detector (PFD) for synthesis applications requiring the
combination of a high speed DDS along with phase-locked loop
(PLL) functions. An analog mixer is also provided on-chip for
applications requiring the combination of a DDS, PLL, and
mixer, such as frequency translation loops, tuners, and so on.
The AD9858 also features a divide-by-2 on the clock input,
allowing the external clock to be as high as 2 GHz.
The AD9858 is specified to operate over the extended industrial
temperature range of –40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
ANALOG
MULTIPLIER
PHASE
ACCUMULATOR
DIV
LO IF RF
PD
CP
CPISET
RESET
DACISET
I
OUT
I
OUT
FUD
SYNCLK
REFCLK
REFCLK
PROFILE
SELECT I/O PORT
(SER/PAR)
DIGITAL PLL
DELTA
FREQUENCY
WORD
DELTA
FREQUENCY
RAMP RATE
FREQUENCY
ACCUMULATOR
RESET
FREQUENCY
TUNING
WORD
PHASE
ACCUMULATOR
RESET
SYNC
PHASE
OFFSET
ADJUST
DAC
DAC CLOCK
CHARGE
PUMP
POWER-
DOWN
LOGIC
PHASE
DETECTOR
TIMING AND CONTROL LOGIC
PHASE-TO-
AMPLITUDE
CONVERSION
÷ M
÷ 8
÷ 2
CONTROL REGISTERS
÷ N
AD9858
15
FREQUENCY
ACCUMULATOR
32
32
14
32
15 10
M
U
X
03166-A-001
Figure 1.
AD9858
Rev. A | Page 2 of 32
TABLE OF CONTENTS
Features .......................................................................................... 1
Applications................................................................................... 1
General Description..................................................................... 1
Functional Block Diagram .......................................................... 1
AD9858—Electrical Specifications ................................................ 3
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration............................................................................. 7
Pin Function Descriptions .............................................................. 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 15
Overview ..................................................................................... 15
Component Blocks..................................................................... 15
Modes of Operation................................................................... 17
Synchronization.......................................................................... 19
Programming the AD9858........................................................ 21
AD9858 Application Suggestions............................................. 29
Evaluation Boards ...................................................................... 30
Outline Dimensions....................................................................... 31
Warning ....................................................................................... 31
Ordering Guide .......................................................................... 31
REVISION HISTORY
11/03—Data Sheet Changed from a REV. 0 to a REV. A
Changes to SPECIFICATIONS........................................................ 5
Moved ESD Caution to ..................................................................... 6
Moved Pin Configuration to............................................................ 7
Moved Pin Function Description to ............................................... 8
Changes to Equations........................................................................ 19
Changes to Delta Frequency Ramp Rate Word (DFRRW) .......... 27
AD9858
Rev. A | Page 3 of 32
AD9858—ELECTRICAL SPECIFICATIONS
Table 1. Unless otherwise noted, VDD = 3.3 V ± 5%, CPVDD = 5 V ± 5%, RSET = 2 kΩ, CPISET = 2.4 kΩ,
Reference Clock Frequency = 1 GHz.
Parameter Temp Test Level Min Typ Max Unit
REF CLOCK INPUT CHARACTERISTICS1, 2
Reference Clock Frequency Range (Divider Off) Full VI 10 1000 MHz
Reference Clock Frequency Range (Divider On) Full VI 20 2000 MHz
Duty Cycle @ 1 GHz 25°C V 42 50 58 %
Input Capacitance 25°C V 3 pF
Input Impedance 25°C IV 1500 Ω
Input Sensitivity Full VI –20 +5 dBm
DAC OUTPUT CHARACTERISTICS
Resolution Full 10 Bits
Full-Scale Output Current Full 5 20 40 mA
Gain Error Full VI –10 +10 % FS
Output Offset Full VI 15 µA
Differential Nonlinearity Full VI 0.5 1 LSB
Integral Nonlinearity Full VI 1 1.5 LSB
Output Impedance Full VI 100 kΩ
Voltage Compliance Range Full VI AVDD – 1.5 AVDD + 0.5 V
Wideband SFDR (DC to Nyquist)
40 MHz FOUT Full V 60 dBc
100 MHz FOUT Full V 54 dBc
180 MHz FOUT Full V 53 dBc
360 MHz FOUT Full V 50 dBc
180 MHz FOUT (700 MHz REFCLK) Full IV 52 dBc
Narrow-Band SFDR33
40 MHz FOUT (±15 MHz) Full V 82 dBc
40 MHz FOUT (±1 MHz) Full V 87 dBc
40 MHz FOUT (±50 kHz) Full V 88 dBc
100 MHz FOUT (±15 MHz) Full V 81 dBc
100 MHz FOUT (±1 MHz) Full V 82 dBc
100 MHz FOUT (±50 kHz) Full V 86 dBc
180 MHz FOUT (±15 MHz) Full V 74 dBc
180 MHz FOUT (±1 MHz) Full V 84 dBc
180 MHz FOUT (±50 kHz) Full V 85 dBc
360 MHz FOUT (±15 MHz) Full V 75 dBc
360 MHz FOUT (±1 MHz) Full V 85 dBc
360 MHz FOUT (±50 kHz) Full V 86 dBc
180 MHz FOUT (±15 MHz) (700 MHz REFCLK) Full V 65 dBc
180 MHz FOUT (±1 MHz) (700 MHz REFCLK) Full V 80 dBc
180 MHz FOUT (±50 kHz) (700 MHz REFCLK) Full V 84 dBc
OUTPUT PHASE NOISE CHARACTERISTICS (@ 103 MHz IOUT)
@ 1 kHz Offset Full V –147 dBc/Hz
@ 10 kHz Offset Full V –150 dBc/Hz
@ 100 kHz Offset Full V –152 dBc/Hz
OUTPUT PHASE NOISE CHARACTERISTICS (@ 403 MHz IOUT)
@ 1 kHz Offset Full V –133 dBc/Hz
@ 10 kHz Offset Full V –137 dBc/Hz
@ 100 kHz Offset Full V –140 dBc/Hz
AD9858
Rev. A | Page 4 of 32
Parameter Temp Test
Level
Min Typ Max Unit
OUTPUT PHASE NOISE CHARACTERISTICS (@ 100 MHz IOUT
with 700 MHz REFCLK)
@ 100 Hz Offset Full V –125 dBc/Hz
@ 1 kHz Offset Full V –140 dBc/Hz
@ 10 kHz Offset Full V –148 dBc/Hz
@ 100 kHz Offset Full V –150 dBc/Hz
@ 1 MHz Offset Full V –150 dBc/Hz
@ 10 MHz Offset Full V –150 dBc/Hz
PHASE DETECTOR AND CHARGE PUMP
Phase Detector Frequency Full VI 150 MHz
Phase Detector Frequency (Divide-by-4 Enabled)4 Full VI 400 MHz
Charge Pump Sink and Source Current5 Full VI 4 mA
Fast Lock Current (Acquisition Only) Full VI 7 mA
Open-Loop Current (Acquisition Only) Full VI 30 mA
Sink and Source Current Absolute Accuracy6 Full V 2.5 %
Sink and Source Current Matching6 Full V 1 %
Input Sensitivity PDIN and DIVIN (50 Ω)7 Full IV –15 0 dBm
Input Impedence PDIN and DIVIN (Single-Ended) Full V 1 kΩ
Phase Noise @ 100 MHz Input Frequency
@ 10 kHz Offset Full V 110 dBc/Hz
@ 100 kHz Offset Full V 140 dBc/Hz
@ 1 MHz Offset Full V 148 dBc/Hz
Charge Pump Output Range8 Full V CPVDD V
MIXER
IFOUT9 Full V 400 MHz
FRF Full VI 2 GHz
FLO Full VI 2 GHz
Conversion Gain Full VI 0.0 3.5 dB
LO Level Full VI –10 +5 dBm
RF Level Full VI –20 dBm
Input IP3 Full VI 5 9 dBm
1 dB Input Compression Power10 Full VI –3 dBm
Input Impedance (Single-Ended)
LO Full V 1 kΩ
RF Full V 1 kΩ
LOGIC INPUTS
Logic 1 Voltage Full VI 2.0 V
Logic 0 Voltage Full VI 0.8 V
Logic 1 Current Full VI 12 µA
Logic 0 Current Full VI 12 µA
Input Capacitance Full V 3 pF
POWER SUPPLY
PDISS (Worst-Case Conditions—Everything on
PFD Input Frequency 150 MHz)
Full VI 2 2.5 W
PDISS (DAC and DDS Core Only Worst-Case) Full VI 1.7 2 W
PDISS (Power-Down Mode) Full VI 65 100 mW
PDISS Mixer Only Full VI 60 75 mW
PDISS PFD and CP (@ 100 MHz) Only Full VI 350 435 mW
AD9858
Rev. A | Page 5 of 32
Parameter Temp Test
Level
Min Typ Max Unit
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency Full IV 10 MHz
Minimum Clock Pulse Width Low (tPWL) Full IV 5.5 ns
Minimum Clock Pulse Width High (tPWH) Full IV 15 ns
Maximum Clock Rise/Fall Time Full IV 1 ms
Minimum Data Setup Time (tDS) Full IV 7 ns
Mimimum Data Hold Time (tDH) Full IV 0 ns
Maximum Data Valid Time (tDV) Full IV 20 ns
Parallel Control Bus
WR Minimum Low Time Full IV 3 ns
WR Minimum High Time Full IV 6 ns
WR Minimum Period Full IV 9 ns
Address to WR Setup (TASU) Full IV 3 ns
Address to WR Setup (TAHU) Full IV 0 ns
Data to WR Setup (TDSU) Full IV 3.5 ns
Data to WR Hold (TDHU) Full IV 0 ns
Miscellaneous Timing Specifications
REFCLK to SYNCLK Full V 2.5 ns
FUD to SYNCLK Setup Time Full IV 4 ns
FUD to SYNCLK Hold Time Full IV 0 ns
REFCLK to SYNCLK Delay Full IV 2.5 3 ns
FUD Rising Edge to Frequency Change
Single Tone Mode 25°C IV 83 sysclk
cycles
Linear Sweep Mode 25°C IV 99 sysclk
cycles
FUD Rising Edge to Phase Offset Change 25°C IV 83 sysclk
cycles
1 The reference clock input is configured to accept a differential or single-ended sine wave input or a 3 V CMOS-level pulse input.
2 REFCLK input is internally dc biased. AC coupling should be used.
3 Reference clock frequency is selected to ensure second harmonic is out of the bandwidth of interest.
4 PD inputs sent @ 400 MHz, with divide-by-4 enabled.
5 The charge pump current is programmable in eight discrete steps, minimum value assumes current sharing.
6 For 0.75 V < VCP < CPVDD – 0.75 V.
7 These differential inputs are internally dc biased. AC coupling should be used.
8 The charge pump supply voltage can range from 4.75 V to 5.25 V.
9 Output interface is differential open collector.
10 For 1 dB output compression; input power measured at 50 Ω.
AD9858
Rev. A | Page 6 of 32
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
AVDD 4 V
DVDD 4 V
CPVDD 6 V
Digital Input Voltage –0.7 V to +VDD
Digital Output Current 5 mA
Storage Temperature –65°C to +150°C
Operating Temperature –40°C to +85°C
θJA EPAD Soldered 25°C/W
Absolute Maximum Ratings are limiting values, to be applied
individually, and beyond which the serviceability of the circuit
may be impaired. Functional operability under any of these
conditions is not necessarily implied. Exposure of absolute
maximum rating conditions for extended periods of time may
affect device reliability.
Table 3. Explanation of Test Levels
I 100% Production Tested.
III Sample Tested Only.
IV Parameter is guaranteed by design and characterization
testing.
V Parameter is a typical value only.
VI Devices are 100% production tested at 25°C and
guaranteed by design and characterization testing for
industrial operating temperature range.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD9858
Rev. A | Page 7 of 32
PIN CONFIGURATION
84 83 82 81 80 79 78 77 76
95 94 93 92 91 90 89 88 87 86 85
10099989796
26 28 29 30 31 32 33 38 39
34 35 36 37 42
40 41 43 44 45 46 47 48 49 50
13
DVDD
D7
D6
D5
D4
DGND
DGND
DVDD
DVDD
D3
D2
D1
D0
ADDR5
ADDR4
ADDR3
RD/CS
DVDD
DVDD
DGND
DVDD
DVDD
AGND
AGND
AVDD
REFCLK
AVDD
REFCLK
AVDD
AVDD
AGND
AGND
AVDD
AGND
AGND
AGND
AVDD
AVDD
LO
LO
AVDD
AGND
AVDD
AGND
PS1
SYNCLK
FUD
PS0
DGND
DGND
RESET
DVDD
DVDD
AVDD
SPSELEC
T
AGND
AVDD
AVDD
AGND
IOUT
AGND
IOUT
IOUT
AGND
IOUT
DACISET
AVDD
DACBP
NC
A
DDR2/IORESE
T
ADDR1/SDO
ADDR0/SDIO
WR/SCLK
DVDD
DGND
AVDD
NC
AGND
AVDD
DIV
DIV
AVDD
AGND
CPGND
CPVDD
CP
CP
CPFL
CPGND
CPVDD
CPISET
RF
RF
AGND
NC
NC
PFD
PFD
IF
IF
AD9858
TOP VIEW
(Not to Scale)
NC = NO CONNECT
27
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
031
66-A-044
Figure 2. 100-Lead EPAD (SV-100) Pin Configuration
AD9858
Rev. A | Page 8 of 32
PIN FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions—100-Lead EPAD (SV-100)
Pin No. Mnemonic I/O Description
1 to 4, 9 to 12 D7 to D0 I Parallel Port DATA. Note that the functionality of these pins is valid only when the I/O port is
configured as a parallel port.
5, 6, 21, 28, 95, 96 DGND Digitial Ground.
7, 8, 20,
23 to 27, 93, 94
DVDD Digital Supply Voltage.
13 to 18 ADDR5 to
ADDR0
I When the I/O port is configured as a parallel port, these pins serve as a 6-bit address select
for accessing the on-chip registers (see the IORESET, SDO, and SDIO pins below for serial
port mode).
16 IORESET I
Note that this is valid only for serial programming mode. Active high input signal that resets the
serial I/O bus controller. It is intended to serve as a means of recovering from an unresponsive
serial bus caused by improper programming protocol. Asserting an I/O reset does not affect the
contents of previously programmed registers nor does it invoke their default values.
17 SDO O
Note that this is valid only for serial programming mode. When operating the I/O port as a
3-wire serial port, this pin serves as a unidirectional serial data output pin. When operated as a
2-wire serial port, this pin is unused.
18 SDIO
I or
I/O
Note that this is valid only for serial programming mode. When operating the I/O port as a
3-wire serial port, this pin is the serial data input. When operated as a 2-wire serial port, this pin
is the bidirectional serial data pin.
19 WR/SCLK I When the I/O port is configured for parallel programming mode, this pin functions as an active
low write pulse (WR). When configured for serial programming mode, this pin functions as the
serial data clock (SCLK).
22 RD/CS I When the I/O port is configured for parallel programming mode, this pin functions as an active
low read pulse (RD). When configured for serial programming mode, this pin functions as an
active low chip select (CS) that allows multiple devices to share the serial bus.
29, 30, 37 to 39,
41, 42, 49, 50,
52, 69, 74, 80, 85,
87, 88
AGND I Analog Ground.
31, 32, 35, 36,
40, 43, 44, 47,
48, 51, 70, 73,
77, 86, 89, 90
AVDD I Analog Supply Voltage.
33 REFCLK I Reference Clock Complementary Input. (Note that when the REFCLK port is operated in single-
ended mode, REFCLK should be decoupled to AVDD with a 0.1 µF capacitor.
34 REFCLK I Reference Clock Input.
45 LO I Mixer Local Oscillator (LO) Complementary Input. Note that when the LO port is operated in
single-ended mode, LO should be decoupled to AVDD with a 0.1 µF capacitor.
46 LO I Mixer Local Oscillator (LO) Input.
53 RF I Analog Mixer RF Complementary Input. Note that when the RF port is operated in single-ended
mode, RF should be decoupled to AVDD with a 0.1 µF capacitor.
54 RF I Analog Mixer RF Input.
55 IF O Analog Mixer IF Output.
56 IF O Analog Mixer IF Complementary Output.
57 PFD I Phase Frequency Detector Complementary Input . Note that when the PFD port is operated in
single-ended mode, PFD should be decoupled to AVDD with a 0.1 µF capacitor.
58 PFD I Phase Frequency Detector Input.
59, 60, 75, 76 NC No Connection.
61 CPISET I
Charge Pump Output Current Control. A resistor connected from CPISET to CPGND establishes
the reference current for the charge pump.
62, 67 CPVDD I Charge Pump Supply Voltage.
63, 68 CPGND I Charge Pump Ground.
64 CPFL O Charge Pump Fast Lock Output.
65, 66 CP O Charge Pump Output.
AD9858
Rev. A | Page 9 of 32
Pin No. Mnemonic I/O Description
71 DIV I Phase Frequency Detector Feedback Input.
72 DIV I Phase Frequency Detector Feedback Complementary Input. Note that when the DIV port is
operated in single-ended mode, DIV should be decoupled to AVDD with a 0.1 µF capacitor.
78 DACBP DAC Baseline Decoupling Pin, Typically Bypassed to Pin 77 with a 0.1 µF Capacitor.
79 DACISET I A Resistor Connected from DACISET to AGND Establishes the Reference Current for the DAC.
81, 82 IOUT O DAC Output.
83, 84 IOUT O DAC Complementary Output.
91 SPSELECT I
I/O Port Serial/Parallel Programming Mode Select Pin. Logic 0: serial programming mode.
Logic 1: parallel programming mode.
92 RESET I
Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9858 to its default
operating conditions.
97, 98 PS0, PS1 I Used to Select One of the Four Internal Profiles. These pins are synchronous to the
SYNCLK output.
99 FUD I
Frequency Update. The rising edge transfers the contents of the internal buffer registers to the
memory registers. This pin is synchronous to the SYNCLK output.
100 SYNCLK O Clock Output Pin that Serves as a Synchronizer for External Hardware. SYNCLK runs at REFCLK/8.
AD9858
Rev. A | Page 10 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–
100 START 0Hz 50MHz/ STOP 500MHz
5kHz
5kHz
50s
RF ATT
UNIT
20dB
dB
A
1AP
REF LVL
5dBm
RBW
VBW
SWT
MARKER 1 [T1]
1.04dBm
26.05210421MHz
03166-A-002
1
Figure 3. Wideband SFDR, 26 MHz FOUT
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–
100 START 0Hz 50MHz/ STOP 500MHz
5kHz
5kHz
50s
RF ATT
UNIT
20dB
dB
A
1AP
REF LVL
5dBm
RBW
VBW
SWT
MARKER 1 [T1]
1.72dBm
65.13026052MHz
03166-A-003
1
Figure 4. Wideband SFDR, 65 MHz FOUT
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–
100 START 0Hz 50MHz/ STOP 500MHz
5kHz
5kHz
50s
RF ATT
UNIT
20dB
dB
A
1AP
REF LVL
5dBm
RBW
VBW
SWT
MARKER 1 [T1]
1.39dBm
126.25250501MHz
03166-A-004
1
Figure 5. Wideband SFDR, 126 MHz FOUT
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–
100 CENTER 26.1MHz 50kHz/ SPAN 500kHz
200Hz
200Hz
64s
RF ATT
UNIT
20dB
dB
A
1AP
REF LVL
5dBm
RBW
VBW
SWT
MARKER 1 [T1]
1.73dBm
26.10050100MHz
03166-A-006
1
Figure 6. Narrow-Band SFDR, 26 MHz FOUT, 1 MHz BW
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–
100 CENTER 65.1MHz 200kHz/ SPAN 2MHz
500Hz
500Hz
40s
RF ATT
UNIT
20dB
dB
A
1AP
REF LVL
5dBm
RBW
VBW
SWT
MARKER 1 [T1]
1.58dBm
65.10200401MHz
03166-A-007
1
Figure 7. Narrow-Band SFDR, 65 MHz FOUT, 1 MHz BW
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–
100 CENTER 126.1MHz 200kHz/ SPAN 2MHz
500Hz
500Hz
40s
RF ATT
UNIT
20dB
dB
A
1AP
REF LVL
5dBm
RBW
VBW
SWT
MARKER 1 [T1]
1.27dBm
126.10200401MHz
03166-A-008
1
Figure 8. Narrow-Band SFDR, 126 MHz FOUT, 1 MHz BW
AD9858
Rev. A | Page 11 of 32
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–
100 START 0Hz 50MHz/ STOP 500MHz
5kHz
5kHz
50s
RF ATT
UNIT
20dB
dB
A
1AP
REF LVL
5dBm
RBW
VBW
SWT
MARKER 1 [T1]
–1.25dBm
375.75150301MHz
03166-A-005
1
Figure 9. Wideband SFDR, 375 MHz FOUT
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–
100 CENTER 216.1MHz 100kHz/ SPAN 1MHz
300Hz
300Hz
56s
RF ATT
UNIT
20dB
dB
A
1AP
REF LVL
5dBm
RBW
VBW
SWT
03166-A-010
Figure 10. Narrow-Band SFDR, 201 MHz FOUT,
1 MHz BW, 1 GHz Clock, Divider Off
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–
100 CENTER 216.1MHz 100kHz/ SPAN 1MHz
300Hz
300Hz
56s
RF ATT
UNIT
20dB
dB
A
1AP
REF LVL
5dBm
RBW
VBW
SWT
03166-A-012
Figure 11. Narrow-Band SFDR, 201 MHz FOUT,
1 MHz BW, 2 GHz Clock, Divider On
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–
100 CENTER 375.1MHz 500kHz/ SPAN 5MHz
500Hz
500Hz
100s
RF ATT
UNIT
20dB
dB
A
1AP
REF LVL
5dBm
RBW
VBW
SWT
MARKER 1 [T1]
–1.35dBm
375.10501002MHz
03166-A-009
1
Figure 12. Narrow-Band SFDR, 375 MHz FOUT, 1 MHz BW
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–
100 START 0Hz 50MHz/ STOP 500MHz
5kHz
5kHz
50s
RF ATT
UNIT
20dB
dB
A
1AP
REF LVL
5dBm
RBW
VBW
SWT
MARKER 1 [T1]
1.12dBm
216.43286573MHz
03166-A-011
1
Figure 13. Wideband SFDR, 201 MHz FOUT, 1GHz Clock, Divider Off
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–
100 START 0Hz 50MHz/ STOP 500MHz
5kHz
5kHz
50s
RF ATT
UNIT
20dB
dB
A
1AP
REF LVL
5dBm
RBW
VBW
SWT
MARKER 1 [T1]
1.12dBm
216.43286573MHz
03166-A-013
1
Figure 14. Wideband SFDR, 201 MHz FOUT, 2 GHz Clock, Divider On
AD9858
Rev. A | Page 12 of 32
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–170
–100
–110
–120
–130
–140
–150
–160
10 10M1M100K10K
FREQUENCY (Hz)
PHASE NOISE, L(f) (dBc/Hz)
1K100
03166-A-014
Figure 15. Residual Phase Noise, 103 MHz FOUT, 1 GHz REFCLK
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–170
–100
–110
–120
–130
–140
–150
–160
10 10M 100M1M100K10K1K100
03166-A-016
FREQUENCY (Hz)
PHASE NOISE, L(f) (dBc /Hz)
Figure 16. Fractional Divider Loop Residual Phase Noise,
FIN = 115 MHz, FOUT = 1550 MHz, Loop BW = 50 kHz
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–
100 CENTER 1.55GHz 150kHz/ SPAN 1.55MHz
1kHz
1kHz
3.8s
RF ATT
UNIT
10dB
dBm
A
1AP
REF LVL
0dBm
RBW
VBW
SWT
DELTA 1 [T1] 0.0dB
0.00000000Hz
03166-A-018
1
Figure 17. Fractional Divider Loop SFDR, FIN = 96.9 MHz,
FOUT = 1550 MHz, BW = 1.5 MHz
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–170
–100
–110
–120
–130
–140
–150
–160
10 10M1M100K10K1K100
03166-A-015
FREQUENCY (Hz)
PHASE NOISE, L(f) (dBc/Hz)
Figure 18. Residual Phase Noise, 403 MHz FOUT, 1 GHz REFCLK
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–170
–100
–110
–120
–130
–140
–150
–160
10 10M 100M1M100K10K1K100
03166-A-019
FREQUENCY (Hz)
PHASE NOISE, L(f) (dBc /Hz)
Figure 19. Translation Loop Residual Phase Noise
FLO = 1500 MHz, FOUT = 1550 MHz, Loop BW = 50 kHz
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–
100 CENTER 1.55GHz 150kHz/ SPAN 1.5MHz
2kHz
2kHz
940s
RF ATT
UNIT
10dB
dBm
A
1AP
REF LVL
0dBm
RBW
VBW
SWT
DELTA 1 [T1]
–56.76dB
423.84769539kHz
03166-A-021
1
1
Figure 20. Fractional Divider Loop SFDR, FIN = 97.3 MHz,
FOUT = 1550 MHz, BW = 1.5 MHz
AD9858
Rev. A | Page 13 of 32
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–
100 CENTER 1.55GHz 15MHz/ SPAN 150MHz
5kHz
5kHz
15s
RF ATT
UNIT
10dB
dBm
A
1AP
∗
REF LVL
0dBm
RBW
VBW
SWT
DELTA 1 [T1] 0.0dB
0.00000000Hz
03166-A-017
1
Figure 21. Fractional Divider Loop SFDR, FIN = 96.9 MHz,
FOUT = 1550 MHz, BW = 150 MHz
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–
100 CENTER 1.55GHz 150kHz/ SPAN 1.5MHz
1kHz
500kHz
7.6s
RF ATT
UNIT
10dB
dBm
A
1AP
REF LVL
0dBm
RBW
VBW
SWT
DELTA 1 [T1]
–81.10dB
57.11422845kHz
03166-A-022
1
Figure 22. Translation Loop SFDR, FLO = 1459 MHz,
FOUT = 1550 MHz, BW = 1.5 MHz
∗
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–
100 CENTER 1.55GHz 15MHz/ SPAN 150MHz
10kHz
500Hz
75s
RF ATT
UNIT
10dB
dBm
A
1AP
REF LVL
0dBm
RBW
VBW
SWT
DELTA 1 [T1]
–96.36dB
–42.98597194MHz
03166-A-023
1
1
Figure 23. Translation Loop SFDR, FLO = 1459 MHz,
FOUT = 1550 MHz, BW = 150 MHz
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–
100 CENTER 1.55GHz 15MHz/ SPAN 150MHz
5kHz
5kHz
15s
RF ATT
UNIT
10dB
dBm
A
1AP
REF LVL
0dBm
RBW
VBW
SWT
DELTA 1 [T1]
–64.55dB
–1.20240481MHz
03166-A-020
1
1
Figure 24. Fractional Divider Loop SFDR, FIN = 97.3 MHz,
FOUT = 1550 MHz, BW = 150 MHz
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–
100 CENTER 1.55GHz 150kHz/ SPAN 1.5MHz
1kHz
500Hz
7.6s
RF ATT
UNIT
10dB
dBm
A
1AP
REF LVL
0dBm
RBW
VBW
SWT
DELTA 1 [T1]
–60.67dB
–57.11422846kHz
03166-A-045
1
1
Figure 25. Translation Loop SFDR, FLO = 1410 MHz,
FOUT = 1550 MHz, BW = 1.5 MHz
–10
0
–20
–30
–40
–50
–60
–70
–80
–90
–
100 CENTER 1.55GHz 15MHz/ SPAN 150MHz
5kHz
5kHz
15s
RF ATT
UNIT
10dB
dBm
A
1AP
REF LVL
0dBm
RBW
VBW
SWT
DELTA 1 [T1]
–64.55dB
–1.20240481MHz
03166-A-046
1
1
Figure 26. Translation Loop SFDR, FLO = 1410 MHz,
FOUT = 1550 MHz, BW = 150 MHz
AD9858
Rev. A | Page 14 of 32
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
00 900675450225 1125
03166-A-025
REF CLOCK (MHz)
POWER DRAWN (W)
Figure 27. Supply Current vs. REFCLK (FOUT = REFCLK/5)
600
3.1V
3.3V 3.5V
500
300
400
200
100
00 70 140 210 280 350 420
03166-A-024
F
OUT
(MHz)
SUPPLY CURRENT (mA)
Figure 28. Supply Current vs. FOUT (1 GHz REFCLK)
AD9858
Rev. A | Page 15 of 32
THEORY OF OPERATION
OVERVIEW
The AD9858 direct digital synthesizer (DDS) is a flexible device
that can address a wide range of applications. The device
consists of an NCO with a 32-bit phase accumulator, 14-bit
phase offset adjustment, a power efficient DDS core, and a one
giga-samples per second (1 GSPS) 10-bit digital-to-analog
converter. The AD9858 incorporates additional capabilities for
automated frequency sweeping. The device also offers an analog
mixer capable of operating at 2 GHz, a phase-frequency
detector (PFD), and a programmable charge pump (CP) with
advanced fast-lock capability. These RF building blocks can be
used for various frequency synthesis loops or as needed in
system design.
The AD9858 can directly generate frequencies up to 400+ MHz
when driven at a 1 GHz internal clock speed. This clock can be
derived from an external clock source of up to 2 GHz by using
the on-chip divide-by-2 feature. The on-chip mixer and
PFD/CP make possible a variety of synthesizer configurations
capable of generating frequencies in the 1 GHz to 2 GHz range
or higher.
The AD9858 offers the advantages of a DDS with the additional
flexibility to work in concert with analog frequency synthesis
techniques (PLL, mixing) to generate precision frequency
signals with high frequency resolution, fast frequency hopping,
fast settling time, and automated frequency sweeping
capabilities.
Writing data to its on-chip digital registers that control all
operations of the device easily configures the AD9858. The
AD9858 offers a choice of both serial and parallel ports for
controlling the device. Four user profiles can be selected by a
pair of external pins. These profiles allow independent setting
of the frequency tuning word and the phase offset adjustment
word for each of four selectable configurations.
The AD9858 can be programmed to operate in single-tone
mode or in frequency-sweeping mode. To save on power
consumption, there is also a programmable full-sleep mode,
during which most of the device is powered down to reduce
current flow.
The operation of a DDS is described in detail in a tutorial
available from Analog Devices at www.analog.com/dds.
COMPONENT BLOCKS
DDS Core
The DDS core generates the numeric values that represent a
sinusoid in the digital domain. Depending on the operating
mode of the DDS, this sinusoid may be changed in frequency,
phase, or perhaps modulated by an information carrying signal.
The frequency of the output signal is determined by a user-
programmed frequency tuning word (FTW). The relation of the
output frequency of the device to the system clock (SYSCLK) is
determined by the following equation:
()
N
O
SYSCLKFTW
F2
×
=
where for the AD9858, N = 32.
For a more detailed explanation of a DDS core, consult the DDS
tutorial at www.analog.com/dds.
DAC Output
The AD9858 incorporates an integrated 10-bit current output
DAC. Two complementary outputs provide a combined full-
scale output current (IOUT). Differential outputs reduce the
amount of common-mode noise that might be present at the
DAC output, offering the advantage of an increased signal-to-
noise ratio. The full-scale current is controlled by means of an
external resistor (RSET) connected between the DACISET pin
and analog ground. The full-scale current is proportional to the
resistor value as follows:
OUTSET IR /19.39=
The maximum full-scale output current of the combined DAC
outputs is 40 mA, but limiting the output to 20 mA provides the
best spurious-free dynamic range (SFDR) performance. The
DAC output compliance range is (AVDD – 1.5 V) to
(AVDD + 0.5 V). Voltages developed beyond this range cause
excessive DAC distortion and could potentially damage the
DAC output circuitry. Proper attention should be paid to the
load termination to keep the output voltage within this
compliance range. When terminating the differential outputs
into a transformer, the center tap should be attached to AVDD.
PLL Frequency Synthesizer
The PLL frequency synthesizer is a group of independent
synthesis blocks, designed to be used with the DDS to expand
the range of synthesis applications. These blocks are a digital
phase-frequency detector (PFD) that drives a charge pump
(CP). The charge pump incorporates fast-locking logic,
described below. Based on system requirements, the user
supplies an external loop filter and one or more VCOs. A high
speed analog mixer is included for translation synthesis loops.
Using the different blocks in the PLL frequency synthesizer in
conjunction with the DDS, the user can create translation loops
(also known as offset loops), fractional divider loops, as well as
traditional PLL loops to multiply the output of the DDS in
frequency.
AD9858
Rev. A | Page 16 of 32
Phase-Frequency Detector
The phase detector has two inputs, PDIN and DIVIN. Both are
analog inputs that can be operated in differential or single-
ended mode. Both are designed to operate at frequencies up to
150 MHz, although signals of up to 400 MHz can be
accommodated on the inputs when the divide-by-4 functions
are used. The expected input level for both the PD and DIV
inputs is in the range of 800 mV p-p (differential), 400 mV p-p
(single-ended). A programmable divider that offers division
ratios of M, N = {1, 2, 4} immediately follows the input. The
division ratio is controlled by means of the control
function register.
Charge Pump
The charge pump output reference current is determined by an
external resistor (~2.4 kΩ), which establishes a 500 µA
maximum internal baseline current (ICP0). The baseline current
is scaled to provide the appropriate drive current for the CP’s
various operating modes (frequency detect mode, wide closed-
loop, and final closed-loop). The amount of scaling in each
mode is programmable by means of the values stored in the
control function register, giving the user maximum flexibility of
the PLL’s frequency locking capability.
The CP polarity can be configured as either positive or negative
with respect to the PD input. When the CP polarity is positive, if
the DIV input leads the PD input, the charge pump attempts to
decrease the voltage at the VCO control node. If the DIV input
lags the PD input, the charge pump works to increase the
voltage at the VCO control node. When the CP polarity is
negative, the opposite occurs. This allows the user to define
either input as the feedback path. This also allows the AD9858
to accommodate ground-referenced or supply-referenced
VCOs. This functionality is defined by the charge pump polarity
(CPP) bit in the control function register. When CPP = 0
(default), the charge pump is set up for operation with a
ground-referenced VCO. When CPP = 1, the charge pump is set
up for a supply-referenced VCO.
Internal to the CP, the ICP0 current is scaled to provide different
output drive current values for the various modes of operation.
In its normal operating mode, the final closed-loop mode can
be programmed to scale ICP0 by 1, 2, 3, or 4. Setting the charge
pump current offset bit, CFR<13>, applies a 2 mA offset to the
programmed charge pump current, allowing scaler values of ICP0
of 5, 6, 7, or 8. The wide closed-loop mode can be programmed
to scale ICP0 by 0, 2, 4, 6, 8, 10, 12, or 14. The frequency detect
mode can be programmed to scale ICP0 by 0, 20, 40, or 60. The
different modes of operation, controlled by the fast-locking
logic, are discussed in the next section
The CP has an independent set of power pins that can operate
at up to 5.25 V. While the device can operate from ground to
rail, the voltage compliance should be kept in the range of 0.5 V
to 4.5 V to ensure the best steady-state performance. The
combination of programmable output current, programmable
polarity, wide compliance range, and proprietary fast-lock
capability offers the flexibility necessary for the digital PLL to
operate within a broad range of PLL applications.
Fast-Locking Logic
The charge pump includes a fast-locking algorithm that helps to
overcome the traditional limitations of PLLs with regard to
frequency switching time. The fast-locking algorithm works in
conjunction with the loop filter shown in Figure 29 to provide
extremely fast frequency switching performance.
Based on the error seen between the feedback signal and the
reference signal, the fast-locking algorithm puts the charge
pump into one of three states: frequency detect mode, a wide
closed-loop mode, and a final closed-loop mode. In the
frequency detect mode, the feedback and reference signals are
registering substantial phase and frequency errors. Rather than
operating in a continuous closed-loop feedback mode, the
charge pump supplies a fixed current of the correct polarity to
the VCO control node that drives the loop towards frequency
lock. Once frequency lock is detected, the fast-locking logic
shifts the part into one of the closed-loop modes. In the closed-
loop modes, either wide or final, the charge pump supplies
current to the loop filter as directed by the phase-frequency
detector PFD. The frequency-detect mode is intended to bring
the system to a level of frequency lock from which the
intermediary closed-loop system can quickly achieve phase lock.
The level of frequency lock accuracy aimed for is typically
referred to as the lock range. Once the frequency is within the
lock range, the time required to achieve phase lock can be
determined by standard PLL transient analysis methods. Note
that the charge pump current sources associated with the
frequency detect mode are connected to Pin 64, while the closed
loop current sources are connected to Pins 65 and 66. Pin 64 is
connected directly to the loop filter zero compensation
capacitor, as shown in Figure 29. This connection allows the
smoothest transition from the frequency detect mode to the
closed-loop modes and enables faster overall switching times.
Pins 65 and 66 are connected to the loop filter in the
conventional manner.
R2
C2
CP
CP
CPFL
AD9858
03166-A-032
Figure 29. Symbolic Representation of
Charge Pump to Loop Filter Connection
AD9858
Rev. A | Page 17 of 32
The frequency detection block works as follows. The
comparison logic in the frequency detection circuitry operates
one eighth of the DDS system clock. A comparison is made of
the frequencies present at the PD input and the DIV input over
19 DDS clock cycles.
To ensure that frequency lock detection is achieved while the
frequency difference is within the PLL lock range, the slew rate
of the VCO input should be limited such that the lock range
cannot be traversed within 152 system clock cycles. The slew
rate of the VCO input is determined by the programmed level
of frequency detect current and the size of the zero
compensation capacitor according to the following relationship:
Z
det
f
C
I
dt
dv =
Once frequency detection occurs, the loop is closed and the
loop is lock based on the current programmed for the wide
closed-loop mode. It is important that the loop be designed for
closed-loop stability while in the wide closed-loop mode. In this
mode, less phase margin can usually be tolerated, because this
mode is only used to enhance the lock time, but is not used in
the “locked” free running state. Once the wide closed-loop
mode achieves phase lock as determined by an internal lock
detector, the phase-detector/charge pump transitions into the
final closed-loop state. If no wide closed-loop current is
programmed, the loop transitions directly from the frequency
detect mode into the final closed-loop state. In the final closed-
loop state, the loop characteristics should be optimized for the
desired free running loop bandwidth.
The frequency detect mode is primarily useful in offset or
translation loop applications where the phase detector inputs
are more likely to detect large frequency transitions. For loop
applications with significant amounts of division in the feed-
back loop, the frequency detection mode may not activate. This
is due to the limited amount of frequency difference that is
experienced at the phase detector inputs. For these applications,
the primary means of accelerating the frequency settling time is
to design the loop to acquire lock with the wide closed-loop
setting and then switch to the final closed-loop setting.
As mentioned earlier, care should be taken when planning for a
large transition using the frequency detect mode to ensure that
the charge pump does not cause the VCO to overshoot the
closed-loop lock range, as cycle slipping could occur, which
would result in extended delays. Figure 30 shows two system
responses. In the first, the charge pump output current is
maximized during the frequency-detect mode so that, after
152 clock cycles, the VCO voltage has exceeded the closed-loop
lock range. The second system provides less current during the
frequency detect mode. While this results in a longer delay in
approaching the closed-loop lock range, because the system
does not exceed the closed-loop range, the fast-locking logic
shifts the charge pump into intermediary closed-loop mode,
resulting in a shorter overall frequency switching time.
TIME
VCO VOLTAGE
03166-A-033
Figure 30. Symbolic Representation of
Charge Pump to Loop Filter Connection
Analog Mixer
The analog mixer is included for translation loops, also known
as offset loops. The radio frequency (RF) and local oscillator
(LO) inputs are designed to operate at frequencies up to 2 GHz.
Both inputs are differential analog input stages. Both input
stages are internally dc biased and should be connected through
an external ac coupling mechanism. The expected input level is
in the range of 800 mV p-p (differential). The IF (intermediate
frequency) output is a differential analog output stage designed
to operate at frequencies less than 400 MHz. This mixer is based
on the Gilbert cell architecture.
MODES OF OPERATION
The AD9858 DDS section has three modes of operation—single
tone, frequency sweeping, and full sleep. The RF building blocks
(PFD, CP, and mixer) can be active or powered down, used or
unused, in either of the active modes.
In the single-tone mode, the device generates a single output
frequency determined by a 32-bit word (frequency tuning
word—FTW) loaded to an internal register. This frequency can
be changed as desired, and frequency hopping can be accompl-
ished at a rate limited only by the time required to update the
appropriate registers. If even faster hopping is needed, the four
profiles allow rapid hopping among the four frequencies stored
in them by means of external select pins.
The frequency-sweeping mode allows for the automation of
most of the frequency-sweeping task, making chirp and other
frequency-sweeping applications possible without the
inconvenience and possible speed limitations imposed by
multiple register operations via the I/O port.
In whichever mode the device is operating, changes in
frequency are phase continuous, which means that they do not
cause discontinuities in the phase of the output signal. The first
phase value after a frequency change is an increment of the last
AD9858
Rev. A | Page 18 of 32
The maximum usable frequency in the fundamental range of
the DDS is typically between 40% and 45% of the Nyquist
frequency, depending on the reconstruction filter. With a 1 GHz
SYSCLK, the AD9858 is capable of producing maximum output
frequencies of between 400 MHz and 450 MHz, depending on
the reconstruction filter and the application system
requirements.
phase value before the change, but at the new tuning word’s
phase increment value (FTW). (Note that this is not the same as
phase-coherent over frequency changes; see Figure 31.)
REFERENCE SIGNAL
F
REF
= A F
REF
= A F
REF
= A
F
OUT
= 2A
F
OUT
= 2A
F
OUT
= A
F
OUT
= A F
OUT
= 2A
F
OUT
= A
PHASE COHERENT
PHASE CONTINUOUS
W
HERE
θ= PHASE OF OUTPUT SIGNAL, Φ= PHASE AT TIME OF FIRST FREQUENCY
TRANSITION, AND Φ' = PHASE AT TIME OF SECOND FREQUENCY TRANSITION.
θ= 2θREFΦ
θ= 2θREF+Φ + Φ'
θ = 2θREF
θ=θREF
θ=θREF
θ=θREF
03166-A-034
For a desired output frequency (FO) and sampling rate
(SYSCLK), the frequency tuning word (FTW) of the AD9858 is
calculated according to the following equation
(
)
SYSCLKFOFTW N/2×=
where N is the phase accumulator resolution in bits (32 in the
AD9858), FO is in Hz, and the FTW is a decimal number.
Once a decimal number has been calculated, it must be rounded
to an integer and converted to a 32-bit binary value. The
frequency resolution of the AD9858 is 0.233 Hz when the
SYSCLK is 1 GHz.
Figure 31. The Difference between a Phase Continuous
Frequency Change and a Phase Coherent Frequency Change
Single-Tone Mode Frequency-Sweeping Mode
When in single-tone mode, the AD9858 generates a signal, or
tone, of a single desired frequency. This frequency is set by the
value loaded by the user into the chip’s frequency tuning word
(FTW) register. This frequency can be between 0 Hz and
somewhat below one-half of the DAC sampling frequency
(SYSCLK). One-half of the sampling frequency is commonly
called the Nyquist frequency. The practical upper limit to the
fundamental frequency range of a DDS is determined by the
characteristics of the external low-pass filter, known as the
reconstruction filter, which must follow the DAC output of the
DDS. This filter reconstructs the desired analog sine wave
output signal from the stream of sampled amplitude values
output by the DAC at the sample rate (SYSCLK).
The AD9858 provides automated frequency sweeping capability.
This allows the AD9858 to generate frequency-swept signals for
chirped radar or other applications. The AD9858 includes
features that automate much of the task of executing frequency
sweeps.
The frequency sweep feature is implemented through the use of
a frequency accumulator (not to be confused with the phase
accumulator). The frequency accumulator repeatedly adds a
frequency incremental quantity to the current value, thereby
creating new instantaneous frequency tuning words, causing the
frequency generated by the DDS to change with time. The
frequency increment, or step size, is loaded into a register
known as the delta frequency tuning word (DFTW). The rate at
which the frequency is incremented is set by another register,
the delta frequency ramp rate word (DFRRW). Together these
two registers enable the AD9858 to sweep from a beginning
frequency set by the FTW, upwards or downwards, at a desired
rate and frequency step size. The result is a linear frequency
sweep or chirp.
A DDS is a sampled-data system. As the fundamental frequency
of the DDS approaches the Nyquist frequency, the lower first
image approaches the Nyquist frequency from above. As the
fundamental frequency approaches the Nyquist frequency, it
becomes difficult, and finally impossible, to design and
construct a low-pass filter that will provide adequate
attenuation for the first image frequency component.
AD9858
Rev. A | Page 19 of 32
40ns 80ns
TIME
FREQUENCY
120ns 160ns
DELTA FREQUENCY RAMP RATE WORD (≥8ns)
8ns 16ns
TIME
FREQUENCY
24ns 32ns
DELTA FREQUENCY TUNING WORD
03166-A-035
Figure 32. Frequency vs. Time Plots for a Given Sweep Profile
The delta frequency ramp rate word (DFRRW) functions as a
countdown timer, in which the value of the DFRRW is decre-
mented at the rate of SYSCLK/8. This means that the most rapid
frequency word update occurs when a value of 1 is loaded into
the DFRRW, and results in a frequency increment at 1/8 of the
SYSCLK rate. With a SYSCLK of 1 GHz, the frequency can be
incremented at a maximum rate of 125 MHz (DFRRW = 1).
The delta frequency tuning word (DFTW) must specify
whether the frequency sweep should proceed up or down from
the starting frequency (FTW). Therefore, the DFTW is
expressed as a twos complement binary value, in which positive
indicates up and negative indicates down.
A DFRRW value of 0 written to the register stops all frequency
sweeping. There is no automatic stop-at-a-given-frequency
function. The user must calculate the time interval required to
reach the final frequency and then issue a command to write 0
into the DFRRW register. The time required for a frequency
sweep is calculated by the following formula
DFTW
DFRRW
SYSCL
K
ff
T2
S
F×
×−
=
34
2
where:
T is the duration of the sweep in seconds.
fS is the starting frequency determined by
SYSCLK
FTW
fS×= 32
2.
fF is the final frequency.
The delta frequency step size is given by
31
2
SYSCLKDFTW
f×
=∆ ,
remembering that DFTW is a signed (twos complement) value.
The time between each frequency step (∆t) is given by
SYSCL
K
DFRRW
t×
=∆ 8
The value of the stop frequency fF is determined by
t
f
Tff S
F∆
∆
×+=
Returning to Starting Frequency
The original frequency tuning word (FTW), which was written
into the frequency tuning register, does not change at any time
during a sweeping operation. This means that the DDS may be
returned to the sweep starting frequency at any time during a
sweep. Setting the control bit named autoclear frequency
accumulator forces the frequency accumulator to zero, instantly
returning the DDS to the frequency stored as FTW.
Full-Sleep Mode
Setting all of the power-down bits in the control function
register activates full-sleep mode. During the power-down
condition, the clocks associated with the various functional
blocks of the device are turned off, thereby offering a significant
power savings.
SYNCHRONIZATION
SYNCLK and FUD Pins
Timing for the AD9858 is provided via the user-supplied
REFCLK input. The REFCLK input is buffered and is the source
for the internally generated SYSCLK. The frequency of SYSCLK
can be either the same as REFCLK or half that of REFCLK (via
a programmable divide-by-2 function set in the control
function register CFR). The REFCLK input is capable of
handling input frequencies as high as 2 GHz. However, the
device is designed for a maximum SYSCLK frequency of 1 GHz.
Thus, it is mandatory that the divide-by-2 SYSCLK function be
enabled when the frequency of REFCLK is greater than 1 GHz.
AD9858
Rev. A | Page 20 of 32
SYSCLK serves as the sample clock for the DAC and is fed to a
divide-by-8 frequency divider to produce SYNCLK. SYNCLK is
provided to the user on the SYNCLK pin. This enables
synchronization of external hardware with the AD9858’s
internal DDS clock. External hardware that is synchronized to
the SYNCLK signal can then be used to provide the frequency
update (FUD) signal to the AD9858. The FUD signal and
SYNCLK are used to transfer the internal buffer register
contents into the memory registers of the device. Figure 33
shows a block diagram of the synchronization methodology,
and Figure 34 shows an I/O synchronization timing diagram.
Note that SYNCLK is also used to synchronize the assertion of
the profile select pins (PS0, PS1). The FUD, PS0, and PS1 pins
must be set up and held around the rising edge of SYNCLK.
These device inputs are designed for zero hold time and 3.5 ns
setup time.
UPDATE REGS
REGISTER
MEMORY
EDGE
DETECTION
LOGIC
REFCLK
P0, P1
FUD
SYNCLK 0
2 GHz DIVIDER
DISABLE SYNCLK
DISABLE
TO CORE LOGIC BUFFER
MEMORY
÷ 2
10
10
D
Q
WR
ADDR
DATA
SYNCLK
D
Q
03166-A-036
÷ 8
Figure 33. I/O Synchronization Block Diagram
SYNCLK
SYSCLK
FUD REGISTERED FUD EDGE DETECTED FUD REGISTERED FUD EDGE DETECTED
VALUE 2
VALUE 1
IO BUFFER
MEMORY
CONTROL
REGISTER
DATA VALUE 0 VALUE 1 VALUE 2
(ASYNCHRONOUSLY LOADED VIA I/O PORT)
FUD*
*FUD IS AN INPUT PROVIDED BY THE USER THAT MUST BE SET UP AND HELD AROUND RISING EDGES OF SYNCLK. THE OCCURRENCE OF
THE RISING EDGE OF SYNCLK DURING THE HIGH STATE OF THE UPDATEREGS SIGNAL CAUSES THE BUFFER MEMORY CONTENTS TO BE
TRANSFERRED INTO THE CONTROL REGISTERS. SIMILARLY, A STATE CHANGE ON THE PS0 OR PS1 PINS IS EQUIVALENT TO ASSERTING A VALID
FUD SEQUENCE. NOTE: I/O UPDATES ARE SYNCHRONOUS TO THE SYNCLK SIGNAL, REGARDLESS OF THE SYNCHRONIZATION MODE SELECTED.
(ASYNCHRONOUSLY LOADED VIA I/O PORT)
03166-A-037
Figure 34. I/O Synchronization Timing Diagram
AD9858
Rev. A | Page 21 of 32
Frequency Planning
To achieve the best possible spurious performance when using
the AD9858 in a hybrid synthesizer configuration, frequency
planning can be employed. Frequency planning consists of
being aware of the mechanisms that determine the location of
the worst-case spurs and then using the appropriate loop tuning
parameters to place these spurs either outside the loop
bandwidth, such that they are attenuated, or completely outside
the frequency range of interest.
When using the fractional divider configuration, the worst-case
spurs occur whenever the images of the DAC harmonics fold
back such that they are close to the DAC fundamental or carrier
frequency. If these images fall within the loop bandwidth, they
will be gained up by approximately 20 × log N, where N is the
gain in the loop. If N is relatively high, these spurs can still
realize significant gain even if they are slightly outside the loop
bandwidth, since the loop attenuation rate is typically
20 dB/decade in this region. DAC images occur at
N × FCLOCK ± M × FOUT
where N and M are integer multiples of FCLOCK and FOUT,
respectively.
Figure 20 shows a high spurious condition where the low-order
odd harmonics are folding back around the fundamental.
Figure 21 shows that the worst spurs are confined to a narrow
region around the carrier and that wideband spurs are
attenuated. Figure 17 shows an alternate frequency plan that
results in the same carrier frequency. Recall that the output
frequency of the DAC is set by the equation
(FOUT = FCLOCK × FTW/2N)
This makes it possible to produce the same FOUT by different
combinations of FCLOCK and FTW. In this case, the worst DAC
spurs are placed well outside the loop bandwidth such that they
are attenuated below the noise floor. Figure 24 shows a
wideband plot for this frequency plan.
Other frequency combinations that can result in high spurious
signals are when subharmonics of FCLOCK fall within or near the
loop bandwidth. To avoid this, ensure that the DAC FOUT is
sufficiently offset from the subharmonics of FCLOCK such that
these products are attenuated by the loop.
Frequency planning for the translation loop is similar in that
the DAC images and the FCLOCK subharmonics need to be
considered. Figure 25 and Figure 26 show results for a high
spurious configuration where odd order images are folding back
close to the carrier. Figure 22 and Figure 23 show an alternative
frequency plan that generates the same carrier frequency with
low spurious content. Because this loop also requires a mixer
LO frequency, additional care is required in planning for this
frequency arrangement. Generally there is some mixer LO
feedthrough. The amount of feedthrough depends on the PCB
board layout isolation as well as the mixer LO power level, but
levels of –80 dBc can typically be achieved. Figure 26 shows
results for a situation where the mixer LO component shows up
in the spectrum at 1.41 GHz, and another spur component
shows up at Mixer LO + FCLOCK/8. This places the mixer LO
frequency well outside the bandwidth of interest, resulting in
the spectrum shown in Figure 25.
PROGRAMMING THE AD9858
The transfer of data from the user to the DDS core of the device
is a 2-step process. In a write operation, the user first writes the
data to the I/O buffer using either the parallel port (which
includes bits for address and data) or serial mode (where the
address and data are combined in a serial word). Regardless of
the method used to enter data to the I/O buffer, the DDS core
cannot access the data until the data is latched into the memory
registers from the I/O buffer. Toggling the FUD pin or changing
one of the profile select pins causes an update of all elements of
the I/O buffer memory into the DDS core’s register memory.
I/O Port Functionality
The I/O port can be operated in either serial or parallel
programming mode. Mode selection is accomplished via the
S/P Select pin. Logic 0 on this pin configures the I/O port for
serial programming, while Logic 1 configures the I/O port for
parallel programming.
The ability to read back the contents of a register is provided in
both modes to facilitate the debug process during the user’s
prototyping phase of a design. In either mode, however, the
reading back of profile registers requires that the profile select
pins (P0, P1) be configured to select the desired register bank.
When reading a register that resides in one of the profiles, the
register address acts as an offset to select one of the registers
among the group of registers defined by the profile. The profile
select pins control the base address of the register bank and
select the appropriate register grouping.
Parallel Programming Mode
In parallel programming mode, the I/O port makes use of eight
bidirectional data pins (D7 to D0), six address input pins (ADDR5
to ADDR0), a read input pin (RD), and a write input pin (WR). A
register is selected by providing the proper address combination as
defined in the register map. Read or write functionality is invoked
by pulsing the appropriate pin (RD or WR); the two operations are
mutually exclusive. The read or write data is transported on the D7
to D0 pins. The correlation between the D7 to D0 data bits and
their functionality at a specific register address is detailed in the
register map and register bit description.
Parallel I/O operation allows write access to each byte of any
register in the I/O buffer memory in a single I/O operation at a 100
MHz rate. However, unlike write operation, readback capability is
not guaranteed at the 100 MHz rate. It is intended as a low speed
function for debug purposes. Timing for both write and read cycles
is depicted in Figure 35 and Figure 36.
AD9858
Rev. A | Page 22 of 32
A3
A1A2
D3
D1D2
T
WRHIGH TWRLOW
T
AHD
T
DHD
T
DOU
T
ASU
T
WR
T
ASU
T
DOU
T
ADH
T
DHD
T
WRLOW
T
WRHIGH
T
WR
SPECIFICATION
3ns
3.5ns
0ns
0ns
3ns
6ns
9ns
VALUE
ADDRESS SETUP TIME TO WR SIGNAL ACTIVE
DATA SETUP TIME TO WR SIGNAL INACTIVE
ADDRESS HOLD TIME TO WR SIGNAL INACTIVE
DATA HOLD TIME TO WR SIGNAL INACTIVE
WR SIGNAL MINIMUM LOW TIME
WR SIGNAL MINIMUM HIGH TIME
WR SIGNAL MINIMUM PERIOD
DESCRIPTION
D<7:0>
A<5:0>
WR
03166-A-038
Figure 35. I/O Port Write Cycle Timing (Parallel)
A
3
A
1
A
2
D
3
D
1
D
2
TRDHOZ TRDLOV
TADV
TAHD
TASU
TADH
TRDLOV
TRDHOZ
SPECIFICATION
15ns
5ns
15ns
10ns
VALUE
ADDRESS TO DATA VALID TIME (MAXIMUM)
ADDRESS HOLD TIME TO RD SIGNAL INACTIVE (MINIMUM)
RD LOW TO OUTPUT VALID (MAXIMUM)
RD HIGH TO DATA THREE-STATE (MAXIMUM)
DESCRIPTION
D<7:0>
A<5:0>
RD
03166-A-039
Figure 36. I/O Port Read Cycle Timing (Parallel)
AD9858
Rev. A | Page 23 of 32
Serial Programming Mode
In serial programming mode, the I/O port uses a chip select pin
(CS), a serial clock pin (SCLK), an I/O reset pin (IORESET),
and either 1 or 2 serial data pins (SDIO and/or SDO). The
number of serial data pins used depends on the configuration
of the I/O port; i.e., whether it has been configured for 2-wire or
3-wire serial operation as defined by the control function
register. In 2-wire mode, the SDIO pin operates as a
bidirectional serial data pin. In 3-wire mode, the SDIO pin
operates only as a serial data input pin, and the SDO pin acts as
the serial output. The maximum rate of SCLK is 10 MHz;
however, during read operation, the 10 MHz rate is not
guaranteed.
The serial port is an SPI compatible serial interface and its
operation is virtually identical to that of the AD9852/AD9854.
Serial port communication occurs in two phases. Phase 1 is an
instruction cycle consisting of an 8-bit word. The MSB of the
instruction byte flags the ensuing operation as a read or write
operation. The 6 LSBs define the serial address of the target
register as defined in the register map. The instruction byte
format is given in Table 5.
Table 5.
D7 (MSB) D6 D5 D4 D3 D2 D1 DO (LSB)
1: Read
0: Write
X A5 A4 A3 A2 A1 A0
Phase 2 of a serial port communication contains the data to be
routed to/from the addressed register. The number of bytes
transferred during Phase 2 depends on the length of the target
register. Serial operation requires that all bits associated with a
serial register address be transferred.
Both phases of a serial port communication require the serial
data clock (SCLK) to be operating. When writing to the device,
serial bits are transferred on the rising edge of SCLK. When
reading from the device, serial output bits are transferred on the
falling edge of SCLK. The bit order for both phases of a serial
port communication is selectable via the control function
register.
The CS pin serves as a chip select control line. When CS is at a
Logic 1 state, the SDO and SDIO pins are disabled (forced into a
high impedance state). Only when the CS pin is at a Logic 0
state are the SDO and SDIO pins active. This allows multiple
devices to exist on a single serial bus. If multiple devices are
connected to the same serial bus, then communication with a
single device is accomplished by setting CS to a Logic 0 state on
the target device, but to a Logic 1 state on all other devices. In
this way, serial communication occurs only between the
controller and the target device.
In the case where I/O synchronization is lost between the
AD9858 and the external controller, the IORESET pin provides
a means to re-establish synchronization without initializing the
entire device. Asserting the active high IORESET pin resets the
serial port state machine. This terminates the current I/O
operation and puts the device into a state in which the next
eight SCLK pulses are expected to be the instruction byte of the
next I/O transfer. Note that any information previously written
to the memory registers during the last valid communication
cycle prior to loss of synchronization remains intact.
Register Map
The registers are listed in Table 6. The serial address and parallel
address numbers associated with each of the registers are shown
in hexadecimal format. Angle brackets <> are used to reference
specific bits or ranges of bits. For example, <3> designates Bit 3,
while <7:3> designates the range of bits from 7 down to 3,
inclusive.
AD9858
Rev. A | Page 24 of 32
Table 6. Register Map
Register Address (LSB)
Name Ser Par
(MSB)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Default
Value Profile
0x00
<7:0>
Not
Used
2 GHz
Divider
Disable
SYNCLK
Out
Disable
Mixer
Power
Down
Phase
Detect
PwrDwn
Power
Down
SDIO
Input
Only
LSB
First
0x18
N/A
0x01
<15:8>
Freq.
Sweep
Enable
Enable
Sine
Output
Charge
Pump
Offset
Bit
Phase Detector
Divider Ratio (N)
(see Table 10)
Charge
Pump
Polarity
Phase Detector
Divider Ratio
(M)
(see Table 11)
0x00
N/A
0x02
<23:16>
AutoClr
Freq.
Accum
AutoClr
Phase
Accum
Load
Delta-
Freq
Timer
Clear
Freq
Accum
Clear
Phase
Accum Open
Fast-
Lock
Enable
Don’t
Use
FTW
for
Fast-
Lock
0x00
N/A
Control
Function
Register
(CFR)
0x00
0x03
<31:24>
Frequency Detect
Charge Pump
Current
(see Table 7)
Final Closed-Loop Charge
Pump Current
(see Table 8)
Wide Closed-Loop Charge
Pump Current
(see Table 9)
0x00
N/A
0x04 Delta Frequency Word <7:0> – N/A
0x05 Delta Frequency Word <15:8> – N/A
0x06 Delta Frequency Word <23:16> – N/A
Delta-Freq
Tuning Word
(DFTW) 0x01
0x07 Delta Frequency Word <31:24> – N/A
0x08 Delta Frequency Ramp Rate Word <7:0> – N/A
Delta-Freq Ramp
Rate (DFRRW) 0x02 0x09 Delta Frequency Ramp Rate Word <15:8> – N/A
0x0A Frequency Tuning Word No. 0 <7:0> 0x00 0
0x0B Frequency Tuning Word No. 0 <15:8> 0x00 0
0x0C Frequency Tuning Word No. 0 <23:16> 0x00 0
Frequency
Tuning Word
No. 0 (FTW0) 0x03
0x0D Frequency Tuning Word No. 0 <31:24> 0x00 0
0x0E Phase Offset Word No. 0 <7:0> 0x00 0
Phase Offset
Word 0 (POW0) 0x04 0x0F Not Used Not Used Phase Offset Word No. 0 <13:8> 0x00 0
0x10 Frequency Tuning Word No. 1 <7:0> – 1
0x11 Frequency Tuning Word No. 1 <15:8> – 1
0x12 Frequency Tuning Word No. 1 <23:16> – 1
Frequency
Tuning
Word No.1(FTW1) 0x05
0x13 Frequency Tuning Word No. 1 <31:24> – 1
0x14 Phase Offset Word No. 1 <7:0> – 1
Phase Offset
Word 1 (POW1) 0x06 0x15 Not Used Not Used Phase Offset Word No. 1 <13:8> – 1
0x16 Frequency Tuning Word No. 2 <7:0> – 2
0x17 Frequency Tuning Word No. 2 <15:8> – 2
0x18 Frequency Tuning Word No. 2 <23:16> – 2
Frequency
Tuning Word
No. 2 (FTW2) 0x07
0x19 Frequency Tuning Word No. 2 <31:24> – 2
0x1A Phase Offset Word No. 2 <7:0> – 2
Phase Offset
Word 2 (POW2) 0x08 0x1B Not Used Not Used Phase Offset Word No. 2 <13:8> – 2
0x1C Frequency Tuning Word No. 3 <7:0> – 3
0x1D Frequency Tuning Word No. 3 <15:8> – 3
0x1E Frequency Tuning Word No. 3 <23:16> – 3
Frequency
Tuning Word
No. 3 (FTW3) 0x09
0x1F Frequency Tuning Word No. 3 <31:24> – 3
0x20 Phase Offset Word No. 3 <7:0> – 3
Phase Offset
Word 3 (POW3) 0x0A 0x21 Not Used Not Used Phase Offset Word No. 3 <13:8> – 3
0x22 Reserved, Do Not Write, Leave at 0xFF 0xFF N/A Reserved 0x0B 0x23 Reserved, Do Not Write, Leave at 0xFF 0xFF N/A
AD9858
Rev. A | Page 25 of 32
Register Bit Descriptions
Control Function Register (CFR)
The CFR is comprised of four bytes located in parallel addresses
0x03 to 0x00. The CFR is used to control the various functions,
features, and modes of the AD9858. The functionality of each
bit is detailed below. Note that the register bits are identified
according to their serial register bit locations beginning with the
most significant bit.
CFR<31:30>: Frequency-Detect Mode Charge Pump Current
These bits are used to set the scale factor for the frequency-
detect mode charge pump output current per Table 7. The
charge pump delivers the scaled output current when the
control logic forces the charge pump into its frequency detect
operating mode. The charge pump’s baseline output current
(ICP0) is determined by the external CPISET resistor and is
given by
T1.24/CPISE ICP0 =
The recommended nominal value of the CPISET resistor is
2.4 kΩ, which yields a baseline current of 500 µA.
Table 7.
CFR<31:30>
Frequency-Detect
Charge Pump
Scale Value
Notes
00b 0 IOUT = 0 (Default)
01b 2 IOUT = 20 × ICP0
10b 3 IOUT = 40 × ICP0
11b 4 IOUT = 60 × ICP0
CFR<29:27>: Final Closed-Loop Mode
Charge Pump Output Current
These bits are used to set the scale factor for the final closed-
loop mode charge pump output current per Table 8. The charge
pump delivers the scaled output current when the control logic
forces the charge pump into its final closed-loop mode.
Table 8.
CFR<29:27>
Final Closed-Loop
CP Scale Value
Notes
0xxb 0 IOUT = 0 (Default)
100b 1 IOUT = ICP0
101b 2 IOUT = 2 × ICP0
110b 3 IOUT = 3 × ICP0
111b 4 IOUT = 4 × ICP0
CFR<26:24>: Wide Closed-Loop Charge Pump
Output Current
These bits are used to set the scale factor for the wide closed-
loop charge pump output current, see Table 9. The charge pump
delivers the scaled output current when the control logic forces
the charge pump into its wide closed-loop operating mode.
Table 9.
CFR<26:24>
Wide Closed-Loop
CP Scale Value
Notes
000b 0 IOUT = 0 (Default)
001b 2 IOUT = 2 × ICP0
010b 4 IOUT = 4 × ICP0
011b 6 IOUT = 6 × ICP0
100b 8 IOUT = 8 × ICP0
101b 10 IOUT = 10 × ICP0
110b 12 IOUT = 12 × ICP0
111b 14 IOUT = 14 × ICP0
CFR<23>: AutoClear Frequency Accumulator Bit
When CFR<23> = 0 (default), a new delta frequency word is
applied to the input of the accumulator and added to the
currently stored value.
When CFR<23> = 1, this bit automatically synchronously clears
(loads zeros into) the frequency accumulator for one cycle upon
reception of the FUD sequence indicator.
CFR<22>: AutoClear Phase Accumulator Bit
When CFR<22> = 0 (default), a new frequency tuning word is
applied to the input of the phase accumulator and added to the
currently stored value.
When CFR<22> = 1, this bit automatically synchronously clears
(loads zeros into) the phase accumulator for one cycle upon
reception of the FUD sequence indicator.
CFR<21>: Load Delta-Frequency Timer
When CFR<21> = 1 (default), the contents of the delta
frequency ramp rate word are loaded into the ramp rate timer
(down counter) upon detection of a FUD sequence.
When CFR<21> = 0, the contents of the delta frequency ramp
rate word are loaded into the ramp rate timer upon timeout
with no regard to the state of the FUD sequence indicator (i.e.,
the FUD sequence indicator is ignored).
CFR<20>: Clear Frequency Accumulator Bit
When CFR<20> = 1, the frequency accumulator is
synchronously cleared and is held clear until CFR<20> is
returned to a Logic 0 state (default).
AD9858
Rev. A | Page 26 of 32
CFR<19>: Clear Phase Accumulator Bit
When CFR<19> = 1, the phase accumulator is synchronously
cleared and is held clear until CFR<19> is returned to a Logic 0
state (default).
CFR<18>: Not Used.
CFR<17>: PLL Fast-Lock Enable Bit
When CFR<17> = 0 (default), the PLL’s fast-lock algorithm is
disabled.
When CFR<17> = 1, the PLL’s fast-lock algorithm is active.
CFR<16>
This bit allows the user to control whether or not the PLL’s fast-
locking algorithm uses the tuning word value to determine
whether or not to enter fast-locking mode.
When CFR<16> = 0 (default), the PLL’s fast-locking algorithm
considers the relationship between the programmed frequency
tuning word and the instantaneous frequency as part of the
locking process.
When CFR<16> = 1, the PLL’s fast-locking algorithm does not
use the frequency tuning word as part of the locking process.
CFR<15>: Frequency Sweep Enable Bit
When CFR<15> = 0 (default), the device is in the single-
tone mode.
When CFR<15> = 1, the device is in the frequency-
sweep mode.
CFR<14>: Sine/Cosine Select Bit
When CFR<14> = 0 (default), the angle-to-amplitude
conversion logic employs a cosine function.
When CFR<14> = 1, the angle-to-amplitude conversion logic
employs a sine function.
CFR<13>: Charge Pump Current Offset Bit
When CFR<13> = 0 (default), the charge pump operates with
normal current settings.
When CFR<13> = 1, the charge pump operates with offset
current settings (see charge pump description).
CFR<12:11>: Phase Detector Reference
Input Frequency Divider Ratio
These bits set the phase detector divide value per Table 10.
Table 10.
CFR<12:11>
Phase Detector
Divider Ratio (N)
Notes
00b 1 Default Value
01b 2
1xb 4 LSB Ignored
CFR<10>: Charge Pump Polarity Select Bit
When CFR<10> = 0 (default), the charge pump is set up for
operation with a ground-referenced VCO. In this mode, the
charge pump sources current when the frequency at PDIN is less
than the frequency at DIVIN. It sinks current when the opposite
is true.
When CFR<10> = 1, the charge pump is set up for a supply-
referenced VCO. In this mode, the charge pump’s source/sink
operation is opposite that for a ground-referenced VCO.
CFR<9:8>: Phase Detector Feedback
Input Frequency Divider Ratio
These bits set the phase detector divide value per Table 11.
Table 11.
CFR<9:8>
Phase Detector Divider
Ratio (M)
Notes
00b 1 Default value
01b 2
1xb 4 LSB ignored
CFR<7>: Not Used
CFR<6>: Disable Bit for the 2 GHz REFCLK Divider
When CFR<6> = 0 (default), the REFCLK divide-by-2 function
is not bypassed. REFCLK input can be up to 2 GHz.
When CFR<6> = 1, the REFCLK divide-by-2 function is
disabled. REFCLK input must be no more than 1 GHz.
CFR<5>: SYNCLK Disable Bit
When CFR<5> = 0 (default), the SYNCLK pin is active.
When CFR<5> = 1, the SYNCLK pin assumes a static Logic 0
state (disabled). In this state, the pin drive logic is shut down to
keep noise generated by the digital circuitry at a minimum.
However, the synchronization circuitry remains active
(internally) to maintain normal device timing.
CFR<4:2>: Power-Down Bits
Active high (Logic 1) powers down the respective function.
Writing a Logic 1 to all three bits causes the device to enter full-
sleep mode.
CFR<4> is used to shut down the analog mixer stage
(default = 1).
AD9858
Rev. A | Page 27 of 32
CFR<3> is used to shut down the phase detector and charge
pump circuitry (default = 1).
CFR<2> is used to shut down the DDS core and DAC and to
stop all internal clocks except SYNCLK (default = 0).
CFR<1>: SDIO Input Only
When CFR<1> = 0 (default), the SDIO pin has bidirectional
operation (2-wire serial programming mode).
When CFR<1> = 1, the serial data I/O pin (SDIO) is configured
as an input only pin (3-wire serial programming mode).
CFR<0>: LSB First
Note that this bit has an effect on device operation only if the
I/O port is configured as a serial port.
When CFR<0> = 0 (default), MSB first format is active.
When CFR<0> = 1, LSB first format is active.
Other Registers
Delta-Frequency Tuning Word (DFTW)
The DFTW register is comprised of four bytes located in
parallel addresses 0x04 to 0x07. The contents of the DFTW are
applied to the input of the frequency accumulator. Unlike the
frequency tuning word associated with the phase register
(which is a 32-bit unsigned integer), the DTFW is a 32-bit
signed integer. Because it controls the rate of change of
frequency, which can either be a positive or negative value, the
DTFW is by definition a signed number. When the device is in
the frequency-sweep mode, the output of the frequency
accumulator is added to the frequency tuning word and fed to
the phase accumulator. This provides the frequency sweep
capability of the AD9858. The DFTW controls the frequency
resolution associated with a frequency sweep.
As shown in Table 6, the most significant byte of the delta
frequency tuning word is located in parallel register address
0x07. The lesser significant bytes appear in descending order at
parallel register addresses 0x06, 0x05, and 0x04.
Delta-Frequency Ramp Rate Word (DFRRW)
The DFRRW is comprised of two bytes located in parallel
addresses 0x08 to 0x09. The DFRRW is a 16-bit unsigned
number that serves as a divider for the timer used to clock the
frequency accumulator. The timer runs at the DDS CLK rate
and generates a clock tick to the frequency accumulator. The
number stored in the DFRRW register determines the number
of DDS CLK cycles between subsequent ticks to the frequency
accumulator. Effectively, the DFRRW controls the rate at which
the DFTW is accumulated.
As shown in Table 6, the most significant byte of the DFRRW is
located in parallel register address 0x09 and the least significant
byte at address 0x08.
User Profile Registers
The user profile registers are comprised of the four frequency
tuning words and four phase adjustment words. Each pair of
frequency and phase registers forms a configurable user profile,
selected by the user profile pins.
User Profiles
The AD9858 features four user profiles (0–3), selected by profile
select pins (PS0, PS1) on the device. Each profile has its own
frequency tuning word. This allows the user to load a different
frequency tuning word into each profile, which can then be
selected as desired by the profile select pins. This makes it
possible to hop among the different frequencies at rates up to
1/8 of the SYSCLK while in the single-tone mode.
The AD9858 also provides a 14-bit phase-offset word (POW)
for each profile. The value in this register is a 14-bit unsigned
number (POW) that represents the proportional (PO/214) phase
offset to be added to the instantaneous phase value. This allows
the phase of the output signal to be adjusted in fine increments
of phase (about 0.022°). It is possible to update the FTW and
POW of any profile while the AD9858 is operating at the
frequency specified by another profile and then switch to the
profile containing the newly loaded frequency. Changing the
current profile updates both parameters so care must be taken
to ensure that no unwanted parameter changes take place.
It is also possible to repeatedly write a new frequency into the
FTW register of a selected profile and to jump to the new
frequency by strobing the frequency update pin (FUD). This
allows hopping to arbitrary frequencies but is limited in the rate
at which this can be accomplished by the speed of the I/O port
(100 MHz in parallel mode) and the necessity to transfer several
bytes of data for each new frequency tuning word. This can be
accomplished rapidly enough for many applications.
Frequency Tuning Control
The output frequency of the DDS is determined by the 32-bit
frequency tuning word (FTW) and the system clock (SYSCLK).
The relationship is described in the following equation
()
N
O
SYSCLKFTW
F2
×
=
where for the AD9858 N = 32.
In single-tone mode, the FTW is supplied by the active profile.
In frequency-sweeping mode, the FTW is the output of the
frequency accumulator.
AD9858
Rev. A | Page 28 of 32
Phase Offset Control
A 14-bit phase offset (θ) may be added to the output of the
phase accumulator by means of the phase offset words stored in
the memory registers. This feature provides the user with three
different methods of phase control.
The first method is a static phase adjustment, where a fixed
phase offset is loaded into the appropriate phase-offset register
and left unchanged. The result is that the output signal is offset
by a constant angle relative to the nominal signal. This allows
the user to phase align the DDS output with an external signal,
if necessary.
The second method of phase control is where the user regularly
updates the appropriate phase-offset register via the I/O port.
By properly modifying the phase offset as a function of time,
the user can implement a phase modulated output signal. The
rate at which phase modulation can be performed is limited by
both the speed of the I/O port and the frequency of SYSCLK.
The third method of phase control involves the profile registers,
in which the user loads up to four different phase-offset values
into the appropriate profiles. The user can then select among
the four preloaded phase-offset values via the AD9858 profile
select pins. Thus, the phase changes are accomplished by driving
the hardware pins rather than writing to the I/O port, thereby
avoiding the speed limitation imposed by the I/O port.
However, this method is restricted to only four phase-offset
values (one phase-offset value per profile). Each profile has an
associated frequency and phase value. Changing the current
profile updates both parameters, so care must be taken to
ensure that no unwanted parameter changes take place.
Note that the phase-offset value is routed through a unit delay
(z–1) block. This is done to ensure that updates of the phase-
offset values exhibit the same amount of latency as updates of
the frequency tuning word. Otherwise, if the user decides to
update both frequency and phase-offset values, the phase-offset
change would propagate through the device before the tuning
word change. The presence of the unit delay in the phase-offset
path ensures that both frequency and phase-offset changes
exhibit similar latency.
Profile Selection
A profile consists of a specific group of memory registers (see
Table 6). In the AD9858 each profile contains a 32-bit frequency
tuning word and a 14-bit phase-offset word. Each profile is
selectable via two external profile select pins (PS0 and PS1) as
defined in Table 12. The specific mapping of registers to profiles
is detailed in the Register Bit Descriptions section. The user
should be aware that selection of a profile is internally
synchronized with DDS CLK using the SYNCLK timing. That
is, SYNCLK is used to synchronize the assertion of the profile
select pins (PS0, PS1). Therefore, the PS0 and PS1 pins must be
set up and held around the rising edge of SYNCLK. The PS0
and PS1 inputs are designed for zero hold time and 3.5 ns
setup time.
Table 12.
PS1 PS0 Profile
0 0 0
0 1 1
1 0 2
1 1 3
The profiles are available to the user to provide rapid changing
of device parameters via external hardware, which alleviates the
speed limitations imposed by the I/O port. For example, the
user might preprogram the four phase offset registers with
values that correspond to phase increments of 90°. By
controlling the PS0 and PS1 pins, the user can implement π/2
phase modulation. The data modulation rate would be much
higher than that possible by repeatedly reloading a single phase-
offset register via the I/O port.
AD9858
Rev. A | Page 29 of 32
AD9858 APPLICATION SUGGESTIONS
DAC FILTER
PHASE/
FREQUENCY
DETECTOR
150MHz
DIVIDER
1/2/4
DIVIDER
1/2
ANALOG
MIXER
CHARGE PUMP
0.5mA–2mA
(0.5mA STEPS)
PLL
LOOP
FILTER
FIXED
LOOP
(LO1)
DDS
1000MSPS
FREQUENCY
TUNING WORD DC–400MHz
2GHz
2GHz ±150MHz
AD9858
2GHz
DDS/DAC
CLOCK 1000MHz
F
REF
DC–150MHz
1032
FILTER
VCO
03166-A-040
Figure 37. DDS Synthesizer Translation Loop Oscillator (Implemented in Translation Loop Evaluation Board)
DAC FILTER
PHASE/
FREQUENCY
DETECTOR
150MHz
DIVIDER
1/2/4 CHARGE PUMP
0.5mA–2mA
(0.5mA STEPS) LOOP
FILTER
DDS
1000MSPS
FREQUENCY
TUNING WORD DC–400MHz
VCO
DDS/DAC CLOCK
AD9858
F = MxF
REF
03166-A-041
F
REF
DC–150MHz
1032
DIVIDER
Figure 38. DDS Synthesizer Single-Loop PLL Up-Conversion
DAC
FILTER
PHASE/
FREQUENCY
DETECTOR
150MHz
DDS
1000MSPS
DIVIDER
1/2/4
DIVIDER
1/2
CHARGE PUMP
0.5mA–2mA
(0.5mA STEPS) LOOP
FILTER
150MHz
REFERENCE
FREQUENCY
TUNING WORD
150MHz
1000
MHz
VCO
2GHz MAX
AD9858
32
03166-A-042
Figure 39. DDS Synthesizer AD9858 as Fractional N Synthesizer (Implemented in Fractional Divide Evaluation Board)
AD9858
Rev. A | Page 30 of 32
EVALUATION BOARDS
The AD9858 has three different evaluation board designs. The
first design is the traditional DDS evaluation board. In this
design, the DDS is clocked and the output is taken directly from
the DAC. The analog mixer and PLL blocks are made available
for separate evaluation.
The second design is a fractional-divide loop. This evaluation
board was designed to incorporate the DDS, the phase-detector,
and the charge pump. In this application, the DDS is used in a
PLL loop. Unlike a fixed divider used in traditional PLL loops,
the output signal is divided and fed back to the phase detector
by the DDS. To do this, the output signal of the PLL loop is fed
to the DDS as REFCLK. The DDS is programmed to match the
reference input frequency. Because the DDS output frequency
can take on 232 potential values between 0 Hz and one half of
the PLL loop output frequency, this enables frequency
resolution on the order of 470 MHz, assuming a PLL loop
output frequency of 2 GHz.
The third design is a translation loop or offset loop. In this
design, the RF mixer is incorporated into the feedback path of
the loop. This allows direct up-conversion to the transmission
frequency.
The three evaluation boards have separate schematics, BOMS,
and instructions. See www.analog.com/dds for more
information.
Table 13.
Part Number Description
AD9858PCB AD9858 Frequency Synthesizer Board
AD9858FDPCB AD9858 Fractional-Divide Loop Frequency
Synthesizer Board
AD9858TLPCB AD9858 Translation Loop Frequency
Synthesizer Board
AD9858
Rev. A | Page 31 of 32
OUTLINE DIMENSIONS
0.27
0.22
0.17
1
2526 49
76100 75
50
14.00 SQ
16.00 SQ
0.50 BSC
1.05
1.00
0.95
0.15
0.05
0.75
0.60
0.45
SEATING
PLANE
1.20
MAX
TOP VIEW
(PINS DOWN)
0.20
0.09
7°
3.5°
0°
9.50 SQ
COPLANARITY
0.08
1
25
2649
76 100
75
50
BOTTOM
VIEW
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
Figure 40. 100-Lead Thin Plastic Quad Flat Package, Exposed Pad [TQFP/EP]
(SV-100)
Dimensions shown in millimeters
WARNING
EPAD (thermal slug) must be attached to ground plane for some other large metal mass for thermal transfer. Failure to do so may cause
excessive die temperature rise and damage to the device.
ORDERING GUIDE
Models Temperature Range Package Description Package Option
AD9858BSV –40°C to +85°C 100-Lead EPAD SV-100
AD9858PCB 25°C Generic Evaluation Board
AD9858FDPCB 25°C Fractional-Divide Evaluation Board
AD9858TLPCB 25°C Translation Loop Evaluation Board
AD9858
Rev. A | Page 32 of 32
NOTES
© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03166–0–11/03(A)
