8-Bit, High Speed, Multiplying
D/A Converter
Data Sheet
DAC08
Rev. D Document Feedback
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FEATURES
Fast settling output current: 85 ns
Full-scale current prematched to ±1 LSB
Direct interface to TTL, CMOS, ECL, HTL, PMOS
Nonlinearity to 0.1% maximum over temperature range
High output impedance and compliance: −10 V to +18 V
Complementary current outputs
Wide range multiplying capability: 1 MHz bandwidth
Low FS current drift: ±10 ppm/°C
Wide power supply range: ±4.5 V to ±18 V
Low power consumption: 33 mW at ±5 V
Low cost
GENERAL DESCRIPTION
The DAC08 series of 8-bit monolithic digital-to-analog convert-
ers provide very high speed performance coupled with low cost
and outstanding applications flexibility.
Advanced circuit design achieves 85 ns settling times with very
low glitch energy and at low power consumption. Monotonic
multiplying performance is attained over a wide 20 to 1 reference
current range. Matching to within 1 LSB between reference and
full-scale currents eliminates the need for full-scale trimming in
most applications.
Direct interface to all popular logic families with full noise
immunity is provided by the high swing, adjustable threshold
logic input.
High voltage compliance complementary current outputs are
provided, increasing versatility and enabling differential operation
to effectively double the peak-to-peak output swing. In many
applications, the outputs can be directly converted to voltage
without the need for an external op amp. All DAC08 series models
guarantee full 8-bit monotonicity, and nonlinearities as tight as
±0.1% over the entire operating temperature range are available.
Device performance is essentially unchanged over the ±4.5 V to
±18 V power supply range, with 33 mW power consumption
attainable at ±5 V supplies.
The compact size and low power consumption make the DAC08
attractive for portable and military/aerospace applications;
devices processed to MIL-STD-883, Level B are available.
DAC08 applications include 8-bit, 1 µs A/D converters, servo
motor and pen drivers, waveform generators, audio encoders
and attenuators, analog meter drivers, programmable power
supplies, LCD display drivers, high speed modems, and other
applications where low cost, high speed, and complete
input/output versatility are required.
FUNCTIONAL BLOCK DIAGRAM
00268-C-001
V
REF
(+) 14
15
V+ V
LC
(MSB)
B1 B2 B3 B4 B5 B6 B7 (LSB)
B8
13 1 5 6 7 8 9 10 11 12
V–
COMP
316
4
2
I
OUT
I
OUT
BIAS
NETWORK
CURRENT
SWITCHES
V
REF
(–)
REFERENCE
AMPLIFIER
DAC08
Figure 1.
DAC08* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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DOCUMENTATION
Application Notes
•AN-17: DAC08 Applications Collection
•AN-19: Differential and Multiplying D/A Converter
Applications
•AN-21: 4-20 mA Digital-to-Process Current Transmitter
•AN-23: D/A Converter Generates Hyperbolic Functions
•AN-6: Single Supply Operation of the DAC08
Data Sheet
•DAC08: 8-Bit, High Speed, Multiplying D/A Converter
(Universal Digital Logic Interface) Data Sheet
•DAC08: Military Data Sheet
SOFTWARE AND SYSTEMS REQUIREMENTS
•JAN to Generic Cross Reference
REFERENCE MATERIALS
Solutions Bulletins & Brochures
•Digital to Analog Converters ICs Solutions Bulletin
DESIGN RESOURCES
•DAC08 Material Declaration
•PCN-PDN Information
•Quality And Reliability
•Symbols and Footprints
DISCUSSIONS
View all DAC08 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
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number.
DOCUMENT FEEDBACK
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DAC08 Data Sheet
Rev. D | Page 2 of 21
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Typical Electrical Characteristics ............................................... 4
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Test and Burn-In Circuits ................................................................ 7
Typical Performance Characteristics ............................................. 8
Basic Connections .......................................................................... 11
Application Information ................................................................ 14
Reference Amplifier Setup ........................................................ 14
Reference Amplifier Compensation for Multiplying
Applications ................................................................................ 14
Logic Inputs................................................................................. 14
Analog Output Currents ........................................................... 14
Power Supplies ............................................................................ 15
Temperature Performance......................................................... 15
Multiplying Operation ............................................................... 15
Settling Time ............................................................................... 15
Analog Devices Current Output DACs ....................................... 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 19
REVISION HISTORY
3/16—Rev. C to Rev. D
Added Thermal Resistance Section ............................................... 5
Changes to Table 4 ............................................................................ 5
Change to Figure 29 ....................................................................... 12
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 10
11/04—Rev. B to Rev. C
Changed SO to SOIC ......................................................... Universal
Removed DIE ...................................................................... Universal
Changes to Figure 30, Figure 31, Figure 32 ................................. 12
Change to Figure 33 ....................................................................... 15
Added Table 4 .................................................................................. 16
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 18
2/02—Rev. A to Rev. B
Edits to Specifications ....................................................................... 2
Edits to Absolute Maximum Ratings .............................................. 3
Edits to Ordering Guide ................................................................... 3
Edits to Wafer Test Limits ................................................................ 5
Edit to Figure 13 ................................................................................ 8
Edits to Figures 14 and 15 ................................................................ 9
Data Sheet DAC08
Rev. D | Page 3 of 21
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VS = ±15 V, IREF = 2.0 mA, –55°C ≤ TA ≤ +125°C for DAC08/DAC08A, 0°C ≤ TA ≤ +70°C for DAC08E and DAC08H, −40°C to +85°C for
DAC08C, unless otherwise noted. Output characteristics refer to both IOUT and IOUT.
Table 1.
Parameter Symbol Test Conditions/Comments
DAC08A/DAC08H DAC08E DAC08C
Unit Min Typ Max Min Typ Max Min Typ Max
RESOLUTION 8 8 8 Bits
MONOTONICITY
8
8
8
Bits
NONLINEARITY NL
±0.1
±0.19
±0.39
%FS
SETTLING TIME tS To ±1/2 LSB, all bits switched
on or off, TA = 25°C1
85 135 85 150 85 150 ns
PROPAGATION DELAY
Each Bit
t
PLH
T
A
= 25°C
1
60
60
60
ns
All Bits Switched tPHL
35 60
35 60
35 60 ns
FULL-SCALE TEMPCO1 TCIFS
±10 ±50
±10 ±80
±10 ±80 ppm/°C
DAC08E
±50
OUTPUT VOLTAGE
Compliance VOC Full-scale current
(True Compliance)
Change <1/2 LSB, ROUT >
20 MΩ typ
−10
+18 −10
+18 –10
+18 V
FULL RANGE CURRENT
I
FR4
V
REF
= 10.000 V R14, R15 =
5.000 kΩ TA = 25°C
1.984
2.000
1.94
2.04
1.94
2.04
mA
FULL RANGE
SYMMETRY
IFRS IFR4 − IFR2 ±0.5 ±4 ±1 ±8 ±2 ±16 µA
ZERO-SCALE CURRENT IZS
0.1 1
0.2 2
0.2 4 µA
OUTPUT CURRENT
RANGE
IOR1 R14, R15 = 5.000 kΩ 2.1
2.1
2.1
mA
IOR2 VREF = +15.0 V, V− = −10 V
VREF = +25.0 V, 4.2 4.2 4.2 mA
V− = −12 V
OUTPUT CURRENT
NOISE
IREF = 2 mA
25
25
25
nA
LOGIC INPUT LEVELS
Logic 0
V
IL
V
LC
= 0 V
0.8
0.8
0.8
V
Logic 1 VIL 2 2 2 V
LOGIC INPUT CURRENT
VLC = 0 V
Logic 0 IIL VIN = −10 V to +0.8 V
−2 −10
−2 −10
−2 −10 µA
Logic 1 IIH VIN = 2.0 V to 18 V
0.002 10
0.002 10
0.002 10 µA
LOGIC INPUT SWING VIS V− = −15 V −10
+18 −10
+18 −10
+18 V
LOGIC THRESHOLD
RANGE
VTHR VS = ±15 V1 −10
+13.5 −10
+13.5 −10
+13.5
V
REFERENCE BIAS
CURRENT
I15
−1 −3
−1 −3
−1 −3 µA
REFERENCE INPUT dI/dt REQ = 200 Ω 4 8
4 8
4 8
mA/µs
SLEW RATE
RL = 100 Ω
CC = 0 pF. See Figure 7.1
DAC08 Data Sheet
Rev. D | Page 4 of 21
Parameter Symbol Test Conditions/Comments
DAC08A/DAC08H DAC08E DAC08C
Unit Min Typ Max Min Typ Max Min Typ Max
POWER SUPPLY
SENSITIVITY
PSSIFS+ V+ = 4.5 V to 18 V
±0.0003 ±0.01
±0.0003 ±0.01
±0.0003 ±0.01
%∆IO/
%∆V+
PSSIFS– V− = −4.5 V to −18 V ±0.002 ±0.01 ±0.002 ±0.01 ±0.002 ±0.01
%∆IO/
%∆V−
IREF = 1.0 mA
POWER SUPPLY
CURRENT
I+
V
S
= ±5 V, I
REF
= 1.0 mA
3.8
3.8
3.8
mA
I−
−4.3 −5.8
−4.3 −5.8
−4.3 −5.8 mA
I+ VS = +5 V, −15 V
2.4 3.8
2.4 3.8
2.4 3.8 mA
I− IREF = 2.0 mA
−6.4 −7.8
−6.4 −7.8
−6.4 −7.8 mA
I+ VS = ±15 V 2.5 3.8 2.5 3.8 2.5 3.8 mA
I−
I
REF
= 2.0 mA
−7.8
−7.8
−7.8
mA
POWER DISSIPATION PD ±5 V, IREF = 1.0 mA +5 V,
−15 V
33 48
33 48
33 48 mW
IREF = 2.0 mA ±15 V, IREF =
2.0 mA
108 136
103 136
108 136 mW
135 174
135 174
135 174 mW
1 Guaranteed by design.
TYPICAL ELECTRICAL CHARACTERISTICS
VS = ±15 V, and IREF = 2.0 mA, unless otherwise noted. Output characteristics apply to both IOUT and IOUT.
Table 2.
Parameter Symbol Test Conditions/Comments All Grades Typical Unit
REFERENCE INPUT SLEW RATE dI/dt 8 mA/µs
PROPAGATION DELAY tPLH, tPHL TA = 25°C, any bit 35 ns
SETTLING TIME tS To ±1/2 LSB, all bits switched on or
off, TA = 25°C
85 ns
Data Sheet DAC08
Rev. D | Page 5 of 21
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Operating Temperature
DAC08AQ, DAC08Q −55°C to +125°C
DAC08HQ, DAC08EQ, DAC08CQ 0°C to +70°C
DAC08CP, DAC08CS −40°C to +85°C
Junction Temperature (TJ) −65°C to +150°C
Storage Temperature Q Package −65°C to +150°C
Storage Temperature P Package −65°C to +125°C
Lead Temperature (Soldering, 60 sec) 300°C
V+ Supply to V− Supply 36 V
Logic Inputs V− to V− + 36 V
VLC V− to V+
Analog Current Outputs (at VS− = 15 V) 4.25 mA
Reference Input (V14 to V15) V− to V+
Reference Input Differential Voltage
(V14 to V15) ±18 V
Reference Input Current (I14) 5.0 mA
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for worst case mounting conditions, that is, θJA is
specified for device in socket for CERDIP, PDIP, and LCC
packages; θJA is specified for device soldered to printed circuit
board for SOIC package.
Table 4. Thermal Resistance
Package Type θJA θ
JC Unit
16-Lead CERDIP (Q) 100 16 °C/W
16-Lead PDIP (P) 82 39 °C/W
20-Terminal LCC (RC) 76 36 °C/W
16-Lead SOIC (S) 111 35 °C/W
ESD CAUTION
DAC08 Data Sheet
Rev. D | Page 6 of 21
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
00268-C-002
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
LC
V–
I
OUT
(MSB) B1
B2
B3
B4
COMP
V
REF
(–)
V
REF
(+)
V+
B8 (LSB)
B7
B6
B5
DAC08
TOP VIEW
(Not To Scale)
I
OUT
Figure 2. 16-Lead Dual In-Line Package (PDIP and CERDIP)
00268-C-003
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V+
VREF (+)
VREF (–)
COMP
VLC
V–
IOUT
B8 (LSB)
B7
B6
B5
B4
B3
B2
B1 (MSB)
DAC08
TOP VIEW
(Not To Scale)
IOUT
Figure 3. 16-Lead Standard Small Outline Package (SOIC_N)
00268-C-004
4
5
6
7
8
18
17
16
15
14
20 19123
910 11 12 13
VREF
(+)
B3
V
LC
NC
V
REF
(–)
NC = NO CONNECT
COMP
V+
NC
B7
I
OUT
V–
I
OUT
NC
(MSB) B1
B2
B4
NC
B5
B6
B8 (LSB)
DAC08
TOP VIEW
(Not To Scale)
Figure 4. DAC08RC/883 20-Terminal Ceramic Leadless Chip Carrier (LCC)
Data Sheet DAC08
Rev. D | Page 7 of 21
TEST AND BURN-IN CIRCUITS
00268-C-006
0V
TYPICALVALUES:
R
IN
=5kΩ
+V
IN
=10V
4
2
14
15 16
OPTIONAL RESISTOR
FOR OFFSET INPUTS RL
RL
RREF
+VREF
RIN
200Ω
RP
NO CAP
REQ ≈
Figure 5. Pulsed Reference Operation
00268-C-007
16 15 14 13 12 11 10 9
DAC08
C1 R1
C2 +18V
C3
R1 = 9kΩ
C1 = 0.001µF
C2, C3 = 0.01µF
–18V MIN
1 2 3 4 5 6 7 8
Figure 6. Burn-In Circuit
DAC08 Data Sheet
Rev. D | Page 8 of 21
TYPICAL PERFORMANCE CHARACTERISTICS
00268-C-008
2.5V
0.5V
–0.5mA
I
OUT
–2.5mA
200ns/DIVISION
R
EQ
≈ 200Ω
R
L
= 100Ω
C
C
= 0
1V
100mV 200ns
Figure 7. Fast Pulsed Reference Operation
00268-C-009
0mA
1.0mA
2.0mA
(0000|0000) (1111|1111)
I
REF
= 2mA
I
OUT
I
OUT
Figure 8. True and Complementary Output Operation
00268-C-010
50ns/DIVISION
100mV
2V
50ns
5mV
2.4V
0.4V
0V
8µA
0
Figure 9. LSB Switching
00268-C-011
SETTLINGTIMEFIXTURE
IFS=2mA,RL=1kΩ
1/2LSB=4µA
50ns/DIVISION
ALL BITS SWITCHED ON
10mV 50ns
1V
2.4V
0.4V
–1/2LSB
0V
+1/2LSB
OUTPUT
SETTLING
Figure 10. Full-Scale Settling Time
00268-C-012
I
REF
, REFERENCE CURRENT (mA)
I
FS
, OUTPUT CURRENT (mA)
5
0
4
3
2
1
01 2 3 4 5
T
A
= T
MIN
TO T
MAX
ALL BITS HIGH
LIMIT FOR
V– = –5V
LIMIT FOR
V– = –15V
Figure 11. Full-Scale Current vs. Reference Current
00268-C-013
IFS, OUTPUT FULL-SCALE CURRENT (mA)
PROPAGATION DELAY (ns)
500
400
300
200
100
00.005 0.02 0.10 0.50 2.00
1LSB = 7.8µA
1LSB = 61nA
10.00
0.01 0.05 0.20 1.00 5.00
Figure 12. LSB Propagation Delay vs. IFS
Data Sheet DAC08
Rev. D | Page 9 of 21
00268-C-014
FREQUENCY (MHz)
RELATIVE OUTPUT (dB)
10
0.1
8
6
4
2
–14 0.2 0.5 1.0 2.0 10.0
2
0
–2
–4
–6
–8
–10
–12
1
5.0
R14 = R15 = 1kΩ
R
L
≤
500V
ALL BITS ON
V
R15
= 0V
C
C
= 15pF, V
IN
= 2.0V p-p
CENTERED AT +1.0V
LARGE SIGNAL
C
C
= 15pF, V
IN
= 50mV p-p
CENTERED AT +200mV
SMALL SIGNAL
Figure 13. Reference Input Frequency Response
00268-C-015
V
15
, REFERENCE COMMON-MODE VOLTAGE (V)
OUTPUT CURRENT (mA)
4.0
–14
3.6
3.2
2.8
2.4
018
2.0
1.6
1.2
0.8
0.4
–10 –6
T
A
= T
MIN
TO T
MAX
NOTE: POSITIVE COMMON-MODE
RANGE IS ALWAYS (V+) –1.5V
I
REF
= 2mA
V– = –15V V– = –5V V+ = +15V
ALL BITS ON
I
REF
= 1mA
I
REF
= 0.2mA
–2 2 6 10 14
Figure 14. Reference Amplifier Common-Mode Range
00268-C-016
LOGIC INPUT VOLTAGE (V)
LOGIC INPUT (µA)
10
–12
8
6
0
4
2
–8 –4 0 4 8 12 16
Figure 15. Logic Input Current vs. Input Voltage
00268-C-017
TEMPERATURE (°C)
VTH–VLC (V)
2.0
–50
1.6
1.2
0
0.8
0.4
0 50 100 150
Figure 16. VTH − VLC vs. Temperature
00268-C-018
OUTPUTVOLTAGE(V)
OUTPUT CURRENT (mA)
4.0
–14
3.6
3.2
2.8
2.4
018
2.0
1.6
1.2
0.8
0.4
–10 –6
T
A
= T
MIN
TO T
MAX
I
REF
= 1mA
I
REF
= 0.2mA
–2 2 6 10 14
V– = –15V V– = –5V I
REF
= 2mA
ALL BITS ON
Figure 17. Output Current vs. Output Voltage (Output Voltage Compliance)
00268-C-019
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
28
24
20
16
12
–12
8
4
0
–4
–8
–50 0 50 100 150
SHADED AREA INDICATES PERMISSIBLE
OUTPUT VOLTAGE RANGE FOR V– = –15V.
I
REF
≤ 2.0mA.
FOR OTHER V– OR I
REF
,
SEE OUTPUT CURRENT VS. OUTPUT
VOLTAGE CURVE.
Figure 18. Output Voltage Compliance vs. Temperature
DAC08 Data Sheet
Rev. D | Page 10 of 21
00268-C-020
LOGIC INPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
1.8
1.6
1.4
1.2
0
1.0
0.8
0.6
0.4
0.2
–12 0 4 8 16–8
B4 B5
–4 12
����
B3
B1
V– = –5V
V– = –15V
B2
I
REF
= 2.0mA
NOTE:
B1 THROUGH B8 HAVE IDENTICAL TRANSFER
CHARACTERISTICS. BITS ARE FULLY SWITCHED WITH LESS
THAN 1/2 LSB ERROR, AT LESS THAN ±100mV FROM ACTUAL
THRESHOLD. THESE SWITCHING POINTS ARE GUARANTEED
TO LIE BETWEEN 0.8V AND 2.0V OVER THE OPERATING
TEMPERATURE RANGE (V
LC
= 0.0V).
Figure 19. Bit Transfer Characteristics
00268-C-021
V+, POSITIVE POWER SUPPLY (V dc)
POWER SUPPLY CURRENT (mA)
10
8
7
6
0
5
4
3
2
1
2
9
4 6 8 12 14 16 18
I–
I+
ALL BITS HIGH OR LOW
0 10 20
Figure 20. Power Supply vs. V+
00268-C-022
V–, NEGATIVE POWER SUPPLY (V dc)
POWER SUPPLY CURRENT (mA)
10
8
7
6
0
5
4
3
2
1
0 –20
–2
9
–4–6–8 –10 –12 –14 –16 –18
I+
BITS MAY BE HIGH OR LOW
I– WITH I
REF
= 2mA
I– WITH I
REF
= 1mA
I– WITH I
REF
= 0.2mA
Figure 21. Power Supply Current vs. V−
00268-C-023
TEMPERATURE (°C)
POWER SUPPLY CURRENT (mA)
10
9
8
7
6
0
5
4
3
2
1
–50 0 50 100 150
I–
I+
ALL BITS HIGH OR LOW
IREF = 2.0mA
V+ = +15V
V– = –15V
Figure 22. Power Supply Current vs. Temperature
Data Sheet DAC08
Rev. D | Page 11 of 21
BASIC CONNECTIONS
00268-C-024
+V
REF
R
REF
I
IN
R
IN
V
IN
14
15
R15
(OPTIONAL)
HIGH INPUT
IMPEDANCE
+V
REF
MUST BE ABOVE PEAK POSITIVE SWING OF V
IN
R
REF
≈R15
I
REF
≥PEAK NEGATIVE SWING OF I
IN
I
REF
R
REF
V
IN
+V
REF
14
15
14
15
Figure 23. Accommodating Bipolar References
00268-C-025
R15
IREF
FOR FIXED REFERENCE,
TTL OPERATION,
TYPICAL VALUES ARE:
VREF = 10.000V
RREF = 5.000kΩ
R15 = R
REF
C
C
= 0.01µF
V
LC
= 0V (GROUND)
MSB
B1B2B3B4B5B6B7
LSB
B8
V–
C
C
COMP
0.1µF
V– V+
VLC
IO
V+
VREF (+)
+VREF RREF
(R14) VREF (–)
14
15
4
2
5678910 11 12
316 13 1IO
0.1µF
IFR =
×
I
O + IO = IFR FOR
ALL LOGIC STATES
+VREF
RREF
255
256
Figure 24. Basic Positive Reference Operation
00268-C-026
I
REF
= 2.000mA
MSB
B1 B2 B3 B4 B5 B6 B7LSB
B8
5.000kΩ
E
O
E
O
5.000kΩ
4
2
I
O
I
O
14
FULL RANGE
HALF SCALE +LSB
HALF SCALE
HALF SCALE –LSB
ZERO SCALE +LSB
ZERO SCALE
B1
1
1
1
0
0
0
B2
1
0
0
1
0
0
B3
1
0
0
1
0
0
B4
1
0
0
1
0
0
B5
1
1
1
0
0
0
B6
1
0
0
1
0
0
B7
1
0
0
1
0
0
B8
1
1
0
1
1
0
I
O
1.992
1.008
1.000
0.992
0.008
0.000
I
O
0.000
0.984
0.992
1.000
1.984
1.992
E
O
–9.960
–5.040
–5.000
–4.960
–0.040
0.000
E
O
–0.000
–4.920
–4.960
–5.000
–9.920
–9.960
Figure 25. Basic Unipolar Negative Operation
00268-C-027
I
REF
= 2.000mA
MSB
B1 B2 B3 B4 B5 B6 B7LSB
B8
10V
10kΩ10kΩ
E
O
E
O
4
2
I
O
I
O
14
POS. FULL RANGE
POS. FULL RANGE –LSB
ZERO SCALE +LSB
ZERO SCALE
ZERO SCALE –LSB
NEG. FULL SCALE +LSB
NEG. FULL SCALE
B1
1
1
1
1
0
0
0
B2
1
1
0
0
1
0
0
B3
1
1
0
0
1
0
0
B4
1
1
0
0
1
0
0
B5
1
1
0
0
1
0
0
B6
1
1
0
0
1
0
0
B7
1
1
0
0
1
0
0
B8
1
0
1
0
1
1
0
E
O
–9.920
–9.840
–0.080
0.000
+0.080
+9.920
+10.000
E
O
+10.000
+9.920
+0.160
+0.080
0.000
–9.840
–9.920
Figure 26. Basic Bipolar Output Operation
DAC08 Data Sheet
Rev. D | Page 12 of 21
00268-C-028
APPROX
5kΩ
≈1V
I
REF
(+) ≈2mA
39kΩ
10kΩ
POT
LOW T.C.
4.5kΩ
V
REF
10V 14
15
Figure 27. Recommended Full-Scale Adjustment Circuit
00268-C-029
R
REF
I
O
I
O
R15
–V
REF
I
FS
≈–V
REF
R
REF
NOTE
R
REF
SETS I
FS
; R15 IS FOR
BIAS CURRENT CANCELLATION.
14
15
4
2
Figure 28. Basic Negative Reference Operation
00268-C-030
E
O
*OR ADR01
4
26
5
10kΩ
+15V –15V –15V
+15V
5.0kΩ
15V MSB
B1 B2 B3 B4 B5 B6 B7LSB
B8
5.000kΩ
5.0kΩ
POS. FULL RANGE
ZERO SCALE
NEG. FULL SCALE +1LSB
NEG. FULL SCALE
B1
1
1
0
0
B2
1
0
0
0
B3
1
0
0
0
B4
1
0
0
0
B5
1
0
0
0
B6
1
0
0
0
B7
1
0
0
0
B8
1
0
1
0
E
O
+4.960
0.000
–4.960
–5.000
10V
REF01*
V
O
–V
4
2
I
O
I
O
V+ C
CVLC
AD8671
Figure 29. Offset Binary Operation
00268-C-031
I
O
R
L
I
O
E
O
0 TO –I
FR
×
R
L
I
FR
= I
REF
255
256
4
2AD8671
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC).
CONNECT INVERTING INPUT OF OP AMP TO I
O
(PIN 2): CONNECT I
O
(PIN 4)
TO GROUND.
Figure 30. Positive Low Impedance Output Operation
00268-C-032
I
O
R
L
I
O
E
O
0 TO –I
FR
×
R
L
I
FR
= I
REF
255
256
4
2
AD8671
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC).
CONNECT NONINVERTING INPUT OF OP AMP TO I
O
(PIN 2): CONNECT I
O
(PIN 4)
TO GROUND.
Figure 31. Negative Low Impedance Output Operation
Data Sheet DAC08
Rev. D | Page 13 of 21
00268-C-033
1
TTL, DTL,
V
TH
= 1.4V
15V
9.1kΩ
6.2kΩ0.1µF
V
LC
13kΩ
39kΩ
ECL
"A"
3kΩTO PIN 1
V
LC
6.2kΩ
–5.2V
20kΩ
20kΩ
V+
"A"
3kΩTO PIN 1
V
LC
R3
400µA
CMOS, HTL,NMOS
TEMPERATURE COMPENSATING V
LC
CIRCUITS
V
TH
= V
LC
1.4V
15V CMOS
V
TH
= 7.6V
V
LC
2N3904 2N3904 2N3904 2N3904
Figure 32. Interfacing with Various Logic Families
DAC08 Data Sheet
Rev. D | Page 14 of 21
APPLICATION INFORMATION
REFERENCE AMPLIFIER SETUP
The DAC08 is a multiplying D/A converter in which the output
current is the product of a digital number and the input reference
current. The reference current may be fixed or may vary from
nearly zero to 4.0 mA. The full-scale output current is a linear
function of the reference current and is given by
REFFR II 256
255
where IREF = I14
In positive reference applications, an external positive reference
voltage forces current through R14 into the VREF(+) terminal (Pin 14)
of the reference amplifier. Alternatively, a negative reference may be
applied to VREF(–) at Pin 15; reference current flows from ground
through R14 into VREF(+) as in the positive reference case. This
negative reference connection has the advantage of a very high
impedance presented at Pin 15. The voltage at Pin 14 is equal to
and tracks the voltage at Pin 15 due to the high gain of the internal
reference amplifier. R15 (nominally equal to R14) cancels bias
current errors; R15 may be eliminated with only a minor
increase in error.
Bipolar references may be accommodated by offsetting VREF or
Pin 15. The negative common-mode range of the reference
amplifier is given by VCM – = V− plus (IREF × 1 kΩ) plus 2.5 V.
The positive common-mode range is V+ less 1.5 V.
When a dc reference is used, a reference bypass capacitor is
recommended. A 5.0 V TTL logic supply is not recommended
as a reference. If a regulated power supply is used as a reference,
R14 must be split into two resistors with the junction bypassed
to ground with a 0.1 μF capacitor.
For most applications, the tight relationship between IREF and IFS
eliminates the need for trimming IREF. If required, full-scale
trimming can be accomplished by adjusting the value of R14, or
by using a potentiometer for R14. An improved method of full-
scale trimming that eliminates potentiometer T.C. effects is shown
in the recommended full-scale adjustment circuit (Figure 27).
Using lower values of reference current reduces negative power
supply current and increases reference amplifier negative common-
mode range. The recommended range for operation with a dc
reference current is 0.2 mA to 4.0 mA.
REFERENCE AMPLIFIER COMPENSATION FOR
MULTIPLYING APPLICATIONS
AC reference applications require the reference amplifier to be
compensated using a capacitor from Pin 16 to V−. e value of
this capacitor depends on the impedance presented to Pin 14;
for R14 values of 1.0 kΩ, 2.5 kΩ, and 5.0 kΩ, minimum values
of CC are 15 pF, 37 pF, and 75 pF. Larger values of R14 require
proportionately increased values of CC for proper phase margin,
so the ratio of CC (pF) to R14 (kΩ) = 15.
For fastest response to a pulse, low values of R14 enabling small
CC values must be used. If Pin 14 is driven by a high impedance
such as a transistor current source, none of the preceding values
suffice, and the amplifier must be heavily compensated, which
decreases overall bandwidth and slew rate. For R14 = 1 kΩ and
CC = 15 pF, the reference amplifier slews at 4 mA/μs, enabling a
transition from IREF = 0 to IREF = 2 mA in 500 ns.
Operation with pulse inputs to the reference amplifier can be
accommodated by an alternate compensation scheme. This
technique provides lowest full-scale transition times. An internal
clamp allows quick recovery of the reference amplifier from a
cutoff (IREF = 0) condition. Full-scale transition (0 mA to 2 mA)
occurs in 120 ns when the equivalent impedance at Pin 14 is 200 Ω
and CC = 0. This yields a reference slew rate of 16 mA/μs, which
is relatively independent of the RIN and VIN values.
LOGIC INPUTS
The DAC08 design incorporates a unique logic input circuit that
enables direct interface to all popular logic families and provides
maximum noise immunity. This feature is made possible by the
large input swing capability, 2 μA logic input current, and
completely adjustable logic threshold voltage. For V− = −15 V, the
logic inputs may swing between −10 V and +18 V. This enables
direct interface with 15 V CMOS logic, even when the DAC08
is powered from a 5 V supply. Minimum input logic swing and
minimum logic threshold voltage are given by
V− + (IREF × 1 kΩ) + 2.5 V
The logic threshold may be adjusted over a wide range by
placing an appropriate voltage at the logic threshold control pin
(Pin 1, VLC). Figure 16 shows the relationship between VLC and
VTH over the temperature range, with VTH nominally 1.4 above
VLC. For TTL and DTL interface, simply ground Pin 1. When
interfacing ECL, an IREF = 1 mA is recommended. For interfacing
other logic families, see Figure 32. For general set-up of the logic
control circuit, note that Pin 1 sources 100 μA typical; external
circuitry must be designed to accommodate this current.
Fastest settling times are obtained when Pin 1 sees a low
impedance. If Pin 1 is connected to a 1 kΩ divider, for example,
it must be bypassed to ground by a 0.01 μF capacitor.
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are provided
where IO + IO = IFS. Current appears at the true (IO) output when
a 1 (logic high) is applied to each logic input. As the binary count
increases, the sink current at Pin 4 increases proportionally, in
the fashion of a positive logic DAC. When a 0 is applied to any
input bit, that current is turned off at Pin 4 and turned on at Pin 2.
A decreasing logic count increases IO as in a negative or inverted
logic DAC. Both outputs may be used simultaneously.
Data Sheet DAC08
Rev. D | Page 15 of 21
If one of the outputs is not required, it must be connected to
ground or to a point capable of sourcing IFS; do not leave an
unused output pin open.
Both outputs have an extremely wide voltage compliance
enabling fast direct current to voltage conversion through a
resistor tied to ground or other voltage source. Positive compli-
ance is 36 V above V− and is independent of the positive supply.
Negative compliance is given by
V− + (IREF × 1 kΩ) + 2.5 V
The dual outputs enable double the usual peak-to-peak load
swing when driving loads in quasi-differential fashion. This
feature is especially useful in cable driving, CRT deflection and
in other balanced applications such as driving center-tapped
coils and transformers.
POWER SUPPLIES
The DAC08 operates over a wide range of power supply voltages
from a total supply of 9 V to 36 V. When operating at supplies
of ±5 V or lower, IREF ≤ 1 mA is recommended. Low reference
current operation decreases power consumption and increases
negative compliance (Figure 11), reference amplifier negative
common-mode range (Figure 14), negative logic input range
(Figure 15), and negative logic threshold range (Figure 16). For
example, operation at −4.5 V with IREF = 2 mA is not recommended
because negative output compliance reduces to near zero.
Operation from lower supplies is possible; however, at least
8 V total must be applied to ensure turn on of the internal bias
network.
Symmetrical supplies are not required, as the DAC08 is quite
insensitive to variations in supply voltage. Battery operation is
feasible because no ground connection is required; however, an
artificial ground can ensure logic swings, etc., remain between
acceptable limits. Power consumption is calculated as follows:
() ( ) ( ) ( )
−−
+++= VIV
IPD
A useful feature of the DAC08 design is that supply current is
constant and independent of input logic states. This is useful in
cryptographic applications and further reduces the size of the
power supply bypass capacitors.
TEMPERATURE PERFORMANCE
The nonlinearity and monotonicity specifications of the DAC08
are guaranteed to apply over the entire rated operating temperature
range. Full-scale output current drift is low, typically ±10 ppm/°C,
with zero-scale output current and drift essentially negligible
compared to 1/2 LSB.
The temperature coefficient of the reference resistor R14 must
match and track that of the output resistor for minimum overall
full-scale drift. Settling times of the DAC08 decrease approximately
10% at –55°C. At +125°C, an increase of about 15% is typical.
The reference amplifier must be compensated by using a capacitor
from Pin 16 to V−. For fixed reference operation, a 0.01 µF
capacitor is recommended. For variable reference applications,
refer to the Reference Amplifier Compensation for Multiplying
Applications section.
MULTIPLYING OPERATION
The DAC08 provides excellent multiplying performance with an
extremely linear relationship between IFS and IREF over a range of
4 µA to 4 mA. Monotonic operation is maintained over a typical
range of IREF from 100 µA to 4.0 mA.
SETTLING TIME
The DAC08 is capable of extremely fast settling times, typically
85 ns at IREF = 2.0 mA. Judicious circuit design and careful board
layout must obtain full performance potential during testing
and application. The logic switch design enables propagation
delays of only 35 ns for each of the 8 bits. Settling time to within
1/2 LSB of the LSB is therefore 35 ns, with each progressively
larger bit taking successively longer. The MSB settles in 85 ns, thus
determining the overall settling time of 85 ns. Settling to 6-bit
accuracy requires about 65 ns to 70 ns. The output capacitance
of the DAC08, including the package, is approximately 15 pF;
therefore the output RC time constant dominates settling time if
RL > 500 Ω.
Settling time and propagation delay are relatively insensitive to
logic input amplitude and rise and fall times, due to the high
gain of the logic switches. Settling time also remains essentially
constant for IREF values. The principal advantage of higher IREF
values lies in the ability to attain a given output level with lower
load resistors, thus reducing the output RC time constant.
Measuring the settling time requires the ability to accurately
resolve ±4 µA; therefore a 1 kΩ load is needed to provide adequate
drive for most oscilloscopes. The settling time fixture shown in
Figure 33 uses a cascade design to permit driving a 1 kΩ load
with less than 5 pF of parasitic capacitance at the measurement
node. At IREF values of less than 1.0 mA, excessive RC damping
of the output is difficult to prevent while maintaining adequate
sensitivity. However, the major carry from 01111111 to 10000000
provides an accurate indicator of settling time. This code change
does not require the normal 6.2 time constants to settle to within
±0.2% of the final value, and thus settling time is observed at
lower values of IREF.
DAC08 switching transients or “glitches” are very low and can
be further reduced by small capacitive loads at the output at a
minor sacrifice in settling time. Fastest operation can be obtained
by using short leads, minimizing output capacitance and load
resistor values, and by adequate bypassing at the supply, reference,
and VLC terminals. Supplies do not require large electrolytic bypass
capacitors because the supply current drain is independent of
input logic states; 0.1 µF capacitors at the supply pins provide
full transient protection.
DAC08 Data Sheet
Rev. D | Page 16 of 21
00268-C-034
R
REF
+15V
I
OUT
V
IN
R15
+V
REF
0.01µF–15V
1kΩ1µF
V
L
MINIMUM
CAPACITANCE
+5V
0.1µF
FORTURN-ON,V
L
=2.7V
FORTURN-OFF,V
L
=0.7V
1kΩ
1µF
2kΩ100kΩ
50µF
V
OUT
1
×
PROBE
15kΩ
–15V
0.1µF
14
15
4
2
5
13
678 9 10 11 12
3 16
0.1µF
0.1µF
DAC08
Q2
0V
0V
+0.4V
–0.4V
Q1
V
CL
0.7V
Figure 33. Settling Time Measurement
Data Sheet DAC08
Rev. D | Page 17 of 21
ANALOG DEVICES, INC., CURRENT OUTPUT DACs
Table 4 lists the latest DACs available from Analog Devices.
Table 5.
Model Bits Outputs Interface Package Comments
AD5425 8 1 SPI, 8-bit load MSOP-10 Fast 8-bit load; see also AD5426
AD5426 8 1 SPI MSOP-10 See also AD5425 fast load
AD5450 8 1 SPI SOT23-8 See also AD5425 fast load
AD5424 8 1 Parallel TSSOP-16
AD5429 8 2 SPI TSSOP-16
AD5428 8 2 Parallel TSSOP-20
AD5432
10
1
SPI
MSOP-10
AD5451 10 1 SPI SOT23-8
AD5433 10 1 Parallel TSSOP-20
AD5439 10 2 SPI TSSOP-16
AD5440 10 2 Parallel TSSOP-24
AD5443 12 1 SPI MSOP-10 See also AD5452 and AD5444
AD5452 12 1 SPI SOT23-8 Higher accuracy version of AD5443; see also AD5444
AD5445 12 1 Parallel TSSOP-20
AD5444 12 1 SPI MSOP-10 Higher accuracy version of AD5443; see also AD5452
AD5449 12 2 SPI TSSOP-16
AD5415 12 2 SPI TSSOP-24 Uncommitted resistors
AD5447 12 2 Parallel TSSOP-24
AD5405 12 2 Parallel LFCSP-40 Uncommitted resistors
AD5453 14 1 SPI SOT23-8
AD5553 14 1 SPI MSOP-8
AD5556 14 1 Parallel TSSOP-28
AD5446 14 1 SPI MSOP-10 MSOP version of AD5453; compatible with AD5443, AD5432, and AD5426
AD5555
14
2
SPI
TSSOP-16
AD5557 14 2 Parallel TSSOP-38
AD5543 16 1 SPI MSOP-8
AD5546 16 1 Parallel TSSOP-28
AD5545 16 2 SPI TSSOP-16
AD5547 16 2 Parallel TSSOP-38
DAC08 Data Sheet
Rev. D | Page 18 of 21
OUTLINE DIMENSIONS
COMPLIANT TO JEDE C S TANDARDS MS- 001-BB
0.022
0.018
0.015
0.150
0.130
0.115
0.070
0.060
0.055
0.021
0.016
0.011
0.045
0.039
0.030
0.195
0.130
0.115
16
18
9
0.100
BSC
0.775
0.755
0.735
0.210
MAX
0.015
MIN
0.280
0.250
0.240
0.430
MAX
0.012
0.010
0.008
0.325
0.310
0.300
0.015
GAUGE
PLANE
03-07-2014-D
SEATING
PLANE
TOP VIEW
SIDE VIEW
END VIEW
PIN 1
INDICATOR
Figure 34. 16-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-16)
Dimensions shown in inches
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.840 (21.34) MAX
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.310 (7.87)
0.220 (5.59)
0.005 (0.13) MIN 0.098 (2.49) MAX
0.100 (2.54) BSC
PIN 1
18
9
16
SEATING
PLANE
0.150
(3.81)
MIN
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
Figure 35. 16-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-16)
Dimensions shown in inches and (millimeters)
Data Sheet DAC08
Rev. D | Page 19 of 21
CONTROLLING DIMENSIONS ARE IN MI LL I MET E RS ; INCH DIM E NS IONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFE RE NCE ON LY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDE C S TANDARDS MS- 012- AC
10.00 ( 0. 3937)
9.80 ( 0. 3858)
16 9
8
16.20 ( 0. 2441)
5.80 ( 0. 2283)
4.00 ( 0. 1575)
3.80 ( 0. 1496)
1.27 ( 0. 0500)
BSC
SEATING
PLANE
0.25 ( 0. 0098)
0.10 ( 0. 0039)
0.51 ( 0. 0201)
0.31 ( 0. 0122)
1.75 ( 0. 0689)
1.35 ( 0. 0531)
0.50 ( 0. 0197)
0.25 ( 0. 0098)
1.27 ( 0. 0500)
0.40 ( 0. 0157)
0.25 ( 0. 0098)
0.17 ( 0. 0067)
COPLANARITY
0.10
8°
0°
060606-A
45°
Figure 36. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
1
20 4
9
8
13
19
14
3
18
BOTTOM
VIEW
0.028 (0.71)
0.022 (0.56)
45° TYP
0.015 (0.38)
MIN
0.055 (1.40)
0.045 (1.14)
0.050 (1.27)
BSC
0.075 (1.91)
REF
0.011 (0.28)
0.007 (0.18)
R TYP
0.095 (2.41)
0.075 (1.90)
0.100 (2.54) REF
0.200 (5.08)
REF
0.150 (3.81)
BSC
0.075 (1.91)
REF
0.358 (9.09)
0.342 (8.69)
SQ
0.358
(9.09)
MAX
SQ
0.100 (2.54)
0.064 (1.63)
0.088 (2.24)
0.054 (1.37)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 37. 20-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-20-1)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1, 2, 3 NL Temperature Range Package Description Package Option No. Parts Per Container
DAC08AQ ±0.10% −55°C to +125°C 16-Lead CERDIP Q-16 25
DAC08AQ/883C ±0.10% −55°C to +125°C 16-Lead CERDIP Q-16 25
DAC08HQ ±0.10% 0°C to 70°C 16-Lead CERDIP Q-16 25
DAC08Q ±0.19% −55°C to +125°C 16-Lead CERDIP Q-16 25
DAC08RC/883C ±0.19% −55°C to +125°C 20-Terminal LCC E-20-1 55
DAC08EQ ±0.19% 0°C to 70°C 16-Lead CERDIP Q-16 25
DAC08ES ±0.19% 0°C to 70°C 16-Lead SOIC R-16 47
DAC08ESZ ±0.19% 0°C to 70°C 16-Lead SOIC R-16 47
DAC08ESZ-REEL ±0.19% 0°C to 70°C 16-Lead SOIC R-16 2500
DAC08CP ±0.39% −40°C to +85°C 16-Lead PDIP N-16 25
DAC08CPZ ±0.39% −40°C to +85°C 16-Lead PDIP N-16 25
DAC08CS ±0.39% −40°C to +85°C 16-Lead SOIC R-16 47
DAC08CS-REEL ±0.39% −40°C to +85°C 16-Lead SOIC R-16 2500
DAC08CSZ ±0.39% −40°C to +85°C 16-Lead SOIC R-16 47
DAC08CSZ-REEL ±0.39% −40°C to +85°C 16-Lead SOIC R-16 2500
DAC08EPZ
±0.19%
0°C to 70°C
16-Lead PDIP
N-16
25
1 Devices processed in total compliance to MIL-STD-883. Consult the factory for the 883 data sheet.
2 For availability and burn-in information on the SOIC package, contact your local sales office.
3 Z = RoHS Compliant Part.
DAC08 Data Sheet
Rev. D | Page 20 of 21
NOTES
Data Sheet DAC08
Rev. D | Page 21 of 21
NOTES
©2002–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00268-0-3/16(D)