REV.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
ADG781/ADG782/ADG783
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: © Analog Devices, Inc.,
2.5 Quad SPST Switches
in Chip Scale Package
FUNCTIONAL BLOCK DIAGRAMS
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG781
SWITCHES SHOWN FOR A LOGIC “1” INPUT
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG782
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG783
FEATURES
1.8 V to 5.5 V Single Supply
Low On Resistance (2.5 Typ)
Low On-Resistance Flatness (0.5 )
–3 dB Bandwidth > 200 MHz
Rail-to-Rail Operation
20-Lead 4 mm 4 mm Chip Scale Package
Fast Switching Times
tON = 16 ns
tOFF = 10 ns
Typical Power Consumption (< 0.01 W)
TTL/CMOS Compatible
For Functionally Equivalent Devices in 16-Lead TSSOP
and SOIC Packages, See ADG711/ADG712/ADG713
APPLICATIONS
Battery Powered Systems
Communication Systems
Sample Hold Systems
Audio Signal Routing
Video Switching
Mechanical Reed Relay Replacement
GENERAL DESCRIPTION
The ADG781, ADG782, and ADG783 are monolithic CMOS
devices containing four independently selectable switches. These
switches are designed on an advanced submicron process that
provides low power dissipation and high switching speed, low on
resistance, low leakage currents and high bandwidth.
They are designed to operate from a single 1.8 V to 5.5 V sup-
ply, making them ideal for use in battery powered instruments
and with the new generation of DACs and ADCs from Analog
Devices. Fast switching times and high bandwidth make the
part suitable for video signal switching.
The ADG781, ADG782, and ADG783 contain four independent
single-pole/single throw (SPST) switches. The ADG781 and
ADG782 differ only in that the digital control logic is inverted.
The ADG781 switches are turned on with a logic low on the
appropriate control input, while a logic high is required to turn
on the switches of the ADG782. The ADG783 contains two
switches whose digital control logic is similar to the ADG781,
while the logic is inverted on the other two switches.
Each switch conducts equally well in both directions when ON.
The ADG783 exhibits break-before-make switching action.
The ADG781/ADG782/ADG783 are available in 20-lead chip
scale packages.
PRODUCT HIGHLIGHTS
1. 20-Lead 4 mm ⫻ 4 mm Chip Scale Package (CSP).
2. 1.8 V to 5.5 V Single Supply Operation. The ADG781,
ADG782, and ADG783 offer high performance and are
fully specified and guaranteed with 3 V and 5 V supply
rails.
3. Very Low R
ON
(4.5 Ω max at 5 V, 8 Ω max at 3 V). At supply
voltage of 1.8 V, R
ON
is typically 35 Ω over the temperature
range.
4. Low On-Resistance Flatness.
5. –3 dB Bandwidth >200 MHz.
6. Low Power Dissipation. CMOS construction ensures low
power dissipation.
7. Fast t
ON
/t
OFF.
8. Break-Before-Make Switching. This prevents channel shorting
when the switches are configured as a multiplexer (ADG783
only).
781/461-3113 2013
C
REV.
–2–
ADG781/ADG782/ADG783–SPECIFICATIONS
(VDD = 5 V 10%, GND = 0 V. All specifications
–40C to +85C unless otherwise noted.)
B Version
–40C to
Parameter +25C +85C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
DD
V
On Resistance (R
ON
) 2.5 Ω typ V
S
= 0 V to V
DD
, I
S
= –10 mA;
4 4.5 Ω max Test Circuit 1
On-Resistance Match Between 0.05 Ω typ V
S
= 0 V to V
DD
, I
S
= –10 mA
Channels (ΔR
ON
) 0.4 Ω max
On-Resistance Flatness (R
FLAT(ON)
) 0.5 Ω typ V
S
= 0 V to V
DD
, I
S
= –10 mA
1.0 Ω max
LEAKAGE CURRENTS V
DD
= 5.5 V;
Source OFF Leakage I
S
(OFF) ±0.01 nA typ V
S
= 4.5 V/1 V, V
D
= 1 V/4.5 V;
±0.1 ±0.2 nA max Test Circuit 2
Drain OFF Leakage I
D
(OFF) ±0.01 nA typ V
S
= 4.5 V/1 V, V
D
= 1 V/4.5 V;
±0.1 ±0.2 nA max Test Circuit 2
Channel ON Leakage I
D
, I
S
(ON) ±0.01 nA typ V
S
= V
D
= 1 V, or 4.5 V;
±0.1 ±0.2 nA max Test Circuit 3
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 V min
Input Low Voltage, V
INL
0.8 V max
Input Current
I
INL
or I
INH
0.005 μA typ V
IN
= V
INL
or V
INH
±0.1 μA max
DYNAMIC CHARACTERISTICS
2
t
ON
11 ns typ R
L
= 300 Ω, C
L
= 35 pF,
16 ns max V
S
= 3 V; Test Circuit 4
t
OFF
6 ns typ R
L
= 300 Ω, C
L
= 35 pF,
10 ns max V
S
= 3 V; Test Circuit 4
Break-Before-Make Time Delay, t
D
6 ns typ R
L
= 300 Ω, C
L
= 35 pF,
(ADG783 Only) 1 ns min V
S1
= V
S2
= 3 V; Test Circuit 5
Charge Injection 3 pC typ V
S
= 2 V; R
S
= 0 Ω, C
L
= 1 nF;
Test Circuit 6
Off Isolation –58 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 10 MHz
–78 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
Test Circuit 7
Channel-to-Channel Crosstalk –90 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 10 MHz;
Test Circuit 8
Bandwidth –3 dB 200 MHz typ R
L
= 50 Ω, C
L
= 5 pF; Test Circuit 9
C
S
(OFF) 10 pF typ f = 1 MHz
C
D
(OFF) 10 pF typ f = 1 MHz
C
D
, C
S
(ON) 22 pF typ f = 1 MHz
POWER REQUIREMENTS V
DD
= 5.5 V
I
DD
0.001 μA typ Digital Inputs = 0 V or 5.5 V
1.0 μA max
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
C
REV. –3–
ADG781/ADG782/ADG783
B Version
–40C to
Parameter +25C +85C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
DD
V
On Resistance (R
ON
) 5 5.5 Ω typ V
S
= 0 V to V
DD
, I
S
= –10 mA;
10 Ω max Test Circuit 1
On-Resistance Match Between 0.1 Ω typ V
S
= 0 V to V
DD
, I
S
= –10 mA
Channels (ΔR
ON
) 0.5 Ω max
On-Resistance Flatness (R
FLAT(ON)
)2.5 Ω typ V
S
= 0 V to V
DD
, I
S
= –10 mA
LEAKAGE CURRENTS V
DD
= 3.3 V;
Source OFF Leakage I
S
(OFF) ±0.01 nA typ V
S
= 3 V/1 V, V
D
= 1 V/3 V;
±0.1 ±0.2 nA max Test Circuit 2
Drain OFF Leakage I
D
(OFF) ±0.01 nA typ V
S
= 3 V/1 V, V
D
= 1 V/3 V;
±0.1 ±0.2 nA max Test Circuit 2
Channel ON Leakage I
D
, I
S
(ON) ±0.01 nA typ V
S
= V
D
= 1 V, or 3 V;
±0.1 ±0.2 nA max Test Circuit 3
DIGITAL INPUTS
Input High Voltage, V
INH
2.0 V min
Input Low Voltage, V
INL
0.8 V max
Input Current
I
INL
or I
INH
0.005 μA typ V
IN
= V
INL
or V
INH
±0.1 μA max
DYNAMIC CHARACTERISTICS
2
t
ON
13 ns typ R
L
= 300 Ω, C
L
= 35 pF,
20 ns max V
S
= 2 V; Test Circuit 4
t
OFF
7 ns typ R
L
= 300 Ω, C
L
= 35 pF,
12 ns max V
S
= 2 V; Test Circuit 4
Break-Before-Make Time Delay, t
D
7 ns typ R
L
= 300 Ω, C
L
= 35 pF,
(ADG783 Only) 1 ns min V
S1
= V
S2
= 2 V; Test Circuit 5
Charge Injection 3 pC typ V
S
= 1.5 V; R
S
= 0 Ω, C
L
= 1 nF;
Test Circuit 6
Off Isolation –58 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 10 MHz
–78 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
Test Circuit 7
Channel-to-Channel Crosstalk –90 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 10 MHz;
Test Circuit 8
Bandwidth –3 dB 200 MHz typ R
L
= 50 Ω, C
L
= 5 pF; Test Circuit 9
C
S
(OFF) 10 pF typ f = 1 MHz
C
D
(OFF) 10 pF typ f = 1 MHz
C
D
, C
S
(ON) 22 pF typ f = 1 MHz
POWER REQUIREMENTS V
DD
= 3.3 V
I
DD
0.001 μA typ Digital Inputs = 0 V or 3.3 V
1.0 μA max
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
SPECIFICATIONS
1
(VDD = 3 V 10%, GND = 0 V. All specifications –40C to +85C unless otherwise noted.)
C
REV.
ADG781/ADG782/ADG783
–4–
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25°C unless otherwise noted.)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
Analog, Digital Inputs
2
. . . . . . . . . . –0.3 V to V
DD
+ 0.3 V or
30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Chip Scale Package
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 32°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 300°C
IR Reflow (<20 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 235°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at IN, S, or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
PIN CONFIGURATIONTable I. Truth Table (ADG781/ADG782)
ADG781 In ADG782 In Switch Condition
01ON
1 0 OFF
Table II. Truth Table (ADG783)
Logic Switch 1, 4 Switch 2, 3
0 OFF ON
1 ON OFF
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG781/ADG782/ADG783 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
(LFCSP)
C
14
13
12
1
3
4
S2
15 D2
V
DD
S3
11 D3
D1
GND
2
S1
S4
5
D4
7
IN4
6
NC
8
NC
9
IN3
10
NC
19 IN1
20 NC
18 NC
17 IN2
16 NC
ADG781/
ADG782/
ADG783
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD TIED TO SUBSTRATE, GND.
REV.
ADG781/ADG782/ADG783
–5–
V
DD
Most positive power supply potential.
GND Ground (0 V) reference.
S Source terminal. May be an input or output.
D Drain terminal. May be an input or output.
IN Logic control input.
R
ON
Ohmic resistance between D and S.
ΔR
ON
On-resistance match between any two chan-
nels (i.e., R
ON
max and R
ON
min).
R
FLAT(ON)
Flatness is defined as the difference between
the maximum and minimum value of on
resistance as measured over the specified
analog signal range.
I
S
(OFF) Source leakage current with the switch “OFF.”
I
D
(OFF) Drain leakage current with the switch “OFF.”
I
D
, I
S
(ON) Channel leakage current with the switch “ON.”
V
D
(V
S
) Analog voltage on terminals D, S.
C
S
(OFF) “OFF” switch source capacitance.
C
D
(OFF) “OFF” switch drain capacitance.
C
D
, C
S
(ON) “ON” switch capacitance.
t
ON
Delay between applying the digital control
input and the output switching on.
t
OFF
Delay between applying the digital control
input and the output switching off.
t
D
“OFF” time or “ON” time measured
between the 90% points of both switches,
when switching from one address state to
another (ADG783 only).
Crosstalk A measure of unwanted signal that is coupled
through from one channel to another as a
result of parasitic capacitance.
Off Isolation A measure of unwanted signal coupling
through an “OFF” switch.
Charge A measure of the glitch impulse transferred
Injection from the digital input to the analog output
during switching.
On Response The frequency response of the “ON” switch.
On Loss The loss due to the on resistance of the switch.
TERMINOLOGY
Typical Performance Characteristics
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
6
RON –
0
0 0.5
VDD = 2.7V
0.5
1
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1 1.5 2 2.5 3 3.5 4 4.5
VDD = 3V
VDD = 4.5V
VDD = 5V
TA = 25C
5
TPC 1. On Resistance as a Function of V
D
(V
S
)
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
6
RON –
0
0
+85C
0.5
1
5.5
5
4.5
4
3.5
3
2.5
2
1.5
13
VDD = 3V
–40C
0.5 1.5 2 2.5
+25C
TPC 2. On Resistance as a Function of V
D
(V
S
) for
Different Temperatures V
DD
= 3 V
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
6
RON –
0
0 0.5
0.5
1
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1 1.5 2 2.5 3 3.5 4 4.5 5
VDD = 5V
+85C
–40C
+25C
TPC 3. On Resistance as a Function of V
D
(V
S
) for
Different Temperatures V
DD
= 5 V
V
DD
= 5V
4 SW
1 SW
FREQUENCY – Hz
10m
1m
1n
100 10M1k
I
SUPPLY
– Amps
10k 100k 1M
100
10
1
100n
10n
TPC 4. Supply Current vs. Input Switching Frequency
C
REV.
ADG781/ADG782/ADG783
–6–
FREQUENCY – Hz
–30
OFF ISOLATION – dB
–40
–110
–120
–130
10k 100k 1M 10M 100M
–100
–90
–80
–70
–60
–50
VDD = 5V, 3V
TPC 5. Off Isolation vs. Frequency
FREQUENCY – Hz
–30
CROSSTALK – dB
–40
–110
–120
–130
10k 100k 1M 10M
V
DD
= 5V, 3V
100M
–100
–90
–80
–70
–60
–50
TPC 6. Crosstalk vs. Frequency
FREQUENCY – Hz
0
ON RESPONSE – dB
–6
10k 100k 1M 10M
V
DD
= 5V
100M
–4
–2
TPC 7. On Response vs. Frequency
SOURCE VOLTAGE – V
25
Q
INJ
– pC
–10
0 0.5
–5
0
20
15
10
5
1 1.5 2 2.5 3 3.5 4 4.5 5
V
DD
= 5V
V
DD
= 3V
T
A
= 25C
TPC 8. Charge Injection vs. Source Voltage
APPLICATIONS
Figure 1 illustrates a photodetector circuit with programmable
gain. An AD820 is used as the output operational amplifier.
With the resistor values shown in the circuit, and using different
combinations of the switches, gain in the range of 2 to 16 can
be achieved.
5V
2.5V
R3
510k
C1
V
OUT
GND
D1
S1 D1
GAIN RANGE 2 TO 16
5V
AD820
S2 D2
S3 D3
S4 D4
(LSB) IN1
IN2
IN3
(MSB) IN4
R4
240k
R5
240k
R6
120k
R7
120k
R8
120k
R9
120k
R10
120k
R1
33k
R2
510k
2.5V
Figure 1. Photodetector Circuit with Programmable Gain
C
REV.
ADG781/ADG782/ADG783
–7–
Test Circuits
Test Circuit 1. On Resistance
V
D
I
S
(OFF) I
D
(OFF)
SD
V
S
A A
Test Circuit 2. Off Leakage
0.1F
V
S
IN
SD
V
DD
GND
R
L
300
C
L
35pF
V
OUT
V
DD
ADG781
ADG782
V
IN
V
IN
V
OUT
t
ON
t
OFF
50% 50%
90% 90%
50% 50%
V
S
Test Circuit 4. Switching Times
S1 D1
0.1F
V
DD
IN1, IN2
V
S1
GND
R
L1
300
C
L1
35pF
V
OUT1
V
S2
V
OUT2
R
L2
300
C
L2
35pF
S2
V
IN
D2
V
DD
ADG783
t
D
t
D
50% 50%
90%
V
IN
V
OUT1
V
OUT2
90%
90%
90%
0V
0V
0V
Test Circuit 5. Break-Before-Make Time Delay, t
D
I
D
(ON)
SD
A
V
D
NC
NC = NO CONNECT
Test Circuit 3. On Leakage
VOUT
VOUT
QINJ = CL VOUT
SW ON
VIN
SW OFF
SD
VDD
IN
RS
GND
VS
VOUT
CL
1nF
VDD
Test Circuit 6. Charge Injection
VS
VOUT
50
NETWORK
ANALYZER
RL
50
GND
S
D
VS
OFF ISOLATION = 20 LOG VOUT
0.1F
VDD
VDD
50
VIN
IN
Test Circuit 7. Off Isolation
CHANNEL-TO-CHANNEL
CROSSTALK = 20 LOG V
OUT
V
S
GND
S1
D2
S2
NETWORK
ANALYZER
IN
D1 NC
V
OUT
R
L
50
0.1F
V
DD
V
DD
50R
L
50
V
S
Test Circuit 8. Channel-to-Channel Crosstalk
C
IDS
SD
V
S
V
RON = V/IDS
REV.
–8–
ADG781/ADG782/ADG783
VS
VOUT
50
NETWORK
ANALYZER
RL
50
GND
S
D
0.1F
VDD
VDD
VIN
IN
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
INSERTION LOSS = 20 LOG
Test Circuit 9. Bandwidth
C
ADG781/ADG782/ADG783
REV. C –9–
OUTLINE DIMENSIONS
Figure 2. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-20-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADG781BCPZ −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
ADG781BCPZ-REEL7 −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
ADG782BCPZ −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
ADG782BCPZ-REEL7 −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
ADG783BCPZ −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
ADG783BCPZ-REEL −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
ADG783BCPZ-REEL7 −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
1 Z = RoHS Compliant Part.
REVISION HISTORY
2/13—Rev. B to Rev. C
Changed Pin 4 from S3 to S4 ........................................................... 4
Changes to Test Circuit 1 ................................................................. 7
Changes to Ordering Guide ............................................................. 9
8/12—Rev. A to Rev. B
Updated Outline Dimensions .......................................................... 9
Changes to Ordering Guide ............................................................. 9
3/02—Rev. 0 to Rev. A
Edits to Typical Performance Characteristics ........................... 5-6
Changes to OUTLINE DIMENSIONS drawing ........................... 8
0.50
BSC
0.65
0.60
0.55
0.30
0.25
0.18
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGD-1.
BOTTOM VIEWTOP VIEW
EXPOSED
PAD
PIN1
INDICATOR
4.10
4.00 SQ
3.90
SEATING
PLANE
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
2.30
2.10 SQ
2.00
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
1
20
6
10
11
1516
5
08-16-2010-B
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02372-0-2/13(C)
