TECHNICAL NOTE High-performance Regulator IC Series for PCs 300mA Linear Regulators for Desktop PC BD35630HFV Description BD35630HFV is a LDO regulator with output current 300mA. The output accuracy is1% of output voltage. With external resistance, it is available to set the output voltage at random (from VFB to 15.0V) and also is used for the wide applications of digital appliances. Over current protection (for protecting the IC destruction by output short circuit), circuit current ON/OFF switch (for setting the circuit current 0A at shutdown mode), and thermal shutdown circuit (for protecting ICs from heat destruction by over load condition) are all built in. Features 1) Output current 300mA 2) High accuracy reference voltage circuit 3) Built-in Over Current Protection circuit (OCP) 4) Built-in Thermal Shut Down circuit (TSD) 5) With shut down switch 6) Output voltage variable type (VFB to 15.0V) 6) Package : HVSOF6 Oct. 2008 Absolute maximum ratings (Ta=25) Parameter Power Supply Voltage EN Voltage Power Dissipation HVSOF6 Operating Temperature Range Storage Temperature Range Junction Temperature Symbol Vcc VEN Pd Topr Tstg Tjmax Limits 24.0 *1 24.0 1700.0 *2 -10+100 -55+150 +150 Unit V V mW *1 Not to exceed Pd *2 Reduced by 13.6mW for each increase in Ta of 1 over 25. (when mounted on a board 70.0mmx70mmx1.6mm Glass-epoxy PCB. (copper foil area : 2500mm2)) Operating Conditions (Ta=25) Parameter Input Power Supply Voltage Output voltage EN Voltage Output Current Symbol Vcc Vo VEN Io Min. 4.5 VFB - Max. 20.0 15.0 20.0 300 Unit V V V mA This product should not be used in a radioactive environment. ELECTRICAL CHARACTERISTICS BD35630HFV (Unless otherwise noted, Ta=25, EN=3V, Vcc=12V, R1=750k, R2=82k) Parameter Symbol Min. Typ. Max. Output Voltage 1 Vo1 7.920 8.000 8.080 Unit V Output Voltage 2 Vo2 7.880 8.000 8.120 V Circuit Current at shutdown mode Bias Current Output Current Ability Isd Icc Io 300 0 250 - 5 300 - A A mA Reg.I - 25 50 mV VFB VEN (Low) VEN (High) IEN 0.780 0 2.4 0.5 0.788 1.0 0.796 0.8 20.0 5.0 V V V A Line Regulation Output Reference Voltage EN Low Voltage EN High Voltage EN Bias Current 2/10 Conditions Io=0mA Tj=0 to 100 Io=0mA300mA EN=0V, @OFF mode Vcc=(Vo+1.8V)15.0V, Io=300mA Io=0mA Reference Data BD35630HFV (Unless otherwise specified, Ta=25, EN=3V, Vcc=12V, R1=750k, R2=82k) Vo Vo 200mV/div 200mV/div EN 5V/div Io Io 200mA/div 200mA/div Vo 5V/div (20m sec/div) (10sec/div) Fig.1 Transient Response (300m0mA), Co=1F (0.2msec/div) Fig.2 Transient Response (0300mA), Co=1F Fig.3 Waveform at output start Co=1F EN EN 5V/div EN 5V/div 5V/div VCC VCC 10V/div 10V/div VCC 10V/div Vo Vo Vo 5V/div 5V/div 5V/div (1msec/div) (1sec/div) Fig.6 Input sequence 2 Co=1F Fig.5 Input sequence 1 Co=1F 230 1.0 8.1 220 0.8 8.0 210 0.6 7.9 Icc [A] 8.2 Icc [A] VOUT [V] Fig.4 Waveform at output OFF Co=1F (1msec/div) 200 190 7.8 7.7 -10 15 40 65 90 0.2 180 100 0.4 -10 10 30 50 70 90 0.0 100 -10 10 30 50 Ta [] Ta [] Fig.7 Ta-Vo (Io=0mA) Fig.9 Ta-Icc (Vcc=12V, VEN=0V) Fig.8 Ta-Icc 2.0 90 100 70 Ta [] 10 8.2 1.6 8 0.8 ISTB [A] 1.2 Vo [V] Ien [A] 8.1 8.0 7.9 0.4 0.0 10 30 50 70 Ta [] Fig.14 Ta-IEN (Vcc=12V, VEN=3V) 90 100 4 2 7.8 -10 6 0 0 50 100 150 200 Io [mA] Fig.15 Io-Vo 3/10 250 300 0 5 10 15 20 Vcc [V] Fig.16 Vcc-ISTB (Vcc=12V, VEN=3V) 25 Reference Data (BD35630HFV) 10 8 Vo [V] 6 4 2 0 0 3 6 9 12 15 Vcc [V] Fig.18 Vcc-Vo Heat Dissipation Characteristics [W] HVSOF6 3.0 PCB size70mmx70mmx1.6mm Board1 layer (copper foil area:100mm2). Board1 layer (copper foil area:900 mm2) Board1 layer (copper foil area: 2500mm2) Power Dissipation [Pd] 2.5 2.0 1.5 1.0 1.70W 1.40W ja=147.1/W ja=89.3/W ja=73.5/W 0.85W 0.5 0 0 25 50 75 100 Ambient Temperature [Ta] 125 150 [] 4/10 Block Diagram (HVSOF6) GND 6 3 (Vo+1.8)20V Vcc Ceramic Capacitor OCP 1F SOFT Vo VFB15.0V 1 R1 2 EN FB TSD 4 Pin Function Table (HVSOF6) Pin No. Pin name 1 2 3 4 5 6 Vo FB GND EN N.C Vcc Pin Function Output Voltage Pin Output Reference Voltage Pin (Feedback Pin) GND Pin Enable Pin Open Input Voltage Pin Pin Layout (HVSOF6) VO 1 6 VCC FB 2 5 N.C GND 3 4 EN 5/10 R2 Ceramic 1F Capacitor Evaluation Board Circuit (HVSOF6) C7 Vcc Vo C6 C9 C2 R1 2 C5 C10 C4 FB N.C. 4 EN GND GND U1 R6 C8 Vo R3 Gate Evaluation Board Parts List Designation R1 R2 R3 R4 R5 R6 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 U1 U2 C1 Vcc 3 R4 5 R2 R5 U2 C3 6 1 Value 750k 82k 1F 1F Part No. MCR01PZPZF7503 MCR01PZPZF8202 CM105B105K16A CM105B105K16A Company ROHM ROHM KYOCERA KYOCERA - BD35630HFV - ROHM - 6/10 SW1 EN Reference landing pattern HVSOF6 MIE b2 D3 e E3 L2 Lead pitch e 0.50 landing pitch MIE 3.00 central pad length D3 1.60 central pad pitch E3 2.60 landing length l2 0.55 (Unit:mm) landing pitch b2 0.25 *It is recommended to design suitable for the actual application. Dimension HVSOF6 (UNIT:mm) HVSOF6 7/10 Operation Notes 1. Absolute maximum ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. 2. Connecting the power supply connector backward Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply lines. An external direction diode can be added. 3. Power supply lines Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line, separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals to ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the circuit, not that capacitance characteristic values are reduced at low temperatures. 4. GND voltage The potential of GND pin must be minimum potential in all operating conditions. 5. Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 6. Inter-pin shorts and mounting errors Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error or if pins are shorted together. 7. Actions in strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. 8. ASO When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO. 9. Thermal shutdown circuit The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed. TSD on temperature [C] (typ.) Hysteresis temperature [C] (typ.) 175 15 BD35630HFV 10. Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure. Use similar precaution when transporting or storing the IC. 8/10 11. Regarding input pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode or transistor. For example, the relation between each potential is as follows: When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode. When GND > Pin B, the P-N junction operates as a parasitic transistor. Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used. Resistor Transistor (NPN) Pin A Pin B C Pin B B E Pin A N P + N P P + N Parasitic element N P+ P substrate Parasitic element GND B N P P C + N E Parasitic element P substrate Parasitic element GND GND GND Other adjacent elements 12. Ground Wiring Pattern. When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern of any external components, either. 9/10 Type Designations (Ordering Information) B 5 3 D 6 0 3 H V F T R TR Emboss tape reel opposite draw-out side: 1 pin Package Type Product Name HFV : HVSOF6 BD35630 HVSOF6 (MAX 1.8 include BURR) (0.45) (1.5) 1.60.1 (1.4) 0.75Max. 123 (0.15) (1.2) (MAX 2.8 include BURR) 2.60.1 3.00.1 654 Tape Embossed carrier tape Quantity 3000pcs Direction of feed TR (The direction is the 1pin of product is at the upper light when you hold reel on the left hand and you pull out the tape on the right hand) 0.1450.05 S X X X X X X 0.1 S 0.220.05 X X X X X X X X X X X X X X X X X X X X X X X X 0.5 1Pin Direction of feed Reel (Unit:mm) When you order , please order in times the amount of package quantity. 10/10 Catalog No.08T456A '08.10 ROHM (c) Appendix Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM CO.,LTD. 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