19-0621; Rev 0; 10/06 3-Wire Interface Full-Speed USB Transceivers With/Without Internal Series Resistors The MAX13342E/MAX13345E USB-compliant transceivers are designed to minimize the area and external components required to interface low-voltage ASICs to USB. The devices comply with USB 2.0 specification for full-speed-only (12Mbps) operation. The transceivers include an internal 3.3V regulator, an internal 1.5k D+ pullup resistor, and built-in 15kV ESD protection circuitry to protect the USB I/0 ports (D+,D-). The MAX13345E also has internal series resistors, allowing it to be wired directly to a USB connector. These devices operate with logic-supply voltages as low as +2.3V, ensuring compatibility with low-voltage ASICs. A low-power mode reduces current consumption to less than 45A. An enumerate function controls the D+ pullup resistor, allowing devices to logically disconnect while remaining plugged in. The MAX13342E has controlled output impedance of 2 (max) on D+/D-, allowing the use of external switches to multiplex two different USB devices onto a single USB connector. The MAX13345E has 43.5 (max) internal resistors on D+/D- for direct connection to the USB connector. The MAX13342E/MAX13345E are equipped with DAT and SE0 interface signals. These transceivers provide a USB detection function that monitors the presence of USB VBUS and signals the event. These devices operate over the extended -40C to +85C temperature range and are available in UCSPTM 2.0mm x 1.5mm and 14-pin TDFN (3mm x 3mm) packages. UCSPTM is a trademark of Maxim Integrated Products, Inc. Features USB 2.0 (Full-Speed, 12Mbps)-Compliant Transceiver Internal Pullup VBUS Detection Internal Series Resistors (MAX13345E) 15kV (HBM) ESD Protection on D+, D-, and VBUS Enumeration Input Controls D+ Pullup Resistor Supports 3-Wire DAT/SE0 Interface +2.3V to +3.6V Interface Voltage (VL) No Power-Supply Sequencing Required Low USB Output Impedance (MAX13342E) Ordering Information PC Peripherals TOP MARK PKG CODE MAX13342EETD+ 14 TDFN-EP (3mm x 3mm) ACZ T1433-2 MAX13342EEBC+* 12 UCSP (2.0mm x 1.5mm) ACU B12-3 MAX13345EETD+ 14 TDFN-EP (3mm x 3mm) ADA T1433-2 MAX13345EEBC+* 12 UCSP (2.0mm x 1.5mm) ACX B12-3 *Future product--contact factory for availability. +Denotes lead-free package. EP = Exposed pad. Applications PDAs PINPACKAGE PART Typical Operating Circuits SYSTEM VOLTAGE SUPPLY Cellular Telephones VBUS VL Data Cradles 1F 0.1F MP3 Players MAX13342E BD SYSTEM INTERFACE Pin Configurations and Selector Guide appear at end of data sheet. VTRM DAT SEO OE 1F ENUM SUS D+ 31.6 GND USB CONNECTOR D31.6 Typical Operating Circuits continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX13342E/MAX13345E General Description MAX13342E/MAX13345E 3-Wire Interface Full-Speed USB Transceivers With/Without Internal Series Resistors ABSOLUTE MAXIMUM RATINGS (All voltages refer to GND unless otherwise noted.) Supply Voltage (VBUS) .............................................-0.3V to +6V System Supply Voltage (VL) .....................................-0.3V to +6V Output of Internal Regulator (VTRM) .........-0.3V to (VBUS + 0.3V) Input Voltage (D+, D-) ..............................................-0.3V to +6V SUS, BD ........................................................-0.3V to (VL + 0.3V) ENUM, SE0, DAT ..........................................-0.3V to (VL + 0.3V) Short-Circuit Current to VBUS or GND (D+, D-) ..............150mA Maximum Continuous Current (all other pins) ..................15mA Continuous Power Dissipation (TA = +70C) 14-Pin TDFN (derate 18.5mW/C above +70C) .......1482mW 4mm x 3mm UCSP (derate 6.5mW/C above +70C) ..............................518mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Bump Soldering ...............................................................+235C Lead Soldering (10s) ...................................................... +300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VBUS = +4.0V to +5.5V, VL = +2.3V to +3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VBUS = +5.0V, VL = +2.5V, TA = +25C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SUPPLY INPUTS (VBUS, VTRM, VL) VBUS Input Range VL Input Range Regulated Supply-Voltage Output Operating VBUS Supply Current Operating VL Supply Current VBUS 4.0 5.5 V VL 2.3 3.6 V 3.6 V 10 mA VTRM IVBUS IVL 3.0 3.3 Full-speed transmitting/receiving at 12Mbps, CL = 50pF on D+ and DFull-speed transmitting/receiving at 12Mbps, CL = 15pF receiver outputs, VL = 2.5V 1.5 mA Full-speed idle, VD+ >2.7V, VD- <0.3V 500 SE0: VD- <0.3V, VD+ <0.3 500 Full-speed idle, SE0 or suspend mode 10 A 45 A VL = GND or open 25 A Sharing-Mode VL Supply Current IVL(SHARING) VBUS = GND or open, OE = low, SE0 = DAT = low or high, SUS = high 5 A D+/D- Supply Current VBUS = GND or open 20 A 3.6 V Full-Speed Idle and SE0 Supply Current IVBUS(IDLE) Static VL Supply Current IVL(STATIC) Suspend Supply Current IVBUS(SUSP) SE0 = DAT= open; SUS = OE = high IVBUS(DIS) Disable-Mode Supply Current ID+/D- 30 A VBUS Power-Supply Detection Threshold VTH_VBUS VBUS Power-Supply Detection Hysteresis VVBUSHYS 100 mV VTH_VL 850 mV VL Power-Supply Threshold 2 VL > 2.3V 0.8 _______________________________________________________________________________________ 3-Wire Interface Full-Speed USB Transceivers With/Without Internal Series Resistors (VBUS = +4.0V to +5.5V, VL = +2.3V to +3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VBUS = +5.0V, VL = +2.5V, TA = +25C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS AND OUTPUTS (DAT, SE0, OE, ENUM, SUS, BD) VIH Input-High Voltage 0.7 x VL Input-Low Voltage VIL Output-Voltage High VOH ISOURCE = 2mA Output-Voltage Low VOL ISINK = 2mA Input Leakage Current ILKG Input Capacitance V 0.3 x VL VL - 0.4 V -1 Measured from input to GND V 0.4 V +1 A 10 pF ANALOG INPUTS AND OUTPUTS (D+/D-) Differential Input Sensitivity VID |VD+ - VD-| 200 Differential Common-Mode Voltage Range VCM Includes VID range 0.8 Single-Ended Input Voltage High VIHSE Single-Ended Input Voltage Low VILSE Receiver Single-Ended Hysteresis VHYS Output-Voltage Low VOLD RL = 1.5k from D+ or D- to 3.6V Output-Voltage High VOHD RL = 15k from D+ or D- to GND 2.8 3.6 V Tri-state driver -1 +1 A Off-State Leakage Current Measured from D+ or D- to GND Driver Output Impedance ROUT MAX13342E MAX13345E Input Impedance ZIN V 0.8 V V 200 CIND RPU 2.5 2.0 Transceiver Capacitance Internal Pullup Resistor mV mV 0.3 20 4 28 1.425 1.500 V pF 14 43 1.575 k Drivers off, tri-state driver, ENUM = 0, VD+, VD- = 0 OR +3.6V 1 M Compensation of linear regulator 1 F LINEAR REGULATOR COUT External Capacitor ESD PROTECTION (D+, D-) Human Body Model 15 kV IEC 61000-4-2 Air-Gap Discharge 8 kV IEC 61000-4-2 Contact Discharge 8 kV _______________________________________________________________________________________ 3 MAX13342E/MAX13345E ELECTRICAL CHARACTERISTICS (continued) MAX13342E/MAX13345E 3-Wire Interface Full-Speed USB Transceivers With/Without Internal Series Resistors TIMING CHARACTERISTICS (VBUS = +4V to +5.5V, VL = +2.3V to +3.6V, ENUM = VL, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VBUS = +5V, VL = +2.5V, TA = +25C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN Rise Time tFR 10% to 90% of |VOHD-VOLD| with an external 31.6 series resistor (MAX13342E), Figures 3, 8 Fall Time tFF TYP MAX UNITS 4 20 ns 10% to 90% of |VOHD-VOLD| with an external 31.6 series resistor (MAX13342E), Figures 3, 8 4 20 ns Figures 3, 8 90 110 % VCRS_L, VCRS_F Figure 4 1.3 2 V tPLH_DRV Low-to-high transition, Figures 4, 8 VL > 2.3V 20 tPHL_DRV High-to-low transition, Figures 4, 8 VL > 2.3V 20 tPZH_DRV Off-to-high transition, Figures 5, 8 VL > 2.3V 18 tPZL_DRV Off-to-low transition, Figures 5, 8 VL > 2.3V 18 tPHZ_DRV High-to-off transition, Figure 5, 9 VL > 2.3V 18 tPLZ_DRV Low-to-off transition, Figures 5, 9 VL > 2.3V 18 tPLH_RCV Low-to-high transition, Figures 6,10 VL > 2.3V 20 tPHL_RCV High-to-low transition, Figures 6,10 VL > 2.3V 20 tPLH_SE Low-to-high transition, Figures 6,10 18 tPHL_SE High-to-low transition, Figures 6,10 18 tPHZ_SE High-to-off transition, Figure 7 VL > 2.3V 20 tPLZ_SE Low-to-off transition, Figure 7 VL > 2.3V 20 tPZH_SE Off-to-high transition, Figure 7 VL > 2.3V 22 tPZL_SE Off-to-low transition, Figure 7 VL > 2.3V 22 TRANSMITTER ( CL = 50pF) Rise-and-Fall Time Matching (Note 1) Output Signal Crossover (Note 2) Driver Propagation Delay tLR/tLF Driver-Enabled Delay Time Driver Disable Delay ns ns ns RECEIVER (CL = 15pF) Differential Receiver Propagation Delay Single-Ended Receiver Propagation Delay Single-Ended Receiver Disable Delay Single-Ended Receiver Enable Delay ns ns ns ns Note 1: Parameters are 100% production tested at +25C, unless otherwise noted. Limits over temperature are guaranteed by design. 4 _______________________________________________________________________________________ 3-Wire Interface Full-Speed USB Transceivers With/Without Internal Series Resistors 14 12 10 TA = -40C 8 6 4 1.2 1.8 2.1 2.4 2.7 3.3 14 12 10 TA = -40C 8 6 24 22 20 12 0 10 4.6 4.9 5.2 TA = +85C 16 14 4.3 TA = +25C 18 2 4.0 MAX13342E toc03 26 4 3.6 OE = SUS = HIGH 28 5.5 TA = -40C 1.2 1.5 1.8 2.1 2.4 2.7 3.0 VBUS (V) VL (V) SINGLE-ENDED RECEIVER PROPAGATION DELAY vs. VBUS TRANSMITTER SKEW vs. TEMPERATURE RECEIVER SKEW vs. TEMPERATURE 12 TA = +25C 8 TA = -40C 6 0.7 0.6 0.5 0.4 0.3 1.4 1.3 1.2 1.1 1.0 0.9 4 0.2 0.8 2 0.1 0.7 0 0 4.3 4.6 4.9 5.2 5.5 0.6 -40 -15 10 35 60 -15 10 35 60 TEMPERATURE (C) TEMPERATURE (C) VL SUPPLY CURRENT vs. D+/D- CAPACITANCE VBUS SUPPLY CURRENT vs. D+/D- CAPACITANCE VBUS SUSPEND CURRENT vs. VBUS SUPPLY VOLTAGE 22 20 18 16 14 12 1.7 1.6 VL = 2.5V 1.5 1.4 1.3 1.2 1.1 10 22 44 66 88 110 132 154 176 198 220 CAPACITANCE (pF) 40 38 36 34 TA = +85C TA = +25C 32 30 28 26 TA = -40C 24 22 1.0 8 85 MAX13342E toc09 24 VBUS SUPPLY CURRENT (A) MAX13342E toc07 26 0 -40 85 VBUS (V) VBUS SUPPLY CURRENT (mA) 4.0 3.6 MAX13342E toc06 MAX13342E toc05 0.8 3.3 1.5 TRANSMITTER SKEW (ns) 14 10 0.9 TRANSMITTER SKEW (ns) TA = +85C 16 1.0 MAX13342E toc04 OE = SUS = HIGH 18 VL SUPPLY CURRENT (mA) 3.0 16 30 VL (V) 20 PROPAGATION DELAY (ns) 1.5 TA = +25C SINGLE-ENDED RECEIVER PROPAGATION DELAY vs. VL PROPAGATION DELAY (ns) TA = +25C TA = +85C 18 MAX13342E toc08 PROPAGATION DELAY (ns) TA = +85C 16 20 MAX13342E toc02 18 DIFFERENTIAL RECEIVER PROPAGATION DELAY vs. VBUS PROPAGATION DELAY (ns) 20 MAX13342E toc01 DIFFERENTIAL RECEIVER PROPAGATION DELAY vs. VL 20 0 22 44 66 88 110 132 154 176 198 220 CAPACITANCE (pF) 4.0 4.3 4.6 4.9 5.2 5.5 VBUS (V) _______________________________________________________________________________________ 5 MAX13342E/MAX13345E Typical Operating Characteristics (VBUS = +5V, VL = +3.3V, TA = +25C, unless otherwise noted.) Typical Operating Characteristics (continued) (VBUS = +5V, VL = +3.3V, TA = +25C, unless otherwise noted.) MAX13342E/MAX13345E TRANSMITTING MAX13342E toc11 MAX13342E toc10 MAX13342E/MAX13345E RECEIVING SEO 2V/div D2V/div D+ 2V/div DAT 2V/div DAT 2V/div D+ SEO 2V/div (2V/div) D100ns/div MAX13342E/MAX13345E BUS DETECTION EYE DIAGRAM MAX13342E toc13 20ns/div 4 VBUS 2V/div BD 1V/div 3 D+ AND D- (V) MAX13342E toc12 MAX13342E/MAX13345E 3-Wire Interface Full-Speed USB Transceivers With/Without Internal Series Resistors 2 1 0 -1 4s 0 10 20 30 40 50 60 70 80 TIME (ns) 6 _______________________________________________________________________________________ 3-Wire Interface Full-Speed USB Transceivers With/Without Internal Series Resistors PIN TDFN UCSP NAME FUNCTION 1 B1 VTRM Regulated Output Voltage. VTRM provides a 3.3V output derived from VBUS. Bypass VTRM to GND with a 1F (min) low-ESR capacitor, such as ceramic or plastic film types. VTRM provides power to internal circuitry and the internal D+ pullup resistor. Do not use VTRM to power external circuitry. These USB transceivers can also be powered by an externally regulated 3.3V supply connected to both VBUS and VTRM. 2 A1 VL System-Side Power-Supply Input. Connect VL to the systems logic-level power supply. Bypass VL to GND with a 0.1F (min) low-ESR ceramic capacitor. 3 A2 SE0 Logic-Side Data Input/Output. SE0 operates as an input when OE is low and as an output when OE is high. As an input, when SE0 is active high, D+ and D- are both driven low. As an output, SE0 goes active high when both D+ and D- are low. (See Tables 3 and 4.) 4 A3 DAT Logic-Side Data Input/Output. DAT operates as an input for data on D+/D- when OE is low. DAT operates as the output of the differential receiver on D+/D- when OE is high. (See Tables 3 and 4.) 5, 12 -- N.C. No Connection. Leave N.C. unconnected. N.C. is not internally connected. 6 B3 SUS Suspend Input. Drive SUS low for normal transceiver operation. Drive SUS high for low-power state. 7 A4 BD USB Detector Output. A high on BD indicates that VBUS is present. Output Enable. OE controls the USB transmitter outputs (D+/D-) and the interface signals (DAT, SE0) when in USB mode. Drive OE high to operate D+/D- as inputs and to operate the logic interface signals as outputs. Drive OE low to operate D+/D- as outputs and to operate the logic interface signals as inputs. 8 B4 OE 9 C4 GND 10 C3 D- Negative USB Differential Data Input/Output. D- is wired to the USB connector directly (MAX13345E) or through a series resistor (MAX13342E). D- operates as an input when OE is high and as an output when OE is low. 11 C2 D+ Positive USB Differential Data Input/Output. D+ is wired to the USB connector directly (MAX13345E) or through a series resistor (MAX13342E). D+ operates as an input when OE is high and as an output when OE is low. 13 B2 ENUM Enumerate. Drive ENUM high to connect the internal 1.5k resistor from D+ to VTRM. Drive ENUM low to disconnect the internal 1.5k resistor. 14 C1 VBUS USB-Side Power-Supply Input. Connect VBUS to the incoming USB power supply. Bypass VBUS to GND with a 1F ceramic capacitor. EP -- EP Ground Exposed Paddle. Connect EP to GND. _______________________________________________________________________________________ 7 MAX13342E/MAX13345E Pin Description MAX13342E/MAX13345E 3-Wire Interface Full-Speed USB Transceivers With/Without Internal Series Resistors MAX13342E MAX13345E VL VBUS BD LDO REGULATOR VTRM ENUM SEO DAT MAX13345E OE SUS D+ LEVEL TRANSLATOR AND LOGIC D- Figure 1. MAX13342E/MAX13345E Functional Diagram Detailed Description The MAX13342E/MAX13345E USB-compliant transceivers are designed to minimize the area and external components required to interface low-voltage ASICs to USB. The devices comply with the USB 2.0 specification for full-speed (12Mbps) operation. The transceivers include an internal 3.3V regulator, an internal 1.5k D+ pullup resistor, and built-in 15kV (HBM) ESD protection circuitry to protect D+, D-. Figure 1 is the MAX13342E/MAX13345E functional diagram. The MAX13342E has controlled output impedance of 12 (max) on D+/D-, allowing the use of external switches to multiplex two different USB devices onto a single USB connector. 8 The MAX13345E uses internal series resistors on D+/Dto allow direct interface to the USB connector. A lowpower mode reduces current consumption to less than 45A. An enumerate function controls connection of the internal D+ pullup resistor. The MAX13342E/MAX13345E are equipped with DAT and SE0 interface signals and support the 3-wire USB tranceiver interface. Although the 3-wire interface is commonly associated with USB On-the-Go transceivers, the MAX13342E/MAX13345E support USB peripherals only. These transceivers provide a USB VBUS detection function that monitors the presence of USB VBUS and signals the event. _______________________________________________________________________________________ 3-Wire Interface Full-Speed USB Transceivers With/Without Internal Series Resistors 45A of supply current. The single-ended D+ and Dreceivers are still active when driving SUS high. Sharing Mode Connect VL to a system power supply and leave VBUS (or V BUS and V TRM ) unconnected or connected to GND. D+ and D- are tri-stated, allowing other circuitry to share the USB D+ and D- line. VL consumes less than 5A of supply current. When operating the transceivers in sharing mode, the SUS input is ignored, and the interface signals (SE0, DAT) are high impedance. Power-Supply Configuration Normal Operating Mode See Table 1 for various power-supply configurations. VBUS supplies power to the USB transceivers. Connect VBUS to a +4V to +5.5V supply. Connect VL to a +2.3V to +3.6V supply. VBUS is typically connected directly to the USB connector. An internal regulator provides 3.3V to internal circuitry, and a regulated 3.3V output at VTRM, in addition to powering the internal D+ pullup resistor. The MAX13342E and MAX13345E can be powered by connecting both VBUS and VTRM to a 3.3V external regulator. Disable Mode Connect VBUS to a system power supply and leave VL unconnected or connect to ground. In disable mode, D+ and D- are tri-stated, and V BUS and/or VTRM (or VBUS and VTRM) consume less than 25A. When operating the transceivers in disable mode, OE, SUS, and inputs to the interface control signals are ignored. (See Table 2.) Low-Power Mode Operate the transceivers in low-power mode by asserting SUS high. In low-power mode, the USB differential receiver is turned off and VBUS consumes less than Table 1. Power-Supply Configuration VBUS (V) VTRM (V) VL (V) CONFIGURATION NOTES +4.0 to +5.5 +3.0 to +3.6 output +2.3 to +3.6 Normal mode -- +4.0 to +5.5 +3.0 to +3.6 output GND or floating Disable mode Table 2 GND or Floating High Z +2.3 to +3.6 Sharing mode Table 2 Table 2. Disable-Mode and Sharing-Mode Connection INPUTS/OUTPUTS DISABLE MODE SHARING MODE VBUS / VTRM 4V to 5.5V Floating or connected to GND VL Floating or connected to GND 2.3V to 3.6V input D+ and D- High impedance High impedance DAT, SE0 High impedance High impedance SUS High impedance High impedance BD Low Low _______________________________________________________________________________________ 9 MAX13342E/MAX13345E Interface The MAX13342E/MAX13345E control signals are used to control the USB D+/D- lines. VL powers the logicside interface and sets the input and output thresholds of these signals. The control signals for the MAX13342E and MAX13345E are DAT, SE0, and OE. MAX13342E/MAX13345E 3-Wire Interface Full-Speed USB Transceivers With/Without Internal Series Resistors 3-Wire DAT/SE0 Interface The MAX13342E/MAX13345E use DAT and SE0 to drive data or a single-ended zero onto the D+/D- lines. When OE is low, SE0 is an input and functions as a single-ended zero driver. When SE0 is high, both D+ and D- are driven low. When SE0 is driven low, the D+/D- outputs are controlled by DAT. DAT is used to send data on D+/D- when both OE and SE0 are low. When DAT is high, D+ is driven high and D- is driven low. When DAT is low, D+ is driven low and D- is driven high. In receive mode (OE = high), DAT is the output of the differential receiver connected to D+ and D-. SE0 only goes active high when both D+ and D- are low. Control Signals USB Detection The MA13342E/MAX13345E USB detection function indicates that V BUS is present. The MAX13342E/ MAX13345E push-pull bus detection output (BD) monitors VBUS, and asserts high when VBUS and VL are present. BD asserts low if VBUS is less than +3.6V and enters sharing mode. OE OE controls the direction of communication when VL and VBUS are both present. When OE is low, DAT and SE0 operate as logic inputs and D+/D - are outputs. When OE is high, DAT and SE0 operate as logic outputs and D+/D- are inputs. 10 SUS SUS determines whether the MAX13342E/MAX13345E operate in normal mode or in suspend mode. Drive SUS low for normal operation. Drive SUS high to enable suspend mode. In suspend mode, the single-ended receivers (D+/D-) are active to detect a wake-up event. Supply current decreases to less than 45A in suspend mode. The MAX13342E/MAX13345E can transmit data on D+ and D- while in suspend mode. This function is used to signal a remote wake-up event. ENUM A 1.5k pullup resistor on D+ is used to indicate fullspeed (12Mbps) operation. Drive ENUM high to connect the internal pullup resistor from D+ to VTRM. Drive ENUM low to disconnect the internal pullup resistor from D+ to VTRM. D+ and DD+ and D- are bidirectional signals and are ESD protected to 15kV (HBM). OE controls the direction of D+ and D- when in USB normal mode (Tables 3 and 4). VTRM An internal linear regulator generates the VTRM voltage (+3.3V typ). VTRM derives power from VBUS (see the Power-Supply Configuration section). VTRM powers the internal USB circuitry and provides the pullup voltage for the internal 1.5k resistor. Bypass VTRM to GND with a 1F ceramic capacitor as close to the device as possible. Do not use VTRM to provide power to external circuitry. ______________________________________________________________________________________ 3-Wire Interface Full-Speed USB Transceivers With/Without Internal Series Resistors Table 4. Receive Truth Table (OE = 0, SUS = 0) INPUTS (OE = 1, SUS = 0) OUTPUTS INPUTS OUTPUTS DAT SE0 D+ D- D+ D- DAT SE0 0 0 0 1 0 0 *DAT 1 0 1 0 0 0 1 **0 0 1 0 1 0 1 0 **1 0 1 1 0 0 1 1 X 0 Applications Information USB Data Transfer Transmitting Data The MAX13342E/MAX13345E transmit USB data to the USB differentially on D+ and D- when OE is low. The D+ and D- outputs are determined by SE0 and DAT (see Table 3). Receiving Data Drive OE high and SUS low to receive data on D+/D-. Differential data received on D+ and D- appear at DAT. SE0 goes high only when both D+ and D- are low (Table 4). External Resistors (MAX13342E) The MAX13342E provides low internal resistance on D+/D-. Two external series resistors for impedance matching are required for USB. Place the resistors in between the MAX13342E and the USB connector (see Figure 2). *Last state **D+/D- differential receiver output X = Undefined External Capacitors Use three external capacitors for proper operation. Bypass V L to GND with a 0.1F ceramic capacitor. Bypass VBUS to GND with a 1F ceramic capacitor. Bypass VTRM to GND with a 1F (min) ceramic or plastic capacitor. Place all capacitors as close to the device as possible. UCSP Application Information For the latest application details on UCSP construction, dimensions, tape carrier information, printed circuit board (PCB) techniques, bump-pad layout, and recommended reflow temperature profile, as well as the latest information on reliability testing results, refer to Application Note 1891: UCSP--A Wafer-Level ChipScale Package available on Maxim's website at www.maxim-ic.com/ucsp. ______________________________________________________________________________________ 11 MAX13342E/MAX13345E Table 3. Transmit Truth Table MAX13342E/MAX13345E 3-Wire Interface Full-Speed USB Transceivers With/Without Internal Series Resistors ESD Protection The MAX13342E/MAX13345E feature 15kV (HBM) ESD protection on D+ and D-. The ESD structures withstand high ESD in all states: normal operation, suspend, and powered down. For the 15kV ESD structures to work correctly, a 1F or greater capacitor must be connected from VTRM to GND. VBUS and D+/D- are characterized for protection to the following limits: * 15kV using the Human Body Model * 8kV using the IEC 61000-4-2 Contact Discharge Method * 8kV using the IEC 61000-4-2 Air-Gap Method ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results. Human Body Model Figure 11 shows the Human Body Model, and Figure 12 shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a 1.5k resistor. IEC 61000-4-2 The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment; it does not specifically refer to integrated circuits. The MAX13342E/ MAX13345E help the user design equipment that meets level 4 of IEC 61000-4-2, without the need for additional ESD-protection components. The major difference between tests done using the Human Body Model and IEC 61000-4-2 is a higher peak current in IEC 61000-42 because series resistance is lower in the IEC 610004-2 model. Hence, the ESD withstand voltage measured to IEC 61000-4-2 is generally lower than that measured using the Human Body Model. Figure 13 shows the IEC 61000-4-2 model. The Air-Gap Discharge Method involves approaching the device with a charged probe. The Contact Discharge Method connects the probe to the device before the probe is energized. SYSTEM VOLTAGE SUPPLY VBUS VL 1.0F 0.1F USB CONNECTOR USB POWER MAX13342E SYSTEM INTERFACE BD DAT SEO OE ENUM SUS VTRM 1.0F 31.6 D+ D+ 31.6 DGND DGND Figure 2. Adding External Resistors to the USB Connector for the MAX13342E 12 ______________________________________________________________________________________ 3-Wire Interface Full-Speed USB Transceivers With/Without Internal Series Resistors tFR, tLR tFF, tLF OE VOHD 90% DAT CONNECTED TO GND, SE0 CONNECTED TO GND. D+ PULLED TO 3.0V WITH 150. 90% D+ 10% tPLZ_DRV 10% tPZL_DRV VOLD D+ Figure 3. Rise and Fall Times tPHZ_DRV RISE/FALL TIMES < 4ns DAT DAT CONNECTED TO VL, SE0 CONNECTED TO GND. D+ PULLED TO GND WITH 150. DAT CONNECTED TO VL, SE0 CONNECTED TO GND. D- PULLED TO VL WITH 150. DtPLZ_DRV D- tPHL_DRV D- tPZL_DRV DAT CONNECTED TO GND, SE0 CONNECTED TO GND. D- PULLED TO GND WITH 150. SEO tPLH_DRV tPZH_DRV tPHZ_DRV tPZH_DRV Figure 5. Enable and Disable Timing, Transmitter VCRS_F , VCRS_L D+ INPUT RISE/FALL TIME < 4ns +3V D+/D- Figure 4. Timing of DAT, SE0 to D+ and D0V VL tPLH_RCV, tPLH_SE DAT/SEO tPHL_RCV, tPHL_SE Figure 6. D+/D- to DAT, SE0 Propagation Delays ______________________________________________________________________________________ 13 MAX13342E/MAX13345E Timing Diagrams/Test Circuits MAX13342E/MAX13345E 3-Wire Interface Full-Speed USB Transceivers With/Without Internal Series Resistors OE D+ CONNECTED TO GND, D- CONNECTED TO +3.0V. DAT PULLED TO VL WITH 330. DAT D+/D- DUT FOR THE MAX13342E TEST POINT 31.6 220 50pF tPLZ_SE tPZL_SE DAT D+ CONNECTED TO +3.0V, D- CONNECTED TO GND. DAT PULLED TO GND WITH 330. tPHZ_SE NOTES: 1) V = 0 FOR tPHZ 2) V = VTRM FOR tPLZ tPZH_SE D+ CONNECTED TO +3.0V, D- CONNECTED TO GND. SE0 PULLED TO VL WITH 330. SE0 tPLZ_SE Figure 9. Load for Disable Time Measurements tPZL_SE SE0 D+ CONNECTED TO GND, D- CONNECTED TO GND. SE0 PULLED TO GND WITH 330. tPHZ_SE TEST POINT DUT DAT/SEO 15pF tPZH_SE LOAD FOR: 1) D+/D- TO DAT/SEO PROPAGATION DELAYS 2) DAT/SEO RISE/FALL TIMES Figure 7. Receiver Enable and Disable Timing FOR THE MAX13342E Figure 10. Load for Receiver Propagation Delay and Receiver Rise/Fall Times TEST POINT DUT D+/D- 31.6 15k 50pF LOAD FOR: 1) ENABLE TIME (D+/D-) MEASUREMENT 2) DAT/SEO TO D+/D- PROPAGATION DELAY 3) D+/D- RISE/FALL TIMES Figure 8. Load for Transmitter Propagation Delay, Enable Time, Transmitter Rise/Fall Times 14 ______________________________________________________________________________________ 3-Wire Interface Full-Speed USB Transceivers With/Without Internal Series Resistors CHARGE-CURRENTLIMIT RESISTOR IP 100% 90% DISCHARGE RESISTANCE Ir MAX13342E/MAX13345E RD 1.5k RC 1M PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) AMPERES HIGHVOLTAGE DC SOURCE Cs 100pF STORAGE CAPACITOR DEVICE UNDER TEST 36.8% 10% 0 0 Figure 11. Human Body ESD Test Model RC 50M TO 100M CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE Cs 150pF tRL TIME tDL CURRENT WAVEFORM Figure 12. Human Body Model Current Waveform RD 330 DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 13. IEC 61000-4-2 ESD Test Model ______________________________________________________________________________________ 15 3-Wire Interface Full-Speed USB Transceivers With/Without Internal Series Resistors MAX13342E/MAX13345E Typical Application Circuit SYSTEM VOLTAGE SUPPLY 1F VBUS MULTIMEDIA PROCESSOR VL 0.1F MAX13342E MAX4717 BD SYSTEM INTERFACE NC1 VTRM DAT SEO OE COM1 1F NO1 NC2 31.6 ENUM SUS D+ USB CONNECTOR COM2 31.6 GND D- NO2 GPIO IN1, IN2 SEO DAT BD VTRM ENUM OE VL + GND 4 D- 3 D+ 2 N.C. TOP VIEW 1 ENUM TOP VIEW (BUMP SIDE DOWN) VBUS Pin Configurations 14 13 12 11 10 9 8 A MAX13342E SUS OE MAX13342E MAX13345E B MAX13345E VBUS D+ D- GND *EP 4 5 6 7 DAT SUS BD 3 N.C. 2 SE0 2.0mm x 1.5mm UCSP VTRM 1 VL + C 3mm x 3mm TDFN *CONNECT EP TO GND Chip Information PROCESS: BiCMOS 16 ______________________________________________________________________________________ 3-Wire Interface Full-Speed USB Transceivers With/Without Internal Series Resistors 6, 8, &10L, DFN THIN.EPS PACKAGE OUTLINE, 6,8,10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm 21-0137 COMMON DIMENSIONS MIN. MAX. PKG. CODE N D2 E2 e JEDEC SPEC b [(N/2)-1] x e A 0.70 0.80 T633-1 6 1.50-0.10 2.30-0.10 0.95 BSC MO229 / WEEA 0.40-0.05 1.90 REF D 2.90 3.10 T633-2 6 1.50-0.10 2.30-0.10 0.95 BSC MO229 / WEEA 0.40-0.05 1.90 REF E 2.90 3.10 T833-1 8 1.50-0.10 2.30-0.10 0.65 BSC MO229 / WEEC 0.30-0.05 1.95 REF A1 0.00 0.05 T833-2 8 1.50-0.10 2.30-0.10 0.65 BSC MO229 / WEEC 0.30-0.05 1.95 REF L 0.20 0.40 T833-3 8 1.50-0.10 2.30-0.10 0.65 BSC MO229 / WEEC 0.30-0.05 1.95 REF T1033-1 10 1.50-0.10 2.30-0.10 0.50 BSC MO229 / WEED-3 0.25-0.05 2.00 REF 0.25 MIN. A2 0.20 REF. 1 2 PACKAGE VARIATIONS SYMBOL k H T1033-2 10 1.50-0.10 2.30-0.10 0.50 BSC MO229 / WEED-3 0.25-0.05 2.00 REF T1433-1 14 1.70-0.10 2.30-0.10 0.40 BSC ---- 0.20-0.05 2.40 REF T1433-2 14 1.70-0.10 2.30-0.10 0.40 BSC ---- 0.20-0.05 2.40 REF PACKAGE OUTLINE, 6,8,10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm -DRAWING NOT TO SCALE- 21-0137 H 2 2 ______________________________________________________________________________________ 17 MAX13342E/MAX13345E Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 12L, UCSP 4x3.EPS MAX13342E/MAX13345E 3-Wire Interface Full-Speed USB Transceivers With/Without Internal Series Resistors PACKAGE OUTLINE, 4x3 UCSP 21-0104 F 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.