QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1369
12/14 BIT, 25 TO125 MSPS ADC
1
LTC2261-14, LTC2261-12, LTC22601-14, LTC22601-12, LTC2259-14,
LTC2259-12, LTC2258-14, LTC2258-12, LTC2257-14, LTC2257-12,
LTC2256-14, LTC2256-12
DESCRIPTION
Demonstration circuit 1369 supports a family
of 14/12 BIT 125 MSPS ADCs. Each assem-
bly features one of the following devices:
LTC2261-14, LTC2261-12, LTC2260-14,
LTC2260-12, LTC2259-14, LTC2259-12,
LTC2258-14, LTC2258-12, LTC2257-14,
LTC2257-12, LTC2256-14, or LTC2256-12
high speed, high dynamic range ADCs.
Demonstration circuit 1369 supports the
LTC2261 family DDR LVDS output mode.
This family of ADCs is also supported by
demonstration circuit 1370A, which is compat-
ible with CMOS and DDR CMOS output mod-
es.
Several versions of the 1369A demo board
supporting the LTC2261 12/14-BIT series of
A/D converters are listed in Table 1. Depend-
ing on the required resolution and sample
rate, the DC1369 is supplied with the appro-
priate ADC. The circuitry on the analog in-
puts is optimized for analog input frequencies
from 5 MHz to 170MHz. Refer to the data-
sheet for proper input networks for different
input frequencies.
Design files for this circuit board are avail-
able. Call the LTC factory.
LTC is a trademark of Linear Technology Corporation
Table 1.
DC1369Variants
DC1369
VARIANTS ADC PART
NUMBER RESOLUTION* MAXIMUM SAMPLE
RATE INPUT FREQUENCY
1369A-A
LTC2261-14 14-BIT 125 Msps 5MHz-170MHz
1369A-B
LTC2261-14 14-BIT 105 Msps 5MHz-170MHz
1369A-C
LTC2259-14 14-BIT 80 Msps 5MHz-170MHz
1369A-D
LTC2258-14 14-BIT 65 Msps 5MHz-170MHz
1369A-E
LTC2257-14 14-BIT 40 Msps 5MHz-170MHz
1369A-F
LTC2256-14 14-BIT 25 Msps 5MHz-170MHz
1369A-G
LTC2261-12 12-BIT 125 Msps 5MHz-170MHz
1369A-H
LTC2260-12 12-BIT 105 Msps 5MHz-170MHz
1369A-I
LTC2259-12 12-BIT 80 Msps 5MHz-170MHz
1369A-J
LTC2258-12 12-BIT 65 Msps 5MHz-170MHz
1369A-K
LTC2257-12 12-BIT 40 Msps 5MHz-170MHz
1369A-L
LTC2256-12 12-BIT 25 Msps 5MHz-170MHz
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1369
12/14 BIT, 25 TO125 MSPS ADC
2
Table 2.
Performance Summary (TA = 25°C)
PARAMETER CONDITION VALUE
Supply Voltage – DC1369A Depending on sampli ng rate and the A/D converter
provided, this supply must provide up to 250mA. Optimized for 3.6V
[3.5V Ù6.0V min/max]
Analog input range Depending on SENSE Pin Voltage 1 VPP to 2VPP
Logic Input Voltages Minimum Logic High 1.3V
Maximum Logic Low 0.6V
Logic Output Voltages (differential)
Nominal Logic levels (100 Ω load, 3.5mA Mode) 350mV/1.25V common mode
Minimum Logic levels (100Ω load, 3.5mA Mode) 247mV/1.25V common mode
Sampling Frequenc y (Convert Clock Fre-
quency) See Table 1
Convert Clock Level Single ended Encode Mode (ENC- tied to GND) 0-3.6V
Convert Clock Level Differential Encode Mode (ENC- not tied to GND) 0.2V-3.6V
Resolution See Table 1
Input frequency range See Table 1
SFDR See Applicable Data Sheet
SNR See Applicable Data Sheet
QUICK START PROCEDURE
Demonstration circuit 1369 is easy to set up to
evaluate the performance of the LTC2261 A/D
converters. Refer to Figure 1 for proper mea-
surement equipment setup and follow the pro-
cedure below:
SETUP
If a DC890 FastDAACS Data Acquisition and
Collection System was supplied with the DC1369
demonstration circuit, follow the DC890 Quick
Start Guide to install the required software and
for connecting the DC890 to the DC1369 and to
a PC running Windows98, 2000 or XP.
3
Figure 1. DC1369 Setup (zoom for detail)
DC1369 DEMONSTRATION CIRCUIT BOARD JUMPERS
The DC1369 demonstration circuit
board should have the following jumper
settings as default positions: (as per
Figure 1)
JP2: PAR/SER : Selects Parallel or Serial
programming mode. (Default - Serial)
JP3: Duty Cycle Stabilizer: Enables/ Disable
Duty Cycle Stabilizer. (Default - Enable)
JP4: SHDN: Enables and disables the
LTC2261. (Default - Enable)
3.5-6V
+
Analog Input
Single Ended
Encode Clock
Parallel Data Output
To DC890
Jumpers are shown in
default positions.
Duty Cycle Stabilizer
SHDN
Parallel/Serial Pro-
gramming mode
4
APPLYING POWER AND SIGNALS TO THE
DC996 DEMONSTRATION CIRCUIT
If a DC890 is used to acquire data from the
DC1369, the DC890 must FIRST be con-
nected to a powered USB port or provided an
external 6-9V BEFORE applying +3.6V to
+6.0V across the pins marked “V+” and
“GND” on the DC1369. DC1369 require 3.6V
for proper operation, regulators on the board
produce the voltages required for the ADC.
The DC1369 demonstration circuit requires up
to 250mA depending on the sampling rate and
the A/D converter supplied.
The DC890 data collection board is powered
by the USB cable and does not require an ex-
ternal power supply unless it must be con-
nected to the PC through an un-powered hub
in which case it must be supplied an external
6-9V on turrets G7(+) and G1(-) or the adja-
cent 2.1mm power jack.
ANALOG INPUT NETWORK
For optimal distortion and noise performance
the RC network on the analog inputs may
need to be optimized for different analog input
frequencies. For input frequencies above 170
MHz, refer to the LTC2261 datasheet for a
proper input network. Other input networks
may be more appropriate for input frequen-
cies less that 5MHz.
In almost all cases, filters will be required on
both analog input and encode clock to provide
data sheet SNR. In the case of the DC1369 a
band pass filter used for the clock should be
used prior to the DC1075A.
The filters should be located close to the in-
puts to avoid reflections from impedance dis-
continuities at the driven end of a long trans-
mission line. Most filters do not present 50Ω
outside the passband. In some cases, 3dB to
10dB pads may be required to obtain low dis-
tortion.
If your generator cannot deliver full scale sig-
nals without distortion, you may benefit from a
medium power amplifier based on a Gallium
Arsenide Gain block prior to the final filter.
This is particularly true at higher frequencies
where IC based operational amplifiers may be
unable to deliver the combination of low noise
figure and High IP3 point required. A high or-
der filter can be used prior to this final amplifi-
er, and a relatively lower Q filter used be-
tween the amplifier and the demo circuit.
ENCODE CLOCK
NOTE: Apply an encode clock to the SMA
connector on the DC1369 demonstration cir-
cuit board marked “J7”. As a default the
DC1369 is populated to have a single ended
input.
For the best noise performance, the ENCODE
INPUT must be driven with a very low jitter,
square wave source. The amplitude should be
large, up to 3VP-P or 13dBm. When using a
sinusoidal signal generator a squaring circuit
can be used. Linear Technology also pro-
vides demo board DC1075A that divides a
high frequency sine wave by four, producing a
low jitter square wave for best results with the
LTC2261.
Using band pass filters on the clock and the
analog input will improve the noise perfor-
mance by reducing the wideband noise power
of the signals. In the case of the DC1369 a
band pass filter used for the clock should be
used prior to the DC1075A. Datasheet FFT
5
plots are taken with 10 pole LC filters made by
TTE (Los Angeles, CA) to suppress signal
generator harmonics, non-harmonically re-
lated spurs and broadband noise. Low phase
noise Agilent 8644B generators are used with
TTE band pass filters for both the Clock input
and the Analog input.
Apply the analog input signal of interest to the
SMA connectors on the DC1369 demonstra-
tion circuit board marked “J5 AIN+”. These
inputs are capacitive coupled to Balun trans-
formers ETC1-1-13.
An internally generated conversion clock out-
put is available on J1 which could be collected
via a logic analyzer, or other data collection
system if populated with a SAMTEC MEC8-
150 type connector or collected by the DC890
QuickEval-II Data Acquisition Board using
PScope software.
SOFTWARE
The DC890B is controlled by the PScope Sys-
tem Software provided or downloaded from
the Linear Technology website at
http://www.linear.com/software/. If a DC890B
was provided, follow the DC890 Quick Start
Guide and the instructions below.
To start the data collection software if
“PScope.exe”, is installed (by default) in
\Program Files\LTC\PScope\, double click the
PScope Icon or bring up the run window un-
der the start menu and browse to the PScope
directory and select PScope.
If the DC1369 demonstration circuit is proper-
ly connected to the DC890, PSCOPE should
automatically detect the DC1369, and confi-
gure itself accordingly. If necessary the pro-
cedure below explains how to manually confi-
gure PSCOPE.
Under the “Configure” menu, go to “ADC
Configuration....” Check the “Config Manual-
ly” box and use the following configuration op-
tions, see Figure 2:
Manual Configuration settings:
Bits: 14
Alignment: 14
FPGA Ld: DDR LVDS
Channs: 2
Bipolar: Checked
Positive-Edge Clk: Checked
Figure 2: ADC configuration
If everything is hooked up properly, powered
and a suitable convert clock is present, click-
ing the “Collect” button should result in time
and frequency plots displayed in the PScope
window. Additional information and help for
PScope is available in the DC890B Quick
Start Guide and in the online help available
within the PScope program itself.
6
SERIAL PROGRAMMING
PScope has the ability to program the DC1369
board serially through the DC890. There are
several options available in the LTC2261 family
that are only available through serially pro-
gramming. PScope allows all of these features
to be te sted.
These options are available by first clicking on
the “Set Demo Bd Options” icon on the PScope
toolbar (Figure 3).
Figure 3: PScope Toolbar
This will b ring up the menu shown in figure 4.
Figure 4: Demobd Configuration Options.
This menu allows any of th e optio ns available for
the LTC2261 family to be programmed serially.
The LTC2261 family has the following options:
Power Control
– Selects between normal oper-
ation, nap, and sleep mod e s:
- Normal (Default) – En tire ADC is powered , and
active
- Nap – ADC core powers down while references
stay active.
- Shutdown – The entire ADC is powered down.
Clock Inversion
– Selects the polarity of the
CLKOUT signal:
- Normal (Default) – No rmal CL KOUT polarity
- Inverted – CLKOUT polarity is inverted
Clock Delay
- Selects the phase delay of the
CLKOUT signal:
- None (Default) – No CLKOUT delay
- 45 deg – CLKOUT delayed by 45 degrees
- 90 deg – CLKOUT delayed by 90 degrees
- 135 deg – CLKOUT delayed by 135 degrees
Clock Duty Cycle
– Enable or disables Duty
Cycle Stabilizer
- Stabilizer off (Default) – Duty Cycle Stabilizer
Disabled
- Stabilizer on – Duty Cycle Stabilizer Enabled
Output Current
– Selects the LVDS outpu t drive
current
- 1.75mA (Default) - LVDS output driver current
- 2.1mA - LVDS output driver current
- 2.5mA - LVDS output driver current
- 3.0mA - LVDS output driver current
- 3.5mA - LVDS output driver current
- 4.0mA - LVDS output driver current
- 4.5mA - LVDS output driver current
Internal Termination
– Enables LVDS internal
termination
7
- Off (Default) – Disables internal termination
- On – Enables internal termination
Outputs
– Enables Digital Outputs
- Enabled (Default) – Enables digital outputs
- Disabled – Disables digital outputs
Output Mode
– Selects Digital output mo de
- Full Rate – Full rate CMOS output mode (This
mode is not supported by the DC1369A, please
use the DC13 70)
- Double LVDS (Default) – double data rate
LVDS output mode
- Double CMOS – double data rate CMOS out-
put mode (This mode is not supported by the
DC1369A, please use the DC1370)
Test Pattern
– Selects Digital output test pat-
terns
- Off (Default) – ADC data presented at output
- All out =1 – All digital outputs are 1
- All out = 0 – All digital outputs are 0
- Checkerboard - OF, and D13-D0 Alternate be-
tween 101 0101 1010 0101 and 010 1010 0101
1010 on alternating samples.
- Alternating – Digital outputs alternate between
all 1’s and all 0’s on alternating samples.
Alternate Bit
– Alternate Bit Polarity (ABP)
Mode
- Off (Default) – Disables alternate bit polarity
- On – Enables alternate bit polarity (Before
enabling ABP, be sure the part is in offset binary
mode)
Randomizer
– Enables Data Output Randomiz-
er
- Off (Default) – Disables data output randomizer
- On – Enables data output randomizer
Two’s complement
– Enables two’s comple-
ment mode
- Off (Default) – Selects offset binary mode
- On – Selects two’s complement mode
Once the desired settings are selected hit OK
and PScope will automatically update the regis-
ter of the device on the DC1369 demo board.
8
-D12/D13
CS
PAR/SER
VDD
R54 0
SCL
U6 LT1763CDE
78
5
6
9
10 2
4
11 3
12
1
GNDSHDN
SENSE
BYP
NC
IN OUT
NC
IN OUT
NC
NC
R47 0
R49
OPT
FAST DAACS BOAR D ID CIRC UITRY
-CLK
C27 0.1uF
C35
0.1uF
C6
0.01uF
1 2
+D0/D1
J9
ENC-
C30
0.1uF
L6
OPT
TP1
EXT REF
U3
FIN1108
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
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28
29
30
31
33
34
36
35
37
38
39
40
41
42
43
44
45
46
48
47
OUT6-
VE1
VE2
EN12
IN1-
IN1+
IN2+
IN2-
IN3-
IN3+
IN4+
IN4-
VC1
EN
IN5-
IN5+
IN6+
IN6-
IN7-
IN7+
IN8+
IN8-
EN34
VE3
VBB
VC2
VC3
EN56
OUT8-
OUT8+
OUT7+
OUT7-
OUT6+
OUT5+
VE4
OUT5-
VE5
OUT4-
OUR4+
OUT3+
OUT3-
OUT2-
OUT2+
OUT1+
OUT1-
EN78
VC5
VC4
+D4/D5
C20
1uF
VDD
J5
AIN+
OVDD
C21
0.1uF
JP4
SHDN
EN
DIS
1
3
2
C29
0.1uF
SDI
R46 OPT
TP3
GND
-D4/D5
VCC_IN
VDD
C22
1uF
R17
100
VDD
R35
1K
R52
OPT
R9 0
W
-D2/D3
R14
1K
C61
0.01uF
1 2
ENABLE
C55
22uF
JP2
PAR
SER
PAR/SER
1
3
2
OVDD
VOUT
SD0
SDI
C33
0.1uF
C13
1uF
SDA
R40
1%
24.9
VDD
C37
0.1uF
TP4
R2
301
1%
R23
100
W
VDD
GND
VOUT
-D8/D9
C1
OPT
1 2
+CLK
SCK
L4
BEAD
R33
1K
R22
100
R56
OPT
C60
0.01uF
1 2
C36
0.1uF
C18
0.1uF
R30
100
R34
1K
RN1 33
1
2
3
4
8
7
6
5
VSS
VCC_IN
R24
100K
C14
1uF
ENABLE
R21
100
R45 86.6 1%
C31
0.1uF
U4 LT1763CDE-1.8
78
5
6
9
10 2
4
11 3
12
1
GNDSHDN
SENSE
BYP
NC
IN OUT
NC
IN OUT
NC
NC
R18
100
+D12/D13
SD0
C12
0.1uF
R7 10K 1%
R1
301
1%
C51
4.7pF
SCL
R50 36nH
R20
100
P1 EDGE-CON-100
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
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70
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96
98
100
1
3
5
7
9
11
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25
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79
81
83
85
87
89
91
93
95
97
99
R10 0
C54
22uF
L1 56uH
VCC_IN
C38
0.01uF
SCL
VDD
SD0
SDA
-D6/D7
U1 24LC025-I/ST
1
2
3
4 5
6
7
8
A0
A1
A2
A3 SDA
SCL
WP
VCC
R16
100
C17
1uF
J7
ENC+
R29 4.99K 1%
SDI
C3
0.01uF
1 2
TP5
GND
R48 0
R8 6.81K 1%
L2
BEAD
D1
HSMS-2822
1 2
3
C56 0.1uF
SDA
C58
0
1 2
R44
86.6
1%
SDI
SCK
C59
0.01uF
1 2
+D2/D3
VSS
R39
1%
24.9
C39
0.01uF
VOUT
-D0/D0
R53 OPT
SCL
SDA
VOUT
C24
4.7uF
R26 4.99K 1%
C34
0.1uF
R19
100
OXA2
VIN
J8
2
4
6
8
10
12
14
1
3
5
7
9
11
13
5V
SCK/SCL
CS
GND
EEVCC
EEGND
NC
VUNREG
GND
MISO
MOSI/SDA
EESDA
EESCL
GND
SCL
U7 24LC32A-I/ST
1
2
3
4 5
6
7
8
A0
A1
A2
A3 SDA
SCL
WP
VCC
C7
0.01uF
1 2
T1
MABA-007159-000000
R4 OPT R55 OPT
+D6/D7
C9
8.2pF
PAR/SER
CS
VOUT
R57
0
RN2 33
1
2
3
4
8
7
6
5
L3 BEAD
VDD
+D8/D9
T3
WBC4-1WL
VSS
OX40
C52
100pF
C32
0.1uF
C26
0.1uF
R36
86.6
1%
R25 4.99K 1%
R51
OPT
L5
BEAD
-D10/D11
SCK
TP2
V+
3.5V - 6V
C10
8.2pF
CS
U2
LTC2261CUJ
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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26
27
28
29
30
31
33
34
36
35
37
38
39
40
41
D10_11+
AIN+
AIN-
GND
REFH
REFH
REFL
REFL
PAR/SER
VDD
VDD
ENC+
ENC-
CS
SCK
SDI
SDO
D0_1-
D0_1+
D2_3-
D2_3+
D4_5-
D4_5+
D6_7-
D6_7+
OGND
OVDD
CLKOUT-
CLKOUT+
D8_9-
D8_9+
D10_11-
D12_13-
D12_13+
OF+
OF-
VCM
VREF
SENSE
VDD
GND
VCC_IN
C23
1uF
VOUT
+D10/D11
SDA
U5
PCF8574TS/3
10
11
12
14416
17
19
20
15
2
1
5
6
7
9
8
3
13
18
P0
P1
P2
P3SDA P4
P5
P6
P7
GND
SCL
INT
VDD
A0
A1
A2
NC
NC
NC
NC
C53
100pF
C19
0.1uF
C2 0.01uF
OXA0
VDD
CS
JP3
DUTY CYCLE ST AB.
EN
DIS
1
3
2
R6
10K
C28
0.1uF
R5 OPT
T2
MABAES0060
C15
0.1uF
C57
0
1 2