1PS8741D 01/12/10
Product Features
• 16 LVCMOS/LVTTL outputs (4 banks of 4 outputs)
• Selectable differential or single-ended clock inputs
• CLK1, nCLK1 pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• CLK0 supports the following input types: LVCMOS, LVTTL
• Maximum output frequency: 250MHz
• Independent bank control for ÷1 or ÷2 operation
• Independent output bank voltage settings for 3.3V, 2.5V, or
1.8V operations
• Output skew: 170ps (max)
• Bank skew: 30ps (max)
• Part-to-part skew: 750ps (max)
• 3.3V core, 3.3V, 2.5V, or 1.8V output operating supply
• -40° to +85°C ambient operating temperature
• Available packages:
-Pb-free & green 48-pin LQFP(FB)
Product Description
The PI6C487016 is a low skew. 1:16 LVCMOS/LVTTL Clock
Driver. The device has 4 banks of 4 outputs and each bank can be
independently selected for ÷1 or ÷2 frequency operation. Each bank
also has its own power supply pins so that the banks can operate
at the following different voltage levels: 3.3V, 2.5V, and 1.8V. The
low impedance LVCMOS/LVTTL outputs are designed to drive
50Ω series or parallel terminated transmission lines.
The divide select inputs, SELA: SELD, control the output frequency
of each bank with either ÷1 or ÷2 frequency operation. The bank
enable inputs, ENA: END, support enabling and disabling each bank
of outputs individually. The outputs synchronized when enabling
or disabling the clock outputs. The master reset input nMR/OE,
resets the ÷1/÷2 fl ip fl ops and also controls the active and high
impedance states of all outputs.
The PI6C487016 is characterized to operate with the core at 3.3V
and the output banks at 3.3V, 2.5V or 1.8V.
Block Diagram Pin Description
PI6C487016
Low Skew, 1-to-16
LVCMOS / LVTTL Clock Driver
GND
QC2
VDDOC
QC3
GND
QD0
VDDOD
QD1
GND
QD2
VDDOD
QD3
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
VDD
CLK0
SELA
SELB
SELC
SELD
ENA
ENB
ENC
END
nMR/OE
GND
GND
QB0
VDDOB
QB1
GND
QB2
VDDOB
QB3
GND
QC0
VDDOC
QC1
QA3
VDDOA
QA2
GND
QA1
VDDOA
QA0
GND
CLK_SEL
nCLK1
CLK1
VDD
1
0
1
0
1
0
0
1
1
0
÷1
÷2
4
4
4
4
D
LE
D
LE
D
LE
D
LE QA0:QA3
QB0:QB3
QC0:QC3
QD0:QD3
nMR/OE
CLK0
CLK1
nCLK1
CLK_SEL
SELA
SELB
SELC
SELD
ENA
ENB
ENC
END
10-0008
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PI6C487016
Low Skew, 1-to-16
LVCMOS/LVTTL Clock Driver
PS8741D 01/12/10
Pin Descriptions
Number Name Type Description
1, 48 VDD Power Core supply pins (3.3V)
2 CLK0 Input Pulldown LVCMOS / LVTTL clock input
3, 4, 5, 6 SELA :
SELD Input Pullup Controls frequency division for outputs. LVCMOS / LVTTL interface
levels. QAx:QDx
7, 8, 9, 10 ENA : END Input Pullup Output enable for QAx : QDx Outputs. Active HIGH. If pin is LOW,
outputs drive low. LVCMOS / LVTTL interface levels.
11 nMR/OE Input Pullup Master reset. When LOW, resets the ÷1/÷2 fl ip fl ops and sets the outputs
to high impedance. LVCMOS / LVTTL interface levels.
12, 16, 20, 24,
28, 32, 36, 40,
44
GND Power Supply Ground
13, 15, 17, 19 QD0 : QD3 Output Bank D Outputs, LVCMOS / LVTTL interface levels.
14, 18 VDDOD Power Voltage supply for QD0 : QD3
21, 23, 25, 27 QC0 : QC3 Output Bank C outputs, LVCMOS / LVTTL interface levels.
22, 26 VDDOC Power Voltage supply for QC0 : QC3
29, 31, 33, 35 QB0 : QB3 Output Bank B outputs, LVCMOS / LVTTL interface levels.
30, 34 VDDOB Power Voltage supply for QB0 : QB3
37, 39, 41, 43 QA0 : QA3 Output Bank A outputs, LVCMOS / LVTTL interface levels.
38, 42 VDDOA Power Voltage supply for QA0 : QA3
45 CLK_SEL Input Pulldown Clock select input, when HIGH, select CLK1, nCLK1 inputs. When
LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
46 nCLK1 Input Pullup Inverting differential clock input
47 CLK1 Input Pulldown Non-inverting differential clock input
Notes:
1. Pullup and Pulldown refer to internal input resistors. See Table 2, Pin characteristics, for typical values.
Function Table Inputs Outputs
nMR/OE ENx SELx Bank X Qx Frequency
0 X X Hi Z N/A
1 1 0 Active FIN/2
1 1 1 Active FIN
1 0 X Low N/A
10-0008
3
PI6C487016
Low Skew, 1-to-16
LVCMOS/LVTTL Clock Driver
PS8741D 01/12/10
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are
stress specifi cations only. Functional operation of products at
these conditions or any conditions beyond those listed in the DC
Characteristics or AC characteristics is not implied. Exposure to
absolute maximum rating conditions for extended periods may af-
fect product reliability.
Absolute Maximum Ratings
Pin Characteristics
Symbol Parameter Test Condition Min. Typ. Max. Units
CIN Input Capacitance 4 pF
RPULLDOWN Input Pulldown Resistor 51 kΩ
RPULLUP Input Pullup Resistor 51
CPD Power Dissipation Capaci-
tance (per output)
VDD, VDDOX = 3.465V 18
pfVDD = 3.465, VDDOX = 2.625V 20
VDD = 3.465, VDDOX = 1.895V 30
ROUT Output Impedance 5 7 12 Ω
Supply Voltage, VDD ....................... 4.6V
Inputs, VI ...................................................... -0.5V to VDD +0.5V
Outputs, V0 .................................................. -0.5V to VDDO +0.5V
Package Thermal Impedance, ØJA .....47.9° C/W (0lfpm)
Storage Temperature, TSTG ................... -65°C to +150°C
Power Supply DC Characteristics, (VDD = 3.3V ±5%, TA = -40º to +85ºC)
Symbol Parameter Min. Typ. Max. Units
VDD Core Supply Voltage 3.135 3.3 3.465
V
VDDOX Output Supply Voltage
3.135 3.3 3.465
2.375 2.5 2.625
1.71 1.8 1.89
IDD Core Supply Current 100 mA
IDDOX Output Supply Current(1) 15
Note:
1. Measured with all outputs disabled (ENx=0, nMR=1)
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PI6C487016
Low Skew, 1-to-16
LVCMOS/LVTTL Clock Driver
PS8741D 01/12/10
LVCMOS/LVTTL DC Characteristics, (VDD = 3.3V ±5%, TA = -40º to +85ºC)
Symbol Parameter Test Conditions Min. Typ. Max. Units
VIH Input High Voltage
SELx, ENX,
nMR/OE, CLK_SEL 2V
DD + 0.3
V
CLK0 2 VDD + 0.3
VIL Input Low Voltage
SELx, ENx,
nMR/OE, CLK_SEL -0.3 0.8
CLK0 -0.3 1.3
IIH Input High Current
ENx, SELx,
nMR/OE VDD = VIN = 3..465V 5
μA
CLK0, CLK_SEL 150
IIL Input Low Current
ENx, SELx,
nMR/OE VDD = 3.465, VIN = 0V -150
CLK0, CLK_SEL -5
VOH Output High Voltage(1)
VDDOX = 3.3 ± 5% 2.6
V
VDDOX = 2.5 ± 5% 1.8
VDDOX = 1.8 ± 5%
IOH = -2mA
VDD -
0.45
VOL Output Low Voltage(1)
VDDOX = 3.3 ± 5% 0.5
VDDOX = 2.5 ± 5% 0.5
VDDOX = 1.8 ± 5%
IOH = -2mA 0.45
IOZL Output Tristate Current Low -5 μA
IOZH Output Tristate Current High 5
Notes:
1. Outputs terminate with 50Ω to VDDOX/2. See Parameter Measurement information, Output Load Test Circuit
Differential DC Characteristics, (VDD = 3.3V ±5%, TA = -40º to +85ºC)
Symbol Parameter Test Conditions Min. Typ. Max. Units
IIH Input High Current nCLK1 VIN = VDD = 3.465V 5
μA
CLK1 VIN = VDD = 3.465V 150
IIL Input Low Current nCLK1 VIN = 0V, VDD = 3.465V -150
CLK1 VIN = 0V, VDD = 3.465V -5
VPP Peak-to-peak Input Voltage 0.15 1.3 V
VCMR Common mode input voltage(1,2) GND + 0.5 VDD -0.85
Notes:
1. For single ended application, the maximum input voltage for CLK1, nCLK1 is VDD + 0.3V.
2. Common mode voltage is defi ned as VIH.
10-0008
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PI6C487016
Low Skew, 1-to-16
LVCMOS/LVTTL Clock Driver
PS8741D 01/12/10
AC Characteristics, (VDD = 3.3V ±5%, VDDOX = 1.8V ±5% to 3.3V ±5%, TA = -40° to +85°C)(7)
Symbol Parameter Test Conditions Min. Typ. Max. Units
fMAX Output Frequency 250 MHz
TpLH Propagation Delay,
Low to High
CLK0(1)
VDDOX = 3.3V 2.3 3.4 3.9
ns
CLK1, nCLK1(2) 2.5 3.4 3.9
CLK0(1)
VDDOX = 2.5V 2.3 3.5 4.0
CLK1, nCLK1(2) 2.5 3.5 4.0
CLK0(1)
VDDOX = 1.8V 2.4 3.9 4.7
CLK1, nCLK1(2) 2.6 3.9 4.7
tsk(b) Bank skew(3) Measured on the rising edge 30
ps
tsk(o) Output skew(4) Measured on the rising edge 170
tsk(pp) Part-to-Part skew(5) 750
tR/tFOutput Rise/Fall Time(5) 20% to 80% 200 700
odc Output duty cycle 40 60 %
tEN Output enable time(6) 10 ns
tDIS Output Disable Time(6) 10
Notes:
1. Measured from the VDD/2 of the input to VDDOX/2 of the output
2. Measured from the differential input crossing point to VDDOX/2 of the output
3. Defi ned as a skew within a bandwidth equal load conditions
4. Defi ned as a skew between outputs at the same supply voltage, same frequency, and with equal load conditions. Measured at VDDOX/2
5. Defi ned as a skew between outputs on a different devices operation at the same supply voltages and with equal load conditions. Using the
same type of input on each device, the output is measured at VDDOX/2.
6. These parameters are guaranteed by characterization. Not tested in production.
7. All parameters are measured at 250MHz with SEL [A:D] = 1 unless noted otherwise.
10-0008
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PI6C487016
Low Skew, 1-to-16
LVCMOS/LVTTL Clock Driver
PS8741D 01/12/10
3.3V Core/3.3V Output Load AC Test Circuit
Parameter Measurement Information
3.3V Core/1.8V Output Load AC Test Circuit Differential Input Level
3.3V Core/2.5V Output Load AC Circuit
SCOPE
Qx
LVCMOS
1.65V±5%
-1.65V±5%
GND
VDD,
VDDOx
SCOPE
Qx
LVCMOS
2.05V±5%
VDDOx
-1.25V±5%
VDD
1.25V±5%
GND
SCOPE
Qx
LVCMOS
2.4±0.9V
VDDOx
GND = -0.9V±5%
VDD
+0.9V±5%
V
CMR
Cross Points
V
PP
GND
CLK1
nCLK1
VDD
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PI6C487016
Low Skew, 1-to-16
LVCMOS/LVTTL Clock Driver
PS8741D 01/12/10
Application Information
Wiring the differential input to accept single ended levels
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 adn R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R1/R2 = 0.609.
Figure 1: Single-ended Signal Driving Differential Input
Single Ended
Clock Input
VDD
R1
1K
R2
1K
C1
0.1μ
CLK1
nCLK1
10-0008
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PI6C487016
Low Skew, 1-to-16
LVCMOS/LVTTL Clock Driver
PS8741D 01/12/10
Package Mechanical: 48-pin LQFP (FB)
Pericom Semiconductor Corporation • 1-800-435-2336 • http://www.pericom.com
Ordering Information
Ordering Code Package Code Package Type
PI6C487016FBE FB Pb-free & Green, 48-pin LQFP
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• Adding an X suffi x = Tape/Reel
DESCRIPTION: 48-Contact, Low Profi le Quad Flat Package (LQFP)
PACKAGE CODE: FB (FB48)
DOCUMENT CONTROL #: PD-2027 REVISION: C
DATE: 09/17/09
09-0012
Note:
• For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
10-0008
