PCIxx12 Single Socket CardBus Controller with Integrated 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller Data Manual Includes: PCI4512GHK, PCI4512ZHK, PCI6412GHK, PCI6412ZHK, PCI6612GHK, PCI6612ZHK, PCI7402GHK, PCI7402ZHK, PCI7412GHK, PCI7412ZHK, PCI7612GHK, PCI7612ZHK, PCI8402GHK, PCI8402ZHK, PCI8412GHK, PCI8412ZHK Literature Number: SCPS110 September 2005 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated Contents Section 1 2 3 Page PCIxx12 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Controller Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 PCI4512 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 PCI6412 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.3 PCI6612 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.4 PCI7402 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.5 PCI7412 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.6 PCI7612 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.7 PCI8402 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.8 PCI8412 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.9 Multifunctional Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.10 PCI Bus Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.11 Power Switch Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Document Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Terms and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 PCIxx12 Data Manual Document History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 Detailed Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Principles of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Clamping Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Peripheral Component Interconnect (PCI) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 1394 PCI Bus Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Device Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 Serial EEPROM I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 Function 0 (CardBus) Subsystem Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.5 Function 1 (OHCI 1394) Subsystem Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.6 Function 2 (Flash Media) Subsystem Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.7 Function 3 (SD Host) Subsystem Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.8 Function 4 (Smart Card) Subsystem Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 PC Card Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 PC Card Insertion/Removal and Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 Low Voltage CardBus Card Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 PC Card Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.4 Flash Media and Smart Card Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.5 Power Switch Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.6 Internal Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.7 Integrated Pullup Resistors for PC Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.8 SPKROUT and CAUDPWM Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.9 LED Socket Activity Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.10 CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.11 48-MHz Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . September 2005 SCPS110 1 3 4 4 4 5 5 6 6 7 7 8 8 8 8 9 9 10 11 11 11 28 43 43 44 44 44 44 45 45 46 47 47 47 47 47 48 48 48 49 50 51 51 51 51 52 52 iii Contents Section Page 3.6 53 53 53 53 55 58 58 60 60 61 61 62 62 63 63 64 64 65 65 66 66 67 68 69 69 72 72 73 74 76 76 77 77 78 79 80 80 80 80 81 81 81 81 82 82 83 83 83 4 iv Serial EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 Serial-Bus Interface Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2 Accessing Serial-Bus Devices Through Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 Serial-Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.4 Serial-Bus EEPROM Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Programmable Interrupt Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.1 PC Card Functional and Card Status Change Interrupts . . . . . . . . . . . . . . . . . . . . . . 3.7.2 Interrupt Masks and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.3 Using Parallel IRQ Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.4 Using Parallel PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.5 Using Serialized IRQSER Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.6 SMI Support in the PCIxx12 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 Power-Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 1394 Power Management (Function 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.2 Integrated Low-Dropout Voltage Regulator (LDO-VR) . . . . . . . . . . . . . . . . . . . . . . . . 3.8.3 Clock Run Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.4 CardBus PC Card Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.5 16-Bit PC Card Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.6 Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.7 Requirements for Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.8 Ring Indicate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.9 PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.10 CardBus Bridge Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.11 ACPI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.12 Master List of PME Context Bits and Global Reset-Only Bits . . . . . . . . . . . . . . . . . . 3.9 IEEE 1394 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.1 PHY Port Cable Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.2 Crystal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.3 Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PC Card Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 PCI Configuration Register Map (Function 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Device ID Register Function 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 CardBus Socket Registers/ExCA Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13 Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.15 PCI Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16 CardBus Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17 Subordinate Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.18 CardBus Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCPS110 September 2005 Section 5 4.19 4.20 4.21 4.22 4.23 4.24 4.25 4.26 4.27 4.28 4.29 4.30 4.31 4.32 4.33 4.34 4.35 4.36 4.37 4.38 4.39 4.40 4.41 4.42 4.43 4.44 4.45 4.46 4.47 4.48 4.49 ExCA 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 Page CardBus Memory Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CardBus Memory Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CardBus I/O Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CardBus I/O Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PC Card 16-Bit I/F Legacy-Mode Base-Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Event Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Event Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multifunction Routing Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Retry Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Card Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Control/Status Bridge Support Extensions Register . . . . . . . . . . . . . . . . . Power-Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Bus Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Bus Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Bus Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Bus Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compatibilty Registers (Function 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Identification and Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Interface Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Power Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Interrupt and General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Card Status-Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Card Status-Change Interrupt Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Address Window Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA I/O Window Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA I/O Windows 0 and 1 End-Address High-Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Memory Windows 0-4 Start-Address Low-Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . ExCA Memory Windows 0-4 Start-Address High-Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . ExCA Memory Windows 0-4 End-Address Low-Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Memory Windows 0-4 End-Address High-Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . September 2005 SCPS110 84 84 85 85 86 86 87 88 88 88 89 91 93 93 94 94 95 96 97 98 99 99 99 100 101 102 102 103 103 104 104 106 110 111 112 113 114 115 116 117 118 118 118 119 119 120 120 121 v Contents Section 6 7 8 vi Page 5.17 ExCA Memory Windows 0-4 Offset-Address Low-Byte Registers . . . . . . . . . . . . . . . . . . . . . . . 5.18 ExCA Memory Windows 0-4 Offset-Address High-Byte Registers . . . . . . . . . . . . . . . . . . . . . . . 5.19 ExCA Card Detect and General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.20 ExCA Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . 5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . 5.23 ExCA Memory Windows 0-4 Page Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CardBus Socket Registers (Function 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Socket Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Socket Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Socket Present State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Socket Force Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 Socket Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 Socket Power Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OHCI Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Class Code and Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 Latency Timer and Class Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 Header Type and BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8 OHCI Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9 TI Extension Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.10 CardBus CIS Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.11 CardBus CIS Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.12 Subsystem Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.13 Power Management Capabilities Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.14 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.15 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.16 Minimum Grant and Maximum Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.17 OHCI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.18 Capability ID and Next Item Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.19 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.20 Power Management Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.21 Power Management Extension Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.22 PCI PHY Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.23 PCI Miscellaneous Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.24 Link Enhancement Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.25 Subsystem Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.26 GPIO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OHCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 OHCI Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 GUID ROM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Asynchronous Transmit Retries Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 CSR Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 CSR Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 CSR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCPS110 121 122 123 124 124 125 125 126 127 128 129 131 132 133 134 135 135 136 137 138 138 139 139 140 140 141 141 141 142 142 143 143 144 145 146 146 147 148 149 150 151 153 156 156 157 157 158 158 September 2005 Section Page 8.7 Configuration ROM Header Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8 Bus Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.9 Bus Options Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.10 GUID High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.11 GUID Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.12 Configuration ROM Mapping Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.13 Posted Write Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.14 Posted Write Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.15 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.16 Host Controller Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.17 Self-ID Buffer Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.18 Self-ID Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.19 Isochronous Receive Channel Mask High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.20 Isochronous Receive Channel Mask Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.21 Interrupt Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.22 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.23 Isochronous Transmit Interrupt Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.24 Isochronous Transmit Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.25 Isochronous Receive Interrupt Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.26 Isochronous Receive Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.27 Initial Bandwidth Available Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.28 Initial Channels Available High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.29 Initial Channels Available Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.30 Fairness Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.31 Link Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.32 Node Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.33 PHY Layer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.34 Isochronous Cycle Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.35 Asynchronous Request Filter High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.36 Asynchronous Request Filter Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.37 Physical Request Filter High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.38 Physical Request Filter Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.39 Physical Upper Bound Register (Optional Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.40 Asynchronous Context Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.41 Asynchronous Context Command Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.42 Isochronous Transmit Context Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.43 Isochronous Transmit Context Command Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.44 Isochronous Receive Context Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.45 Isochronous Receive Context Command Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.46 Isochronous Receive Context Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TI Extension Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 DV and MPEG2 Timestamp Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Isochronous Receive Digital Video Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 Isochronous Receive Digital Video Enhancements Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 Link Enhancement Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 Timestamp Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PHY Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 Base Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . September 2005 SCPS110 159 159 160 161 161 161 162 162 162 163 164 165 166 167 168 170 172 172 173 173 174 174 175 175 176 177 178 178 179 181 182 184 184 185 186 187 188 188 189 190 191 191 192 192 194 195 196 196 vii Contents Section Page 10.2 Port Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Vendor Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 Vendor-Dependent Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 Power-Class Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash Media Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5 Class Code and Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6 Latency Timer and Class Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.7 Header Type and BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.8 Flash Media Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.9 Subsystem Vendor Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.10 Subsystem Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.11 Capabilities Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.12 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.13 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.14 Minimum Grant Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.15 Maximum Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.16 Capability ID and Next Item Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.17 Power-Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.18 Power-Management Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.19 Power-Management Bridge Support Extension Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.20 Power-Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.21 General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.22 Subsystem Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.23 Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SD Host Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 Class Code and Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 Latency Timer and Class Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7 Header Type and BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.8 SD Host Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.9 Subsystem Vendor Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.10 Subsystem Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.11 Capabilities Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.12 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.13 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.14 Minimum Grant Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.15 Maximum Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.16 Slot Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.17 Capability ID and Next Item Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.18 Power-Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.19 Power-Management Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii SCPS110 199 200 201 202 203 203 204 204 205 206 206 207 207 207 208 208 208 209 209 210 210 211 212 212 212 213 214 214 215 216 216 217 218 219 219 220 220 221 221 221 221 222 222 223 223 223 224 225 September 2005 Section Page 12.20 Power-Management Bridge Support Extension Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 12.21 Power-Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 12.22 General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 12.23 Subsystem Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 12.24 Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 12.25 Slot 0 3.3-V Maximum Current Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 13 Smart Card Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 13.1 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 13.2 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 13.3 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 13.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 13.5 Class Code and Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 13.6 Latency Timer and Class Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 13.7 Header Type and BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 13.8 Smart Card Base Address Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 13.9 Smart Card Base Address Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 13.10 Subsystem Vendor Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 13.11 Subsystem Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 13.12 Capabilities Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 13.13 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 13.14 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 13.15 Minimum Grant Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 13.16 Maximum Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 13.17 Capability ID and Next Item Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 13.18 Power-Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 13.19 Power-Management Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 13.20 Power-Management Bridge Support Extension Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 13.21 Power-Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 13.22 General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 13.23 Subsystem ID Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 13.24 Class Code Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 13.25 Smart Card Configuration 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 13.26 Smart Card Configuration 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 14 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 14.1 Absolute Maximum Ratings Over Operating Temperature Ranges . . . . . . . . . . . . . . . . . . . . . . . 242 14.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 14.3 Electrical Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . 244 14.4 Electrical Characteristics Over Recommended Ranges of Operating Conditions . . . . . . . . . . . 244 14.4.1 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 14.4.2 Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 14.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 14.5 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 14.6 Switching Characteristics for PHY Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 14.7 Operating, Timing, and Switching Characteristics of XI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 14.8 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 14.9 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 15 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 September 2005 SCPS110 ix Figures List of Figures Figure 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 5-1 5-2 6-1 14-1 14-2 14-3 14-4 14-5 x Page PCI4512 GHK/ZHK-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI6412 GHK/ZHK-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI6612 GHK/ZHK-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI7402 GHK/ZHK-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI7412 GHK/ZHK-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI7612 GHK/ZHK-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI8402 GHK/ZHK-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI8412 GHK/ZHK-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCIxx12 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-State Bidirectional Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Reset Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial ROM Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPKROUT Connection to Speaker Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sample LED Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial-Bus Start/Stop Conditions and Bit Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial-Bus Protocol Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial-Bus Protocol--Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial-Bus Protocol--Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Interface Doubleword Data Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Diagram Implementing CardBus Device Class Power Management . . . . . . . . . . . . . . . . . . Signal Diagram of Suspend Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RI_OUT Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram of a Status/Enable Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TP Cable Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Compliant DC Isolated Outer Shield Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-DC Isolated Outer Shield Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Capacitance for the PCIxx12 PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Crystal and Capacitor Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Register Access Through I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Register Access Through Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accessing CardBus Socket Registers Through PCI Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cold Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Warm Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Deactivation Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCPS110 12 13 14 15 16 17 18 19 43 44 45 46 51 52 54 54 54 55 55 61 63 65 66 69 72 72 73 74 74 107 107 126 245 247 247 248 248 September 2005 List of Tables Table 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 4-1 4-2 4-3 4-4 Page Functional Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terms and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Names by GHK Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CardBus PC Card Signal Names Sorted Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-Bit PC Card Signal Names Sorted Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial PC Card Power Switch Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel PC Card Power Switch Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multifunction and Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-Bit PC Card Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-Bit PC Card Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CardBus PC Card Interface System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CardBus PC Card Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CardBus PC Card Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1394 Physical Layer Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No Connect Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SD/MMC Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Stick/PRO Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Smart Media/XD Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Smart Card Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Bus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PC Card--Card Detect and Voltage Sense Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TPS2228 Control Logic--xVPP/VCORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TPS2228 Control Logic--xVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TPS2226 Control Logic--xVPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TPS2226 Control Logic--xVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCIxx12 Registers Used to Program Serial-Bus Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Loading Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Mask and Flag Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PC Card Interrupt Events and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Pin Register Cross Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Requirements for Internal/External 1.5-V Core Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function 1 Power-Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function 2 Power-Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function 3 Power-Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function 4 Power-Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Field Access Tag Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function 0 PCI Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . September 2005 SCPS110 3 10 21 24 26 29 30 30 30 31 32 33 34 35 36 37 38 38 39 39 40 40 41 42 44 49 50 50 50 50 52 53 56 59 59 61 62 64 67 68 68 68 68 76 76 78 79 xi Tables Table 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 6-1 6-2 6-3 6-4 6-5 6-6 6-7 7-1 7-2 7-3 7-4 7-5 xii Page Secondary Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Pin Register Cross Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bridge Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Event Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Event Enable Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Input Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Output Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multifunction Routing Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Retry Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Card Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostic Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Capabilities Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Control/Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Control/Status Bridge Support Extensions Register Description . . . . . . . . . . Serial Bus Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Bus Index Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Bus Slave Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Bus Control/Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Registers and Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Identification and Revision Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Interface Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Power Control Register Description--82365SL Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Power Control Register Description--82365SL-DF Support . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Interrupt and General Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Card Status-Change Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Card Status-Change Interrupt Configuration Register Description . . . . . . . . . . . . . . . . . . . . . ExCA Address Window Enable Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA I/O Window Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Memory Windows 0-4 Start-Address High-Byte Registers Description . . . . . . . . . . . . . . . . ExCA Memory Windows 0-4 End-Address High-Byte Registers Description . . . . . . . . . . . . . . . . . ExCA Memory Windows 0-4 Offset-Address High-Byte Registers Description . . . . . . . . . . . . . . . ExCA Card Detect and General Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Global Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Socket Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Socket Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Socket Present State Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Socket Force Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Socket Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Socket Power Management Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function 1 Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class Code and Revision ID Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latency Timer and Class Cache Line Size Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCPS110 82 86 87 89 91 93 93 94 94 95 96 97 98 99 100 101 102 103 103 104 105 108 110 111 112 112 113 114 115 116 117 120 121 122 123 124 126 127 128 129 131 132 133 134 136 137 138 138 September 2005 Table 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 8-20 8-21 8-22 8-23 8-24 8-25 8-26 8-27 8-28 8-29 8-30 8-31 Page Header Type and BIST Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OHCI Base Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TI Base Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CardBus CIS Base Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Subsystem Identification Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Line Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Interrupt Pin Register--Read-Only INTPIN Per Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Minimum Grant and Maximum Latency Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OHCI Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capability ID and Next Item Pointer Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Capabilities Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Control and Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Extension Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI PHY Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Miscellaneous Configuration Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Link Enhancement Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Subsystem Access Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OHCI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OHCI Version Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GUID ROM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Transmit Retries Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CSR Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration ROM Header Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Options Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration ROM Mapping Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Posted Write Address Low Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Posted Write Address High Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Controller Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-ID Count Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Receive Channel Mask High Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Receive Channel Mask Low Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Transmit Interrupt Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Receive Interrupt Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initial Bandwidth Available Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initial Channels Available High Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initial Channels Available Low Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fairness Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Link Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node Identification Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHY Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Cycle Timer Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Request Filter High Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Request Filter Low Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Request Filter High Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Request Filter Low Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Context Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . September 2005 SCPS110 139 139 140 140 141 142 142 143 143 144 145 146 146 147 148 149 150 153 156 156 157 158 159 160 161 162 162 163 165 166 167 168 170 172 173 174 174 175 175 176 177 178 178 179 181 182 184 185 xiii Tables Table Page 8-32 8-33 8-34 8-35 9-1 9-2 9-3 9-4 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 xiv Asynchronous Context Command Pointer Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Transmit Context Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Receive Context Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Receive Context Match Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TI Extension Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Receive Digital Video Enhancements Register Description . . . . . . . . . . . . . . . . . . . . . Link Enhancement Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timestamp Offset Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Base Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Base Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 0 (Port Status) Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 0 (Port Status) Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 1 (Vendor ID) Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 1 (Vendor ID) Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 7 (Vendor-Dependent) Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 7 (Vendor-Dependent) Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Class Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function 2 Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class Code and Revision ID Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latency Timer and Class Cache Line Size Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . Header Type and BIST Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Media Base Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Minimum Grant Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Latency Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capability ID and Next Item Pointer Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Management Capabilities Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Management Control and Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Subsystem Access Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostic Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function 3 Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class Code and Revision ID Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latency Timer and Class Cache Line Size Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . Header Type and BIST Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SD Host Base Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Minimum Grant Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Latency Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Latency Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capability ID and Next Item Pointer Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Management Capabilities Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Management Control and Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCPS110 186 187 188 190 191 192 194 195 196 197 199 199 200 200 201 201 202 203 204 205 206 206 207 207 209 209 210 210 211 212 213 214 214 215 217 218 219 219 220 220 222 222 223 223 223 224 225 226 September 2005 Table 12-16 12-17 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 13-13 13-14 13-15 13-16 Page Subsystem Access Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostic Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function 4 Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class Code and Revision ID Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latency Timer and Class Cache Line Size Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . Header Type and BIST Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Minimum Grant Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Latency Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capability ID and Next Item Pointer Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Management Capabilities Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Management Control and Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Subsystem ID Alias Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Smart Card Configuration 1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Smart Card Configuration 2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . September 2005 SCPS110 227 227 228 230 231 232 232 233 235 235 236 236 237 238 239 239 241 241 xv Tables (This page has been left blank intentionally.) xvi SCPS110 September 2005 Features 1 PCIxx12 Features D PC Card Standard 8.1 Compliant D PCI Bus Power Management Interface D D D D D D D D D D D D D D D D Specification 1.1 Compliant Advanced Configuration and Power Interface (ACPI) Specification 2.0 Compliant PCI Local Bus Specification Revision 2.3 Compliant Windows Logo Program Compliant PCI Bus Interface Specification for PCI-to-CardBus Bridges Fully Compliant with Provisions of IEEE Std 1394-1995 for a High-Performance Serial Bus and IEEE Std 1394a-2000 Fully Compliant with 1394 Open Host Controller Interface Specification 1.1 1.5-V Core Logic and 3.3-V I/O Cells with Internal Voltage Regulator to Generate 1.5-V Core VCC Universal PCI Interfaces Compatible with 3.3-V and 5-V PCI Signaling Environments Supports PC Card or CardBus with Hot Insertion and Removal Supports 132-MBps Burst Transfers to Maximize Data Throughput on Both the PCI Bus and the CardBus Supports Serialized IRQ with PCI Interrupts Programmable Multifunction Terminals Many Interrupt Modes Supported Serial ROM Interface for Loading Subsystem ID and Subsystem Vendor ID ExCA-Compatible Registers Are Mapped in Memory or I/O Space Intel 82365SL-DF Register Compatible D Supports Ring Indicate, SUSPEND, and PCI D D D D D D D D D D D D D CLKRUN Protocols Provides VGA/Palette Memory and I/O, and Subtractive Decoding Options, LED Activity Terminals Fully Interoperable with FireWireE and i.LINKE Implementations of IEEE Std 1394 Compliant with Intel Mobile Power Guideline 2000 Full IEEE Std 1394a-2000 Support Includes: Connection Debounce, Arbitrated Short Reset, Multispeed Concatenation, Arbitration Acceleration, Fly-By Concatenation, and Port Disable/Suspend/Resume Power-Down Features to Conserve Energy in Battery-Powered Applications Include: Automatic Device Power Down During Suspend, PCI Power Management for Link-Layer, and Inactive Ports Powered Down, Ultralow-Power Sleep Mode Two IEEE Std 1394a-2000 Fully Compliant Cable Ports at 100M Bits/s, 200M Bits/s, and 400M Bits/s Cable Ports Monitor Line Conditions for Active Connection to Remote Node Cable Power Presence Monitoring Separate Cable Bias (TPBIAS) for Each Port Physical Write Posting of up to Three Outstanding Transactions PCI Burst Transfers and Deep FIFOs to Tolerate Large Host Latency External Cycle Timer Control for Customized Synchronization Extended Resume Signaling for Compatibility with Legacy DV Components MicroStar BGA is a trademark of Texas Instruments. Other trademarks are the property of their respective owners. September 2005 SCPS110 1 Features D PHY-Link Logic Performs System D D D D D Initialization and Arbitration Functions PHY-Link Encode and Decode Functions Included for Data-Strobe Bit Level Encoding PHY-Link Incoming Data Resynchronized to Local Clock Low-Cost 24.576-MHz Crystal Provides Transmit and Receive Data at 100M Bits/s, 200M Bits/s, and 400M Bits/s Node Power Class Information Signaling for System Power Management Register Bits Give Software Control of Contender Bit, Power Class Bits, Link Active Control Bit, and IEEE Std 1394a-2000 Features D Isochronous Receive Dual-Buffer Mode D Out-Of-Order Pipelining for Asynchronous Transmit Requests D Register Access Fail Interrupt When the D D D D PHY SCLK Is Not Active PCI Power-Management D0, D1, D2, and D3 Power States Initial Bandwidth Available and Initial Channels Available Registers PME Support Per 1394 Open Host Controller Interface Specification Advanced Submicron, Low-Power CMOS Technology Table 1-1. Figure 1-1. 2 SCPS110 September 2005 Introduction 2 Introduction The Texas Instruments PCI4512 controller is an integrated single-socket PC Card controller, IEEE 1394 open HCI host controller and two-port PHY. This high-performance integrated solution provides the latest in PC Card and IEEE 1394 technology. The Texas Instruments PCI6412 controller is an integrated single-socket PC Card controller and flash media controller. This high-performance integrated solution provides the latest in PC Card, SD, MMC, Memory Stick/PRO, SmartMedia, and xD technology. The Texas Instruments PCI6612 controller is an integrated single-socket PC Card controller, Smart Card controller, and flash media controller. This high-performance integrated solution provides the latest in PC Card, Smart Card, SD, MMC, Memory Stick/PRO, SmartMedia, and xD technology. The Texas Instruments PCI7402 controller is an integrated single-socket IEEE 1394 open HCI host controller and two-port PHY and flash media controller. This high-performance integrated solution provides the latest in IEEE 1394, SD, MMC, Memory Stick/PRO, SmartMedia, and xD technology. The Texas Instruments PCI7412 controller is an integrated single-socket PC Card controller, IEEE 1394 open HCI host controller and two-port PHY, and flash media controller. This high-performance integrated solution provides the latest in PC Card, IEEE 1394, SD, MMC, Memory Stick/PRO, SmartMedia, and xD technology. The Texas Instruments PCI7612 controller is an integrated single-socket PC Card controller, Smart Card controller, IEEE 1394 open HCI host controller and two-port PHY, and flash media controller. This high-performance integrated solution provides the latest in PC Card, Smart Card, IEEE 1394, SD, MMC, Memory Stick/PRO, SmartMedia, and xD technology. The Texas Instruments PCI8402 controller is an integrated single-socket IEEE 1394 open HCI host controller and one-port PHY and flash media controller. This high-performance integrated solution provides the latest in IEEE 1394, SD, MMC, Memory Stick/PRO, SmartMedia, and xD technology. The Texas Instruments PCI8412 controller is an integrated single-socket PC Card controller, IEEE 1394 open HCI host controller and one-port PHY, and flash media controller. This high-performance integrated solution provides the latest in PC Card, IEEE 1394, SD, MMC, Memory Stick/PRO, SmartMedia, and xD technology. For the remainder of this document, the PCIxx12 controller refers to the PCI4512, PCI6412, PCI6612, PCI7402, PCI7412, PCI7612, PCI8402, and PCI8412 controllers. Table 2-1 shows a summary of the PCIxx12 functions listed by controller. Table 2-1. Functional Summary Controller Function 0 (CardBus) Function 1 (1394 OHCI) Function 2 (Flash Media) Function 3 (SD Host) PCI4512 X X PCI6412 PCI6612 X X X X X X X X X PCI7402 PCI7412 X X X X PCI7612 X X X X X X X X X X PCI8402 PCI8412 September 2005 X Function 4 (Smart Card) X X SCPS110 3 Introduction 2.1 Controller Functional Description 2.1.1 PCI4512 Controller The PCI4512 controller is a two-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3. Function 0 provides an independent PC Card socket controller compliant with the PC Card Standard (Release 8.1). The PCI4512 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports Smart Card, 16-bit, CardBus, or USB custom card interface PC Cards, powered at 5 V or 3.3 V, as required. All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI4512 controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI4512 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI4512 controller can be programmed to accept posted writes to improve bus utilization. Function 1 of the PCI4512 controller is compatible with IEEE Std 1394a-2000 and the latest 1394 Open Host Controller Interface Specification. The chip provides the IEEE1394 link and 2-port PHY function and is compatible with data rates of 100, 200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The PCI4512 controller provides physical write posting and a highly tuned physical data path for SBP-2 performance. 2.1.2 PCI6412 Controller The PCI6412 controller is a three-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3. Function 0 provides an independent PC Card socket controller compliant with the PC Card Standard (Release 8.1). The PCI6412 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports Smart Card, 16-bit, CardBus, or USB custom card interface PC Cards, powered at 5 V or 3.3 V, as required. All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI6412 controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI6412 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI6412 controller can be programmed to accept posted writes to improve bus utilization. Function 2 of the PCI6412 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory Stick-Pro, SmartMedia, xD, SD, and MMC cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function includes DMA capabilities for improved Flash Media performance. Function 3 of the PCI6412 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard Specification and includes DMA capabilities, support for high-speed mode, and support for SD suspend/resume. 4 SCPS110 September 2005 Introduction 2.1.3 PCI6612 Controller The PCI6612 controller is a four-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3. Function 0 provides an independent PC Card socket controller compliant with the PC Card Standard (Release 8.1). The PCI6612 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports Smart Card, 16-bit, CardBus, or USB custom card interface PC Cards, powered at 5 V or 3.3 V, as required. All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI6612 controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI6612 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI6612 controller can be programmed to accept posted writes to improve bus utilization. Function 2 of the PCI6612 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory Stick-Pro, SmartMedia, xD, SD, and MMC cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function includes DMA capabilities for improved Flash Media performance. Function 3 of the PCI6612 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard Specification and includes DMA capabilities, support for high-speed mode, and support for SD suspend/resume. Function 4 of the PCI6612 controller is a PCI-based Smart Card controller used for communication with Smart Cards inserted in PC Card adapters. Utilizing Smart Card technology from Gemplus, this function provides compatibility with many different types of Smart Cards. 2.1.4 PCI7402 Controller The PCI7402 controller is a four-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3. Function 0 is a dummy PC Card controller function. The PC Card socket is non-functional and the pins associated with the PC card socket may be left unconnected. The function is required for device enumeration and is provided for BIOS compatibility with existing devices. The PC Card function may be hidden from the OS by the BIOS. Function 1 of the PCI7402 controller is compatible with IEEE Std 1394a-2000 and the latest 1394 Open Host Controller Interface Specification. The chip provides the IEEE1394 link and 2-port PHY function and is compatible with data rates of 100, 200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The PCI7402 controller provides physical write posting and a highly tuned physical data path for SBP-2 performance. Function 2 of the PCI7402 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory Stick-Pro, SmartMedia, xD, SD, and MMC cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function includes DMA capabilities for improved Flash Media performance. Function 3 of the PCI7402 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard Specification and includes DMA capabilities, support for high-speed mode, and support for SD suspend/resume. September 2005 SCPS110 5 Introduction 2.1.5 PCI7412 Controller The PCI7412 controller is a four-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3. Function 0 provides an independent PC Card socket controller compliant with the PC Card Standard (Release 8.1). The PCI7412 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports 16-bit, CardBus, or USB custom card interface PC Cards, powered at 5 V or 3.3 V, as required. All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI7412 controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI7412 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI7412 controller can be programmed to accept posted writes to improve bus utilization. Function 1 of the PCI7412 controller is compatible with IEEE Std 1394a-2000 and the latest 1394 Open Host Controller Interface Specification. The chip provides the IEEE1394 link and 2-port PHY function and is compatible with data rates of 100, 200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The PCI7412 controller provides physical write posting and a highly tuned physical data path for SBP-2 performance. Function 2 of the PCI7412 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory Stick-Pro, SmartMedia, xD, SD, and MMC cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function includes DMA capabilities for improved Flash Media performance. Function 3 of the PCI7412 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard Specification and includes DMA capabilities, support for high-speed mode, and support for SD suspend/resume. 2.1.6 PCI7612 Controller The PCI7612 controller is a five-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3. Function 0 provides an independent PC Card socket controller compliant with the PC Card Standard (Release 8.1). The PCI7612 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports Smart Card, 16-bit, CardBus, or USB custom card interface PC Cards, powered at 5 V or 3.3 V, as required. All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI7612 controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI7612 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI7612 controller can be programmed to accept posted writes to improve bus utilization. Function 1 of the PCI7612 controller is compatible with IEEE Std 1394a-2000 and the latest 1394 Open Host Controller Interface Specification. The chip provides the IEEE1394 link and 2-port PHY function and is compatible with data rates of 100, 200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The PCI7612 controller provides physical write posting and a highly tuned physical data path for SBP-2 performance. Function 2 of the PCI7612 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory Stick-Pro, SmartMedia, xD, SD, and MMC cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function includes DMA capabilities for improved Flash Media performance. 6 SCPS110 September 2005 Introduction Function 3 of the PCI7612 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard Specification and includes DMA capabilities, support for high-speed mode, and support for SD suspend/resume. Function 4 of the PCI7612 controller is a PCI-based Smart Card controller used for communication with Smart Cards inserted in PC Card adapters. Utilizing Smart Card technology from Gemplus, this function provides compatibility with many different types of Smart Cards. 2.1.7 PCI8402 Controller The PCI8402 controller is a four-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3. Function 0 is a dummy PC Card controller function. The PC Card socket is non-functional and the pins associated with the PC card socket may be left unconnected. The function is required for device enumeration and is provided for BIOS compatibility with existing devices. The PC Card function may be hidden from the OS by the BIOS. Function 1 of the PCI8402 controller is compatible with IEEE Std 1394a-2000 and the latest 1394 Open Host Controller Interface Specification. The chip provides the IEEE1394 link and 1-port PHY function and is compatible with data rates of 100, 200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The PCI8402 controller provides physical write posting and a highly tuned physical data path for SBP-2 performance. Function 2 of the PCI8402 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory Stick-Pro, SmartMedia, xD, SD, and MMC cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function includes DMA capabilities for improved Flash Media performance. Function 3 of the PCI8402 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard Specification and includes DMA capabilities, support for high-speed mode, and support for SD suspend/resume. 2.1.8 PCI8412 Controller The PCI8412 controller is a four-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3. Function 0 provides an independent PC Card socket controller compliant with the PC Card Standard (Release 8.1). The PCI8412 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports Smart Card, 16-bit, CardBus, or USB custom card interface PC Cards, powered at 5 V or 3.3 V, as required. All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI8412 controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI8412 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI8412 controller can be programmed to accept posted writes to improve bus utilization. Function 1 of the PCI8412 controller is compatible with IEEE Std 1394a-2000 and the latest 1394 Open Host Controller Interface Specification. The chip provides the IEEE1394 link and 1-port PHY function and is compatible with data rates of 100, 200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The PCI8412 controller provides physical write posting and a highly tuned physical data path for SBP-2 performance. September 2005 SCPS110 7 Introduction Function 2 of the PCI8412 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory Stick-Pro, SmartMedia, xD, SD, and MMC cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function includes DMA capabilities for improved Flash Media performance. Function 3 of the PCI8412 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard Specification and includes DMA capabilities, support for high-speed mode, and support for SD suspend/resume. 2.1.9 Multifunctional Terminals Various implementation-specific functions and general-purpose inputs and outputs are provided through eight multifunction terminals. These terminals present a system with options in serial and parallel interrupts, PC Card activity indicator LEDs, flash media LEDs, and other platform-specific signals. PCI-compliant general-purpose events may be programmed and controlled through the multifunction terminals, and an ACPI-compliant programming interface is included for the general-purpose inputs and outputs. 2.1.10 PCI Bus Power Management The PCIxx12 controller is compliant with the latest PCI Bus Power Management Specification, and provides several low-power modes, which enable the host power system to further reduce power consumption. 2.1.11 Power Switch Interface The PCIxx12 controller supports both the three-pin serial interface compatible with the Texas Instruments TPS2228 (default), TPS2226, TPS2224, and TPS2223A power switches and the four-pin parallel interface compatible with the Texas Instruments TPS2211A and TPS2212 power switches. The interface mode is selected by strapping the RSVD/VD0/VCCD1 terminal either high (three-pin serial mode) or low (four-pin parallel mode). Note that when using the four-pin parallel mode the Smart Card and Flash Media sockets must be powered via discrete power switches. All of the power switches provide power to the CardBus socket on the PCIxx12 controller. The power to each dedicated flash media socket is controlled through separate power control pins or it may be configured to source power through BVCC of a dual-socket PCMCIA power switch. The power to the dedicated Smart Card socket is controlled through a separate power control pin that can control an external 5-V power switch or it may be configured to source power through BVPP of a dual-socket PCMCIA power switch. Each of the dedicated power control pins can be connected to an external power switch. 2.2 8 Related Documents * Advanced Configuration and Power Interface (ACPI) Specification (Revision 2.0) * 1394 Open Host Controller Interface Specification (Release 1.1) * IEEE Standard for a High Performance Serial Bus (IEEE Std 1394-1995) * IEEE Standard for a High Performance Serial Bus--Amendment 1 (IEEE Std 1394a-2000) * PC Card Standard (Release 8.1) * PCI Bus Power Management Interface Specification (Revision 1.1) * Serial Bus Protocol 2 (SBP-2) * Serialized IRQ Support for PCI Systems * PCI Mobile Design Guide * PCI Bus Power Management Interface Specification for PCI to CardBus Bridges SCPS110 September 2005 Introduction 2.3 * PCI to PCMCIA CardBus Bridge Register Description * Texas Instruments TPS2224 and TPS2226 product data sheet, SLVS317 * Texas Instruments TPS2223A product data sheet, SLVS428 * Texas Instruments TPS2228 product data sheet, SLVS419 * PCI Local Bus Specification (Revision 2.3) * PCMCIA Proposal (262) * The Multimedia Card System Specification, Version 3.31 * SD Memory Card Specifications, SD Group, March 2000 * Memory Stick Format Specification, Version 2.0 (Memory Stick-Pro) * ISO Standards for Identification Cards ISO/IEC 7816 * SD Host Controller Standard Specification, rev. 1.0 * Memory Stick Format Specification, Sony Confidential, ver. 2.0 * SmartMedia Standard 2000, May 19, 2000 Trademarks Intel is a trademark of Intel Corporation. TI and MicroStar BGA are trademarks of Texas Instruments. FireWire is a trademark of Apple Computer, Inc. i.LINK is a trademark of Sony Corporation of America. Memory Stick is a trademark of Sony Kabushiki Kaisha TA Sony Corporation, Japan. Other trademarks are the property of their respective owners. 2.4 Document Conventions Throughout this data manual, several conventions convey information. These conventions are listed below: 1. To identify a binary number or field, a lower case b follows the numbers. For example: 000b is a 3-bit binary field. 2. To identify a hexadecimal number or field, a lower case h follows the numbers. For example: 8AFh is a 12-bit hexadecimal field. 3. All other numbers that appear in this document that do not have either a b or h following the number are assumed to be decimal format. 4. If the signal or terminal name has a bar above the name (for example, GRST), then this indicates the logical NOT function. When asserted, this signal is a logic low, 0, or 0b. 5. RSVD indicates that the referenced item is reserved. 6. In Sections 4 through 13, the configuration space for the controller is defined. For each register bit, the software access method is identified in an access column. The legend for this access column includes the following entries: r - read-only access ru - read-only access with updates by the controller internal hardware September 2005 SCPS110 9 Introduction rw - read and write access rcu - read access with the option to clear an asserted bit with a write-back of 1b including updates by the controller internal hardware. 2.5 Terms and Definitions Terms and definitions used in this document are given in Table 2-2. Table 2-2. Terms and Definitions TERM DEFINITIONS AT AT (advanced technology, as in PC AT) attachment interface CIS Card information structure. Tuple list defined by the PC Card standard to communicate card information to the host computer. CSR Control and status register Flash Media SmartMedia, Memory Stick, MS/PRO, xD, MMC, or SD/MMC Flash operating in an ATA compatible mode ISO/IEC 7816 The Smart Card standard Memory Stick A small-form-factor flash interface that is defined, promoted, and licensed by Sony Memory Stick Pro Memory Stick Version 2.0, same physical dimensions of MS with higher speed data exchange and higher data capacity than conventional Memory Stick. MMC MultiMediaCard. Specified by the MMC Association, and scope is encompassed by the SD Flash specification. OHCI Open host controller interface PCMCIA Personal Computer Memory Card International Association. Standards body that governs the PC Card standards. RSVD Reserved for future use SD Flash Secure Digital Flash. Standard governed by the SD Association. Smart Card The name applied to ID cards containing integrated circuits, as defined by ISO/IEC 7816-1 SPI Serial peripheral interface, a general-purpose synchronous serial interface. For more information, see the Multimedia Card System Specification, version 3.2. SSFDC Solid State Floppy Disk Card. The SSFDC Forum specifies SmartMedia. TI Smart Card driver A qualified software component provided by Texas Instruments that loads when an UltraMedia-based Smart Card adapter is inserted into a PC Card slot. This driver is logically attached to a CIS provided by the PCI7621 when the adapter and media are both inserted. UltraMedia De facto industry standard promoted by Texas Instruments that integrates CardBus, Smart Card, Memory Stick, MultiMediaCard/Secure Digital and SmartMedia functionality into one controller. xD Extreme Digital, small form factor flash based on SmartMedia cards, developed by Fuji Film and Olympus Optical. 10 SCPS110 September 2005 Introduction 2.6 Ordering Information ORDERING NUMBER PCI4512GHK PCI4512ZHK PCI6412GHK PCI6412ZHK PCI6612GHK PCI6612ZHK PCI7402GHK PCI7402ZHK PCI7412GHK PCI7412ZHK PCI7612GHK PCI7612ZHK PCI8402GHK PCI8402ZHK PCI8412GHK PCI8412ZHK 2.7 2.8 NAME PACKAGE COMMENT Single Socket CardBus Controller with Integrated 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller 216-ball PBGA Standard lead (Pb) device 216-ball PBGA Lead-free (Pb-free) device Single Socket CardBus Controller with Dedicated Flash Media Socket 216-ball PBGA Standard lead (Pb) device 216-ball PBGA Lead-free (Pb-free) device Single Socket CardBus Controller with Dedicated Flash Media and Smart Card Sockets 216-ball PBGA Standard lead (Pb) device 216-ball PBGA Lead-free (Pb-free) device Single Socket CardBus Controller with Integrated 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller with Dedicated Flash Media Socket 216-ball PBGA Standard lead (Pb) device 216-ball PBGA Lead-free (Pb-free) device Single Socket CardBus Controller with Integrated 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller with Dedicated Flash Media Socket 216-ball PBGA Standard lead (Pb) device 216-ball PBGA Lead-free (Pb-free) device Single Socket CardBus Controller with Integrated 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller with Dedicated Flash Media and Smart Card Sockets 216-ball PBGA Standard lead (Pb) device 216-ball PBGA Lead-free (Pb-free) device Single Socket CardBus Controller with Integrated 1394a-2000 OHCI One-Port PHY/Link-Layer Controller with Dedicated Flash Media Socket 216-ball PBGA Standard lead (Pb) device 216-ball PBGA Lead-free (Pb-free) device Single Socket CardBus Controller with Integrated 1394a-2000 OHCI One-Port PHY/Link-Layer Controller with Dedicated Flash Media Socket 216-ball PBGA Standard lead (Pb) device 216-ball PBGA Lead-free (Pb-free) device PCIxx12 Data Manual Document History DATE PAGE NUMBER 05/2005 All REVISION Draft copy Terminal Assignments The PCIxx12 controller is available in the 216-terminal MicroStar BGA package (GHK) or the 216-terminal lead-free (Pb, atomic number 82) MicroStar BGA package (ZHK). Figure 2-1 is a terminal diagram of the PCI4512 package. Figure 2-2 is a terminal diagram of the PCI6412 package. Figure 2-3 is a terminal diagram of the PCI6612 package. Figure 2-4 is a terminal diagram of the PCI7402 package. Figure 2-5 is a terminal diagram of the PCI7412 package. Figure 2-6 is a terminal diagram of the PCI7612 package. Figure 2-7 is a terminal diagram of the PCI8402 package. Figure 2-8 is a terminal diagram of the PCI8412 package. September 2005 SCPS110 11 Introduction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 AD16 TRDY SERR AD15 VCCP AD11 C/BE0 AD4 NC TPB0N TPA0N TPB1N TPA1N TPBIAS 1 V IRDY STOP C/BE1 AD12 AD10 AD7 AD3 NC TPB0P TPA0P TPB1P TPA1P U C/BE2 DEVSEL PAR AD13 AD9 AD6 AD2 NC AGND AGND AVDD_ _33 W T AD18 AD17 R AD22 AD21 AD19 P VCCP C/BE3 AD23 N AD26 AD25 M AD31 L FRAME PERR AD14 AD8 AD5 AD0 CPS TPBIAS 0 AGND AD20 VCC GND VCC GND VCC AD1 TEST0 AVDD_ _33 AVDD_ _33 AD24 IDSEL GND AD30 AD29 AD27 AD28 PCLK GNT REQ RI_OUT / PME K VR_ PORT VR_EN PRST J MFUNC 4 MFUNC 5 H MFUNC 3 G 18 19 VDD PLL_33 VSSPLL R0 R1 XO XI VDD PLL_15 PHY_ TEST_ MA CCD1 // CD1 CAD2 // D11 CAD1 // D4 CAD4 // D12 GND CAD3 // D5 CAD6 // D13 CAD5 // D6 RSVD // D14 VCC VCC CAD9 // A10 CC/ BE0 // CE1 CAD8 // D15 CAD7 // D7 GRST GND GND CAD12 // A11 CAD11 // OE CAD10 // CE2 VR_ PORT MFUNC 6 SUSPEND VCC VCC CAD14 // A9 CAD15 // IOWR CAD13 // IORD VCCCB MFUNC 2 SPKR OUT MFUNC 1 GND CPAR // A13 CBLOC K // A19 RSVD // A18 CC/ BE1 // A8 CAD16 // A17 MFUNC 0 SCL SDA RSVD VCC GND CTRDY // A22 CGNT // WE CSTOP // A20 CPERR // A14 F GND RSVD RSVD RSVD VCC GND RSVD VCC GND CAD29 // D1 VCC GND VCC CAD17 // A24 CIRDY // A15 CCLK // A16 CDEVSEL // A21 E RSVD RSVD RSVD NC RSVD RSVD RSVD RSVD USB_ EN CAD28 // D8 CINT // READY (IREQ) CC/ BE3 // REG CAD21 // A5 CAD18 // A7 CC/ BE2 // A12 CFRAM E // A23 D RSVD CAD19 // A25 C RSVD / VD0 / VCCD1 RSVD RSVD RSVD RSVD LATCH / VD3 / VPPD0 CAD31 // D10 CAD27 // D0 CSERR // WAIT CAD25 // A1 CREQ // INPACK CRST // RESET B RSVD RSVD RSVD RSVD RSVD DATA / VD2 / VPPD1 RSVD // D2 CCD2 // CD2 CAUDIO // BVD2 (SPKR) CAD26 // A0 CAD23 // A3 CAD22 // A4 CVS2 // VS2 RSVD RSVD RSVD RSVD RSVD RSVD CLOCK / VD1 / VCCD0 CAD30 // D9 CCLK RUN // WP (IOIS16) CSTS CHG // BVD1 (STSC HG/RI) CVS1 // VS1 CAD24 // A2 VCCCB CAD20 // A6 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A 1 CAD0 // D3 2 17 18 19 Figure 2-1. PCI4512 GHK/ZHK-Package Terminal Diagram 12 SCPS110 September 2005 Introduction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 AD16 TRDY SERR AD15 VCCP AD11 C/BE0 AD4 NC RSVD RSVD RSVD RSVD RSVD V IRDY STOP C/BE1 AD12 AD10 AD7 AD3 NC RSVD RSVD RSVD RSVD U C/BE2 DEVSEL PAR AD13 AD9 AD6 AD2 NC GND GND VCC W T AD18 AD17 R AD22 AD21 AD19 P VCCP C/BE3 AD23 N AD26 AD25 M AD31 L FRAME PERR AD14 AD8 AD5 AD0 GND RSVD GND AD20 VCC GND VCC GND VCC AD1 TEST0 VCC VCC AD24 IDSEL GND AD30 AD29 AD27 AD28 PCLK GNT REQ RI_OUT / PME K VR_ PORT VR_EN PRST J MFUNC 4 MFUNC 5 H MFUNC 3 G F 18 19 VCC GND GND GND RSVD RSVD RSVD PHY_ TEST_ MA CCD1 // CD1 CAD2 // D11 CAD1 // D4 CAD4 // D12 GND CAD3 // D5 CAD6 // D13 CAD5 // D6 RSVD // D14 VCC VCC CAD9 // A10 CC/ BE0 // CE1 CAD8 // D15 CAD7 // D7 GRST GND GND CAD12 // A11 CAD11 // OE CAD10 // CE2 VR_ PORT MFUNC 6 SUSPEND VCC VCC CAD14 // A9 CAD15 // IOWR CAD13 // IORD VCCCB MFUNC 2 SPKR OUT MFUNC 1 GND CPAR // A13 CBLOC K // A19 RSVD // A18 CC/ BE1 // A8 CAD16 // A17 MFUNC 0 SCL SDA RSVD VCC GND CTRDY // A22 CGNT // WE CSTOP // A20 CPERR // A14 CLK_48 RSVD RSVD RSVD VCC GND CAD17 // A24 CIRDY // A15 CCLK // A16 CDEVSEL // A21 NC SD_ DAT3 / SM_D7 SD_WP / SM_CE CAD18 // A7 CC/ BE2 // A12 CFRAM E // A23 MC_ PWR_ CTRL_ 1/ VCC GND CAD29 // D1 VCC GND VCC SD_CD USB_ EN CAD28 // D8 CINT // READY (IREQ) CC/ BE3 // REG CAD21 // A5 CAD0 // D3 SM_R/B E RSVD D RSVD RSVD RSVD MS_BS / SD_ CMD / SM_WE CAD19 // A25 C RSVD / VD0 / VCCD1 SD_ CMD / SM_ ALE SD_ DAT0 / SM_D4 MS_ DATA1 / SD_ DAT1 / SM_D1 MC_ PWR_ CTRL_ 0 LATCH / VD3 / VPPD0 CAD31 // D10 CAD27 // D0 CSERR // WAIT CAD25 // A1 CREQ // INPACK CRST // RESET B SM_ CLE SD_ DAT2 / SM_D6 MS_ DATA3 / SD_ DAT3 / SM_D3 MS_ SDIO (DATA0) / SD_ DAT0 / SM_D0 SM_CD DATA / VD2 / VPPD1 RSVD // D2 CCD2 // CD2 CAUDIO // BVD2 (SPKR) CAD26 // A0 CAD23 // A3 CAD22 // A4 CVS2 // VS2 XD_CD / SM_ PHYS_ WP SD_ CLK / SM_RE SD_ DAT1 / SM_D5 MS_ DATA2 / SD_ DAT2 / SM_D2 MS_ CLK / SD_ CLK / SM_EL_ WP MS_CD CLOCK / VD1 / VCCD0 CAD30 // D9 CCLK RUN // WP (IOIS16) CSTS CHG // BVD1 (STSC HG/RI) CVS1 // VS1 CAD24 // A2 VCCCB CAD20 // A6 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A 1 2 17 18 19 Figure 2-2. PCI6412 GHK/ZHK-Package Terminal Diagram September 2005 SCPS110 13 Introduction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 AD16 TRDY SERR AD15 VCCP AD11 C/BE0 AD4 NC RSVD RSVD RSVD RSVD RSVD V IRDY STOP C/BE1 AD12 AD10 AD7 AD3 NC RSVD RSVD RSVD RSVD U C/BE2 DEVSEL PAR AD13 AD9 AD6 AD2 NC GND GND VCC W T AD18 AD17 R AD22 AD21 AD19 P VCCP C/BE3 AD23 N AD26 AD25 M AD31 L FRAME PERR AD14 AD8 AD5 AD0 GND RSVD AGND AD20 VCC GND VCC GND VCC AD1 TEST0 VCC VCC AD24 IDSEL GND AD30 AD29 AD27 AD28 PCLK GNT REQ RI_OUT / PME K VR_ PORT VR_EN PRST J MFUNC 4 MFUNC 5 H MFUNC 3 G F 18 19 VCC GND GND GND RSVD RSVD RSVD PHY_ TEST_ MA CCD1 // CD1 CAD2 // D11 CAD1 // D4 CAD4 // D12 GND CAD3 // D5 CAD6 // D13 CAD5 // D6 RSVD // D14 VCC VCC CAD9 // A10 CC/ BE0 // CE1 CAD8 // D15 CAD7 // D7 GRST GND GND CAD12 // A11 CAD11 // OE CAD10 // CE2 VR_ PORT MFUNC 6 SUSPEND VCC VCC CAD14 // A9 CAD15 // IOWR CAD13 // IORD VCCCB MFUNC 2 SPKR OUT MFUNC 1 GND CPAR // A13 CBLOC K // A19 RSVD // A18 CC/ BE1 // A8 CAD16 // A17 MFUNC 0 SCL SDA SC_ PWR_ CTRL SC_ VCC_ 5V GND CTRDY // A22 CGNT // WE CSTOP // A20 CPERR // A14 CLK_48 SC_OC SC_CD SC_ RST VCC GND CAD17 // A24 CIRDY // A15 CCLK // A16 CDEVSEL // A21 NC SD_ DAT3 / SM_D7 / SC_ GPIO3 SD_WP / SM_CE CAD18 // A7 CC/ BE2 // A12 CFRAM E // A23 MC_ PWR_ CTRL_ 1/ VCC GND CAD29 // D1 VCC GND VCC SD_CD USB_ EN CAD28 // D8 CINT // READY (IREQ) CC/ BE3 // REG CAD21 // A5 CAD0 // D3 SM_R/B E SC_ DATA D SC_ RFU SC_ CLK SC_ FCB MS_BS / SD_ CMD / SM_WE CAD19 // A25 C RSVD / VD0 / VCCD1 SD_ CMD / SM_ ALE / SC_ GPIO2 SD_ DAT0 / SM_D4 / SC_ GPIO6 MS_ DATA1 / SD_ DAT1 / SM_D1 MC_ PWR_ CTRL_ 0 LATCH / VD3 / VPPD0 CAD31 // D10 CAD27 // D0 CSERR // WAIT CAD25 // A1 CREQ // INPACK CRST // RESET B SM_ CLE / SC_ GPIO0 SD_ DAT2 / SM_D6 / SC_ GPIO4 MS_ DATA3 / SD_ DAT3 / SM_D3 MS_ SDIO (DATA0) / SD_ DAT0 / SM_D0 SM_CD DATA / VD2 / VPPD1 RSVD // D2 CCD2 // CD2 CAUDIO // BVD2 (SPKR) CAD26 // A0 CAD23 // A3 CAD22 // A4 CVS2 // VS2 XD_CD / SM_ PHYS_ WP SD_ CLK / SM_RE / SC_ GPIO1 SD_ DAT1 / SM_D5 / SC_ GPIO5 MS_ DATA2 / SD_ DAT2 / SM_D2 MS_ CLK / SD_ CLK / SM_EL_ WP MS_CD CLOCK / VD1 / VCCD0 CAD30 // D9 CCLK RUN // WP (IOIS16) CSTS CHG // BVD1 (STSC HG/RI) CVS1 // VS1 CAD24 // A2 VCCCB CAD20 // A6 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A 1 2 17 18 19 Figure 2-3. PCI6612 GHK/ZHK-Package Terminal Diagram 14 SCPS110 September 2005 Introduction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 AD16 TRDY SERR AD15 VCCP AD11 C/BE0 AD4 NC TPB0N TPA0N TPB1N TPA1N TPBIAS 1 V IRDY STOP C/BE1 AD12 AD10 AD7 AD3 NC TPB0P TPA0P TPB1P TPA1P U C/BE2 DEVSEL PAR AD13 AD9 AD6 AD2 NC AGND AGND AVDD_ _33 W T AD18 AD17 R AD22 AD21 AD19 P VCCP C/BE3 AD23 N AD26 AD25 M AD31 L FRAME PERR AD14 AD8 AD5 AD0 CPS TPBIAS 0 AGND AD20 VCC GND VCC GND VCC AD1 TEST0 AVDD_ _33 AVDD_ _33 AD24 IDSEL GND AD30 AD29 AD27 AD28 PCLK GNT REQ RI_OUT / PME K VR_ PORT VR_EN PRST J MFUNC 4 MFUNC 5 H MFUNC 3 G F 18 19 VDD PLL_33 VSSPLL R0 R1 XO XI VDD PLL_15 PHY_ TEST_ MA RSVD RSVD RSVD RSVD GND RSVD RSVD RSVD RSVD VCC VCC RSVD RSVD RSVD RSVD GRST GND GND RSVD RSVD RSVD VR_ PORT MFUNC 6 SUSPEND VCC VCC RSVD RSVD RSVD RSVD MFUNC 2 SPKR OUT MFUNC 1 GND RSVD RSVD RSVD RSVD RSVD MFUNC 0 SCL SDA RSVD VCC GND RSVD RSVD RSVD RSVD CLK_48 RSVD RSVD RSVD VCC RSVD RSVD RSVD RSVD RSVD RSVD RSVD GND MC_ PWR_ CTRL_ 1/ VCC GND RSVD VCC GND VCC SD_CD RSVD RSVD RSVD RSVD RSVD RSVD SM_R/B E RSVD D RSVD RSVD NC RSVD SD_ DAT3 / SM_D7 SD_WP / SM_CE MS_BS / SD_ CMD / SM_WE RSVD C RSVD / VD0 / VCCD1 SD_ CMD / SM_ ALE SD_ DAT0 / SM_D4 MS_ DATA1 / SD_ DAT1 / SM_D1 MC_ PWR_ CTRL_ 0 LATCH / VD3 / VPPD0 RSVD RSVD RSVD RSVD RSVD RSVD B SM_ CLE SD_ DAT2 / SM_D6 MS_ DATA3 / SD_ DAT3 / SM_D3 MS_ SDIO (DATA0) / SD_ DAT0 / SM_D0 SM_CD DATA / VD2 / VPPD1 RSVD RSVD RSVD RSVD RSVD RSVD RSVD XD_CD / SM_ PHYS_ WP SD_ CLK / SM_RE SD_ DAT1 / SM_D5 MS_ DATA2 / SD_ DAT2 / SM_D2 MS_ CLK / SD_ CLK / SM_EL_ WP MS_CD CLOCK / VD1 / VCCD0 RSVD RSVD RSVD RSVD RSVD RSVD RSVD 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A 1 2 17 18 19 Figure 2-4. PCI7402 GHK/ZHK-Package Terminal Diagram September 2005 SCPS110 15 Introduction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 AD16 TRDY SERR AD15 VCCP AD11 C/BE0 AD4 NC TPB0N TPA0N TPB1N TPA1N TPBIAS 1 V IRDY STOP C/BE1 AD12 AD10 AD7 AD3 NC TPB0P TPA0P TPB1P TPA1P U C/BE2 DEVSEL PAR AD13 AD9 AD6 AD2 NC AGND AGND AVDD_ _33 W T AD18 AD17 R AD22 AD21 AD19 P VCCP C/BE3 AD23 N AD26 AD25 M AD31 L FRAME PERR AD14 AD8 AD5 AD0 CPS TPBIAS 0 AGND AD20 VCC GND VCC GND VCC AD1 TEST0 AVDD_ _33 AVDD_ _33 AD24 IDSEL GND AD30 AD29 AD27 AD28 PCLK GNT REQ RI_OUT / PME K VR_ PORT VR_EN PRST J MFUNC 4 MFUNC 5 H MFUNC 3 G F 18 19 VDD PLL_33 VSSPLL R0 R1 XO XI VDD PLL_15 PHY_ TEST_ MA CCD1 // CD1 CAD2 // D11 CAD1 // D4 CAD4 // D12 GND CAD3 // D5 CAD6 // D13 CAD5 // D6 RSVD // D14 VCC VCC CAD9 // A10 CC/ BE0 // CE1 CAD8 // D15 CAD7 // D7 GRST GND GND CAD12 // A11 CAD11 // OE CAD10 // CE2 VR_ PORT MFUNC 6 SUSPEND VCC VCC CAD14 // A9 CAD15 // IOWR CAD13 // IORD VCCCB MFUNC 2 SPKR OUT MFUNC 1 GND CPAR // A13 CBLOC K // A19 RSVD // A18 CC/ BE1 // A8 CAD16 // A17 MFUNC 0 SCL SDA RSVD VCC GND CTRDY // A22 CGNT // WE CSTOP // A20 CPERR // A14 CLK_48 RSVD RSVD RSVD VCC GND CAD17 // A24 CIRDY // A15 CCLK // A16 CDEVSEL // A21 NC SD_ DAT3 / SM_D7 SD_WP / SM_CE CAD18 // A7 CC/ BE2 // A12 CFRAM E // A23 MC_ PWR_ CTRL_ 1/ VCC GND CAD29 // D1 VCC GND VCC SD_CD USB_ EN CAD28 // D8 CINT // READY (IREQ) CC/ BE3 // REG CAD21 // A5 CAD0 // D3 SM_R/B E RSVD D RSVD RSVD RSVD MS_BS / SD_ CMD / SM_WE CAD19 // A25 C RSVD / VD0 / VCCD1 SD_ CMD / SM_ ALE SD_ DAT0 / SM_D4 MS_ DATA1 / SD_ DAT1 / SM_D1 MC_ PWR_ CTRL_ 0 LATCH / VD3 / VPPD0 CAD31 // D10 CAD27 // D0 CSERR // WAIT CAD25 // A1 CREQ // INPACK CRST // RESET B SM_ CLE SD_ DAT2 / SM_D6 MS_ DATA3 / SD_ DAT3 / SM_D3 MS_ SDIO (DATA0) / SD_ DAT0 / SM_D0 SM_CD DATA / VD2 / VPPD1 RSVD // D2 CCD2 // CD2 CAUDIO // BVD2 (SPKR) CAD26 // A0 CAD23 // A3 CAD22 // A4 CVS2 // VS2 XD_CD / SM_ PHYS_ WP SD_ CLK / SM_RE SD_ DAT1 / SM_D5 MS_ DATA2 / SD_ DAT2 / SM_D2 MS_ CLK / SD_ CLK / SM_EL_ WP MS_CD CLOCK / VD1 / VCCD0 CAD30 // D9 CCLK RUN // WP (IOIS16) CSTS CHG // BVD1 (STSC HG/RI) CVS1 // VS1 CAD24 // A2 VCCCB CAD20 // A6 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A 1 2 17 18 19 Figure 2-5. PCI7412 GHK/ZHK-Package Terminal Diagram 16 SCPS110 September 2005 Introduction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 AD16 TRDY SERR AD15 VCCP AD11 C/BE0 AD4 NC TPB0N TPA0N TPB1N TPA1N TPBIAS 1 V IRDY STOP C/BE1 AD12 AD10 AD7 AD3 NC TPB0P TPA0P TPB1P TPA1P U C/BE2 DEVSEL PAR AD13 AD9 AD6 AD2 NC AGND AGND AVDD_ _33 W T AD18 AD17 R AD22 AD21 AD19 P VCCP C/BE3 AD23 N AD26 AD25 M AD31 L FRAME PERR AD14 AD8 AD5 AD0 CPS TPBIAS 0 AGND AD20 VCC GND VCC GND VCC AD1 TEST0 AVDD_ _33 AVDD_ _33 AD24 IDSEL GND AD30 AD29 AD27 AD28 PCLK GNT REQ RI_OUT / PME K VR_ PORT VR_EN PRST J MFUNC 4 MFUNC 5 H MFUNC 3 G F 18 19 VDD PLL_33 VSSPLL R0 R1 XO XI VDD PLL_15 PHY_ TEST_ MA CCD1 // CD1 CAD2 // D11 CAD1 // D4 CAD4 // D12 GND CAD3 // D5 CAD6 // D13 CAD5 // D6 RSVD // D14 VCC VCC CAD9 // A10 CC/ BE0 // CE1 CAD8 // D15 CAD7 // D7 GRST GND GND CAD12 // A11 CAD11 // OE CAD10 // CE2 VR_ PORT MFUNC 6 SUSPEND VCC VCC CAD14 // A9 CAD15 // IOWR CAD13 // IORD VCCCB MFUNC 2 SPKR OUT MFUNC 1 GND CPAR // A13 CBLOC K // A19 RSVD // A18 CC/ BE1 // A8 CAD16 // A17 MFUNC 0 SCL SDA SC_ PWR_ CTRL SC_ VCC_ 5V GND CTRDY // A22 CGNT // WE CSTOP // A20 CPERR // A14 CLK_48 SC_OC SC_CD SC_ RST VCC GND CAD17 // A24 CIRDY // A15 CCLK // A16 CDEVSEL // A21 NC SD_ DAT3 / SM_D7 / SC_ GPIO3 SD_WP / SM_CE CAD18 // A7 CC/ BE2 // A12 CFRAM E // A23 MC_ PWR_ CTRL_ 1/ VCC GND CAD29 // D1 VCC GND VCC SD_CD USB_ EN CAD28 // D8 CINT // READY (IREQ) CC/ BE3 // REG CAD21 // A5 CAD0 // D3 SM_R/B E SC_ DATA D SC_ RFU SC_ CLK SC_ FCB MS_BS / SD_ CMD / SM_WE CAD19 // A25 C RSVD / VD0 / VCCD1 SD_ CMD / SM_ ALE / SC_ GPIO2 SD_ DAT0 / SM_D4 / SC_ GPIO6 MS_ DATA1 / SD_ DAT1 / SM_D1 MC_ PWR_ CTRL_ 0 LATCH / VD3 / VPPD0 CAD31 // D10 CAD27 // D0 CSERR // WAIT CAD25 // A1 CREQ // INPACK CRST // RESET B SM_ CLE / SC_ GPIO0 SD_ DAT2 / SM_D6 / SC_ GPIO4 MS_ DATA3 / SD_ DAT3 / SM_D3 MS_ SDIO (DATA0) / SD_ DAT0 / SM_D0 SM_CD DATA / VD2 / VPPD1 RSVD // D2 CCD2 // CD2 CAUDIO // BVD2 (SPKR) CAD26 // A0 CAD23 // A3 CAD22 // A4 CVS2 // VS2 XD_CD / SM_ PHYS_ WP SD_ CLK / SM_RE / SC_ GPIO1 SD_ DAT1 / SM_D5 / SC_ GPIO5 MS_ DATA2 / SD_ DAT2 / SM_D2 MS_ CLK / SD_ CLK / SM_EL_ WP MS_CD CLOCK / VD1 / VCCD0 CAD30 // D9 CCLK RUN // WP (IOIS16) CSTS CHG // BVD1 (STSC HG/RI) CVS1 // VS1 CAD24 // A2 VCCCB CAD20 // A6 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A 1 2 17 18 19 Figure 2-6. PCI7612 GHK/ZHK-Package Terminal Diagram September 2005 SCPS110 17 Introduction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 AD16 TRDY SERR AD15 VCCP AD11 C/BE0 AD4 NC TPB0N TPA0N RSVD RSVD RSVD V IRDY STOP C/BE1 AD12 AD10 AD7 AD3 NC TPB0P TPA0P RSVD RSVD U C/BE2 DEVSEL PAR AD13 AD9 AD6 AD2 NC AGND AGND AVDD_ _33 W T AD18 AD17 R AD22 AD21 AD19 P VCCP C/BE3 AD23 N AD26 AD25 M AD31 L FRAME PERR AD14 AD8 AD5 AD0 CPS TPBIAS 0 AGND AD20 VCC GND VCC GND VCC AD1 TEST0 AVDD_ _33 AVDD_ _33 AD24 IDSEL GND AD30 AD29 AD27 AD28 PCLK GNT REQ RI_OUT / PME K VR_ PORT VR_EN PRST J MFUNC 4 MFUNC 5 H MFUNC 3 G F 18 19 VDD PLL_33 VSSPLL R0 R1 XO XI VDD PLL_15 PHY_ TEST_ MA RSVD RSVD RSVD RSVD GND RSVD RSVD RSVD RSVD VCC VCC RSVD RSVD RSVD RSVD GRST GND GND RSVD RSVD RSVD VR_ PORT MFUNC 6 SUSPEND VCC VCC RSVD RSVD RSVD RSVD MFUNC 2 SPKR OUT MFUNC 1 GND RSVD RSVD RSVD RSVD RSVD MFUNC 0 SCL SDA RSVD VCC GND RSVD RSVD RSVD RSVD CLK_48 RSVD RSVD RSVD VCC RSVD RSVD RSVD RSVD RSVD RSVD RSVD GND MC_ PWR_ CTRL_ 1/ VCC GND RSVD VCC GND VCC SD_CD RSVD RSVD RSVD RSVD RSVD RSVD SM_R/B E RSVD D RSVD RSVD NC RSVD SD_ DAT3 / SM_D7 SD_WP / SM_CE MS_BS / SD_ CMD / SM_WE RSVD C RSVD / VD0 / VCCD1 SD_ CMD / SM_ ALE SD_ DAT0 / SM_D4 MS_ DATA1 / SD_ DAT1 / SM_D1 MC_ PWR_ CTRL_ 0 LATCH / VD3 / VPPD0 RSVD RSVD RSVD RSVD RSVD RSVD B SM_ CLE SD_ DAT2 / SM_D6 MS_ DATA3 / SD_ DAT3 / SM_D3 MS_ SDIO (DATA0) / SD_ DAT0 / SM_D0 SM_CD DATA / VD2 / VPPD1 RSVD RSVD RSVD RSVD RSVD RSVD RSVD XD_CD / SM_ PHYS_ WP SD_ CLK / SM_RE SD_ DAT1 / SM_D5 MS_ DATA2 / SD_ DAT2 / SM_D2 MS_ CLK / SD_ CLK / SM_EL_ WP MS_CD CLOCK / VD1 / VCCD0 RSVD RSVD RSVD RSVD RSVD RSVD RSVD 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A 1 2 17 18 19 Figure 2-7. PCI8402 GHK/ZHK-Package Terminal Diagram 18 SCPS110 September 2005 Introduction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 AD16 TRDY SERR AD15 VCCP AD11 C/BE0 AD4 NC TPB0N TPA0N RSVD RSVD RSVD V IRDY STOP C/BE1 AD12 AD10 AD7 AD3 NC TPB0P TPA0P RSVD RSVD U C/BE2 DEVSEL PAR AD13 AD9 AD6 AD2 NC AGND AGND AVDD_ _33 W T AD18 AD17 R AD22 AD21 AD19 P VCCP C/BE3 AD23 N AD26 AD25 M AD31 L FRAME PERR AD14 AD8 AD5 AD0 CPS TPBIAS 0 AGND AD20 VCC GND VCC GND VCC AD1 TEST0 AVDD_ _33 AVDD_ _33 AD24 IDSEL GND AD30 AD29 AD27 AD28 PCLK GNT REQ RI_OUT / PME K VR_ PORT VR_EN PRST J MFUNC 4 MFUNC 5 H MFUNC 3 G F 18 19 VDD PLL_33 VSSPLL R0 R1 XO XI VDD PLL_15 PHY_ TEST_ MA CCD1 // CD1 CAD2 // D11 CAD1 // D4 CAD4 // D12 GND CAD3 // D5 CAD6 // D13 CAD5 // D6 RSVD // D14 VCC VCC CAD9 // A10 CC/ BE0 // CE1 CAD8 // D15 CAD7 // D7 GRST GND GND CAD12 // A11 CAD11 // OE CAD10 // CE2 VR_ PORT MFUNC 6 SUSPEND VCC VCC CAD14 // A9 CAD15 // IOWR CAD13 // IORD VCCCB MFUNC 2 SPKR OUT MFUNC 1 GND CPAR // A13 CBLOC K // A19 RSVD // A18 CC/ BE1 // A8 CAD16 // A17 MFUNC 0 SCL SDA RSVD VCC GND CTRDY // A22 CGNT // WE CSTOP // A20 CPERR // A14 CLK_48 RSVD RSVD RSVD VCC GND CAD17 // A24 CIRDY // A15 CCLK // A16 CDEVSEL // A21 NC SD_ DAT3 / SM_D7 SD_WP / SM_CE CAD18 // A7 CC/ BE2 // A12 CFRAM E // A23 MC_ PWR_ CTRL_ 1/ VCC GND CAD29 // D1 VCC GND VCC SD_CD USB_ EN CAD28 // D8 CINT // READY (IREQ) CC/ BE3 // REG CAD21 // A5 CAD0 // D3 SM_R/B E RSVD D RSVD RSVD RSVD MS_BS / SD_ CMD / SM_WE CAD19 // A25 C RSVD / VD0 / VCCD1 SD_ CMD / SM_ ALE SD_ DAT0 / SM_D4 MS_ DATA1 / SD_ DAT1 / SM_D1 MC_ PWR_ CTRL_ 0 LATCH / VD3 / VPPD0 CAD31 // D10 CAD27 // D0 CSERR // WAIT CAD25 // A1 CREQ // INPACK CRST // RESET B SM_ CLE SD_ DAT2 / SM_D6 MS_ DATA3 / SD_ DAT3 / SM_D3 MS_ SDIO (DATA0) / SD_ DAT0 / SM_D0 SM_CD DATA / VD2 / VPPD1 RSVD // D2 CCD2 // CD2 CAUDIO // BVD2 (SPKR) CAD26 // A0 CAD23 // A3 CAD22 // A4 CVS2 // VS2 XD_CD / SM_ PHYS_ WP SD_ CLK / SM_RE SD_ DAT1 / SM_D5 MS_ DATA2 / SD_ DAT2 / SM_D2 MS_ CLK / SD_ CLK / SM_EL_ WP MS_CD CLOCK / VD1 / VCCD0 CAD30 // D9 CCLK RUN // WP (IOIS16) CSTS CHG // BVD1 (STSC HG/RI) CVS1 // VS1 CAD24 // A2 VCCCB CAD20 // A6 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A 1 2 17 18 19 Figure 2-8. PCI8412 GHK/ZHK-Package Terminal Diagram September 2005 SCPS110 19 Introduction Table 2-3 lists the terminal assignments arranged in terminal-number order, with corresponding signal names for both CardBus and 16-bit PC Cards for the PCIxx12 GHK packages. Table 2-4 and Table 2-5 list the terminal assignments arranged in alphanumerical order by signal name, with corresponding terminal numbers for the GHK package; Table 2-4 is for CardBus signal names and Table 2-5 is for 16-bit PC Card signal names. Terminal E5 on the GHK package is an identification ball used for device orientation. 20 SCPS110 September 2005 Introduction Table 2-3. Signal Names by GHK Terminal Number TERMINAL NUMBER SIGNAL NAME SIGNAL NAME TERMINAL NUMBER CardBus PC Card 16-Bit PC Card XD_CD / SM_PHYS_WP C11 CAD27 D0 SD_CLK / SM_RE / SC_GPIO1 SD_CLK / SM_RE / SC_GPIO1 C12 CSERR WAIT A05 SD_DAT1 / SM_D5 / SC_GPIO5 SD_DAT1 / SM_D5 / SC_GPIO5 C13 CAD25 A1 A06 MS_DATA2 / SD_DAT2 / SM_D2 MS_DATA2 / SD_DAT2 / SM_D2 C14 CREQ INPACK A07 MS_CLK / SD_CLK / SM_EL_WP MS_CLK / SD_CLK / SM_EL_WP C15 CRST RESET A08 MS_CD MS_CD D01 SC_RFU SC_RFU A09 CLOCK / VD1 / VCCD0 CLOCK / VD1 / VCCD0 D19 CAD19 A25 A10 CAD30 D9 E01 SC_DATA SC_DATA CardBus PC Card 16-Bit PC Card A03 XD_CD / SM_PHYS_WP A04 A11 CCLKRUN WP(IOIS16) E02 SC_CLK SC_CLK A12 CSTSCHG BVD1(STSCHG/RI) E03 SC_FCB SC_FCB A13 CVS1 VS1 E05 NC NC A14 CAD24 A2 E06 SD_DAT3 / SM_D7 / SC_GPIO3 SD_DAT3 / SM_D7 / SC_GPIO3 A15 VCCCB VCCCB E07 SD_WP / SM_CE SD_WP / SM_CE A16 CAD20 A6 E08 MS_BS / SD_CMD / SM_WE MS_BS / SD_CMD / SM_WE B04 SM_CLE / SC_GPIO0 SM_CLE / SC_GPIO0 E09 SD_CD SD_CD B05 SD_DAT2 / SM_D6 / SC_GPIO4 SD_DAT2 / SM_D6 / SC_GPIO4 E10 USB_EN USB_EN B06 MS_DATA3 / SD_DAT3 / SM_D3 MS_DATA3 / SD_DAT3 / SM_D3 E11 CAD28 D8 B07 MS_SDIO(DATA0) / SD_DAT0 / SM_D0 MS_SDIO(DATA0) / SD_DAT0 / SM_D0 E12 CINT READY(IREQ) B08 SM_CD SM_CD E13 CC/BE3 REG B09 DATA / VD2 / VPPD1 DATA / VD2 / VPPD1 E14 CAD21 A5 B10 RSVD D2 E17 CAD18 A7 A12 B11 CCD2 CD2 E18 CC/BE2 B12 CAUDIO BVD2(SPKR) E19 CFRAME A23 B13 CAD26 A0 F01 CLK_48 CLK_48 B14 CAD23 A3 F02 SC_OC SC_OC B15 CAD22 A4 F03 SC_CD SC_CD B16 CVS2 VS2 F05 SC_RST SC_RST C04 RSVD / VD0 / VCCD1 RSVD / VD0 / VCCD1 F06 VCC VCC C05 SD_CMD / SM_ALE / SC_GPIO2 SD_CMD / SM_ALE / SC_GPIO2 F07 GND GND C06 SD_DAT0 / SM_D4 / SC_GPIO6 SD_DAT0 / SM_D4 / SC_GPIO6 F08 MC_PWR_CTRL_1 / SM_R/B MC_PWR_CTRL_1 / SM_R/B C07 MS_DATA1 / SD_DAT1 / SM_D1 MS_DATA1 / SD_DAT1 / SM_D1 F09 VCC VCC C08 MC_PWR_CTRL_0 MC_PWR_CTRL_0 F10 GND GND C09 LATCH / VD3 / VPPD0 LATCH / VD3 / VPPD0 F11 CAD29 D1 C10 CAD31 D10 F12 VCC VCC September 2005 SCPS110 21 Introduction Table 2-3. Signal Names by GHK Terminal Number (Continued) 22 SIGNAL NAME SIGNAL NAME TERMINAL NUMBER CardBus PC Card 16-Bit PC Card TERMINAL NUMBER CardBus PC Card 16-Bit PC Card F13 GND GND K17 CAD11 OE F14 VCC VCC K18 CAD10 CE2 F15 CAD17 A24 K19 VR_PORT VR_PORT F17 CIRDY A15 L01 PCLK PCLK F18 CCLK A16 L02 GNT GNT F19 CDEVSEL A21 L03 REQ REQ G01 MFUNC0 MFUNC0 L05 RI_OUT/PME RI_OUT/PME G02 SCL SCL L06 VCC VCC G03 SDA SDA L14 VCC VCC G05 SC_PWR_CTRL SC_PWR_CTRL L15 CAD9 A10 G06 SC_VCC_5V SC_VCC_5V L17 CC/BE0 CE1 G14 GND GND L18 CAD8 D15 G15 CTRDY A22 L19 CAD7 D7 G17 CGNT WE M01 AD31 AD31 G18 CSTOP A20 M02 AD30 AD30 G19 CPERR A14 M03 AD29 AD29 H01 MFUNC3 MFUNC3 M05 AD27 AD27 H02 MFUNC2 MFUNC2 M06 AD28 AD28 H03 SPKROUT SPKROUT M14 GND GND H05 MFUNC1 MFUNC1 M15 CAD3 D5 H06 GND GND M17 CAD6 D13 H14 CPAR A13 M18 CAD5 D6 H15 CBLOCK A19 M19 RSVD D14 H17 RSVD A18 N01 AD26 AD26 H18 CC/BE1 A8 N02 AD25 AD25 H19 CAD16 A17 N03 AD24 AD24 J01 MFUNC4 MFUNC4 N05 IDSEL IDSEL J02 MFUNC5 MFUNC5 N06 GND GND J03 MFUNC6 MFUNC6 N15 CCD1 CD1 J05 SUSPEND SUSPEND N17 CAD2 D11 J06 VCC VCC N18 CAD1 D4 J14 VCC VCC N19 CAD4 D12 J15 CAD14 A9 P01 VCCP VCCP J17 CAD15 IOWR P02 C/BE3 C/BE3 J18 CAD13 IORD P03 AD23 AD23 J19 VCCCB VCCCB P05 AD20 AD20 K01 VR_PORT VR_PORT P06 VCC VCC K02 VR_EN VR_EN P07 GND GND K03 PRST PRST P08 VCC VCC K05 GRST GRST P09 GND GND K06 GND GND P10 VCC VCC K14 GND GND P11 AD1 AD1 K15 CAD12 A11 P12 TEST0 TEST0 SCPS110 September 2005 Introduction Table 2-3. Signal Names by GHK Terminal Number (Continued) SIGNAL NAME SIGNAL NAME TERMINAL NUMBER CardBus PC Card 16-Bit PC Card TERMINAL NUMBER P13 AVDD_33 AVDD_33 U12 NC NC P14 AVDD_33 AVDD_33 U13 AGND AGND P15 VDDPLL_15 VDDPLL_15 U14 AGND AGND P17 PHY_TEST_MA PHY_TEST_MA U15 AVDD_33 AVDD_33 P19 CAD0 D3 U19 VDDPLL_33 VDDPLL_33 R01 AD22 AD22 V05 IRDY IRDY R02 AD21 AD21 V06 STOP STOP R03 AD19 AD19 V07 C/BE1 C/BE1 R06 FRAME FRAME V08 AD12 AD12 R07 PERR PERR V09 AD10 AD10 R08 AD14 AD14 V10 AD7 AD7 R09 AD8 AD8 V11 AD3 AD3 R10 AD5 AD5 V12 NC NC R11 AD0 AD0 V13 TPB0P TPB0P R12 CPS CPS V14 TPA0P TPA0P R13 TPBIAS0 TPBIAS0 V15 TPB1P TPB1P R14 AGND AGND V16 TPA1P TPA1P R17 VSSPLL VSSPLL W04 AD16 AD16 R18 XO XO W05 TRDY TRDY R19 XI XI W06 SERR SERR T01 AD18 AD18 W07 AD15 AD15 T02 AD17 AD17 W08 VCCP VCCP T18 R0 R0 W09 AD11 AD11 CardBus PC Card 16-Bit PC Card T19 R1 R1 W10 C/BE0 C/BE0 U05 C/BE2 C/BE2 W11 AD4 AD4 U06 DEVSEL DEVSEL W12 NC NC U07 PAR PAR W13 TPB0N TPB0N U08 AD13 AD13 W14 TPA0N TPA0N U09 AD9 AD9 W15 TPB1N TPB1N U10 AD6 AD6 W16 TPA1N TPA1N U11 AD2 AD2 W17 TPBIAS1 TPBIAS1 September 2005 SCPS110 23 Introduction Table 2-4. CardBus PC Card Signal Names Sorted Alphabetically 24 SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER AD0 R11 CAD5 M18 CGNT G17 AD1 P11 CAD6 M17 CINT E12 AD2 U11 CAD7 L19 CIRDY F17 AD3 V11 CAD8 L18 CLK_48 F01 AD4 W11 CAD9 L15 CLOCK / VD1 / VCCD0 A09 AD5 R10 CAD10 K18 CPAR H14 AD6 U10 CAD11 K17 CPERR G19 AD7 V10 CAD12 K15 CPS R12 AD8 R09 CAD13 J18 CREQ C14 AD9 U09 CAD14 J15 CRST C15 AD10 V09 CAD15 J17 CSERR C12 AD11 W09 CAD16 H19 CSTOP G18 AD12 V08 CAD17 F15 CSTSCHG A12 AD13 U08 CAD18 E17 CTRDY G15 AD14 R08 CAD19 D19 CVS1 A13 AD15 W07 CAD20 A16 CVS2 B16 AD16 W04 CAD21 E14 DATA / VD2 / VPPD1 B09 AD17 T02 CAD22 B15 DEVSEL U06 AD18 T01 CAD23 B14 FRAME R06 AD19 R03 CAD24 A14 GND F07 AD20 P05 CAD25 C13 GND F10 AD21 R02 CAD26 B13 GND F13 AD22 R01 CAD27 C11 GND G14 AD23 P03 CAD28 E11 GND H06 AD24 N03 CAD29 F11 GND K06 AD25 N02 CAD30 A10 GND K14 AD26 N01 CAD31 C10 GND M14 AD27 M05 CAUDIO B12 GND N06 AD28 M06 C/BE0 W10 GND P07 AD29 M03 C/BE1 V07 GND P09 AD30 M02 C/BE2 U05 GNT L02 AD31 M01 C/BE3 P02 GRST K05 AGND R14 CBLOCK H15 IDSEL N05 AGND U13 CC/BE0 L17 IRDY V05 AGND U14 CC/BE1 H18 LATCH / VD3 / VPPD0 C09 AVDD_33 P13 CC/BE2 E18 MC_PWR_CTRL_0 C08 AVDD_33 P14 CC/BE3 E13 MC_PWR_CTRL_1 / SM_R/B F08 AVDD_33 U15 CCD1 N15 MFUNC0 G01 CAD0 P19 CCD2 B11 MFUNC1 H05 CAD1 N18 CCLK F18 MFUNC2 H02 CAD2 N17 CCLKRUN A11 MFUNC3 H01 CAD3 M15 CDEVSEL F19 MFUNC4 J01 CAD4 N19 CFRAME E19 MFUNC5 J02 SCPS110 September 2005 Introduction Table 2-4. CardBus PC Card Signal Names Sorted Alphabetically (Continued) SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER MFUNC6 J03 SCL G02 TPB0P V13 MS_BS / SD_CMD / SM_WE E08 SC_OC F02 TPB1N W15 MS_CD A08 SC_PWR_CTRL G05 TPB1P V15 MS_CLK / SD_CLK / SM_EL_WP A07 SC_RFU D01 TRDY W05 MS_DATA1 / SD_DAT1 / SM_D1 C07 SC_RST F05 USB_EN E10 MS_DATA2 / SD_DAT2 / SM_D2 A06 SC_VCC_5V G06 VCC F06 MS_DATA3 / SD_DAT3 / SM_D3 B06 SDA G03 VCC F09 MS_SDIO(DATA0) / SD_DAT0 / SM_D0 B07 SD_CD E09 VCC F12 NC E05 SD_CLK / SM_RE / SC_GPIO1 A04 VCC F14 NC U12 SD_CMD / SM_ALE / SC_GPIO2 C05 VCC J06 NC V12 SD_DAT0 / SM_D4 / SC_GPIO6 C06 VCC J14 NC W12 SD_DAT1 / SM_D5 / SC_GPIO5 A05 VCC L06 PAR U07 SD_DAT2 / SM_D6 / SC_GPIO4 B05 VCC L14 PCLK L01 SD_DAT3 / SM_D7 / SC_GPIO3 E06 VCC P06 PERR R07 SD_WP / SM_CE E07 VCC P08 PHY_TEST_MA P17 SERR W06 VCC P10 PRST K03 SM_CD B08 VCCCB A15 REQ L03 SM_CLE / SC_GPIO0 B04 VCCCB J19 RI_OUT/PME L05 SPKROUT H03 VCCP P01 RSVD B10 STOP V06 VCCP W08 RSVD H17 SUSPEND J05 VDDPLL_15 P15 RSVD M19 TEST0 P12 VDDPLL_33 U19 RSVD / VD0 / VCCD1 C04 TPA0N W14 VR_EN K02 R0 T18 TPA0P V14 VR_PORT K01 R1 T19 TPA1N W16 VR_PORT K19 SC_CD F03 TPA1P V16 VSSPLL R17 SC_CLK E02 TPBIAS0 R13 XD_CD / SM_PHYS_WP A03 SC_DATA E01 TPBIAS1 W17 XI R19 SC_FCB E03 TPB0N W13 XO R18 September 2005 SCPS110 25 Introduction Table 2-5. 16-Bit PC Card Signal Names Sorted Alphabetically 26 SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER AD0 R11 A4 B15 D5 M15 AD1 P11 A5 E14 D6 M18 AD2 U11 A6 A16 D7 L19 AD3 V11 A7 E17 D8 E11 AD4 W11 A8 H18 D9 A10 AD5 R10 A9 J15 D10 C10 AD6 U10 A10 L15 D11 N17 AD7 V10 A11 K15 D12 N19 AD8 R09 A12 E18 D13 M17 AD9 U09 A13 H14 D14 M19 AD10 V09 A14 G19 D15 L18 AD11 W09 A15 F17 FRAME R06 AD12 V08 A16 F18 GND F07 AD13 U08 A17 H19 GND F10 AD14 R08 A18 H17 GND F13 AD15 W07 A19 H15 GND G14 AD16 W04 A20 G18 GND H06 AD17 T02 A21 F19 GND K06 AD18 T01 A22 G15 GND K14 AD19 R03 A23 E19 GND M14 AD20 P05 A24 F15 GND N06 AD21 R02 A25 D19 GND P07 AD22 R01 BVD1(STSCHG/RI) A12 GND P09 AD23 P03 BVD2(SPKR) B12 GNT L02 AD24 N03 C/BE0 W10 GRST K05 AD25 N02 C/BE1 V07 IDSEL N05 AD26 N01 C/BE2 U05 INPACK C14 AD27 M05 C/BE3 P02 IORD J18 AD28 M06 CD1 N15 IOWR J17 AD29 M03 CD2 B11 IRDY V05 AD30 M02 CE1 L17 LATCH / VD3 / VPPD0 C09 AD31 M01 CE2 K18 MC_PWR_CTRL_0 C08 AGND R14 CLK_48 F01 MC_PWR_CTRL_1 / SM_R/B F08 AGND U13 CLOCK / VD1 / VCCD0 A09 MFUNC0 G01 AGND U14 CPS R12 MFUNC1 H05 AVDD_33 P13 DATA / VD2 / VPPD1 B09 MFUNC2 H02 AVDD_33 P14 DEVSEL U06 MFUNC3 H01 AVDD_33 U15 D0 C11 MFUNC4 J01 A0 B13 D1 F11 MFUNC5 J02 A1 C13 D2 B10 MFUNC6 J03 A2 A14 D3 P19 MS_CD A08 A3 B14 D4 N18 MS_BS / SD_CMD / SM_WE E08 SCPS110 September 2005 Introduction Table 2-5. 16-Bit PC Card Signal Names Sorted Alphabetically (Continued) TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER MS_CLK / SD_CLK / SM_EL_WP A07 SC_RFU D01 USB_EN E10 MS_DATA1 / SD_DAT1 / SM_D1 C07 SC_RST F05 VCC F06 MS_DATA2 / SD_DAT2 / SM_D2 A06 SC_VCC_5V G06 VCC F09 MS_DATA3 / SD_DAT3 / SM_D3 B06 SDA G03 VCC F12 MS_SDIO(DATA0) / SD_DAT0 / SM_D0 B07 SD_CD E09 VCC F14 NC E05 SD_CLK / SM_RE / SC_GPIO1 A04 VCC J06 NC U12 SD_CMD / SM_ALE / SC_GPIO2 C05 VCC J14 NC V12 SD_DAT0 / SM_D4 / SC_GPIO6 C06 VCC L06 NC W12 SD_DAT1 / SM_D5 / SC_GPIO5 A05 VCC L14 OE K17 SD_DAT2 / SM_D6 / SC_GPIO4 B05 VCC P06 PAR U07 SD_DAT3 / SM_D7 / SC_GPIO3 E06 VCC P08 PCLK L01 SD_WP / SM_CE E07 VCC P10 SIGNAL NAME PERR R07 SERR W06 VCCCB A15 PHY_TEST_MA P17 SM_CD B08 VCCCB J19 PRST K03 SM_CLE / SC_GPIO0 B04 VCCP P01 READY(IREQ) E12 SPKROUT H03 VCCP W08 REG E13 STOP V06 VDDPLL_15 P15 REQ L03 SUSPEND J05 VDDPLL_33 U19 RI_OUT/PME L05 TEST0 P12 VR_EN K02 RESET C15 TPA0N W14 VR_PORT K01 RSVD / VD0 / VCCD1 C04 TPA0P V14 VR_PORT K19 R0 T18 TPA1N W16 VSSPLL R17 R1 T19 TPA1P V16 VS1 A13 SC_CD F03 TPBIAS0 R13 VS2 B16 SC_CLK E02 TPBIAS1 W17 WAIT C12 SC_DATA E01 TPB0N W13 WE G17 SC_FCB E03 TPB0P V13 WP(IOIS16) A11 SCL G02 TPB1N W15 XD_CD / SM_PHYS_WP A03 SC_OC F02 TPB1P V15 XI R19 SC_PWR_CTRL G05 TRDY W05 XO R18 September 2005 SCPS110 27 Introduction 2.9 Detailed Terminal Descriptions Please see Table 2-6 through Table 2-24 for more detailed terminal descriptions. The following list defines the column headings and the abbreviations used in the detailed terminal description tables. * - - - - - - I/O Type: I = Digital input O = Digital output I/O = Digital input/output AI = Analog input PWR = Power GND = Ground - - - - - - - - - - - - - - - - - - - - - - - - Input/Output Description: AF = Analog feedthrough TTLI1 = 5-V tolerant TTL input buffer TTLI2 = 5-V tolerant TTL input buffer with hysteresis TTLO1 = 5-V tolerant low-noise 4-mA TTL output buffer PCII1 = 3.3-V PCI input buffer PCII3 = Universal 5-V tolerant PCI input buffer PCII4 = 5-V tolerant PCMCIA input buffer PCII5 = 5-V Smart Card input buffer PCII6 = 5-V tolerant PCMCIA input buffer, failsafe PCII7 = 5-V tolerant PCIMCIA input buffer PCIO1 = 3.3-V PCI output buffer PCIO3 = Universal 5-V tolerant PCI output buffer PCIO4 = 5-V tolerant PCMCIA output buffer PCIO5 = 5-V Smart Card output buffer PCIO6 = 5-V Smart Card output buffer PCIO7 = 5-V tolerant PCMCIA output buffer PCIO8 = 5-V Smart Card output buffer LVCI1 = LVCMOS input buffer LVCI2 = LVCMOS input buffer with hysteresis, failsafe LVCI3 = LVCMOS input buffer with hysteresis LVCO1 = Low-noise 4-mA LVCMOS output buffer LVCO2 = Low-noise 4-mA LVCMOS open drain output buffer LVCO3 = Low-noise 8-mA LVCMOS output buffer TP = 1394a transceiver * * 28 PU/PD signifies whether the terminal has an internal pullup or pulldown resistor. These pullups are disabled and enabled by design when appropriate to preserve power. - PD1 = 20-A pulldown - PD2 = 100-A pulldown - PU2 = 100-A pullup - PU4 = 5-V tolerant 100-A pullup - PU5 = 100-A pullup SCPS110 September 2005 Introduction - - - SW1 = Switchable 50-A pullup/200-A pulldown implemented depending on situation SW2 = Switchable 100-A pullup/100-A pulldown implemented depending on situation SW3 = Switchable 200-A pullup/200-A pulldown implemented depending on situation * Power Rail signifies which rail the terminal is clamped to for protection. * External Components signifies any external components needed for normal operation. * Pin Strapping (If Unused) signifies how the terminal must be implemented if its function is not needed. The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The terminal numbers are also listed for convenient reference. Table 2-6. Power Supply Terminals Output description, internal pullup/pulldown resistors, and the power rail designation are not applicable for the power supply terminals. TERMINAL NAME AGND DESCRIPTION NUMBER I/O TYPE INPUT EXTERNAL COMPONENTS R14, U13, U14 Analog circuit ground terminals GND AVDD_33 P13, P14, U15 Analog circuit power terminals. A parallel combination of high frequency decoupling capacitors near each terminal is suggested, such as 0.1 F and 0.001 F. Lower frequency 10-F filtering capacitors are also recommended. These supply terminals are separated from VDDPLL_33 internal to the controller to provide noise isolation. They must be tied to a low-impedance point on the circuit board. GND GND F07, F10, F13, G14, H06, K06, K14, M14, N06, P07, P09 Digital ground terminal GND VCC F06, F09, F12, F14, J06, J14, L06, L14, P06, P08, P10 Power supply terminal for I/O and internal voltage regulator PWR 0.1-F and 0.001-F decoupling capacitors 0.1-F capacitor tied to GND VCCCB A15, J19 Clamp voltage for PC Card interface. Matches card signaling environment, 5 V or 3.3 V PWR VCCP P01, W08 Clamp voltage for PCI and miscellaneous I/O, 5 V or 3.3 V PWR PIN STRAPPING (IF UNUSED) NA 0.1-F, 0.001-F, and 10-F capacitors tied to AGND NA NA NA Float NA P15 1.5-V PLL circuit power terminal. An external capacitor (0.1 F recommended) must be placed between terminals T18 and R17 (VSSPLL) when the internal voltage regulator is enabled (VR_EN = 0 V). When the internal voltage regulator is disabled, 1.5-V must be supplied to this terminal and a parallel combination of high frequency decoupling capacitors near the terminal is suggested, such as 0.1 F and 0.001 F. Lower frequency 10-F filtering capacitors are also recommended. 0.1-F, 0.001-F, and 10-F capacitors tied to VSSPLL NA VDDPLL_33 U19 3.3-V PLL circuit power terminal. A parallel combination of high frequency decoupling capacitors near the terminal is suggested, such as 0.1 F and 0.001 F. Lower frequency 10-F filtering capacitors are also recommended. This supply terminal is separated from AVDD internal to the controller to provide noise isolation. It must be tied to a low-impedance point on the circuit board. When the internal voltage regulator is disabled (VR_EN = 3.3 V), no voltage is required to be supplied to this terminal. PWR 0.1-F, 0.001-F, and 10-F capacitors tied to VSSPLL NA VR_EN K02 Internal voltage regulator enable. Active low AF Pulled directly to GND NA VSSPLL R17 PLL circuit ground terminal. This terminal must be tied to the low-impedance circuit board ground plane. GND 1.5-V output from the internal voltage regulator PWR VDDPLL_15 VR_PORT September 2005 K01, K19 NA 0.1-F capacitor tied to GND NA SCPS110 29 Introduction Table 2-7. Serial PC Card Power Switch Terminals Internal pullup/pulldown resistors, power rail designation, and pin strapping are not applicable for the power switch terminals. TERMINAL NAME NO. DESCRIPTION I/O TYPE INPUT OUTPUT EXTERNAL COMPONENTS TTLI1 TTLO1 PCMCIA power switch CLOCK A09 Power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. CLOCK defaults to an input, but can be changed to an output by using bit 27 (P2CCLK) in the system control register (offset 80h, see Section 4.29). I/O DATA B09 Power switch data. DATA is used to communicate socket power control information serially to the power switch. O LVCO1 PCMCIA power switch LATCH C09 Power switch latch. LATCH is asserted by the controller to indicate to the power switch that the data on the DATA line is valid. O LVCO1 PCMCIA power switch Table 2-8. Parallel PC Card Power Switch Terminals Internal pullup/pulldown resistors, power rail designation, and pin strapping are not applicable for the power switch terminals. TERMINAL NAME NO. I/O DESCRIPTION INPUT OUTPUT TTLI1 LVCI1 TTLO1 LVCO1 VD1/VCCD0 VD0/VCCD1 A09 C04 I/O Logic controls to the TPS2211A PC Card power interface switch to control VCCCB. RSVD/VD0/VCCD1 (terminal C04) controls the power switch interface mode. If it is pulled up, the power switch interface uses the 3-pin serial power interface. If it is pulled down, the power switch interface uses the 4-pin parallel power switch interface. VD3/VPPD0 VD2/VPPD1 C09 B09 O Logic controls to the TPS2211A PC Card power interface switch to control VPP LVCO1 LVCO1 Table 2-9. PCI System Terminals Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI terminals. TERMINAL NAME NO. DESCRIPTION I/O TYPE INPUT I LVCI2 POWER RAIL GRST K05 Global reset. When the global reset is asserted, the GRST signal causes the controller to place all output buffers in a high-impedance state and reset all internal registers. When GRST is asserted, the controller is completely in its default state. For systems that require wake-up from D3, GRST is normally asserted only during initial boot. PRST must be asserted following initial boot so that PME context is retained when transitioning from D3 to D0. For systems that do not require wake-up from D3, GRST must be tied to PRST. When the SUSPEND mode is enabled, the controller is protected from the GRST, and the internal registers are preserved. All outputs are placed in a high-impedance state, but the contents of the registers are preserved. PCLK L01 PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK. I PCII3 VCCP K03 PCI bus reset. When the PCI bus reset is asserted, PRST causes the controller to place all output buffers in a high-impedance state and reset some internal registers. When PRST is asserted, the controller is completely nonfunctional. After PRST is deasserted, the controller is in a default state. When SUSPEND and PRST are asserted, the controller is protected from PRST clearing the internal registers. All outputs are placed in a high-impedance state, but the contents of the registers are preserved. I PCII3 VCCP PRST 30 SCPS110 EXTERNAL COMPONENTS Power-on reset or tied to PRST September 2005 Introduction Table 2-10. PCI Address and Data Terminals Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI address and data terminals. TERMINAL NAME NO. AD31 M01 AD30 M02 AD29 M03 AD28 M06 AD27 M05 AD26 N01 AD25 N02 AD24 N03 AD23 P03 AD22 R01 AD21 R02 AD20 P05 AD19 R03 AD18 T01 AD17 T02 AD16 W04 AD15 W07 AD14 R08 AD13 U08 AD12 V08 AD11 W09 AD10 V09 AD09 U09 AD08 R09 AD07 V10 AD06 U10 AD05 R10 AD04 W11 AD03 V11 AD02 U11 AD01 P11 AD00 R11 C/BE3 P02 C/BE2 U05 C/BE1 V07 C/BE0 W10 PAR U07 September 2005 DESCRIPTION I/O TYPE INPUT OUTPUT POWER RAIL PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary-bus PCI cycle, AD31-AD0 contain a 32-bit address or other destination information. During the data phase, AD31-AD0 contain data. I/O PCII3 PCIO3 VCCP PCI-bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary-bus PCI cycle, C/BE3-C/BE0 define the bus command. During the data phase, this 4-bit bus is used as a byte enable. The byte enable determines which byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to byte 0 (AD7-AD0), C/BE1 applies to byte 1 (AD15-AD8), C/BE2 applies to byte 2 (AD23-AD16), and C/BE3 applies to byte 3 (AD31-AD24). I/O PCII3 PCIO3 VCCP PCI-bus parity. In all PCI-bus read and write cycles, the controller calculates even parity across the AD31-AD0 and C/BE3-C/BE0 buses. As an initiator during PCI cycles, the controller outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the controller compares its calculated parity to the parity indicator of the initiator. A compare error results in the assertion of a parity error (PERR). I/O PCII3 PCIO3 VCCP SCPS110 31 Introduction Table 2-11. PCI Interface Control Terminals Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI interface control terminals. TERMINAL DESCRIPTION I/O TYPE INPUT OUTPUT U06 PCI device select. The controller asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the controller monitors DEVSEL until a target responds. If no target responds before timeout occurs, then the controller terminates the cycle with an initiator abort. I/O PCII3 PCIO3 VCCP Pullup resistor per PCI specification R06 PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME is deasserted, the PCI bus transaction is in the final data phase. I/O PCII3 PCIO3 VCCP Pullup resistor per PCI specification GNT L02 PCI bus grant. GNT is driven by the PCI bus arbiter to grant the controller access to the PCI bus after the current data transaction has completed. GNT may or may not follow a PCI bus request, depending on the PCI bus parking algorithm. I PCII3 VCCP IDSEL N05 Initialization device select. IDSEL selects the controller during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus. I PCII3 VCCP IRDY V05 PCI initiator ready. IRDY indicates the ability of the PCI bus initiator to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted. I/O PCII3 PCIO3 VCCP Pullup resistor per PCI specification PERR R07 PCI parity error indicator. PERR is driven by a PCI controller to indicate that calculated parity does not match PAR when PERR is enabled through bit 6 of the command register (PCI offset 04h, see Section 4.4). I/O PCII3 PCIO3 VCCP Pullup resistor per PCI specification REQ L03 PCI bus request. REQ is asserted by the controller to request access to the PCI bus as an initiator. O PCIO3 VCCP SERR W06 PCI system error. SERR is an output that is pulsed from the controller when enabled through bit 8 of the command register (PCI offset 04h, see Section 4.4) indicating a system error has occurred. The controller need not be the target of the PCI cycle to assert this signal. When SERR is enabled in the command register, this signal also pulses, indicating that an address parity error has occurred on a CardBus interface. O PCIO3 VCCP Pullup resistor per PCI specification STOP V06 PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction. STOP is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers. I/O PCII3 PCIO3 VCCP Pullup resistor per PCI specification W05 PCI target ready. TRDY indicates the ability of the primary bus target to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are inserted. I/O PCII3 PCIO3 VCCP Pullup resistor per PCI specification NAME NO. DEVSEL FRAME TRDY 32 SCPS110 POWER RAIL EXTERNAL COMPONENTS September 2005 Introduction Table 2-12. Multifunction and Miscellaneous Terminals The power rail designation is not applicable for the multifunction and miscellaneous terminals. TERMINAL NAME NO. DESCRIPTION A 48-MHz clock must be connected to this terminal. I/O TYPE INPUT I LVCI1 OUTPUT PU/ PD EXTERNAL COMPONENTS PIN STRAPPING (IF UNUSED) 48 MHz clock source CLK_48 F01 MFUNC0 G01 I/O PCII3 PCIO3 10-k to 47-k pullup resistor MFUNC1 H05 I/O PCII3 PCIO3 10-k to 47-k pullup resistor MFUNC2 H02 I/O PCII3 PCIO3 10-k to 47-k pullup resistor MFUNC3 H01 I/O PCII3 PCIO3 10-k to 47-k pullup resistor MFUNC4 J01 I/O PCII3 PCIO3 10-k to 47-k pullup resistor MFUNC5 J02 I/O PCII3 PCIO3 10-k to 47-k pullup resistor MFUNC6 J03 I/O PCII3 PCIO3 10-k to 47-k pullup resistor PHY_TEST_MA P17 PHY test pin. Not for customer use. It must be pulled high with a 4.7-k resistor. I LCVI1 RI_OUT / PME L05 Ring indicate out and power management event output. This terminal provides an output for ring-indicate or PME signals. O G02 Serial clock. At PRST, the SCL signal is sampled to determine if a two-wire serial ROM is present. If the serial ROM is detected, then this terminal provides the serial clock signaling and is implemented as open-drain. For normal operation (a ROM is implemented in the design), this terminal must be pulled high to the ROM VDD with a 2.7-k resistor. Otherwise, it must be pulled low to ground with a 220- resistor. G03 Serial data. This terminal is implemented as open-drain, and for normal operation (a ROM is implemented in the design), this terminal must be pulled high to the ROM VDD with a 2.7-k resistor. Otherwise, it must be pulled low to ground with a 220- resistor. I/O SPKROUT H03 Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the controller from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card SPKR//CAUDIO inputs. O SUSPEND J05 Suspend. SUSPEND protects the internal registers from clearing when the GRST or PRST signal is asserted. See Section 3.8.6, Suspend Mode, for details. I LVCI2 TEST0 P12 Terminal TEST0 is used for factory test of the controller and must be connected to ground for normal operation. I/O LVCI1 USB_EN E10 USB enable. ThIs output terminal controlS an external CBT switch for the socket when an USB card is inserted into the socket. O SCL SDA September 2005 Multifunction terminals 0-6. See Section 4.35, Multifunction Routing Status Register, for configuration details. I/O TTLI1 TTLI1 PU2 NA LVCO2 Pullup resistor per PCI specification NA TTLO2 Pullup resistor per I2C specification (value depends on EEPROM, typically 2.7 k) Tie to GND if not using EEPROM TTLO2 Pullup resistor per I2C specification (value depends on EEPROM, typically 2.7 k) Tie to GND if not using EEPROM TTLO1 10-k to 47-k pulldown resistor 10-k to 47-k pullup resistor PD1 LVCO1 10-k to 47-k pullup resistor Tie to GND CBT switch Float SCPS110 33 Introduction Table 2-13. 16-Bit PC Card Address and Data Terminals External components are not applicable for the 16-bit PC Card address and data terminals. If any 16-bit PC Card address and data terminal is unused, then the terminal may be left floating. For input, output, pullup, and pulldown information refer to information by terminal number in Table 2-15, Table 2-16, and Table 2-17. TERMINAL NAME NO. A25 D19 A24 F15 A23 E19 A22 G15 A21 F19 A20 G18 A19 H15 A18 H17 A17 H19 A16 F18 A15 F17 A14 G19 A13 H14 A12 E18 A11 K15 A10 L15 A9 J15 A8 H18 A7 E17 A6 A16 A5 E14 A4 B15 A3 B14 A2 A14 A1 C13 A0 B13 D15 L18 D14 M19 D13 M17 D12 N19 D11 N17 D10 C10 D9 A10 D8 E11 D7 L19 D6 M18 D5 M15 D4 N18 D3 P19 D2 B10 D1 F11 D0 C11 DESCRIPTION I/O TYPE POWER RAIL PC Card address. 16-bit PC Card address lines. A25 is the most significant bit. O VCCCB PC Card data. 16-bit PC Card data lines. D15 is the most significant bit. I/O VCCCB These terminals are reserved for the PCI7402 and PCI8402 controllers. 34 SCPS110 September 2005 Introduction Table 2-14. 16-Bit PC Card Interface Control Terminals External components are not applicable for the 16-bit PC Card interface control terminals. If any 16-bit PC Card interface control terminal is unused, then the terminal may be left floating. For input, output, pullup, and pulldown information refer to information by terminal number in Table 2-15, Table 2-16, and Table 2-17. TERMINAL NAME BVD1 (STSCHG/RI) NO. A12 DESCRIPTION Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and must be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See Section 5.6, ExCA Card Status-Change Interrupt Configuration Register, for enable bits. See Section 5.5, ExCA Card Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the status bits for this signal. I/O TYPE POWER RAIL I VCCCB I VCCCB Status change. STSCHG alerts the system to a change in the READY, write protect, or battery voltage dead condition of a 16-bit I/O PC Card. Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection. BVD2 (SPKR) B12 Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and must be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See Section 5.6, ExCA Card Status-Change Interrupt Configuration Register, for enable bits. See Section 5.5, ExCA Card Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the status bits for this signal. Speaker. SPKR is an optional binary audio signal available only when the card and socket have been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the controller and are output on SPKROUT. DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation. CD1 CD2 N15 B11 Card detect 1 and card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled low. For signal status, see Section 5.2, ExCA Interface Status Register. I CE1 CE2 L17 K18 Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes. CE1 enables even-numbered address bytes, and CE2 enables odd-numbered address bytes. O VCCCB INPACK C14 Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read cycle at the current address. DMA request. INPACK can be used as the DMA request signal during DMA operations from a 16-bit PC Card that supports DMA. If it is used as a strobe, then the PC Card asserts this signal to indicate a request for a DMA operation. I VCCCB IORD J18 I/O read. IORD is asserted by the controller to enable 16-bit I/O PC Card data output during host I/O read cycles. DMA write. IORD is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The controller asserts IORD during DMA transfers from the PC Card to host memory. O VCCCB IOWR J17 I/O write. IOWR is driven low by the controller to strobe write data into 16-bit I/O PC Cards during host I/O write cycles. DMA read. IOWR is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The controller asserts IOWR during transfers from host memory to the PC Card. O VCCCB These terminals are reserved for the PCI7402 and PCI8402 controllers. September 2005 SCPS110 35 Introduction Table 2-14. 16-Bit PC Card Interface Control Terminals (Continued) TERMINAL NAME OE NO. K17 READY (IREQ) E12 DESCRIPTION I/O TYPE Output enable. OE is driven low by the controller to enable 16-bit memory PC Card data output during host memory read cycles. DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit PC Card that supports DMA. The controller asserts OE to indicate TC for a DMA write operation. O VCCCB I VCCCB O VCCCB Ready. The ready function is provided when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command. POWER RAIL Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a controller on the 16-bit I/O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is requested. REG E13 Attribute memory select. REG remains high for all common memory accesses. When REG is asserted, access is limited to attribute memory (OE or WE active) and to the I/O space (IORD or IOWR active). Attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information. DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a 16-bit PC Card that supports DMA. The controller asserts REG to indicate a DMA operation. REG is used in conjunction with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data. RESET C15 PC Card reset. RESET forces a hard reset to a 16-bit PC Card. O VCCCB VS1 VS2 A13 B16 Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other, determine the operating voltage of the PC Card. I/O VCCCB WAIT C12 Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion of the memory or I/O cycle in progress. I VCCCB G17 Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for memory PC Cards that employ programmable memory technologies. DMA terminal count. WE is used as a TC during DMA operations to a 16-bit PC Card that supports DMA. The controller asserts WE to indicate the TC for a DMA read operation. O VCCCB I VCCCB WE Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16) function. WP (IOIS16) A11 I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses. DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, then the PC Card asserts WP to indicate a request for a DMA operation. These terminals are reserved for the PCI7402 and PCI8402 controllers. Table 2-15. CardBus PC Card Interface System Terminals A 33- to 47- series damping resistor (per PC Card specification) is the only external component needed for terminal C16 (CCLK). If any CardBus PC Card interface system terminal is unused, then the terminal may be left floating. TERMINAL NAME NO. DESCRIPTION I/O TYPE INPUT OUTPUT PU/ PD POWER RAIL CCLK F18 CardBus clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All signals except CRST, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2, CCD1, CVS2, and CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings. CCLKRUN A11 CardBus clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK frequency, and by the controller to indicate that the CCLK frequency is going to be decreased. I/O PCII4 PCIO4 PU3 VCCCB C15 CardBus reset. CRST brings CardBus PC Card-specific registers, sequencers, and signals to a known state. When CRST is asserted, all CardBus PC Card signals are placed in a high-impedance state, and the controller drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK. O PCII4 PCIO4 PU3 VCCCB CRST O PCIO3 VCCCB These terminals are reserved for the PCI7402 and PCI8402 controllers. 36 SCPS110 September 2005 Introduction Table 2-16. CardBus PC Card Address and Data Terminals External components are not applicable for the 16-bit PC Card address and data terminals. If any CardBus PC Card address and data terminal is unused, then the terminal may be left floating. TERMINAL NAME NO. CAD31 C10 CAD30 A10 CAD29 F11 CAD28 E11 CAD27 C11 CAD26 B13 CAD25 C13 CAD24 A14 CAD23 B14 CAD22 B15 CAD21 E14 CAD20 A16 CAD19 D19 CAD18 E17 CAD17 F15 CAD16 H19 CAD15 J17 CAD14 J15 CAD13 J18 CAD12 K15 CAD11 K17 CAD10 K18 CAD9 L15 CAD8 L18 CAD7 L19 CAD6 M17 CAD5 M18 CAD4 N19 CAD3 M15 CAD2 N17 CAD1 N18 CAD0 P19 CC/BE3 E13 CC/BE2 E18 CC/BE1 H18 CC/BE0 L17 CPAR H14 DESCRIPTION I/O TYPE INPUT OUTPUT POWER RAIL CardBus address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31-CAD0 contain a 32-bit address. During the data phase of a CardBus cycle, CAD31-CAD0 contain data. CAD31 is the most significant bit. I/O PCII7 PCIO7 VCCCB CardBus bus commands and byte enables. CC/BE3-CC/BE0 are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE3-CC/BE0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. CC/BE0 applies to byte 0 (CAD7-CAD0), CC/BE1 applies to byte 1 (CAD15-CAD8), CC/BE2 applies to byte 2 (CAD23-CAD16), and CC/BE3 applies to byte 3 (CAD31-CAD24). I/O PCII7 PCIO7 VCCCB CardBus parity. In all CardBus read and write cycles, the controller calculates even parity across the CAD and CC/BE buses. As an initiator during CardBus cycles, the controller outputs CPAR with a one-CCLK delay. As a target during CardBus cycles, the controller compares its calculated parity to the parity indicator of the initiator; a compare error results in a parity error assertion. I/O PCII7 PCIO7 VCCCB These terminals are reserved for the PCI7402 and PCI8402 controllers. September 2005 SCPS110 37 Introduction Table 2-17. CardBus PC Card Interface Control Terminals If any CardBus PC Card interface control terminal is unused, then the terminal may be left floating. TERMINAL I/O TYPE INPUT OUTPUT PU/ PD CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The controller supports the binary audio mode and outputs a binary signal from the card to SPKROUT. I/O PCII4 PCIO4 PU3 VCCCB H15 CardBus lock. CBLOCK is used to gain exclusive access to a target. I/O PCII4 PCIO4 PU3 VCCCB CCD1 CCD2 N15 B11 CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type. I TTLI2 CDEVSEL F19 CardBus device select. The controller asserts CDEVSEL to claim a CardBus cycle as the target device. As a CardBus initiator on the bus, the controller monitors CDEVSEL until a target responds. If no target responds before timeout occurs, then the controller terminates the cycle with an initiator abort. I/O PCII4 PCIO4 CFRAME E19 CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When CFRAME is deasserted, the CardBus bus transaction is in the final data phase. I/O PCII7 PCIO7 VCCCB CGNT G17 CardBus bus grant. CGNT is driven by the controller to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed. I/O PCII7 PCIO7 VCCCB CINT E12 CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host. I/O PCII4 PCIO4 PU3 VCCCB CIRDY F17 CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY and CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted. I/O PCII4 PCIO4 PU3 VCCCB CPERR G19 CardBus parity error. CPERR reports parity errors during CardBus transactions, except during special cycles. It is driven low by a target two clocks following the data cycle during which a parity error is detected. I/O PCII4 PCIO4 PU3 VCCCB CREQ C14 CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator. I/O PCII4 PCIO4 PU3 VCCCB CSERR C12 CardBus system error. CSERR reports address parity errors and other system errors that could lead to catastrophic results. CSERR is driven by the card synchronous to CCLK, but deasserted by a weak pullup; deassertion may take several CCLK periods. The controller can report CSERR to the system by assertion of SERR on the PCI interface. I/O PCII4 PCIO4 PU3 VCCCB CSTOP G18 CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP is used for target disconnects, and is commonly asserted by target devices that do not support burst data transfers. I/O PCII4 PCIO4 PU3 VCCCB CSTSCHG A12 CardBus status change. CSTSCHG alerts the system to a change in the card status, and is used as a wake-up mechanism. I PCII6 SW1 VCCCB CTRDY G15 CardBus target ready. CTRDY indicates the ability of the CardBus target to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY and CTRDY are asserted; until this time, wait states are inserted. I/O PCII1 PCIO1 PU5 VCCCB CVS1 CVS2 A13 B16 CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and card type. I/O TTLI2 TTLO1 PU4 VCCCB NAME NO. CAUDIO B12 CBLOCK DESCRIPTION POWER RAIL PU4 PU3 VCCCB These terminals are reserved for the PCI7402 and PCI8402 controllers. Table 2-18. Reserved Terminals TERMINAL NAME RSVD 38 B10, H17, M19 SCPS110 DESCRIPTION NUMBER Reserved (CardBus reserved) PIN STRAPPING Float September 2005 Introduction Table 2-19. IEEE 1394 Physical Layer Terminals Table 2-19 is only applicable to the PCI4512, PCI7402, PCI7412, PCI7612, PCI8402, and PCI8412 controllers. TERMINAL NAME I/O TYPE DESCRIPTION NO. R12 Cable power status input. This terminal is normally connected to cable power through a 400-k resistor. This circuit drives an internal comparator that is used to detect the presence of cable power. If CPS is not used to detect cable power, then this terminal must be pulled to GND. R0 R1 T18 T19 Current-setting resistor terminals. These terminals are connected to an external resistance to set the internal operating currents and cable driver output currents. A resistance of 6.34 k 1% is required to meet the IEEE Std 1394-1995 output voltage limits. TPA0P TPA0N V14 W14 TPA1P TPA1N V16 W16 TPBIAS0 TPBIAS1 R13 W17 TPB0P TPB0N V13 W13 TPB1P TPB1N V15 W15 CPS XI XO R19 R18 Twisted-pair cable A differential signal terminals. Board trace lengths from each pair of positive and negative differential signal pins must be matched and as short as possible to the external load resistors and to the cable connector. For an unused port, TPA+ and TPA- can be left open. Twisted-pair bias output. This provides the 1.86-V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for signaling to the remote nodes that there is an active cable connection. Each of these pins must be decoupled with a 1.0-F capacitor to ground. Twisted-pair cable B differential signal terminals. Board trace lengths from each pair of positive and negative differential signal pins must be matched and as short as possible to the external load resistors and to the cable connector. For an unused port, TPB+ and TPB- must be pulled to ground. Crystal oscillator inputs. These pins connect to a 24.576-MHz parallel resonant fundamental mode crystal. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used (see Section 3.9.2, Crystal Selection). An external clock input can be connected to the XI terminal. When using an external clock input, the XO terminal must be left unconnected, and the clock must be supplied before the controller is taken out of reset. Refer to Section 3.9.2 for the operating characteristics of the XI terminal. INPUT OUTPUT EXTERNAL COMPONENTS PIN STRAPPING (IF UNUSED) AF 390-k series resistor to BUSPOWER if providing power through the 1394 port Tie to GND AF 6.34-k 1% resistor between R0 and R1 per 1394 specification Tie to GND I/O TP TP 1394 termination (see reference schematics) Float I//O TP TP 1394 termination (see reference schematics) Float 1394 termination (see reference schematics) Float AF I/O TP TP 1394 termination (see reference schematics) Float I/O TP TP 1394 termination (see reference schematics) Float 24.576-MHz oscillator (see implementation guide) Float AF These terminals are reserved for the PCI6412 and PCI6612 controllers. Table 2-20. No Connect Terminals TERMINAL NAME NUMBER NC U12, V12, W12 NC E05 September 2005 DESCRIPTION PIN STRAPPING No connect. These terminals do not have a connection anywhere on this device. Float No connect. This terminal is an identification ball used for device orientation. Float SCPS110 39 Introduction Table 2-21. SD/MMC Terminals If any SD/MMC terminal is unused, then the terminal may be left floating. TERMINAL NAME NO. MC_PWR_CTRL_0 C08 MC_PWR_CTRL_1 F08 SD_CD E09 DESCRIPTION A07 SD_CMD C05, E08 SD_DAT3 E06, B06 SD_DAT2 B05, A06 SD_DAT1 A05, C07 SD_DAT0 C06, B07 SD_WP E07 INPUT O OUTPUT PU/ PD POWER RAIL EXTERNAL COMPONENTS Power switch or FET to turn power on to FM socket I/O LVCI1 LVCO1 PU2 VCC VCC SD/MMC card detect. This input is asserted when SD/MMC cards are inserted. I LVCI1 LVCO1 PU2 VCC SD flash clock. This output provides the SD/MMC clock, which operates at 16 MHz. I/O LVCI3 LVCO3 PU2 LVCI3 LVCO3 VCC VCC SD flash command. This signal provides the SD command per the SD Memory Card Specifications. I/O LVCI1 LVCO1 SW2 VCC SD flash data [3:0]. These signals provide the SD data path per the SD Memory Card Specifications. I/O LVCI1 LVCO1 SW2 VCC SD write protect data. This signal indicates that the media inserted in the socket is write protected. I/O LVCI1 LVCO1 PU2 VCC Media card power control for flash media sockets A04 SD_CLK I/O TYPE LVCO1 These terminals are reserved for the PCI4512 controller. Table 2-22. Memory Stick/PRO Terminals If any Memory Stick/PRO terminal is unused, then the terminal may be left floating. TERMINAL NAME NO. MC_PWR_CTRL_0 C08 MC_PWR_CTRL_1 F08 MS_BS E08 MS_CD DESCRIPTION I/O TYPE INPUT O OUTPUT PU/ PD POWER RAIL LVCO1 I/O LVCI1 LVCO1 PU2 VCC VCC Memory Stick bus state. This signal provides Memory Stick bus state information. I/O LVCI1 LVCO1 SW2 VCC A08 Media Card detect. This input is asserted when a Memory Stick or Memory Stick Pro media is inserted. I LVCI1 PU2 VCC MS_CLK A07 Memory Stick clock. This output provides the MS clock, which operates at 16 MHz. I/O LVCI3 LVCO3 MS_DATA3 B06 MS_DATA2 A06 Memory Stick data [3:1]. These signals provide the Memory Stick data path. I/O LVCI1 LVCO1 SW2 VCC MS_DATA1 C07 MS_SDIO (DATA0) B07 Memory Stick serial data I/O. This signal provides Memory Stick data input/output. Memory Stick data 0. I/O LVCI1 LVCO1 SW2 VCC Media card power control for flash media sockets EXTERNAL COMPONENTS Power switch or FET to turn power on to FM socket VCC These terminals are reserved for the PCI4512 controller. 40 SCPS110 September 2005 Introduction Table 2-23. Smart Media/XD Terminals If any Smart Media/XD terminal is unused, then the terminal may be left floating. TERMINAL DESCRIPTION I/O TYPE C08 Media card power control for flash media sockets O SM_ALE C05 SmartMedia address latch enable. This signal functions as specified in the SmartMedia specification, and is used to latch addresses passed over SM_D7-SM_D0. I/O LVCI1 SM_CD B08 SmartMedia card detect. This input is asserted when SmartMedia cards are inserted. I LVCI1 SM_CE E07 SmartMedia card enable. This signal functions as specified in the SmartMedia specification, and is used to enable the media for a pending transaction. I/O LVCI1 SM_CLE B04 SmartMedia command latch enable. This signal functions as specified in the SmartMedia specification, and is used to latch commands passed over SM_D7-SM_D0. I/O SM_D7 E06 SM_D6 B05 SmartMedia data terminals. These signals pass data to and from the SmartMedia, and functions as specified in the SmartMedia specifications. NAME MC_PWR_CTRL_0 NO. SM_D5 A05 SM_D4 C06 SM_D3 B06 INPUT OUTPUT PU/ PD LVCO1 LVCO1 POWER RAIL VCC SW2 VCC PU2 VCC LVCO1 PU2 VCC LVCI1 LVCO1 PD2 VCC I/O LVCI1 LVCO1 SW2 VCC I/O LVCI3 LVCO3 I LVCI1 I/O LVCI1 SM_D2 A06 SM_D1 C07 SM_D0 B07 SM_EL_WP A07 SmartMedia electrical write protect SM_PHYS_WP A03 SmartMedia physical write protect. This input comes from the write protect tab of the SmartMedia card. SM_RE A04 SmartMedia read enable. This signal functions as specified in the SmartMedia specification, and is used to latch a read transfer from the card. SM_R/B F08 SmartMedia read/busy. This signal functions as specified in the SmartMedia specification, and is used to pace data transfers to the card. I/O LVCI1 LVCO1 SM_WE E08 SmartMedia write enable. This signal functions as specified in the SmartMedia specification, and is used to latch a write transfer to the card. I/O LVCI1 LVCO1 XD_CD A03 I LVCI1 EXTERNAL PARTS Power switch or FET to turn power on to FM socket 100-k pullup resistor to VCC for xD compliance VCC PU2 LVCO1 VCC 100-k pullup resistor to VCC for xD compliance PU2 VCC 10-k to 47-k pullup resistor to VCC for xD compliance SW2 VCC 100-k pullup resistor to VCC for xD compliance PU2 VCC PU2 These terminals are reserved for the PCI4512 controller. September 2005 SCPS110 41 Introduction Table 2-24. Smart Card Terminals If any Smart Card terminal is unused, then the terminal may be left floating, except for SC_VCC_5V which must be connected to 5 V. Smart Card terminals are only functional in the PCI6612 and PCI7612 controllers. TERMINAL NAME SC_CD NO. F03 DESCRIPTION Smart Card card detect. This input is asserted when Smart Cards are inserted. I/O TYPE INPUT OUTPUT PU/ PD POWER RAIL I/O LVCI1 LVCO1 PU2 VCC SC_CLK E02 Smart Card clock. The controller drives a 3-MHz clock to the Smart Card interface when enabled. O SC_DATA E01 Smart Card data input/output I/O PCII5 PCIO5 SW3 SC_VCC_5V SC_FCB E03 Smart Card function code. The controller does not support synchronous Smart Cards as specified in ISO/IEC 7816-10, and this terminal is in a high-impedance state. I/O PCII5 PCIO5 SW3 SC_VCC_5V SC_GPIO6 C06 LVCI1 LVCO1 SW2 VCC SC_GPIO5 A05 LVCI1 LVCO1 SW2 VCC SC_GPIO4 B05 LVCI1 LVCO1 SW2 VCC SC_GPIO3 E06 LVCI1 LVCO1 SW2 VCC SC_GPIO2 C05 LVCI1 LVCO1 SW2 VCC SC_GPIO1 A04 LVCI3 LVCO3 PU2 VCC SC_GPIO0 B04 LVCI3 LVCO3 PU2 VCC SC_OC F02 PU2 VCC Smart Card general-purpose I/O terminals. These signals can be controlled by firmware and are used as control signals for an external Smart Card interface chip or level shifter. Smart Card overcurrent. This input comes from the Smart Card power switch. I/O I SC_PWR_CTRL G05 Smart Card power control for the Smart Card socket O SC_RFU D01 Smart Card reserved. This terminal is in a high-impedance state. I/O SC_RST F05 Smart Card This signal starts and stops the Smart Card reset sequence. The controller asserts this reset when requested by the host. O SC_VCC_5V G06 Smart Card power terminal PCIO8 LVCI1 SC_VCC_5V LVCO1 PCII5 PCIO5 PCIO6 VCC SW3 EXTERNAL PARTS Series resistor or 22 k resistor to GND 68 pF capacitor to GND Power switch or FET to turn on power to FM socket SC_VCC_5V SC_VCC_5V PWR These terminals are reserved for the PCI4512, PCI6412, PCI7402, PCI7412, PCI8402, and PCI8412 controllers. 42 SCPS110 September 2005 Principles of Operation 3 Principles of Operation The following sections give an overview of the PCIxx12 controller. Figure 3-1 shows the connections to the controller. The PCI interface includes all address/data and control signals for PCI protocol. The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. PCI Bus EEPROM SD/MMC MS/MSPRO SM/xD PCIxx12 SD/MMC 1394a Socket Smart Card Power Switch PC Card Power Switch Power Switch Power Switch Figure 3-1. PCIxx12 System Block Diagram 3.1 Power Supply Sequencing The PCIxx12 controller contains 3.3-V I/O buffers with 5-V tolerance requiring a core power supply and clamp voltages. The core power supply is always 1.5 V. The clamp voltages can be either 3.3 V or 5 V, depending on the interface. The following power-up and power-down sequences are recommended. The power-up sequence is: 1. Power core 1.5 V. 2. Apply the I/O voltage. 3. Apply the analog voltage. 4. Apply the clamp voltage. The power-down sequence is: 1. Remove the clamp voltage. 2. Remove the analog voltage. 3. Remove the I/O voltage. 4. Remove power from the core. NOTE: If the voltage regulator is enabled, then steps 2, 3, and 4 of the power-up sequence and steps 1, 2, and 3 of the power-down sequence all occur simultaneously. September 2005 SCPS110 43 Principles of Operation 3.2 I/O Characteristics The PCIxx12 controller meets the ac specifications of the PC Card Standard (release 8.1) and the PCI Local Bus Specification. Figure 3-2 shows a 3-state bidirectional buffer. Section 14.2, Recommended Operating Conditions, provides the electrical characteristics of the inputs and outputs. VCCP Tied for Open Drain OE Pad Figure 3-2. 3-State Bidirectional Buffer 3.3 Clamping Voltages The clamping voltages are set to match whatever external environment the PCIxx12 controller is interfaced with: 3.3 V or 5 V. The I/O sites can be pulled through a clamping diode to a voltage rail that protects the core from external signals. The core power supply is 1.5 V and is independent of the clamping voltages. For example, PCI signaling can be either 3.3 V or 5 V, and the controller must reliably accommodate both voltage levels. This is accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a system designer desires a 5-V PCI bus, then VCCP can be connected to a 5-V power supply. 3.4 Peripheral Component Interconnect (PCI) Interface The PCIxx12 controller is fully compliant with the PCI Local Bus Specification. The controller provides all required signals for PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling environment by connecting the VCCP terminals to the desired voltage level. In addition to the mandatory PCI signals, the controller provides the optional interrupt signals INTA, INTB, INTC, and INTD. 3.4.1 1394 PCI Bus Master As a bus master, the 1394 function of the PCIxx12 controller supports the memory commands specified in Table 3-1. The PCI master supports the memory read, memory read line, and memory read multiple commands. The read command usage for read transactions of greater than two data phases are determined by the selection in bits 9-8 (MR_ENHANCE field) of the PCI miscellaneous configuration register (refer to Section 7.23 for details). For read transactions of one or two data phases, a memory read command is used. Table 3-1. PCI Bus Support PCI Memory read 44 SCPS110 COMMAND C/BE3-C/BE0 OHCI MASTER FUNCTION 0110 DMA read from memory Memory write 0111 DMA write to memory Memory read multiple 1100 DMA read from memory Memory read line 1110 DMA read from memory Memory write and invalidate 1111 DMA write to memory September 2005 Principles of Operation 3.4.2 Device Resets The following are the requirements for proper reset of the PCIxx12 controller: 1. GRST and PRST must both be asserted at power on. 2. GRST must be asserted for at least 2 ms at power on. 3. PRST must be deasserted either at the same time or after GRST is asserted. 4. PCLK must be stable for 100 s before PRST is deasserted. > 2 ms > 0 ns VCC GRST PRST PCLK > 100 ms Figure 3-3. PCI Reset Requirement 3.4.3 Serial EEPROM I 2C Bus The PCIxx12 controller offers many choices for modes of operation, and these choices are selected by programming several configuration registers. For system board applications, these registers are normally programmed through the BIOS routine. For add-in card and docking-station/port-replicator applications, the controller provides a two-wire inter-integrated circuit (IIC or I2C) serial bus for use with an external serial EEPROM. The controller is always the bus master, and the EEPROM is always the slave. Either device can drive the bus low, but neither device drives the bus high. The high level is achieved through the use of pullup resistors on the SCL and SDA signal lines. The controller is always the source of the clock signal, SCL. System designers who wish to load register values with a serial EEPROM must use pullup resistors on the SCL and SDA terminals. If the controller detects a logic-high level on the SCL terminal at the end of GRST, then it initiates incremental reads from the external EEPROM. Any size serial EEPROM up to the I2C limit of 16 Kbits can be used, but only the first 96 bytes (from offset 00h to offset 5Fh) are required to configure the controller. Figure 3-3 shows a serial EEPROM application. September 2005 SCPS110 45 Principles of Operation In addition to loading configuration data from an EEPROM, the I2C bus can be used to read and write from other I2C serial devices. A system designer can control the I2C bus, using the controller as bus master, by reading and writing PCI configuration registers. Setting bit 3 (SBDETECT) in the serial bus control/status register (PCI offset B3h, see Section 4.49) causes the controller to route the SDA and SCL signals to the SDA and SCL terminals, respectively. The read/write data, slave address, and byte addresses are manipulated by accessing the serial bus data, serial bus index, and serial bus slave address registers (PCI offsets B0h, B1h, and B2h; see Sections 4.46, 4.47, and 4.48, respectively). EEPROM interface status information is communicated through the serial bus control and status register (PCI offset B3h, see Section 4.49). Bit 3 (SBDETECT) in this register indicates whether or not the serial ROM circuitry detects the pullup resistor on SCL. Any undefined condition, such as a missing acknowledge, results in bit 0 (ROM_ERR) being set. Bit 4 (ROMBUSY) is set while the subsystem ID register is loading (serial ROM interface is busy). The subsystem vendor ID for functions 2 and 3 is also loaded through EEPROM. The EEPROM load data goes to all four functions from the serial EEPROM loader. VCC Serial ROM A0 A1 SCL SCL A2 SDA SDA PCIxx12 Figure 3-4. Serial ROM Application 3.4.4 Function 0 (CardBus) Subsystem Identification The subsystem vendor ID register (PCI offset 40h, see Section 4.26) and subsystem ID register (PCI offset 42h, see Section 4.27) make up a doubleword of PCI configuration space for function 0. This doubleword register is used for system and option card (mobile dock) identification purposes and is required by some operating systems. Implementation of this unique identifier register is a PC 99/PC 2001 requirement. The PCIxx12 controller offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers is read-only, but can be made read/write by clearing bit 5 (SUBSYSRW) in the system control register (PCI offset 80h, see Section 4.29). Once this bit is cleared, the BIOS can write a subsystem identification value into the registers at PCI offset 40h. The BIOS must set the SUBSYSRW bit such that the subsystem vendor ID register and subsystem ID register are limited to read-only access. This approach saves the added cost of implementing the serial electrically erasable programmable ROM (EEPROM). In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register must be loaded with a unique identifier via a serial EEPROM. The controller loads the data from the serial EEPROM after a reset of the primary bus. Note that the SUSPEND input gates the PCI reset from the entire PCIxx12 core, including the serial-bus state machine (see Section 3.8.6, Suspend Mode, for details on using SUSPEND). 46 SCPS110 September 2005 Principles of Operation The controller provides a two-line serial-bus host controller that can interface to a serial EEPROM. See Section 3.6, Serial EEPROM Interface, for details on the two-wire serial-bus controller and applications. 3.4.5 Function 1 (OHCI 1394) Subsystem Identification The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCI configuration space (see Section 7.25, Subsystem Access Register). See Table 7-22 for a complete description of the register contents. Write access to the subsystem access register updates the subsystem identification registers identically to OHCI-Lynx. The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at Function 1 PCI offsets 2Ch and 2Eh, respectively. The system ID value written to this register may also be read back from this register. See Table 7-22 for a complete description of the register contents. 3.4.6 Function 2 (Flash Media) Subsystem Identification The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset 50h in the PCI configuration space (see Section 11.22, Subsystem Access Register). See Table 11-15 for a complete description of the register contents. The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at Function 2 PCI offsets 2Ch and 2Eh, respectively. See Table 11-15 for a complete description of the register contents. 3.4.7 Function 3 (SD Host) Subsystem Identification The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset 8Ch in the PCI configuration space (see Section 12.23, Subsystem Access Register). See Table 12-16 for a complete description of the register contents. The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at Function 3 PCI offsets 2Ch and 2Eh, respectively. See Table 12-16 for a complete description of the register contents. 3.4.8 Function 4 (Smart Card) Subsystem Identification The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset 50h in the PCI configuration space (see Section 13.23, Subsystem ID Alias Register). See Table 13-14 for a complete description of the register contents. The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at Function 4 PCI offsets 2Ch and 2Eh, respectively. See Table 13-14 for a complete description of the register contents. 3.5 PC Card Applications The PCIxx12 controller supports all the PC Card features and applications as described below. * * * * * Card insertion/removal and recognition per the PC Card Standard (release 8.1) Speaker and audio applications LED socket activity indicators PC Card controller programming model CardBus socket registers September 2005 SCPS110 47 Principles of Operation 3.5.1 PC Card Insertion/Removal and Recognition The PC Card Standard (release 8.1) addresses the card-detection and recognition process through an interrogation procedure that the socket must initiate on card insertion into a cold, nonpowered socket. Through this interrogation, card voltage requirements and interface (CardBus versus 16-bit) are determined. The scheme uses the card-detect and voltage-sense signals. The configuration of these four terminals identifies the card type and voltage requirements of the PC Card interface. 3.5.2 Low Voltage CardBus Card Detection The card detection logic of the PCIxx12 controller includes the detection of Cardbus cards with VCC = 3.3 V and VPP = 1.8 V. The reporting of the 1.8-V CardBus card (VCC = 3.3 V, VPP = 1.8 V) is reported through the socket present state register as follows based on bit 10 (12V_SW_SEL) in the general control register (PCI offset 86h, see Section 4.30): * If the 12V_SW_SEL bit is 0b (TPS2228 is used), then the 1.8-V CardBus card causes the 3VCARD bit in the socket present state register to be set. * If the 12V_SW_SEL bit is 1b (TPS2226 is used), then the 1.8-V CardBus card causes the XVCARD bit in the socket present state register to be set. 3.5.3 PC Card Detection The PC Card Standard addresses the card detection and recognition process through an interrogation procedure that the socket must initiate upon card insertion into a cold, unpowered socket. Through this interrogation, card voltage requirements and interface type (16-bit vs. CardBus) are determined. The scheme uses the CD1, CD2, VS1, and VS2 signals (CCD1, CCD2, CVS1, CVS2 for CardBus). A PC Card designer connects these four terminals in a certain configuration to indicate the type of card and its supply voltage requirements. The encoding scheme for this, defined in the PC Card Standard, is shown in Table 3-2. In addition, to 16-bit and CardBus cards, the controller supports the detection of USB custom cards via the custom card detection method defined by the PC Card Standard. Other types of custom cards are not supported and if detected the socket registers will report values as if it were empty. 48 SCPS110 September 2005 Principles of Operation Table 3-2. PC Card--Card Detect and Voltage Sense Connections CCD2//CD2 CCD1//CD1 CVS2//VS2 CVS1//VS1 Key Interface Ground Ground Ground Ground Ground 16-bit PC Card VCC 5V VPP/VCORE Per CIS (VPP) Open Open 5V Open Ground 5V 16-bit PC Card 5 V and 3.3 V Per CIS (VPP) Ground Ground Ground 5V 16-bit PC Card 5 V, 3.3 V, and Per CIS (VPP) Ground Ground Open Ground LV 16-bit PC Card 3.3 V Per CIS (VPP) Ground Connect to CVS1 Open Connect to CCD1 LV CardBus PC Card 3.3 V Per CIS (VPP) Ground X.X V Ground Ground Ground LV 16-bit PC Card 3.3 V and X.X V Per CIS (VPP) Connect to CVS2 Ground Connect to CCD2 Ground LV CardBus PC Card 3.3 V and X.X V Per CIS (VPP) Connect to CVS1 Ground Ground Connect to CCD2 LV CardBus PC Card 3.3 V, X.X V, and Y.Y V Per CIS (VPP) Ground Ground Ground Open LV 16-bit PC Card X.X V Per CIS (VPP) Connect to CVS2 Ground Connect to CCD2 Open LV CardBus PC Card 3.3 V 1.8 V (VCORE) Ground Connect to CVS2 Connect to CCD1 Open LV CardBus PC Card X.X V and Y.Y V Per CIS (VPP) Connect to CVS1 Ground Open Connect to CCD2 LV CardBus PC Card Y.Y V Per CIS (VPP) Ground Connect to CVS1 Ground Connect to CCD1 LV UltraMedia Ground Connect to CVS2 Connect to CCD1 Ground Reserved Per query terminals Reserved 3.5.4 Flash Media and Smart Card Detection The PCIxx12 controller detects flash media card insertions through the SD_CD, MS_CD, SM_CD, and XD_CD terminals. When one of these terminals is 0b, a flash media device is inserted in the respective socket. The controller debounces these signals such that instability of the signal does not cause false card insertions. The debounce time is approximately 50 ms. The detect signals are not debounced on card removals. The filtered detect signals are used in the flash media card detection and power control logic. The MMC/SD card detection and power control logic contains three main states: * * * Socket empty, power off Card inserted, power off Card inserted, power on The controller detects a Smart Card insertion through the SC_CD terminal. When this terminal is 0b, a Smart Card is inserted in the socket. The controller debounces the SC_CD signal such that instability of the signal does not cause false card insertions. The debounce time is approximately 50 ms. The SC_CD signal is not debounced on card removals. The filtered SC_CD signal is used in the Smart Card detection and power control logic. The Smart Card detection and power control logic contains three main states: * * * Socket empty, power off Card inserted, power off Card inserted, power on September 2005 SCPS110 49 Principles of Operation 3.5.5 Power Switch Interface The power switch interface of the PCIxx12 controller supports either the 3-pin serial interface or the 4-pin parallel interface. The RSVD/VD0/VCCD1 pin selects whether the 3-pin serial interface or the 4-pin parallel interface is used. If the RSVD/VD0/VCCD1 pin is sampled high on the rising edge of GRST, then the 3-pin serial interface is used. If the RSVD/VD0/VCCD1 pin is sampled low on the rising edge of GRST, then the 4-pin parallel interface is used. The 3-pin interface is implemented such that the controller can connect to both the TPS2226 and TPS2228 power switches. Bit 10 (12V_SW_SEL) in the general control register (PCI offset 86h, see Section 4.30) selects the power switch that is implemented. The controller defaults to use the control logic for the TPS2228 power switch. See Table 3-3 and Table 3-6 below for the power switch control logic. Table 3-3. TPS2228 Control Logic--xVPP/VCORE OUTPUT V_AVPP/VCORE D8(SHDN) D4 D5 D10 X 0V 1 0 0 X 0V 0 3.3 V 1 0 1 0 3.3 V 1 5V 1 0 1 1 5V X Hi-Z 1 1 0 X Hi-Z 0 Hi-Z 1 1 1 0 Hi-Z AVPP/VCORE CONTROL SIGNALS D8(SHDN) D0 D1 D9 1 0 0 1 0 1 1 0 1 1 1 0 1 1 1 BVPP/VCORE CONTROL SIGNALS OUTPUT V_BVPP/VCORE 1 1 1 1 1.8 V 1 1 1 1 1.8 V 0 X X X Hi-Z 0 X X X Hi-Z Table 3-4. TPS2228 Control Logic--xVCC OUTPUT V_AVCC D8(SHDN) D6 D7 0 0V 1 0 0 0V 1 3.3 V 1 0 1 3.3 V 0 5V 1 1 0 5V AVCC CONTROL SIGNALS D8(SHDN) D3 D2 1 0 1 0 1 1 OUTPUT V_BVCC BVCC CONTROL SIGNALS 1 1 1 0V 1 1 1 0V 0 X X Hi-Z 0 X X Hi-Z Table 3-5. TPS2226 Control Logic--xVPP OUTPUT V_AVPP D8(SHDN) D4 D5 D10 X 0V 1 0 0 X 0V 0 3.3 V 1 0 1 0 3.3 V 1 5V 1 0 1 1 5V X 12 V 1 1 0 X 12 V X Hi-Z 1 1 1 X Hi-Z X Hi-Z 0 X X X Hi-Z AVPP CONTROL SIGNALS D8(SHDN) D0 D1 D9 1 0 0 1 0 1 1 0 1 1 1 0 1 1 1 0 X X BVPP CONTROL SIGNALS OUTPUT V_BVPP Table 3-6. TPS2226 Control Logic--xVCC D8(SHDN) D3 D2 OUTPUT V_AVCC D8(SHDN) D6 D7 OUTPUT V_BVCC 1 0 0 0V 1 0 0 0V 1 0 1 3.3 V 1 0 1 3.3 V 1 1 0 5V 1 1 0 5V AVCC CONTROL SIGNALS 50 BVCC CONTROL SIGNALS 1 1 1 0V 1 1 1 0V 0 X X Hi-Z 0 X X Hi-Z SCPS110 September 2005 Principles of Operation 3.5.6 Internal Ring Oscillator The internal ring oscillator provides an internal clock source for the PCIxx12 controller so that neither the PCI clock nor an external clock is required in order for the controller to power down a socket or interrogate a PC Card. This internal oscillator, operating nominally at 16 kHz, is always enabled. 3.5.7 Integrated Pullup Resistors for PC Card Interface The PC Card Standard requires pullup resistors on various terminals to support both CardBus and 16-bit PC Card configurations. The PCIxx12 controller has integrated all of these pullup resistors and requires no additional external components. The I/O buffer on the CSTSCHG//BVD1(STSCHG) terminal has the capability to switch to an internal pullup resistor when a 16-bit PC Card is inserted, or switch to an internal pulldown resistor when a CardBus card is inserted. This prevents inadvertent CSTSCHG events. 3.5.8 SPKROUT and CAUDPWM Usage The SPKROUT terminal carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured for I/O mode, the BVD2 terminal becomes the SPKR input terminal from the card. This terminal, in CardBus applications, is referred to as CAUDIO. SPKR passes a TTL-level binary audio signal to the PCIxx12 controller. The CardBus CAUDIO signal also can pass a single-amplitude binary waveform as well as a PWM signal. The binary audio signal from the PC Card socket is enabled by bit 1 (SPKROUTEN) of the card control register (PCI offset 91h, see Section 4.37). Older controllers support CAUDIO in binary or PWM mode, but use the same output terminal (SPKROUT). Some audio chips may not support both modes on one terminal and may have a separate terminal for binary and PWM. The PCIxx12 implementation includes a signal for PWM, CAUDPWM, which can be routed to an MFUNC terminal. Bit 2 (AUD2MUX), located in the card control register, is programmed to route a CardBus CAUDIO PWM terminal to CAUDPWM. See Section 4.35, Multifunction Routing Register, for details on configuring the MFUNC terminals. Figure 3-5 illustrates the SPKROUT connection. System Core Logic BINARY_SPKR SPKROUT Speaker Subsystem PCIxx12 CAUDPWM PWM_SPKR Figure 3-5. SPKROUT Connection to Speaker Driver 3.5.9 LED Socket Activity Indicators The socket activity LEDs indicate when a PC Card is being accessed. The LEDA1 and LEDSKT signals can be routed to the multifunction terminals. When configured for LED outputs, these terminals output an active high signal to indicate socket activity. See Section 4.35, Multifunction Routing Status Register, for details on configuring the multifunction terminals. The active-high LED signal is driven for 64 ms. When the LED is not being driven high, it is driven to a low state. Either of the two circuits shown in Figure 3-6 can be implemented to provide LED signaling, and the board designer must implement the circuit that best fits the application. The LED activity signals are valid when a card is inserted, powered, and not in reset. For PC Card-16, the LED activity signals are pulsed when READY(IREQ) is low. For CardBus cards, the LED activity signals are pulsed if CFRAME, IRDY, or CREQ is active. September 2005 SCPS110 51 Principles of Operation Current Limiting R 150 MFUNCx Socket LED PCIxx12 Figure 3-6. Sample LED Circuit As indicated, the LED signals are driven for a period of 64 ms by a counter circuit. To avoid the possibility of the LEDs appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when the SUSPEND signal is asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1 power state. If any additional socket activity occurs during this counter cycle, then the counter is reset and the LED signal remains driven. If socket activity is frequent (at least once every 64 ms), then the LED signals remain driven. 3.5.10 CardBus Socket Registers The PCIxx12 controller contains all registers for compatibility with the PCI Local Bus Specification and the PC Card Standard. These registers, which exist as the CardBus socket registers, are listed in Table 3-7. Table 3-7. CardBus Socket Registers REGISTER NAME 00h Socket mask 04h Socket present state 08h Socket force event 0Ch Socket control Reserved Socket power management 3.5.11 OFFSET Socket event 10h 14h-1Ch 20h 48-MHz Clock Requirements The PCIxx12 controller is designed to use an external 48-MHz clock connected to the CLK_48 terminal to provide the reference for an internal oscillator circuit. This oscillator in turn drives a PLL circuit that generates the various clocks required for the flash media function (Function 2) of the controller. The 48-MHz clock is needed as follows in the designated states: * * * * * Power-up D0: D1/D2/D3: D1/D2/D3hot to D0: D3cold to D0: Follow the power-up sequence Clock must not be stopped Clock can be stopped Need 10 clocks before D0 state Need 10 clocks before PRST de-assert The 48-MHz clock must maintain a frequency of 48 MHz 0.8% over normal operating conditions. This clock must maintain a duty cycle of 40% - 60%. The controller requires that the 48-MHz clock be running and stable (a minimum of 10 clock pulses) before a GRST deassertion. 52 SCPS110 September 2005 Principles of Operation The following are typical specifications for crystals used with the controller in order to achieve the required frequency accuracy and stability. * Crystal mode of operation: Fundamental * Frequency tolerance @ 25C: Total frequency variation for the complete circuit is 100 ppm. A crystal with 30 ppm frequency tolerance is recommended for adequate margin. * Frequency stability (overtemperature and age): A crystal with 30 ppm frequency stability is recommended for adequate margin. NOTE: The total frequency variation must be kept below 100 ppm from nominal with some allowance for error introduced by board and device variations. Trade-offs between frequency tolerance and stability may be made as long as the total frequency variation is less than 100 ppm. For example, the frequency tolerance of the crystal may be specified at 50 ppm and the temperature tolerance may be specified at 30 ppm to give a total of 80 ppm possible variation due to the crystal alone. Crystal aging also contributes to the frequency variation. 3.6 Serial EEPROM Interface The PCIxx12 controller has a dedicated serial bus interface that can be used with an EEPROM to load certain registers in the controller. The EEPROM is detected by a pullup resistor on the SCL terminal. See Table 3-9 for the EEPROM loading map. 3.6.1 Serial-Bus Interface Implementation The PCIxx12 controller drives SCL at nearly 100 kHz during data transfers, which is the maximum specified frequency for standard mode I2C. The serial EEPROM must be located at address A0h. Some serial device applications may include PC Card power switches, card ejectors, or other devices that may enhance the user's PC Card experience. The serial EEPROM device and PC Card power switches are discussed in the sections that follow. 3.6.2 Accessing Serial-Bus Devices Through Software The PCIxx12 controller provides a programming mechanism to control serial bus devices through software. The programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3-8 lists the registers used to program a serial-bus device through software. Table 3-8. PCIxx12 Registers Used to Program Serial-Bus Devices PCI OFFSET REGISTER NAME DESCRIPTION B0h Serial-bus data Contains the data byte to send on write commands or the received data byte on read commands. B1h Serial-bus index The content of this register is sent as the word address on byte writes or reads. This register is not used in the quick command protocol. B2h Serial-bus slave address Write transactions to this register initiate a serial-bus transaction. The slave device address and the R/W command selector are programmed through this register. B3h Serial-bus control and status Read data valid, general busy, and general error status are communicated through this register. In addition, the protocol-select bit is programmed through this register. 3.6.3 Serial-Bus Interface Protocol The SCL and SDA signals are bidirectional, open-drain signals and require pullup resistors as shown in Figure 3-4. The PCIxx12 controller, which supports up to 100-Kb/s data-transfer rate, is compatible with standard mode I2C using 7-bit addressing. All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start condition, which is signaled when the SDA line transitions to the low state while SCL is in the high state, as shown in Figure 3-7. The end of a requested data transfer is indicated by a stop condition, which is signaled by a low-to-high transition of SDA while SCL is in the high state, as shown in Figure 3-7. Data on SDA must remain stable during the high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control signals, that is, a start or a stop condition. September 2005 SCPS110 53 Principles of Operation SDA SCL Start Condition Stop Condition Change of Data Allowed Data Line Stable, Data Valid Figure 3-7. Serial-Bus Start/Stop Conditions and Bit Transfers Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by the receiver pulling the SDA signal low, so that it remains low during the high state of the SCL signal. Figure 3-8 illustrates the acknowledge protocol. SCL From Master 1 2 3 7 8 9 SDA Output By Transmitter SDA Output By Receiver Figure 3-8. Serial-Bus Protocol Acknowledge The controller is a serial bus master; all other devices connected to the serial bus external to the controller are slave devices. As the bus master, the controller drives the SCL clock at nearly 100 kHz during bus cycles and places SCL in a high-impedance state (zero frequency) during idle states. Typically, the controller masters byte reads and byte writes under software control. Doubleword reads are performed by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under software control. See Section 3.6.4, Serial-Bus EEPROM Application, for details on how the controller automatically loads the subsystem identification and other register defaults through a serial-bus EEPROM. Figure 3-9 illustrates a byte write. The controller issues a start condition and sends the 7-bit slave device address and the command bit zero. A 0b in the R/W command bit indicates that the data transfer is a write. The slave device acknowledges if it recognizes the address. If no acknowledgment is received by the controller, then an appropriate status bit is set in the serial-bus control/status register (PCI offset B3h, see Section 4.49). The word address byte is then sent by the controller, and another slave acknowledgment is expected. Then the controller delivers the data byte MSB first and expects a final acknowledgment before issuing the stop condition. Slave Address S Word Address b6 b5 b4 b3 b2 b1 b0 0 A Data Byte b7 b6 b5 b4 b3 b2 b1 b0 A b7 b6 b5 b4 b3 b2 b1 b0 A P R/W A = Slave Acknowledgement S/P = Start/Stop Condition Figure 3-9. Serial-Bus Protocol--Byte Write 54 SCPS110 September 2005 Principles of Operation Figure 3-10 illustrates a byte read. The read protocol is very similar to the write protocol, except the R/W command bit must be set to 1b to indicate a read-data transfer. In addition, the PCIxx12 master must acknowledge reception of the read bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data transfers. The SCL signal remains driven by the PCIxx12 master. Slave Address S Word Address b6 b5 b4 b3 b2 b1 b0 0 A Slave Address b7 b6 b5 b4 b3 b2 b1 b0 S b6 b5 b4 b3 b2 b1 b0 Restart R/W Start A 1 A R/W Data Byte b7 b6 b5 b4 b3 b2 b1 b0 M P Stop A = Slave Acknowledgement M = Master Acknowledgement S/P = Start/Stop Condition Figure 3-10. Serial-Bus Protocol--Byte Read Figure 3-11 illustrates EEPROM interface doubleword data collection protocol. Slave Address S 1 0 1 0 0 Word Address 0 0 Start 0 A Slave Address b7 b6 b5 b4 b3 b2 b1 b0 M A = Slave Acknowledgement S 1 0 1 0 0 Data Byte 2 M Data Byte 1 M = Master Acknowledgement M Data Byte 0 0 0 1 A R/W Restart R/W Data Byte 3 A M P S/P = Start/Stop Condition Figure 3-11. EEPROM Interface Doubleword Data Collection 3.6.4 Serial-Bus EEPROM Application When the PCI bus is reset and the serial-bus interface is detected, the PCIxx12 controller attempts to read the subsystem identification and other register defaults from a serial EEPROM. This format must be followed for the controller to load initializations from a serial EEPROM. All bit fields must be considered when programming the EEPROM. The serial EEPROM is addressed at slave address 1010 000b by the controller. All hardware address bits for the EEPROM must be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample application (Figure 3-11) assumes the 1010b high-address nibble. The lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND. September 2005 SCPS110 55 Principles of Operation Table 3-9. EEPROM Loading Map SERIAL ROM OFFSET BYTE DESCRIPTION 00h CardBus function indicator (00h) 01h Number of bytes (22h) PCI 04h, command register, function 0, bits 8, 6-5, 2-0 02h [7] [6] [5] [4:3] [2] [1] [0] Command register, bit 8 Command register, bit 6 Command register, bit 5 RSVD Command register, bit 2 Command register, bit 1 Command register, bit 0 03h Reserved 04h PCI 40h, subsystem vendor ID, byte 0 05h PCI 41h, subsystem vendor ID, byte 1 06h PCI 42h, subsystem ID, byte 0 07h PCI 43h, subsystem ID, byte 1 08h PCI 44h, PC Card 16-bit I/F legacy mode base address register, byte 0, bits 7-1 09h PCI 45h, PC Card 16-bit I/F legacy mode base address register, byte 1 0Ah PCI 46h, PC Card 16-bit I/F legacy mode base address register, byte 2 0Bh PCI 47h, PC Card 16-bit I/F legacy mode base address register, byte 3 0Ch PCI 80h, system control, function 0, byte 0, bits 6-0 0Dh Reserved 0Eh PCI 81h, system control, byte 1, bits 7, 6 0Fh Reserved nonloadable (PCI 82h, system control, byte 2) 10h PCI 83h, system control, byte 3 11h PCI 8Ch, MFUNC routing, byte 0 12h PCI 8Dh, MFUNC routing, byte 1 13h PCI 8Eh, MFUNC routing, byte 2 14h PCI 8Fh, MFUNC routing, byte 3 15h PCI 90h, retry status, bits 7, 6 16h PCI 91h, card control, bit 7 17h PCI 92h, device control, bits 6-1 (bit 0 must be programmed to 0b) 18h PCI 93h, diagnostic, bits 7, 4-0 19h PCI A2h, power-management capabilities, function 0, bit 15 (bit 7 of EEPROM offset 19h corresponds to bit 15) 1Ah Reserved 1Bh Reserved 1Ch Reserved 1Dh ExCA 00h, ExCA identification and revision, bits 7-0 1Eh PCI 86h, general control, byte 0, bits 7-0 1Fh PCI 87h, general control, byte 1, bits 7, 6 (can only be set to 1b if bits 1:0 = 01b), 4-0 20h PCI 89h, GPE enable, bits 7, 6, 4-0 21h PCI 8Bh, general-purpose output, bits 4-0 22h PCI 85h, general control byte 1, bits 2-0 23h Reserved 24h 1394 OHCI function indicator (01h) 25h 26h 27h 56 SCPS110 Number of bytes (17h) PCI 3Fh, maximum latency bits 7-4 PCI 3Eh, minimum grant, bits 3-0 PCI 2Ch, subsystem vendor ID, byte 0 September 2005 Principles of Operation Table 3-9. EEPROM Loading Map (Continued) SERIAL ROM OFFSET BYTE DESCRIPTION 28h PCI 2Dh, subsystem vendor ID, byte 1 29h PCI 2Eh, subsystem ID, byte 0 2Ah PCI 2Fh, subsystem ID, byte 1 2Bh PCI F4h, Link_Enh, byte 0, bits 7, 2, 1 OHCI 50h, host controller control, bit 23 2Ch [7] [6] [5:3] [2] [1] [0] Link_Enh. enab_unfair HCControl.Program Phy Enable RSVD Link_Enh, bit 2 Link_Enh. enab_accel RSVD Mini-ROM address, this byte indicates the MINI ROM offset into the EEPROM 00h = No MINI ROM Other Values = MINI ROM offset 2Dh OHCI 24h, GUIDHi, byte 0 2Eh OHCI 25h, GUIDHi, byte 1 2Fh OHCI 26h, GUIDHi, byte 2 30h OHCI 27h, GUIDHi, byte 3 31h OHCI 28h, GUIDLo, byte 0 32h OHCI 29h, GUIDLo, byte 1 33h OHCI 2Ah, GUIDLo, byte 2 34h OHCI 2Bh, GUIDLo, byte 3 35h Checksum (Reserved--no bit loaded) 36h PCI F5h, Link_Enh, byte 1, bits 7, 6, 5, 4 37h PCI F0h, PCI miscellaneous, byte 0, bits 7, 5, 4, 2, 1, 0 38h PCI F1h, PCI miscellaneous, byte 1, bits 7-0 39h Reserved 3Ah Reserved (CardBus CIS pointer) 3Bh Reserved 3Ch PCI ECh, PCI PHY control, bits 7, 3, 1 3Dh Flash media core function indicator (02h) 3Eh Number of bytes (05h) 3Fh PCI 2Ch, subsystem vendor ID, byte 0 40h PCI 2Dh, subsystem vendor ID, byte 1 41h PCI 2Eh, subsystem ID, byte 0 42h PCI 2Fh, subsystem ID, byte 1 43h PCI 4Ch, general control, bits 7-4, 2-0 44h SD host controller function indicator (03h) 45h Number of bytes (0Bh) 46h PCI 2Ch, subsystem vendor ID, byte 0 47h PCI 2Dh, subsystem vendor ID, byte 1 48h PCI 2Eh, subsystem ID, byte 0 49h PCI 2Fh, subsystem ID, byte 1 4Ah PCI 88h, general control bits 7-3, 1, 0 4Bh PCI 94h, slot 0 3.3 V maximum current 4Ch Reserved (PCI 98h, slot 1 3.3 V maximum current) 4Dh Reserved (PCI 9Ch, slot 2 3.3 V maximum current) September 2005 SCPS110 57 Principles of Operation Table 3-9. EEPROM Loading Map (Continued) SERIAL ROM OFFSET BYTE DESCRIPTION 4Eh Reserved (PCI A0h, slot 3 3.3 V maximum current) 4Fh Reserved (PCI A4h, slot 4 3.3 V maximum current) 50h Reserved (PCI A8h, slot 5 3.3 V maximum current) 51h PCI Smart Card function indicator (04h) 3.7 52h Number of bytes (0Eh) 53h PCI 09h, class code, byte 0 54h PCI 0Ah, class code, byte 1 55h PCI 0Bh, class code, byte 2 56h PCI 2Ch, subsystem vendor ID, byte 0 57h PCI 2Dh, subsystem vendor ID, byte 1 58h PCI 2Eh, subsystem ID, byte 0 59h PCI 2Fh, subsystem ID, byte 1 5Ah PCI 4Ch, general control bits 7-4 5Bh PCI 58h, Smart Card configuration 1, byte 0, bits 4, 0 5Ch PCI 59h, Smart Card configuration 1, byte 1, bits 4, 0 5Dh PCI 5Ah, Smart Card configuration 1, byte 2, bits 4, 0 5Eh PCI 5Bh, Smart Card configuration 1, byte 3, bits 7-4, 0 5Fh PCI 5Ch, Smart Card configuration 2, byte 0 60h PCI 5Dh, Smart Card configuration 2, byte 1 61h End-of-list indicator (80h) Programmable Interrupt Subsystem Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic nature of PC Cards and the abundance of PC Card I/O applications require substantial interrupt support from the PCIxx12 controller. The controller provides several interrupt signaling schemes to accommodate the needs of a variety of platforms. The different mechanisms for dealing with interrupts in this controller are based on various specifications and industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the CardBus socket register set provides interrupt control for the CardBus PC Card functions. The controller is, therefore, backward compatible with existing interrupt control register definitions, and new registers have been defined where required. The controller detects PC Card interrupts and events at the PC Card interface and notifies the host controller using one of several interrupt signaling protocols. To simplify the discussion of interrupts in the controller, PC Card interrupts are classified either as card status change (CSC) or as functional interrupts. The method by which any type of interrupt is communicated to the host interrupt controller varies from system to system. The controller offers system designers the choice of using parallel PCI interrupt signaling, parallel ISA-type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. It is possible to use the parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs, as detailed in the sections that follow. All interrupt signaling is provided through the seven multifunction terminals, MFUNC0-MFUNC6. 3.7.1 PC Card Functional and Card Status Change Interrupts PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by 16-bit I/O PC Cards and by CardBus PC Cards. 58 SCPS110 September 2005 Principles of Operation Card status change (CSC)-type interrupts are defined as events at the PC Card interface that are detected by the PCIxx12 controller and may warrant notification of host card and socket services software for service. CSC events include both card insertion and removal from PC Card sockets, as well as transitions of certain PC Card signals. Table 3-10 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and functional interrupt sources are dependent on the type of card inserted in the PC Card socket. The four types of cards that can be inserted into any PC Card socket are: * * * * 16-bit memory card 16-bit I/O card CardBus cards UltraMedia card Table 3-10. Interrupt Mask and Flag Registers CARD TYPE EVENT MASK FLAG Battery conditions (BVD1, BVD2) ExCA offset 05h/805h bits 1 and 0 ExCA offset 04h/804h bits 1 and 0 Wait states (READY) ExCA offset 05h/805h bit 2 ExCA offset 04h/804h bit 2 16-bit I/O Change in card status (STSCHG) ExCA offset 05h/805h bit 0 ExCA offset 04h/804h bit 0 16-bit I/O Interrupt request (IREQ) Always enabled PCI configuration offset 91h bit 0 Power cycle complete ExCA offset 05h/805h bit 3 ExCA offset 04h/804h bit 3 Change in card status (CSTSCHG) Socket mask bit 0 Socket event bit 0 Interrupt request (CINT) Always enabled PCI configuration offset 91h bit 0 Power cycle complete Socket mask bit 3 Socket event bit 3 Card insertion or removal Socket mask bits 2 and 1 Socket event bits 2 and 1 16-bit memory All 16-bit PC Cards/Smart Card adaptors CardBus Functional interrupt events are valid only for CardBus and 16-bit I/O cards; that is, the functional interrupts are not valid for 16-bit memory cards. Furthermore, card insertion and removal-type CSC interrupts are independent of the card type. Table 3-11. PC Card Interrupt Events and Description CARD TYPE EVENT TYPE SIGNAL DESCRIPTION CSTSCHG // BVD1(STSCHG) A transition on BVD1 indicates a change in the PC Card battery conditions. CAUDIO // BVD2(SPKR) A transition on BVD2 indicates a change in the PC Card battery conditions. Battery conditions (BVD1, BVD2) CSC Wait states (READY) CSC CINT // READY(IREQ) 16-bit I/O Change in card status (STSCHG) CSC CSTSCHG // BVD1(STSCHG) 16-bit I/O Interrupt request (IREQ) Functional CINT // READY(IREQ) The assertion of IREQ indicates an interrupt request from the PC Card. Change in card status (CSTSCHG) CSC CSTSCHG // BVD1(STSCHG) The assertion of CSTSCHG indicates a status change on the PC Card. Interrupt request (CINT) Functional CINT // READY(IREQ) The assertion of CINT indicates an interrupt request from the PC Card. Card insertion or removal CSC CCD1 // CD1, CCD2 // CD2 A transition on either CD1//CCD1 or CD2//CCD2 indicates an insertion or removal of a 16-bit or CardBus PC Card. Power cycle complete CSC N/A An interrupt is generated when a PC Card power-up cycle has completed. 16-bit memory CardBus All PC Cards/ Smart Card adaptors September 2005 A transition on READY indicates a change in the ability of the memory PC Card to accept or provide data. The assertion of STSCHG indicates a status change on the PC Card. SCPS110 59 Principles of Operation The naming convention for PC Card signals describes the function for CardBus, 16-bit memory, and 16-bit I/O cards. For example, CINT//READY(IREQ) includes CINT for CardBus cards, READY for 16-bit memory cards, and IREQ for 16-bit I/O cards. The CardBus signal name is first. The 16-bit memory card signal name follows after a double slash (//) with the 16-bit I/O card signal name second, enclosed in parentheses. The 1997 PC Card Standard describes the power-up sequence that must be followed by the controller when an insertion event occurs and the host requests that the socket VCC and VPP be powered. Upon completion of this power-up sequence, the PCIxx12 interrupt scheme can be used to notify the host system (see Table 3-11), denoted by the power cycle complete event. This interrupt source is considered a PCIxx12 internal event, because it depends on the completion of applying power to the socket rather than on a signal change at the PC Card interface. 3.7.2 Interrupt Masks and Flags Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 3-11 by setting the appropriate bits in the PCIxx12 controller. By individually masking the interrupt sources listed, software can control those events that cause a PCIxx12 interrupt. Host software has some control over the system interrupt the controller asserts by programming the appropriate routing registers. The controller allows host software to route PC Card CSC and PC Card functional interrupts to separate system interrupts. Interrupt routing somewhat specific to the interrupt signaling method used is discussed in more detail in the following sections. When an interrupt is signaled by the controller, the interrupt service routine must determine which of the events listed in Table 3-10 caused the interrupt. Internal registers in the controller provide flags that report the source of an interrupt. By reading these status bits, the interrupt service routine can determine the action to be taken. Table 3-10 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts. Notice that there is not a mask bit to stop the controller from passing PC Card functional interrupts through to the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there must never be a card interrupt that does not require service after proper initialization. Table 3-10 lists the various methods of clearing the interrupt flag bits. The flag bits in the ExCA registers (16-bit PC Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1b to the flag bit to clear and the other is by reading the flag bit register. The selection of flag bit clearing methods is made by bit 2 (IFCMODE) in the ExCA global control register (ExCA offset 1Eh/81Eh, see Section 5.20), and defaults to the flag-cleared-on-read method. The CardBus-related interrupt flags can be cleared by an explicit write of 1b to the interrupt flag in the socket event register (see Section 6.1). Although some of the functionality is shared between the CardBus registers and the ExCA registers, software must not program the chip through both register sets when a CardBus card is functioning. 3.7.3 Using Parallel IRQ Interrupts The seven multifunction terminals, MFUNC6-MFUNC0, implemented in the PCIxx12 controller can be routed to obtain a subset of the ISA IRQs. The IRQ choices provide ultimate flexibility in PC Card host interruptions. To use the parallel ISA-type IRQ interrupt signaling, software must program the device control register (PCI offset 92h, see Section 4.38), to select the parallel IRQ signaling scheme. See Section 4.35, Multifunction Routing Status Register, for details on configuring the multifunction terminals. A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA, to signal CSC events. This requirement is dictated by certain card and socket-services software. The INTA requirement calls for routing the MFUNC0 terminal for INTA signaling. The INTRTIE bit is used, in this case, to route socket interrupt events to INTA. This leaves (at a maximum) six different IRQs to support legacy 16-bit PC Card functions. 60 SCPS110 September 2005 Principles of Operation As an example, suppose the six IRQs used by legacy PC Card applications are IRQ3, IRQ4, IRQ5, IRQ9, IRQ10, and IRQ15. The multifunction routing status register must be programmed to a value of 0A9F 5432h. This value routes the MFUNC0 terminal to INTA signaling and routes the remaining terminals as illustrated in Figure 3-12. Not shown is that INTA must also be routed to the programmable interrupt controller (PIC), or to some circuitry that provides parallel PCI interrupts to the host. PCIxx12 MFUNC1 IRQ3 MFUNC2 IRQ4 MFUNC3 IRQ5 MFUNC4 IRQ15 MFUNC5 IRQ9 MFUNC6 IRQ10 PIC Figure 3-12. IRQ Implementation Power-on software is responsible for programming the multifunction routing status register to reflect the IRQ configuration of a system implementing the controller. The multifunction routing status register is a global register that is shared between the four PCIxx12 functions. See Section 4.35, Multifunction Routing Status Register, for details on configuring the multifunction terminals. The parallel ISA-type IRQ signaling from the MFUNC6-MFUNC0 terminals is compatible with the input signal requirements of the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs. Design constraints may demand more MFUNC6-MFUNC0 IRQ terminals than the controller makes available. 3.7.4 Using Parallel PCI Interrupts Parallel PCI interrupts are available when exclusively in parallel PCI interrupt/parallel ISA IRQ signaling mode, and when only IRQs are serialized with the IRQSER protocol. The INTA, INTB, INTC, and INTD can be routed to MFUNC terminals (MFUNC0, MFUNC1, MFUNC2, and MFUNC4). If bit 29 (INTRTIE) is set in the system control register (PCI offset 80h, see Section 4.29), then INTA and INTB are tied internally. When the TIEALL bit is set, all functions return a value of 01h on reads from the interrupt pin register for both parallel and serial PCI interrupts. The INTRTIE and TIEALL bits affect the read-only value provided through accesses to the interrupt pin register (PCI offset 3Dh, see Section 4.24). Table 3-12 summarizes the interrupt signaling modes. Table 3-12. Interrupt Pin Register Cross Reference INTRTIE Bit TIEALL Bit INTPIN Function 0 (CardBus) INTPIN Function 1 (1394 OHCI) 0 0 0x01 (INTA) 0x02 (INTB) 1 0 0x01 (INTA) 0x01 (INTA) X 1 0x01 (INTA) 0x01 (INTA) INTPIN Function 2 (Flash Media) INTPIN Function 3 (SD Host) INTPIN Function 4 (Smart Card) Determined by bits 6-5 (INT_SEL field) in flash media general control register (see Section 11.21) Determined by bits 6-5 (INT_SEL field) in SD host general control register (see Section 12.22) Determined by bits 6-5 (INT_SEL field) in Smart Card general control register (see Section 13.22) 0x01 (INTA) 0x01 (INTA) 0x01 (INTA) 3.7.5 Using Serialized IRQSER Interrupts The serialized interrupt protocol implemented in the PCIxx12 controller uses a single terminal to communicate all interrupt status information to the host controller. The protocol defines a serial packet consisting of a start cycle, multiple interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI clock. The packet data describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INTA, INTB, INTC, and INTD. For details on the IRQSER protocol, refer to the document Serialized IRQ Support for PCI Systems. September 2005 SCPS110 61 Principles of Operation 3.7.6 SMI Support in the PCIxx12 Controller The PCIxx12 controller provides a mechanism for interrupting the system when power changes have been made to the PC Card socket interfaces. The interrupt mechanism is designed to fit into a system maintenance interrupt (SMI) scheme. SMI interrupts are generated by the controller, when enabled, after either a write cycle to the socket control register (CB offset 10h, see Section 6.5) of the CardBus register set, or the ExCA power control register (ExCA offset 02h/802h, see Section 5.3) causes a power cycle change sequence to be sent on the power switch interface. The SMI control is programmed through three bits in the system control register (PCI offset 80h, see Section 4.29). These bits are SMIROUTE (bit 26), SMISTATUS (bit 25), and SMIENB (bit 24). Table 3-13 describes the SMI control bits function. Table 3-13. SMI Control BIT NAME FUNCTION SMIROUTE This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2. SMISTAT This socket-dependent bit is set when an SMI interrupt is pending. This status flag is cleared by writing back a 1b. SMIENB When set, SMI interrupt generation is enabled. If CSC SMI interrupts are selected, then the SMI interrupt is sent as the CSC on a per-socket basis. The CSC interrupt can be either level or edge mode, depending upon the CSCMODE bit in the ExCA global control register (ExCA offset 1Eh/81Eh, see Section 5.20). If IRQ2 is selected by SMIROUTE, then the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ/Data slot. In a parallel ISA IRQ system, the support for an active low IRQ2 is provided only if IRQ2 is routed to either MFUNC3 or MFUNC6 through the multifunction routing status register (PCI offset 8Ch, see Section 4.35). 3.8 Power-Management Overview In addition to the low-power CMOS technology process used for the PCIxx12 controller, various features are designed into the controller to allow implementation of popular power-saving techniques. These features and techniques are as follows: * * * * * * * * 62 Clock run protocol Cardbus PC Card power management 16-bit PC Card power management Suspend mode Ring indicate PCI power management Cardbus bridge power management ACPI support SCPS110 September 2005 Principles of Operation PCI Bus EEPROM SD/MMC MS/MSPRO SM/xD PCIxx12 SD/MMC 1394a Socket Power Switch Smart Card PC Card Power Switch Power Switch Power Switch The system connection to GRST is implementation-specific. GRST must be asserted on initial power up of the PCIxx12 controller. PRST must be asserted for subsequent warm resets. Figure 3-13. System Diagram Implementing CardBus Device Class Power Management 3.8.1 1394 Power Management (Function 1) The PCIxx12 controller complies with PCI Bus Power Management Interface Specification. The controller supports the D0 (uninitialized), D0 (active), D1, D2, and D3 power states as defined by the power-management definition in the 1394 Open Host Controller Interface Specification, Appendix A.4 and PCI Bus Power Management Specification. PME is supported to provide notification of wake events. Per Section A.4.2, the 1394 OHCI sets PMCSR.PME_STS in the D0 state due to unmasked interrupt events. In previous OHCI implementations, unmasked interrupt events were interpreted as (IntEvent.n && IntMask.n && IntMask.masterIntEnable), where n represents a specific interrupt event. Based on feedback from Microsoft this implementation may cause problems with the existing Windows power-management arcitecture as a PME and an interrupt could be simultaneously signaled on a transition from the D1 to D0 state where interrupts were enabled to generate wake events. If bit 10 (ignore_mstrIntEna_for_pme) in the PCI miscellaneous configuration register (OHCI offset F0h, see Section 7.23) is set, then the controller implements the preferred behavior as (IntEvent.n && IntMask.n). Otherwise, the controller implements the preferred behavior as (IntEvent.n && IntMask.n && IntMask.masterIntEnable). In addition, when the ignore_mstrIntEna_for_pme bit is set, it causes bit 26 of the OHCI vendor ID register (OHCI offset 40h, see Section 8.15) to read 1b, otherwise, bit 26 reads 0b. An open drain buffer is used for PME. If PME is enabled in the power-management control/status register (PCI offset A4h, see Section 4.43), then insertion of a PC Card causes the controller to assert PME, which wakes the system from a low power state (D3, D2, or D1). The OS services PME and takes the PCIxx12 controller to the D0 state. 3.8.2 Integrated Low-Dropout Voltage Regulator (LDO-VR) The PCIxx12 controller requires 1.5-V core voltage. The core power can be supplied by the controller itself using the internal LDO-VR. The core power can be alternatively supplied by an external power supply through the VR_PORT terminal. Table 3-14 lists the requirements for both the internal core power supply and the external core power supply. September 2005 SCPS110 63 Principles of Operation Table 3-14. Requirements for Internal/External 1.5-V Core Power Supply SUPPLY VCC VR_EN VR_PORT NOTE Internal 3.3 V GND 1.5-V output Internal 1.5-V LDO-VR is enabled. A 1.0-F bypass capacitor is required on the VR_PORT terminal for decoupling. This output is not for external use. External 3.3 V VCC 1.5-V input Internal 1.5-V LDO-VR is disabled. An external 1.5-V power supply, of minimum 50-mA capacity, is required. A 0.1-F bypass capacitor on the VR_PORT terminal is required. 3.8.3 Clock Run Protocol The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCIxx12 controller. CLKRUN signaling is provided through the MFUNC6 terminal. Since some chip sets do not implement CLKRUN, this is not always available to the system designer, and alternate power-saving features are provided. For details on the CLKRUN protocol see the PCI Mobile Design Guide. The controller does not permit the central resource to stop the PCI clock under any of the following conditions: * Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.29) is set. * The 16-bit PC Card resource manager is busy. * The PCIxx12 CardBus master state machine is busy. A cycle may be in progress on CardBus. * The PCIxx12 master is busy. There may be posted data from CardBus, 1394, flash media core, SD host core, or Smart Card core to PCI in the controller or DMA is active. * Interrupts are pending from CardBus, 1394, flash media core, SD host core, or Smart Card core * The CardBus CCLK for the socket has not been stopped by the PCIxx12 CCLKRUN manager. * Bit 0 (KEEP_PCLK) in the miscellaneous configuration register (PCI offset F0h, see Section 7.23) is set. * The 1394 resource manager is busy. * The PCIxx12 1394 master state machine is busy. A cycle may be in progress on 1394. * PC Card interrogation is in progress. * Flash media or Smart Card insertion/removal processing * The 1394 bus is not idle. * Smart card DES request or decryption in progress The controller restarts the PCI clock using the CLKRUN protocol under any of the following conditions: * * * * * * * * * A 16-bit PC Card IREQ or a CardBus CINT has been asserted by either card. A CardBus CBWAKE (CSTSCHG) or 16-bit PC Card STSCHG/RI event occurs in the socket. A CardBus attempts to start the CCLK using CCLKRUN. A CardBus card arbitrates for the CardBus bus using CREQ. A 1394 device changes the status of the twisted pair lines from idle to active. Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.29) is set. Data is in any of the FIFOs (receive or transmit). The master state machine is busy. There are pending interrupts from CardBus, 1394, flash media core, SD host core, or Smart Card core. 3.8.4 CardBus PC Card Power Management The PCIxx12 controller implements its own card power-management engine that can turn off the CCLK to a socket when there is no activity to the CardBus PC Card. The PCI clock-run protocol is followed on the CardBus CCLKRUN interface to control this clock management. 64 SCPS110 September 2005 Principles of Operation 3.8.5 16-Bit PC Card Power Management The COE bit (bit 7) of the ExCA power control register (ExCA offset 02h/802h, see Section 5.3) and PWRDWN bit (bit 0) of the ExCA global control register (ExCA offset 1Eh/81Eh, see Section 5.20) are provided for 16-bit PC Card power management. The COE bit places the card interface in a high-impedance state to save power. The power savings when using this feature are minimal. The COE bit resets the PC Card when used, and the PWRDWN bit does not. Furthermore, the PWRDWN bit is an automatic COE, that is, the PWRDWN performs the COE function when there is no card activity. NOTE: The 16-bit PC Card must implement the proper pullup resistors for the COE and PWRDWN modes. 3.8.6 Suspend Mode The SUSPEND signal, provided for backward compatibility, gates the PRST (PCI reset) signal and the GRST (global reset) signal from the PCIxx12 controller. Besides gating PRST and GRST, SUSPEND also gates PCLK inside the controller in order to minimize power consumption. It should also be noted that asynchronous signals, such as card status change interrupts and RI_OUT, can be passed to the host system without a PCI clock. However, if card status change interrupts are routed over the serial interrupt stream, then the PCI clock must be restarted in order to pass the interrupt, because neither the internal oscillator nor an external clock is routed to the serial-interrupt state machine. Figure 3-14 is a signal diagram of the suspend function. RESET GNT SUSPEND PCLK External Terminals Internal Signals RESETIN SUSPENDIN PCLKIN Figure 3-14. Signal Diagram of Suspend Function September 2005 SCPS110 65 Principles of Operation 3.8.7 Requirements for Suspend Mode The suspend mode prevents the clearing of all register contents on the assertion of reset (PRST or GRST) which would require the reconfiguration of the PCIxx12 controller by software. Asserting the SUSPEND signal places the PCI outputs of the controller in a high-impedance state and gates the PCLK signal internally to the controller unless a PCI transaction is currently in process (GNT is asserted). It is important that the PCI bus not be parked on the controller when SUSPEND is asserted because the outputs are in a high-impedance state. The GPIOs, MFUNC signals, and RI_OUT signal are all active during SUSPEND, unless they are disabled in the appropriate PCIxx12 registers. 3.8.8 Ring Indicate The RI_OUT output is an important feature in power management, allowing a system to go into a suspended mode and wake-up on modem rings and other card events. TI-designed flexibility permits this signal to fit wide platform requirements. RI_OUT on the PCIxx12 controller can be asserted under any of the following conditions: * A 16-bit PC Card modem in a powered socket asserts RI to indicate to the system the presence of an incoming call. * A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake-up. * A powered CardBus card asserts CSTSCHG from the insertion/removal of cards or change in battery voltage levels. Figure 3-15 shows various enable bits for the PCIxx12 RI_OUT function; however, it does not show the masking of CSC events. See Table 3-10 for a detailed description of CSC interrupt masks and flags. RI_OUT Function CSTSMASK PC Card Socket A RIENB CSC Card I/F RINGEN RI_OUT RI CDRESUME CSC Figure 3-15. RI_OUT Functional Diagram RI from the 16-bit PC Card interface is masked by bit 7 (RINGEN) in the ExCA interrupt and general control register (ExCA offset 03h/803h, see Section 5.4). This is programmed on a per-socket basis and is only applicable when a 16-bit card is powered in the socket. The CBWAKE signaling to RI_OUT is enabled through the same mask as the CSC event for CSTSCHG. The mask bit (bit 0, CSTSMASK) is programmed through the socket mask register (CB offset 04h, see Section 6.2) in the CardBus socket registers. RI_OUT can be routed through any of three different pins, RI_OUT/PME, MFUNC2, or MFUNC4. The RI_OUT function is enabled by setting bit 7 (RIENB) in the card control register (PCI offset 91h, see Section 4.37). The PME function is enabled by setting bit 8 (PME_ENABLE) in the power-management control/status register (PCI offset A4h, see Section 4.43). When bit 0 (RIMUX) in the system control register (PCI offset 80h, see Section 4.29) is set to 0b, both the RI_OUT function and the PME function are routed to the RI_OUT/PME terminal. Therefore, in a system using both the RI_OUT function and the PME function, RIMUX must be set to 1b and RI_OUT must be routed to either MFUNC2 or MFUNC4. 66 SCPS110 September 2005 Principles of Operation 3.8.9 PCI Power Management 3.8.9.1 CardBus (Function 0) Power Management The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges establishes the infrastructure required to let the operating system control the power of PCI functions. This is accomplished by defining a standard PCI interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of seven power-management states, resulting in varying levels of power savings. The seven power-management states of PCI functions are: * * * * * * * D0-uninitialized - Before controller configuration, controller not fully functional D0-active - Fully functional state D1 - Low-power state D2 - Low-power state D3hot - Low-power state. Transition state before D3cold D3cold - PME signal-generation capable. Main power is removed and VAUX is available. D3off - No power and completely nonfunctional NOTE 1: In the D0-uninitialized state, the PCIxx12 controller does not generate PME and/or interrupts. When bits 0 (IO_EN) and 1 (MEM_EN) of the command register (PCI offset 04h, see Section 4.4) are both set, the PCIxx12 controller switches the state to D0-active. Transition from D3cold to the D0-uninitialized state happens at the deassertion of PRST. The assertion of GRST forces the controller to the D0-uninitialized state immediately. NOTE 2: The PWR_STATE bits (bits 1-0) of the power-management control/status register (PCI offset A4h, see Section 4.43) only code for four power states, D0, D1, D2, and D3hot. The differences between the three D3 states is invisible to the software because the controller is not accessible in the D3cold or D3off state. Similarly, bus power states of the PCI bus are B0-B3. The bus power states B0-B3 are derived from the device power state of the originating bridge device. For the operating system (OS) to manage the controller power states on the PCI bus, the PCI function must support four power-management operations. These operations are: * * * * Capabilities reporting Power status reporting Setting the power state System wake-up The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of capabilities in addition to the standard PCI capabilities is indicated by a 1b in bit 4 (CAPLIST) of the status register (PCI offset 06h, see Section 4.5). The capabilities pointer provides access to the first item in the linked list of capabilities. For the PCIxx12 controller, a CardBus bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an offset of 14h. The first byte of each capability register block is required to be a unique ID of that capability. PCI power management has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there are no more items in the list, then the next item pointer must be set to 0. The registers following the next item pointer are specific to the capability of the function. The PCI power-management capability implements the register block outlined in Table 3-15. Table 3-15. Power-Management Registers REGISTER NAME Power-management capabilities Data Power-management control/status register bridge support extensions OFFSET Next item pointer Capability ID Power-management control/status (CSR) A0h A4h The power-management capabilities register (PCI offset A2h, see Section 4.42) provides information on the capabilities of the function related to power management. The power-management control/status register (PCI offset A4h, see Section 4.43) enables control of power-management states and enables/monitors power-management events. The data register is an optional register that can provide dynamic data. September 2005 SCPS110 67 Principles of Operation For more information on PCI power management, see the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges. 3.8.9.2 OHCI 1394 (Function 1) Power Management The PCIxx12 controller complies with the PCI Bus Power Management Interface Specification. The controller supports the D0 (unitialized), D0 (active), D1, D2, and D3 power states as defined by the power-management definition in the 1394 Open Host Controller Interface Specification, Appendix A4. Table 3-16. Function 1 Power-Management Registers REGISTER NAME Power-management capabilities Data Power-management control/status register bridge support extensions 3.8.9.3 OFFSET Next item pointer Capability ID Power-management control/status (CSR) 44h 48h Flash Media (Function 2) Power Management The PCI Bus Power Management Interface Specification is applicable for the flash media dedicated sockets. This function supports the D0 and D3 power states. Table 3-17. Function 2 Power-Management Registers REGISTER NAME Power-management capabilities Data Power-management control/status register bridge support extensions 3.8.9.4 OFFSET Next item pointer Capability ID Power-management control/status (CSR) 44h 48h SD Host (Function 3) Power Management The PCI Bus Power Management Interface Specification is applicable for the SD host dedicated sockets. This function supports the D0 and D3 power states. Table 3-18. Function 3 Power-Management Registers REGISTER NAME Power-management capabilities Data Power-management control/status register bridge support extensions 3.8.9.5 OFFSET Next item pointer Capability ID Power-management control/status (CSR) 80h 84h Smart Card (Function 4) Power Management The PCI Bus Power Management Interface Specification is applicable for the Smart Card dedicated sockets. This function supports the D0 and D3 power states. Table 3-19. Function 4 Power-Management Registers REGISTER NAME Power-management capabilities Data Power-management control/status register bridge support extensions 3.8.10 OFFSET Next item pointer Capability ID Power-management control/status (CSR) 44h 48h CardBus Bridge Power Management The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges was approved by PCMCIA in December of 1997. This specification follows the device and bus state definitions provided in the PCI Bus Power Management Interface Specification published by the PCI Special Interest Group (SIG). The main issue addressed in the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges is wake-up from D3hot or D3cold without losing wake-up context (also called PME context). The specific issues addressed by the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges for D3 wake-up are as follows: * 68 Preservation of device context. The specification states that a reset must occur during the transition from D3 to D0. Some method to preserve wake-up context must be implemented so that the reset does not clear the PME context registers. SCPS110 September 2005 Principles of Operation * Power source in D3cold if wake-up support is required from this state. The Texas Instruments PCIxx12 controller addresses these D3 wake-up issues in the following manner: * * 3.8.11 Two resets are provided to handle preservation of PME context bits: - Global reset (GRST) is used only on the initial boot up of the system after power up. It places the controller in its default state and requires BIOS to configure the controller before becoming fully functional. - PCI reset (PRST) has dual functionality based on whether PME is enabled or not. If PME is enabled, then PME context is preserved. If PME is not enabled, then PRST acts the same as a normal PCI reset. Please see the master list of PME context bits in Section 3.8.12. Power source in D3cold if wake-up support is required from this state. Since VCC is removed in D3cold, an auxiliary power source must be supplied to the PCIxx12 VCC terminals. Consult the PCI14xx Implementation Guide for D3 Wake-Up or the PCI Power Management Interface Specification for PCI to CardBus Bridges for further information. ACPI Support The Advanced Configuration and Power Interface (ACPI) Specification provides a mechanism that allows unique pieces of hardware to be described to the ACPI driver. The PCIxx12 controller offers a generic interface that is compliant with ACPI design rules. Two doublewords of general-purpose ACPI programming bits reside in PCIxx12 PCI configuration space at offset 88h. The programming model is broken into status and control functions. In compliance with ACPI, the top level event status and enable bits reside in the general-purpose event status register (PCI offset 88h, see Section 4.31) and general-purpose event enable register (PCI offset 89h, see Section 4.32). The status and enable bits are implemented as defined by ACPI and illustrated in Figure 3-16. Status Bit Event Input Enable Bit Event Output Figure 3-16. Block Diagram of a Status/Enable Cell The status and enable bits generate an event that allows the ACPI driver to call a control method associated with the pending status bit. The control method can then control the hardware by manipulating the hardware control bits or by investigating child status bits and calling their respective control methods. A hierarchical implementation would be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report events. For more information of ACPI, see the Advanced Configuration and Power Interface (ACPI) Specification. 3.8.12 Master List of PME Context Bits and Global Reset-Only Bits PME context bit means that the bit is cleared only by the assertion of GRST when the PME enable bit, bit 8 of the power-management control/status register (PCI offset A4h, see Section 4.43) is set. If PME is not enabled, then these bits are cleared when either PRST or GRST is asserted. The PME context bits (function 0) are: * * * * * Bridge control register (PCI offset 3Eh, see Section 4.25): bit 6 System control register (PCI offset 80h, see Section 4.29): bits 10-8 Power-management control/status register (PCI offset A4h, see Section 4.43): bit 15 ExCA power control register (ExCA 802h, see Section 5.3): bits 7, 5 (82365SL mode only), 7, 4, 3, 1, 0 ExCA interrupt and general control (ExCA 803h, see Section 5.4): bits 6, 5 September 2005 SCPS110 69 Principles of Operation * * * * * * * ExCA card status-change register (ExCA 804h, see Section 5.5): bits 3-0 ExCA card status-change interrupt configuration register (ExCA 805h, see Section 5.6): bits 3-0 ExCA card detect and general control register (ExCA 816h, see Section 5.19): bits 7, 6 Socket event register (CardBus offset 00h, see Section 6.1): bits 3-0 Socket mask register (CardBus offset 04h, see Section 6.2): bits 3-0 Socket present state register (CardBus offset 08h, see Section 6.3): bits 13-7, 5-1 Socket control register (CardBus offset 10h, see Section 6.5): bits 6-4, 2-0 Global reset-only bits, as the name implies, are cleared only by GRST. These bits are never cleared by PRST, regardless of the setting of the PME enable bit. The GRST signal is gated only by the SUSPEND signal. This means that assertion of SUSPEND blocks the GRST signal internally, thus preserving all register contents. Figure 3-13 is a diagram showing the application of GRST and PRST. The global reset-only bits (function 0) are: * * * * * * * * * * * * * * * * * * * * * * * * Status register (PCI offset 06h, see Section 4.5): bits 15-11, 8 Secondary status register (PCI offset 16h, see Section 4.14): bits 15-11, 8 Subsystem vendor ID register (PCI offset 40h, see Section 4.26): bits 15-0 Subsystem ID register (PCI offset 42h, see Section 4.27): bits 15-0 PC Card 16-bit I/F legacy-mode base-address register (PCI offset 44h, see Section 4.28): bits 31-0 System control register (PCI offset 80h, see Section 4.29): bits 31-24, 22-13, 11, 6-0 General control register (PCI offset 84h, see Section 4.30): bits 31-16, 10-0 General-purpose event status register (PCI offset 88h, see Section 4.31): bits 7, 6, 4-0 General-purpose event enable register (PCI offset 89h, see Section 4.32): bits 7, 6, 4-0 General-purpose output register (PCI offset 8Bh, see Section 4.34): bits 4-0 Multifunction routing register (PCI offset 8Ch, see Section 4.35): bits 31-0 Retry status register (PCI offset 90h, see Section 4.36): bits 7-5, 3, 1 Card control register (PCI offset 91h, see Section 4.37): bits 7, 2-0 Device control register (PCI offset 92h, see Section 4.38): bits 7-5, 3-0 Diagnostic register (PCI offset 93h, see Section 4.39): bits 7-0 Power-management capabilities register (PCI offset A2h, see Section 4.42): bit 15 Power-management CSR register (PCI offset A4h, see Section 4.43): bits 15, 8 Serial bus data register (PCI offset B0h, see Section 4.46): bits 7-0 Serial bus index register (PCI offset B1h, see Section 4.47): bits 7-0 Serial bus slave address register (PCI offset B2h, see Section 4.48): bits 7-0 Serial bus control/status register (PCI offset B3h, see Section 4.49): bits 7, 3-0 ExCA identification and revision register (ExCA 800h, see Section 5.1): bits 7-0 ExCA global control register (ExCA 81Eh, see Section 5.20): bits 2-0 CardBus socket power-management register (CardBus 20h, see Section 6.6): bits 25, 24 The global reset-only bit (function 1) is: * * * * * * * * * * * * * 70 Subsystem vendor ID register (PCI offset 2Ch, see Section 7.12): bits 15-0 Subsystem ID register (PCI offset 2Eh, see Section 7.12): bits 15-0 Minimum grant and maximum latency register (PCI offset 3Eh, see Section 7.16): bits 15-0 Power-management control and status register (PCI offset 48h, see Section 7.20): bits 15, 8, 1, 0 PHY control register (PCI offset ECh, see Section 7.22): bits 7, 4-0 Miscellaneous configuration register (PCI offset F0h, see Section 7.23): bits 15-7, 5-0 Link enhancement control register (PCI offset F4h, see Section 7.24): bits 15-12, 10, 8, 7, 2, 1 Subsystem access register (PCI offset F8h, see Section 7.25): bits 31-0 OHCI version register (OHCI offset 00h, see Section 8.1): bits 24 Bus options register (OHCI offset 20h, see Section 8.9): bits 15-12 GUID high register (OHCI offset 24h, see Section 8.10): bits 31-0 GUID low register (OHCI offset 28h, see Section 8.11): bits 31-0 Host controller control register (OHCI offset 50h/54h, see Section 8.16): bit 23 SCPS110 September 2005 Principles of Operation * * Link control register (OHCI offset E0h/E4h, see Section 8.31): bit 6 Link enhancement control set/clear register (TI Extension offset A88/A8Ch, see Section 9.4): bits 15-12, 10, 8, 7, 2, 1 The global reset-only (function 2) register bits: * * * * * * Subsystem vendor ID register (PCI offset 2Ch, see Section 11.9): bits 15-0 Subsystem ID register (PCI offset 2Eh, see Section 11.10): bits 15-0 Power-management control and status register (PCI offset 48h, see Section 11.18): bits 15, 8, 1, 0 General control register (PCI offset 4Ch, see Section 11.21): bits 7-4, 2-0 Subsystem access register (PCI offset 50h, see Section 11.22): bits 31-0 Diagnostic register (PCI offset 54h, see Section 11.23): bits 31-0 The global reset-only (function 3) register bits: * * * * * * * Subsystem vendor ID register (PCI offset 2Ch, see Section 12.9): bits 15-0 Subsystem ID register (PCI offset 2Eh, see Section 12.10): bits 15-0 Power-management control and status register (PCI offset 84h, see Section 12.19): bits 15, 8, 1, 0 General control register (PCI offset 88h, see Section 12.22): bits 6-3, 0 Subsystem access register (PCI offset 8Ch, see Section 12.23): bits 31-0 Diagnostic register (PCI offset 90h, see Section 12.24): bits 31-0 Slot 0 max current register (PCI offset 94h, see Section 12.25): bits 7-0 The global reset-only (function 4) register bits: * * * * * * * * Subsystem vendor ID register (PCI offset 2Ch, see Section 13.10): bits 15-0 Subsystem ID register (PCI offset 2Eh, see Section 13.11): bits 15-0 Power-management control and status register (PCI offset 48h, see Section 13.19): bits 15, 8, 1, 0 General control register (PCI offset 4Ch, see Section 13.22): bits 7-4, 0 Subsystem ID alias register (PCI offset 50h, see Section 13.23): bits 31-0 Class code alias register (PCI offset 54h, see Section 13.24): bits 31-0 Smart card configuration 1 register (PCI offset 58h, see Section 13.25): bits 31-0 Smart card configuration 2 register (PCI offset 5Ch, see Section 13.26): bits 31-0 September 2005 SCPS110 71 Principles of Operation 3.9 IEEE 1394 Application Information 3.9.1 PHY Port Cable Connection PCIxx12 400 k CPS Cable Power Pair 1 F TPBIAS 56 56 TPA+ Cable Pair A TPA- Cable Port TPB+ Cable Pair B TPB- 56 220 pF (see Note A) 56 5 k Outer Shield Termination NOTE A: IEEE Std 1394-1995 calls for a 250-pF capacitor, which is a nonstandard component value. A 220-pF capacitor is recommended. Figure 3-17. TP Cable Connections Outer Cable Shield 1 M 0.01 F 0.001 F Chassis Ground Figure 3-18. Typical Compliant DC Isolated Outer Shield Termination 72 SCPS110 September 2005 Principles of Operation Outer Cable Shield Chassis Ground Figure 3-19. Non-DC Isolated Outer Shield Termination 3.9.2 Crystal Selection The PCIxx12 controller is designed to use an external 24.576-MHz crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit. This oscillator in turn drives a PLL circuit that generates the various clocks required for transmission and resynchronization of data at the S100 through S400 media data rates. A variation of less than 100 ppm from nominal for the media data rates is required by IEEE Std 1394-1995. Adjacent PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHY devices must be able to compensate for this difference over the maximum packet length. Large clock variations may cause resynchronization overflows or underflows, resulting in corrupted packet data. The following are some typical specifications for crystals used with the PHYs from TI in order to achieve the required frequency accuracy and stability: * Crystal mode of operation: Fundamental * Frequency tolerance @ 25C: Total frequency variation for the complete circuit is 100 ppm. A crystal with 30 ppm frequency tolerance is recommended for adequate margin. * Frequency stability (over temperature and age): A crystal with 30 ppm frequency stability is recommended for adequate margin. NOTE: The total frequency variation must be kept below 100 ppm from nominal with some allowance for error introduced by board and device variations. Trade-offs between frequency tolerance and stability may be made as long as the total frequency variation is less than 100 ppm. For example, the frequency tolerance of the crystal may be specified at 50 ppm and the temperature tolerance may be specified at 30 ppm to give a total of 80 ppm possible variation due to the crystal alone. Crystal aging also contributes to the frequency variation. * Load capacitance: For parallel resonant mode crystal circuits, the frequency of oscillation is dependent upon the load capacitance specified for the crystal. Total load capacitance (CL) is a function of not only the discrete load capacitors, but also board layout and circuit. It is recommended that load capacitors with a maximum of 5% tolerance be used. For example, load capacitors (C9 and C10 in Figure 3-20) of 16 pF each were appropriate for the layout of the PCIxx12 evaluation module (EVM), which uses a crystal specified for 12-pF loading. The load specified for the crystal includes the load capacitors (C9 and C10), the loading of the PHY pins (CPHY), and the loading of the board itself (CBD). The value of CPHY is typically about 1 pF, and CBD is typically 0.8 pF per centimeter of board etch; a typical board can have 3 pF to 6 pF or more. The load capacitors C9 and C10 combine as capacitors in series so that the total load capacitance is: C L + C9 C10 ) C PHY ) C BD C9 ) C10 September 2005 SCPS110 73 Principles of Operation C9 X1 X1 24.576 MHz IS CPHY + CBD X0 C10 Figure 3-20. Load Capacitance for the PCIxx12 PHY The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency, minimizing noise introduced into the PHY phase-lock loop, and minimizing any emissions from the circuit. The crystal and two load capacitors must be considered as a unit during layout. The crystal and the load capacitors must be placed as close as possible to one another while minimizing the loop area created by the combination of the three components. Varying the size of the capacitors may help in this. Minimizing the loop area minimizes the effect of the resonant current (Is) that flows in this resonant circuit. This layout unit (crystal and load capacitors) must then be placed as close as possible to the PHY X1 and X0 terminals to minimize etch lengths, as shown in Figure 3-21. C9 C10 X1 For more details on crystal selection, see application report SLLA051 available from the TI website: http://www.ti.com/sc/1394. Figure 3-21. Recommended Crystal and Capacitor Layout 3.9.3 Bus Reset In the PCIxx12 controller, the initiate bus reset (IBR) bit may be set to 1b in order to initiate a bus reset and initialization sequence. The IBR bit is located in PHY register 1, along with the root-holdoff bit (RHB) and Gap_Count field, as required by IEEE Std 1394a-2000. Therefore, whenever the IBR bit is written, the RHB and Gap_Count are also written. The RHB and Gap_Count may also be updated by PHY-config packets. The PCIxx12 controller is IEEE 1394a-2000 compliant, and therefore both the reception and transmission of PHY-config packets cause the RHB and Gap_Count to be loaded, unlike older IEEE 1394-1995 compliant PHY devices which decode only received PHY-config packets. The gap-count is set to the maximum value of 63 after 2 consecutive bus resets without an intervening write to the Gap_Count, either by a write to PHY register 1 or by a PHY-config packet. This mechanism allows a PHY-config packet to be transmitted and then a bus reset initiated so as to verify that all nodes on the bus have updated their RHBs and Gap_Count values, without having the Gap_Count set back to 63 by the bus reset. The subsequent connection of a new node to the bus, which initiates a bus reset, then causes the Gap_Count of each node to be set to 63. Note, however, that if a subsequent bus reset is instead initiated by a write to register 1 to set the IBR bit, all other nodes on the bus have their Gap_Count values set to 63, while this node Gap_Count remains set to the value just loaded by the write to PHY register 1. Therefore, in order to maintain consistent gap-counts throughout the bus, the following rules apply to the use of the IBR bit, RHB, and Gap_Count in PHY register 1: 74 SCPS110 September 2005 Principles of Operation * Following the transmission of a PHY-config packet, a bus reset must be initiated in order to verify that all nodes have correctly updated their RHBs and Gap_Count values and to ensure that a subsequent new connection to the bus causes the Gap_Count to be set to 63 on all nodes in the bus. If this bus reset is initiated by setting the IBR bit to 1b, then the RHB and Gap_Count field must also be loaded with the correct values consistent with the just transmitted PHY-config packet. In the PCIxx12 controller, the RHB and Gap_Count are updated to their correct values upon the transmission of the PHY-config packet, so these values may first be read from register 1 and then rewritten. * Other than to initiate the bus reset, which must follow the transmission of a PHY-config packet, whenever the IBR bit is set to 1b in order to initiate a bus reset, the Gap_Count value must also be set to 63 so as to be consistent with other nodes on the bus, and the RHB must be maintained with its current value. * The PHY register 1 must not be written to except to set the IBR bit. The RHB and Gap_Count must not be written without also setting the IBR bit to 1b. An alternative and preferred method is for software to use the initiate short bus reset (ISBR) in PHY register 5 since it does not have any side effects on the gap count. September 2005 SCPS110 75 PC Card Controller Programming Model 4 PC Card Controller Programming Model This chapter describes the PCIxx12 PCI configuration registers that make up the 256-byte PCI configuration header for each PCIxx12 function. There are some bits which affect more than function 0, but which, in order to work properly, must be accessed only through function 0. These are called global bits. Registers containing one or more global bits are denoted by in Table 4-2. Any bit followed by a is not cleared by the assertion of PRST (see CardBus Bridge Power Management, Section 3.8.10, for more details) if PME is enabled (PCI offset A4h, bit 8). In this case, these bits are cleared only by GRST. If PME is not enabled, then these bits are cleared by GRST or PRST. These bits are sometimes referred to as PME context bits and are implemented to allow PME context to be preserved during the transition from D3hot or D3cold to D0. If a bit is followed by a , then this bit is cleared only by GRST in all cases (not conditional on PME being enabled). These bits are intended to maintain device context such as interrupt routing and MFUNC programming during warm resets. A bit description table, typically included when the register contains bits of more than one type or purpose, indicates bit field names, a detailed field description, and field access tags which appear in the type column. Table 4-1 describes the field access tags. Table 4-1. Bit Field Access Tag Descriptions 4.1 ACCESS TAG NAME R Read Field can be read by software. W Write Field can be written by software to any value. S Set C Clear U Update MEANING Field can be set by a write of 1b. Writes of 0b have no effect. Field can be cleared by a write of 1b. Writes of 0b have no effect. Field can be autonomously updated by the PCIxx12 controller. PCI Configuration Register Map (Function 0) The PCIxx12 controller is a multifunction PCI device, and the PC Card controller is integrated as PCI function 0. The configuration header, compliant with the PCI Local Bus Specification as a CardBus bridge header, is PC99/PC2001 compliant as well. Table 4-2 illustrates the PCI configuration register map, which includes both the predefined portion of the configuration space and the user-definable registers. Table 4-2. Function 0 PCI Configuration Register Map REGISTER NAME OFFSET Device ID Vendor ID Status Command Class code BIST Header type Latency timer 00h 04h Revision ID 08h Cache line size 0Ch CardBus socket registers/ExCA base address register Secondary status CardBus latency timer Subordinate bus number 10h Reserved Capability pointer CardBus bus number PCI bus number 14h 18h CardBus memory base register 0 1Ch CardBus memory limit register 0 20h CardBus memory base register 1 24h CardBus memory limit register 1 28h One or more bits in this register are cleared only by the assertion of GRST. 76 SCPS110 September 2005 PC Card Controller Programming Model Table 4-2. Function 0 PCI Configuration Register Map (Continued) REGISTER NAME OFFSET CardBus I/O base register 0 2Ch CardBus I/O limit register 0 30h CardBus I/O base register 1 34h CardBus I/O limit register 1 Bridge control 38h Interrupt pin Subsystem ID Interrupt line 3Ch Subsystem vendor ID 40h PC Card 16-bit I/F legacy-mode base-address 44h Reserved 48h-7Ch System control General control General-purpose output General-purpose input Diagnostic Device control 80h Reserved MC_CD debounce 84h General-purpose event enable General-purpose event status 88h Multifunction routing status 8Ch Card control Retry status Next item pointer Capability ID 90h Reserved Power management capabilities Power management data (Reserved) Power management control/status bridge support extensions Serial bus control/status Serial bus slave address 94h-9Ch A0h A4h Power management control/status Reserved A8h-ACh Serial bus index Serial bus data B0h Reserved B4h-FCh One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or GRST. One or more bits in this register are cleared only by the assertion of GRST. One or more bits in this register are global in nature and must be accessed only through function 0. 4.2 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG that identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch. PCI register offset: Register type: Default value: 00h (Function 0) Read-only 104Ch BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 4.3 Device ID Register Function 0 This read-only register contains the device ID assigned by TI to the PCIxx12 CardBus controller functions. PCI register offset: Register type: Default value: 02h (Function 0) Read-only 8039h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 September 2005 SCPS110 77 PC Card Controller Programming Model 4.4 Command Register The PCI command register provides control over the PCIxx12 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification (see Table 4-3). None of the bit functions in this register are shared among the PCIxx12 PCI functions. Five command registers exist in the controller, one for each function. Software manipulates the functions as separate entities when enabling functionality through the command register. The SERR_EN and PERR_EN enable bits in this register are internally-wired OR between the five functions, and these control bits appear to software to be separate for each function. PCI register offset: Register type: Default value: 04h Read-only, Read/Write 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4-3. Command Register Description BIT SIGNAL TYPE 15-11 RSVD R 10 INT_DISABLE RW INTx disable. When set to 1b, this bit disables the function from asserting interrupts on the INTx signals. 0 = INTx assertion is enabled (default) 1 = INTx assertion is disabled 9 FBB_EN R Fast back-to-back enable. The controller does not generate fast back-to-back transactions; therefore, this bit is read-only. This bit returns a 0b when read. System error (SERR) enable. This bit controls the enable for the SERR driver on the PCI interface. SERR can be asserted after detecting an address parity error on the PCI bus. Both this bit and bit 6 must be set for the controller to report address parity errors. 0 = Disables the SERR output driver (default) 1 = Enables the SERR output driver 8 SERR_EN RW 7 RSVD R Reserved. Bit 7 returns 0b when read. 6 PERR_EN RW Parity error response enable. This bit controls the PCIxx12 response to parity errors through the PERR signal. Data parity errors are indicated by asserting PERR, while address parity errors are indicated by asserting SERR. 0 = Controller ignores detected parity errors (default) 1 = Controller responds to detected parity errors 5 VGA_EN RW VGA palette snoop. When set to 1b, palette snooping is enabled (i.e., the controller does not respond to palette register writes and snoops the data). When the bit is 0b, the controller treats all palette accesses like all other accesses. 4 MWI_EN R Memory write-and-invalidate enable. This bit controls whether a PCI initiator device can generate memory write-and-invalidate commands. The controller does not support memory write-and-invalidate commands, it uses memory write commands instead; therefore, this bit is hardwired to 0b. This bit returns 0b when read. Writes to this bit have no effect. 3 SPECIAL R Special cycles. This bit controls whether or not a PCI device ignores PCI special cycles. The controller does not respond to special cycle operations; therefore, this bit is hardwired to 0b. This bit returns 0b when read. Writes to this bit have no effect. RW Bus master control. This bit controls whether or not the controller can act as a PCI bus initiator (master). The controller can take control of the PCI bus only when this bit is set. 0 = Disables the PCIxx12 ability to generate PCI bus accesses (default) 1 = Enables the PCIxx12 ability to generate PCI bus accesses 2 78 FUNCTION Reserved. Bits 15-11 return 00000b when read. MAST_EN 1 MEM_EN RW Memory space enable. This bit controls whether or not the controller can claim cycles in PCI memory space. 0 = Disables the PCIxx12 response to memory space accesses (default) 1 = Enables the PCIxx12 response to memory space accesses 0 IO_EN RW I/O space control. This bit controls whether or not the controller can claim cycles in PCI I/O space. 0 = Disables the controller from responding to I/O space accesses (default) 1 = Enables the controller to respond to I/O space accesses SCPS110 September 2005 PC Card Controller Programming Model 4.5 Status Register The status register provides device information to the host system. Bits in this register can be read normally. A bit in the status register is reset when a 1b is written to that bit location; a 0b written to a bit location has no effect. All bit functions adhere to the definitions in the PCI Bus Specification, as seen in the bit descriptions. PCI bus status is shown through each function. See Table 4-4 for a complete description of the register contents. PCI register offset: Register type: Default value: 06h (Function 0) Read-only, Read/Write 0210h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 Table 4-4. Status Register Description BIT SIGNAL TYPE FUNCTION 15 PAR_ERR RW Detected parity error. This bit is set when a parity error is detected, either an address or data parity error. Write a 1b to clear this bit. 14 SYS_ERR RW Signaled system error. This bit is set when SERR is enabled and the controller signaled a system error to the host. Write a 1b to clear this bit. 13 MABORT RW Received master abort. This bit is set when a cycle initiated by the controller on the PCI bus has been terminated by a master abort. Write a 1b to clear this bit. 12 TABT_REC RW Received target abort. This bit is set when a cycle initiated by the controller on the PCI bus was terminated by a target abort. Write a 1b to clear this bit. 11 TABT_SIG RW Signaled target abort. This bit is set by the controller when it terminates a transaction on the PCI bus with a target abort. Write a 1b to clear this bit. 10-9 PCI_SPEED R DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired to 01b indicating that the controller asserts this signal at a medium speed on nonconfiguration cycle accesses. Data parity error detected. Write a 1b to clear this bit. 0 = The conditions for setting this bit have not been met 1 = A data parity error occurred and the following conditions were met: a. PERR was asserted by any PCI device including the controller b. The controller was the bus master during the data parity error c. Bit 6 (PERR_EN) in the command register (offset 04h, see Section 4.4) is set 8 DATAPAR RW 7 FBB_CAP R Fast back-to-back capable. The controller cannot accept fast back-to-back transactions; thus, this bit is hardwired to 0b. 6 UDF R UDF supported. The controller does not support user-definable features; therefore, this bit is hardwired to 0b. 5 66MHZ R 66-MHz capable. The controller operates at a maximum PCLK frequency of 33 MHz; therefore, this bit is hardwired to 0b. 4 CAPLIST R Capabilities list. This bit returns 1b when read. This bit indicates that capabilities in addition to standard PCI capabilities are implemented. The linked list of PCI power-management capabilities is implemented in this function. 3 INT_STATUS RU Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE) in the command register (PCI offset 04h, see Section 4.4) is a 0b and this bit is a 1b, is the function's INTx signal asserted. Setting the INT_DISABLE bit to a 1b has no effect on the state of this bit. 2-0 RSVD R Reserved. These bits return 000b when read. This bit is cleared only by the assertion of GRST. September 2005 SCPS110 79 PC Card Controller Programming Model 4.6 Revision ID Register The revision ID register indicates the silicon revision of the controller. PCI register offset: Register type: Default value: 08h (Function 0) Read-only 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 4.7 Class Code Register The class code register recognizes PCIxx12 function 0 as a bridge device (06h) and a CardBus bridge device (07h), with a 00h programming interface. PCI register offset: Register type: Default value: BIT NUMBER 23 22 21 NAME RESET STATE 4.8 09h (Function 0) Read-only 06 0700h 20 19 18 17 16 15 14 13 Base class 0 0 0 0 0 12 11 10 9 8 7 6 Subclass 1 1 0 0 0 0 0 0 5 4 3 2 1 0 0 0 Programming interface 1 1 1 0 0 0 0 0 0 Cache Line Size Register The cache line size register is programmed by host software to indicate the system cache line size. PCI register offset: Register type: Default value: 0Ch (Function 0) Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 4.9 Latency Timer Register The latency timer register specifies the latency timer for the controller, in units of PCI clock cycles. When the controller is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires before the PCIxx12 transaction has terminated, then the controller terminates the transaction when its GNT is deasserted. PCI register offset: Register type: Default value: 0Dh Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 80 SCPS110 September 2005 PC Card Controller Programming Model 4.10 Header Type Register The header type register returns 82h when read, indicating that the function 0 configuration spaces adhere to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI registers 00h-7Fh, and 80h-FFh is user-definable extension registers. PCI register offset: Register type: Default value: 0Eh (Function 0) Read-only 82h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 1 0 0 0 0 0 1 0 4.11 BIST Register Because the controller does not support a built-in self-test (BIST), this register returns the value of 00h when read. PCI register offset: Register type: Default value: 0Fh (Function 0) Read-only 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 4.12 CardBus Socket Registers/ExCA Base Address Register This register is programmed with a base address referencing the CardBus socket registers and the memory-mapped ExCA register set. Bits 31-12 are read/write, and allow the base address to be located anywhere in the 32-bit PCI memory address space on a 4-Kbyte boundary. Bits 11-0 are read-only, returning 000h when read. When software writes FFFF FFFFh to this register, the value read back is FFFF F000h, indicating that at least 4K bytes of memory address space are required. The CardBus registers start at offset 000h, and the memory-mapped ExCA registers begin at offset 800h. PCI register offset: Register type: Default value: 10h Read-only, Read/Write 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4.13 Capability Pointer Register The capability pointer register provides a pointer into the PCI configuration header where the PCI power management register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. This register is read-only and returns A0h when read. PCI register offset: Register type: Default value: 14h Read-only A0h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 1 0 1 0 0 0 0 0 September 2005 SCPS110 81 PC Card Controller Programming Model 4.14 Secondary Status Register The secondary status register is compatible with the PCI-PCI bridge secondary status register. It indicates CardBus-related device information to the host system. This register is very similar to the PCI status register (PCI offset 06h, see Section 4.5), and status bits are cleared by a writing a 1b. See Table 4-5 for a complete description of the register contents. PCI register offset: Register type: Default value: 16h Read-only, Read/Clear 0200h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Table 4-5. Secondary Status Register Description BIT SIGNAL TYPE FUNCTION 15 CBPARITY RC Detected parity error. This bit is set when a CardBus parity error is detected, either an address or data parity error. Write a 1b to clear this bit. 14 CBSERR RC Signaled system error. This bit is set when CSERR is signaled by a CardBus card. The controller does not assert the CSERR signal. Write a 1b to clear this bit. 13 CBMABORT RC Received master abort. This bit is set when a cycle initiated by the controller on the CardBus bus is terminated by a master abort. Write a 1b to clear this bit. 12 REC_CBTA RC Received target abort. This bit is set when a cycle initiated by the controller on the CardBus bus is terminated by a target abort. Write a 1b to clear this bit. 11 SIG_CBTA RC Signaled target abort. This bit is set by the controller when it terminates a transaction on the CardBus bus with a target abort. Write a 1b to clear this bit. 10-9 CB_SPEED R CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired to 01b indicating that the controller asserts this signal at a medium speed. CardBus data parity error detected. Write a 1b to clear this bit. 0 = The conditions for setting this bit have not been met 1 = A data parity error occurred and the following conditions were met: a. CPERR was asserted on the CardBus interface b. The controller was the bus master during the data parity error c. Bit 0 (CPERREN) in the bridge control register (PCI offset 3Eh, see Section 4.25) is set 8 CB_DPAR RC 7 CBFBB_CAP R Fast back-to-back capable. The controller cannot accept fast back-to-back transactions; therefore, this bit is hardwired to 0b. 6 CB_UDF R User-definable feature support. The controller does not support user-definable features; therefore, this bit is hardwired to 0b. 5 CB66MHZ R 66-MHz capable. The PCIxx12 CardBus interface operates at a maximum CCLK frequency of 33 MHz; therefore, this bit is hardwired to 0b. 4-0 RSVD R These bits return 00000b when read. This bit is cleared only by the assertion of GRST. 4.15 PCI Bus Number Register The PCI bus number register is programmed by the host system to indicate the bus number of the PCI bus to which the controller is connected. The controller uses this register in conjunction with the CardBus bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses. PCI register offset: Register type: Default value: 18h (Function 0) Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 82 SCPS110 September 2005 PC Card Controller Programming Model 4.16 CardBus Bus Number Register The CardBus bus number register is programmed by the host system to indicate the bus number of the CardBus bus to which the controller is connected. The controller uses this register in conjunction with the PCI bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses. This register is separate for each controller function. PCI register offset: Register type: Default value: 19h Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 4.17 Subordinate Bus Number Register The subordinate bus number register is programmed by the host system to indicate the highest numbered bus below the CardBus bus. The controller uses this register in conjunction with the PCI bus number and CardBus bus number registers to determine when to forward PCI configuration cycles to its secondary buses. PCI register offset: Register type: Default value: 1Ah Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 4.18 CardBus Latency Timer Register The CardBus latency timer register is programmed by the host system to specify the latency timer for the CardBus interface, in units of CCLK cycles. When the controller is a CardBus initiator and asserts CFRAME, the CardBus latency timer begins counting. If the latency timer expires before the PCIxx12 transaction has terminated, then the controller terminates the transaction at the end of the next data phase. A recommended minimum value for this register of 20h allows most transactions to be completed. PCI register offset: Register type: Default value: 1Bh (Function 0) Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 September 2005 SCPS110 83 PC Card Controller Programming Model 4.19 CardBus Memory Base Registers 0, 1 These registers indicate the lower address of a PCI memory address range. They are used by the controller to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. Bits 31-12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11-0 are read-only and always return 000h. Writes to these bits have no effect. Bits 8 and 9 of the bridge control register (PCI offset 3Eh, see Section 4.25) specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero in order for the controller to claim any memory transactions through CardBus memory windows (i.e., these windows by default are not enabled to pass the first 4 Kbytes of memory to CardBus). PCI register offset: Register type: Default value: 1Ch, 24h Read-only, Read/Write 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4.20 CardBus Memory Limit Registers 0, 1 These registers indicate the upper address of a PCI memory address range. They are used by the controller to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. Bits 31-12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11-0 are read-only and always return 000h. Writes to these bits have no effect. Bits 8 and 9 of the bridge control register (PCI offset 3Eh, see Section 4.25) specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero in order for the controller to claim any memory transactions through CardBus memory windows (i.e., these windows by default are not enabled to pass the first 4 Kbytes of memory to CardBus). PCI register offset: Register type: Default value: 20h, 28h Read-only, Read/Write 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 84 SCPS110 September 2005 PC Card Controller Programming Model 4.21 CardBus I/O Base Registers 0, 1 These registers indicate the lower address of a PCI I/O address range. They are used by the controller to determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to the PCI bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64-Kbyte page. The upper 16 bits (31-16) are all 0000h, which locates this 64-Kbyte page in the first page of the 32-bit PCI I/O address space. Bits 31-2 are read/write and always return 0s forcing I/O windows to be aligned on a natural doubleword boundary in the first 64-Kbyte page of PCI I/O address space. Bits 1-0 are read-only, returning 00b or 01b when read, depending on the value of bit 11 (IO_BASE_SEL) in the general control register (PCI offset 86h, see Section 4.30). These I/O windows are enabled when either the I/O base register or the I/O limit register is nonzero. The I/O windows by default are not enabled to pass the first doubleword of I/O to CardBus. Either the I/O base register or the I/O limit register must be nonzero to enable any I/O transactions. PCI register offset: Register type: Default value: BIT NUMBER 31 30 2Ch, 34h Read-only, Read/Write 0000 000Xh 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 4.22 CardBus I/O Limit Registers 0, 1 These registers indicate the upper address of a PCI I/O address range. They are used by the controller to determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. The lower 16 bits of this register locate the top of the I/O window within a 64-Kbyte page, and the upper 16 bits are a page register which locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 15-2 are read/write and allow the I/O limit address to be located anywhere in the 64-Kbyte page (indicated by bits 31-16 of the appropriate I/O base register) on doubleword boundaries. Bits 31-16 are read-only and always return 0000h when read. The page is set in the I/O base register. Bits 15-2 are read/write and bits 1-0 are read-only, returning 00b or 01b when read, depending on the value of bit 12 (IO_LIMIT_SEL) in the general control register (PCI offset 86h, see Section 4.30). Writes to read-only bits have no effect. These I/O windows are enabled when either the I/O base register or the I/O limit register is nonzero. By default, the I/O windows are not enabled to pass the first doubleword of I/O to CardBus. Either the I/O base register or the I/O limit register must be nonzero to enable any I/O transactions. PCI register offset: Register type: Default value: 30h, 38h Read-only, Read/Write 0000 000Xh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X September 2005 SCPS110 85 PC Card Controller Programming Model 4.23 Interrupt Line Register The interrupt line register is a read/write register used by the host software. As part of the interrupt routing procedure, the host software writes this register with the value of the system IRQ assigned to the function. PCI register offset: Register type: Default value: 3Ch Read/Write FFh BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 1 1 1 1 1 1 1 1 4.24 Interrupt Pin Register The value read from this register is function dependent. The default value for function 0 is 01h (INTA), the default value for function 1 is 02h (INTB), the default value for function 2 is 01h (INTA), the default value for function 3 is 01h (INTA), the default value for function 4 is 01h (INTA). The value also depends on the values of bits 28, the tie-all bit (TIEALL), and 29, the interrupt tie bit (INTRTIE), in the system control register (PCI offset 80h, see Section 4.29). The INTRTIE bit is compatible with previous TI CardBus controllers, and when set to 1b, ties INTB to INTA internally. The TIEALL bit ties INTA, INTB, INTC, and INTD together internally. The internal interrupt connections set by INTRTIE and TIEALL are communicated to host software through this standard register interface. This read-only register is described for all PCIxx12 functions in Table 4-6. PCI register offset: Register type: Default value: 3Dh Read-only 01h (function 0), 02h (function 1), 01h (function 2), 01h (function 3), 01h (function 4) PCI function 0 BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 1 PCI function 1 BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 1 1 PCI function 2 BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 X X X PCI function 3 BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 X X X PCI function 4 BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 X X X Table 4-6. Interrupt Pin Register Cross Reference INTRTIE BIT (BIT 29, OFFSET 80H) TIEALL BIT (BIT 28, OFFSET 80H) 0 0 01h (INTA) 02h (INTB) 1 0 01h (INTA) 01h (INTA) X 1 01h (INTA) 01h (INTA) 86 SCPS110 INTPIN INTPIN FUNCTION 0 FUNCTION 1 (CARDBUS) (1394 OHCI) INTPIN FUNCTION 2 (FLASH MEDIA) INTPIN FUNCTION 3 (SD HOST) INTPIN FUNCTION 4 (SMART CARD) Determined by bits 6-5 (INT_SEL) in the flash media general control register (see Section 11.21) Determined by bits 6-5 (INT_SEL) in the SD host general control register (see Section 12.22) Determined by bits 6-5 (INT_SEL) in the Smart Card general control register (see Section 13.22) 01h (INTA) 01h (INTA) 01h (INTA) September 2005 PC Card Controller Programming Model 4.25 Bridge Control Register The bridge control register provides control over various PCIxx12 bridging functions. Some bits in this register are global in nature and must be accessed only through function 0. See Table 4-7 for a complete description of the register contents. PCI register offset: Register type: Default value: 3Eh (Function 0) Read-only, Read/Write 0340h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 Table 4-7. Bridge Control Register Description BIT SIGNAL TYPE 15-11 RSVD R FUNCTION 10 POSTEN RW Write posting enable. Enables write posting to and from the CardBus socket. Write posting enables the posting of write data on burst cycles. Operating with write posting disabled impairs performance on burst cycles. Note that burst write data can be posted, but various write transactions may not. These bits return 00000b when read. 9 PREFETCH1 RW Memory window 1 type. This bit specifies whether or not memory window 1 is prefetchable. This bit is encoded as: 0 = Memory window 1 is nonprefetchable 1 = Memory window 1 is prefetchable (default) 8 PREFETCH0 RW Memory window 0 type. This bit specifies whether or not memory window 0 is prefetchable. This bit is encoded as: 0 = Memory window 0 is nonprefetchable 1 = Memory window 0 is prefetchable (default) 7 INTR RW PCI interrupt - IREQ routing enable. This bit selects whether PC Card functional interrupts are routed to PCI interrupts or to the IRQ specified in the ExCA registers. 0 = Functional interrupts are routed to PCI interrupts (default). 1 = Functional interrupts are routed by ExCA registers. 6 CRST RW CardBus reset. When this bit is set, the CRST signal is asserted on the CardBus interface. The CRST signal can also be asserted by passing a PRST assertion to CardBus. 0 = CRST is deasserted 1 = CRST is asserted (default) This bit is not cleared by the assertion of PRST. It is only cleared by the assertion of GRST. Master abort mode. This bit controls how the controller responds to a master abort when the controller is an initiator on the CardBus interface. 0 = Master aborts not reported (default) 1 = Signal target abort on PCI and signal SERR, if enabled 5 MABTMODE RW 4 RSVD R 3 VGAEN RW VGA enable. This bit affects how the controller responds to VGA addresses. When this bit is set, accesses to VGA addresses are forwarded. 2 ISAEN RW ISA mode enable. This bit affects how the controller passes I/O cycles within the 64-Kbyte ISA range. When this bit is set, the controller does not forward the last 768 bytes of each 1K I/O range to CardBus. 1 CSERREN RW CSERR enable. This bit controls the response of the controller to CSERR signals on the CardBus bus. 0 = CSERR is not forwarded to PCI SERR (default) 1 = CSERR is forwarded to PCI SERR RW CardBus parity error response enable. This bit controls the response of the controller to CardBus parity errors. 0 = CardBus parity errors are ignored (default) 1 = CardBus parity errors are reported using CPERR 0 CPERREN This bit returns 0b when read. One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or GRST. September 2005 SCPS110 87 PC Card Controller Programming Model 4.26 Subsystem Vendor ID Register The subsystem vendor ID register, used for system and option card identification purposes, may be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register (PCI offset 80h, See Section 4.29). When bit 5 is 0b, this register is read/write; when bit 5 is 1b, this register is read-only. The default mode is read-only. All bits in this register are reset by GRST only. PCI register offset: Register type: Default value: 40h (Function 0) Read-only, (Read/Write when bit 5 in the system control register is 0) 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4.27 Subsystem ID Register The subsystem ID register, used for system and option card identification purposes, may be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register (PCI offset 80h, see Section 4.29). When bit 5 is 0b, this register is read/write; when bit 5 is 1b, this register is read-only. The default mode is read-only. All bits in this register are reset by GRST only. If an EEPROM is present, then the subsystem ID and subsystem vendor ID is loaded from the EEPROM after a reset. PCI register offset: Register type: Default value: 42h (Function 0) Read-only, (Read/Write when bit 5 in the system control register is 0) 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4.28 PC Card 16-Bit I/F Legacy-Mode Base-Address Register The controller supports the index/data scheme of accessing the ExCA registers, which is mapped by this register. An address written to this register is the address for the index register and the address+1 is the data address. Using this access method, applications requiring index/data ExCA access can be supported. The base address can be mapped anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read-only, returning 1b when read. As specified in the PCI to PCMCIA CardBus Bridge Register Description specification. See the ExCA register set description in Section 5 for register offsets. All bits in this register are reset by GRST only. PCI register offset: Register type: Default value: 44h (Function 0) Read-only, Read/Write 0000 0001h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 88 SCPS110 September 2005 PC Card Controller Programming Model 4.29 System Control Register System-level initializations are performed through programming this doubleword register. Some of the bits are global in nature and must be accessed only through function 0. See Table 4-8 for a complete description of the register contents. PCI register offset: Register type: Default value: 80h (Function 0) Read-only, Read/Write 0844 9060h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 Table 4-8. System Control Register Description BIT SIGNAL TYPE FUNCTION 31-30 SER_STEP RW Serial input stepping. In serial PCI interrupt mode, these bits are used to configure the serial stream PCI interrupt frames, and can be used to accomplish an even distribution of interrupts signaled on the four PCI interrupt slots. 00 = INTA/INTB/INTC/INTD signal in INTA/INTB/INTC/INTD slots (default) 01 = INTA/INTB/INTC/INTD signal in INTB/INTC/INTD/INTA slots 10 = INTA/INTB/INTC/INTD signal in INTC/INTD/INTA/INTB slots 11 = INTA/INTB/INTC/INTD signal in INTD/INTA/INTB/INTC slots 29 INTRTIE RW This bit ties INTA to INTB internally (to INTA), and reports this through the interrupt pin register (PCI offset 3Dh, see Section 4.24). This bit has no effect on INTC or INTD. 28 TIEALL RW This bit ties INTA, INTB, INTC, and INTD internally (to INTA), and reports this through the interrupt pin register (PCI offset 3Dh, see Section 4.24). RW P2C power switch clock. The PCIxx12 CLOCK signal clocks the serial interface power switch and the internal state machine. The default state for this bit is 0b, requiring an external clock source provided to the CLOCK terminal. Bit 27 can be set to 1b, allowing the internal oscillator to provide the clock signal. 0 = CLOCK is provided externally, input to the controller 1 = CLOCK is generated by the internal oscillator and driven by the controller (default) RW SMI interrupt routing. This bit selects whether IRQ2 or CSC is signaled when a write occurs to power a PC Card socket. 0 = PC Card power change interrupts are routed to IRQ2 (default) 1 = A CSC interrupt is generated on PC Card power changes RW SMI interrupt status. This bit is set when a write occurs to set the socket power, and the SMIENB bit is set. Writing a 1b to this bit clears the status. 0 = SMI interrupt is signaled 1 = SMI interrupt is not signaled SMI interrupt mode enable. When this bit is set, the SMI interrupt signaling generates an interrupt when a write to the socket power control occurs. This bit defaults to 0b (disabled). 0 = SMI interrupt mode is disabled (default) 1 = SMI interrupt mode is enabled 27 26 25 PSCCLK SMIROUTE SMISTATUS 24 SMIENB RW 23 RSVD R Reserved 22 CBRSVD RW CardBus reserved terminals signaling. When this bit is set, the RSVD CardBus terminals are driven low when a CardBus card has been inserted. When this bit is low, these signals are placed in a high-impedance state. 0 = Place the CardBus RSVD terminals in a high-impedance state 1 = Drive the CardBus RSVD terminals low (default) 21 VCCPROT RW VCC protection enable. 0 = VCC protection is enabled for 16-bit cards (default) 1 = VCC protection is disabled for 16-bit cards These bits are cleared only by the assertion of GRST. These bits are global in nature and must be accessed only through function 0. September 2005 SCPS110 89 PC Card Controller Programming Model Table 4-8. System Control Register Description (Continued) BIT SIGNAL TYPE 20-16 RSVD RW These bits are reserved. Do not change the value of these bits. RW Memory read burst enable downstream. When this bit is set, the controller allows memory read transactions to burst downstream. 0 = MRBURSTDN downstream is disabled 1 = MRBURSTDN downstream is enabled (default) 15 MRBURSTDN FUNCTION 14 MRBURSTUP RW Memory read burst enable upstream. When this bit is set, the controller allows memory read transactions to burst upstream. 0 = MRBURSTUP upstream is disabled (default) 1 = MRBURSTUP upstream is enabled 13 SOCACTIVE R Socket activity status. When set, this bit indicates access has been performed to or from a PC Card. Reading this bit causes it to be cleared. 0 = No socket activity (default) 1 = Socket activity 12 RSVD R Reserved. This bit returns 1b when read. R Power-stream-in-progress status bit. When set, this bit indicates that a power stream to the power switch is in progress and a powering change has been requested. When this bit is cleared, it indicates that the power stream is complete. 0 = Power stream is complete, delay has expired (default) 1 = Power stream is in progress R Power-up delay-in-progress status bit. When set, this bit indicates that a power-up stream has been sent to the power switch, and proper power may not yet be stable. This bit is cleared when the power-up delay has expired. 0 = Power-up delay has expired (default) 1 = Power-up stream sent to switch. Power might not be stable. R Power-down delay-in-progress status bit. When set, this bit indicates that a power-down stream has been sent to the power switch, and proper power may not yet be stable. This bit is cleared when the power-down delay has expired. 0 = Power-down delay has expired (default) 1 = Power-down stream sent to switch. Power might not be stable. 11 10 9 PWRSTREAM DELAYUP DELAYDOWN 8 INTERROGATE R Interrogation in progress. When set, this bit indicates an interrogation is in progress, and clears when the interrogation completes. 0 = Interrogation not in progress (default) 1 = Interrogation in progress 7 RSVD R Reserved. This bit returns 0b when read. 6 PWRSAVINGS RW Power savings mode enable. When this bit is set, the controller consumes less power with no performance loss. 0 = Power savings mode disabled 1 = Power savings mode enabled (default) 5 SUBSYSRW RW Subsystem ID and subsystem vendor ID, ExCA ID and revision register read/write enable. This bit also controls read/write for the function 2 subsystem ID register. 0 = Registers are read/write 1 = Registers are read-only (default) 4 CB_DPAR RW CardBus data parity SERR signaling enable. 0 = CardBus data parity not signaled on PCI SERR signal (default) 1 = CardBus data parity signaled on PCI SERR signal 3 RSVD R Reserved. This bit returns 0b when read. 2 EXCAPOWER R ExCA power control bit. 0 = Enables 3.3 V (default) 1 = Enables 5 V One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or GRST. These bits are cleared only by the assertion of GRST. These bits are global in nature and must be accessed only through function 0. 90 SCPS110 September 2005 PC Card Controller Programming Model Table 4-8. System Control Register Description (Continued) BIT 1 SIGNAL KEEPCLK TYPE FUNCTION RW Keep clock. When this bit is set, the controller follows the CLKRUN protocol to maintain the system PCLK and the CCLK (CardBus clock). This bit is global to the PCIxx12 functions. 0 = Allow system PCLK and CCLK clocks to stop (default) 1 = Never allow system PCLK or CCLK clock to stop Note that the functionality of this bit has changed relative to that of the PCI12XX family of TI CardBus controllers. In these CardBus controllers, setting this bit only maintains the PCI clock, not the CCLK. In the PCIxx12 controller, setting this bit maintains both the PCI clock and the CCLK. 0 RIMUX RW PME/RI_OUT select bit. When this bit is 1b, the PME signal is routed to the PME/RI_OUT terminal (R03). When this bit is 0b and bit 7 (RIENB) of the card control register is 1b, the RI_OUT signal is routed to the PME/RI_OUT terminal. If this bit is 0b and bit 7 (RIENB) of the card control register is 0b, then the output is placed in a high-impedance state. This terminal is encoded as: 0 = RI_OUT signal is routed to the PME/RI_OUT terminal if bit 7 of the card control register is 1b (default) 1 = PME signal is routed to the PME/RI_OUT terminal of the controller NOTE: If this bit (bit 0) is 0b and bit 7 of the card control register (PCI offset 91h, see Section 4.37) is 0b, then the output on the PME/RI_OUT terminal is placed in a high-impedance state. This bit is cleared only by the assertion of GRST. These bits are global in nature and must be accessed only through function 0. 4.30 General Control Register The general control register provides top level PCI arbitration control. It also provides the ability to disable the features of the device and provides control over miscellaneous new functionality. See Table 4-9 for a complete description of the register contents. PCI register offset: Register type: Default value: 84h Read/Write, Read-only 0003 0019h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 Table 4-9. General Control Register Description BIT SIGNAL TYPE FUNCTION 31 FM_PWR_CTRL _POL RW Flash media power control pin polarity. This bit controls the polarity of the MC_PWR_CTRL_0 and MC_PWR_CTRL_1 terminals. 0 = MC_PWR_CTRL_x terminals are active low (default) 1 = MC_PWR_CTRL_x terminals are active high Smart Card interface select. This bit controls the selection of the dedicated Smart Card interface used by the controller. 0 = EMV interface selected (default) 1 = PCI7x10-style interface selected Note: The PCI7x10-style interface is only allowed when bits 25-24 (FM_IF_SEL field) are 01b. If bits 25-24 contain any other value, then this bit is 0b. Care must be taken in the design to ensure that this bit can be set to 1b at the same time that bits 25-24 are set to 01b. Note: If bit 9 (SC_SOCKET_SEL) is set to 1b, then this bit has no effect on the design. 30 SC_IF_SEL RWU 29 SIM_MODE RW When this bit is set, it reduces the query time for UltraMedia card types. 0 = Query time is unaffected (default) 1 = Query time is reduced for simulation purposes 28 IO_LIMIT_SEL RW When this bit is set, bit 0 in the I/O limit registers (PCI offsets 30h and 38h) is set. 0 = Bit 0 in the I/O limit registers is 0b (default) 1 = Bit 0 in the I/O limit registers is 1b These bits are cleared only by the assertion of GRST. September 2005 SCPS110 91 PC Card Controller Programming Model Table 4-9. General Control Register Description (Continued) BIT SIGNAL TYPE FUNCTION 27 IO_BASE_SEL RW When this bit is set, bit 0 in the I/O base registers (PCI offsets 2Ch and 34h) is set. 0 = Bit 0 in the I/O base registers is 0b (default) 1 = Bit 0 in the I/O base registers is 1b 26 12V_SW_SEL RW Power switch select. This bit selects which power switch is implemented in the system. 0 = A 1.8-V capable power switch (TPS2228) is used (default) 1 = A 12-V capable power switch (TPS2226) is used 25-24 FM_IF_SEL RW Dedicated flash media interface selection. This field controls the mode of the dedicated flash media interface. 00 = Flash media interface configured as SD/MMC socket + MS socket (default) 01 = Flash media interface configured as 2-in-1 (SD/MMC, MS) socket 10 = Flash media interface configured as 3-in-1 (SD/MMC, MS, SM/xD) socket 11 = Reserved 23 DISABLE_SC RW When this bit is set, the Smart Card function is completely nonaccessible and nonfunctional. 22 DISABLE_SD RW When this bit is set, the SD host controller function is completely nonaccessible and nonfunctional. 21 DISABLE_FM RW When this bit is set, the flash media function is completely nonaccessible and nonfunctional. 20 RSVD RW Reserved. This bit does not affect any functionality within the CardBus core. 19 DISABLE_OHCI RW When this bit is set, the OHCI 1394 controller function is completely nonaccessible and nonfunctional. 18 DED_SC_PWR_ CTRL RW Dedicated Smart Card power control. This bit determines how power to the dedicated Smart Card socket is controlled. 0 = Controlled through the SC_PWR_CTRL terminal (default) 1 = Controlled through the VPP voltage of socket B of the CardBus power switch 17-16 ARB_CTRL RW 15-11 RSVD R 10 DISABLE_CB _CD 9 SC_SOCKET _SEL Controls top level PCI arbitration: 00 = 1394 OHCI priority 01 = CardBus priority 10 = Flash media/SD host priority 11 = Fair round robin Note: When Flash media/SD host priority is selected, there must be a two-level priority scheme with the first level being a round robin between the Flash media/SD host functions and the second level being a round robin between the CardBus and 1394 functions. Reserved. These bits return 00000b when read. RW Disable CardBus card detection. When this bit is set, the CardBus core does not detect any CardBus or 16-bit card insertions. Instead, the registers in the CardBus core contain the values they would contain if the socket was empty. This bit does not affect the detection of Flash media or Smart Card adapters. RW Smart Card socket select. This bit selects whether the Smart Card logic is connected to the dedicated Smard Card interface or the CardBus socket. 0 = Smart Card logic connected to the dedicated Smart Card interface (default) 1 = Smart Card logic connected to the CardBus socket for use with a Smart Card adapter 8 DED_FM_PWR_ CTL RW Dedicated Flash media socket 0 power control. This bit determines how power to the dedicated Flash media socket 0 is controlled. 0 = Controlled through the MC_PWR_CTRL_0 signal (default) 1 = Controlled through the VCC voltage of socket B of the CardBus power switch (the design ensures that this mode can only be set when the 3-pin serial power switch interface is selected) 7-0 MC_CD_ DEBOUNCE RW MC_CD debounce. This field provides debounce time in units of 2 ms for the MC_CD signal on the UltraMedia cards. This register defaults to 19h which gives a default debounce time of 50 ms. These bits are cleared only by the assertion of GRST. 92 SCPS110 September 2005 PC Card Controller Programming Model 4.31 General-Purpose Event Status Register The general-purpose event status register contains status bits that are set when general events occur, and can be programmed to generate general-purpose event signaling through GPE. See Table 4-10 for a complete description of the register contents. PCI register offset: Register type: Default value: 88h Read/Clear/Update, Read-only 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 4-10. General-Purpose Event Status Register Description BIT SIGNAL TYPE FUNCTION 7 PWR_STS RCU Power change status. This bit is set when software changes the VCC or VPP power state of the socket. 6 VPP12_STS RCU 12-V VPP request status. This bit is set when software has changed the requested VPP level to or from 12 V for the socket. 5 RSVD R 4 GP4_STS RCU GPI4 status. This bit is set on a change in status of the MFUNC5 terminal input level if configured as a general-purpose input, GPI4. 3 GP3_STS RCU GPI3 status. This bit is set on a change in status of the MFUNC4 terminal input level if configured as a general-purpose input, GPI3. 2 GP2_STS RCU GPI2 status. This bit is set on a change in status of the MFUNC2 terminal input level if configured as a general-purpose input, GPI2. 1 GP1_STS RCU GPI1 status. This bit is set on a change in status of the MFUNC1 terminal input level if configured as a general-purpose input, GPI1. 0 GP0_STS RCU GPI0 status. This bit is set on a change in status of the MFUNC0 terminal input level if configured as a general-purpose input, GPI0. Reserved. This bit returns 0b when read. A write has no effect. This bit is cleared only by the assertion of GRST. 4.32 General-Purpose Event Enable Register The general-purpose event enable register contains bits that are set to enable GPE signals. See Table 4-11 for a complete description of the register contents. PCI register offset: Register type: Default value: 89h Read-only, Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 4-11. General-Purpose Event Enable Register Description BIT SIGNAL TYPE 7 PWR_EN RW Power change GPE enable. When this bit is set, GPE is signaled on PWR_STS events. FUNCTION 6 VPP12_EN RW 12-V VPP GPE enable. When this bit is set, GPE is signaled on VPP12_STS events. 5 RSVD R 4 GP4_EN RW Reserved. This bit returns 0b when read. A write has no effect. GPI4 GPE enable. When this bit is set, GPE is signaled on GP4_STS events. 3 GP3_EN RW GPI3 GPE enable. When this bit is set, GPE is signaled on GP3_STS events. 2 GP2_EN RW GPI2 GPE enable. When this bit is set, GPE is signaled on GP2_STS events. 1 GP1_EN RW GPI1 GPE enable. When this bit is set, GPE is signaled on GP1_STS events. 0 GP0_EN RW GPI0 GPE enable. When this bit is set, GPE is signaled on GP0_STS events. This bit is cleared only by the assertion of GRST. September 2005 SCPS110 93 PC Card Controller Programming Model 4.33 General-Purpose Input Register The general-purpose input register contains the logical value of the data input to the GPI terminals. See Table 4-12 for a complete description of the register contents. PCI register offset: Register type: Default value: 8Ah Read/Update, Read-only XXh BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 X X X X X Table 4-12. General-Purpose Input Register Description BIT SIGNAL TYPE 7-5 RSVD R FUNCTION 4 GPI4_DATA RU GPI4 data input. This bit represents the logical value of the data input from GPI4. 3 GPI3_DATA RU GPI3 data input. This bit represents the logical value of the data input from GPI3. 2 GPI2_DATA RU GPI2 data input. This bit represents the logical value of the data input from GPI2. 1 GPI1_DATA RU GPI1 data input. This bit represents the logical value of the data input from GPI1. 0 GPI0_DATA RU GPI0 data input. This bit represents the logical value of the data input from GPI0. Reserved. These bits return 000b when read. Writes have no effect. 4.34 General-Purpose Output Register The general-purpose output register is used to drive the GPO4-GPO0 outputs. See Table 4-13 for a complete description of the register contents. PCI register offset: Register type: Default value: 8Bh Read-only, Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 4-13. General-Purpose Output Register Description BIT SIGNAL TYPE 7-5 RSVD R FUNCTION 4 GPO4_DATA RW This bit represents the logical value of the data driven to GPO4. 3 GPO3_DATA RW This bit represents the logical value of the data driven to GPO3. 2 GPO2_DATA RW This bit represents the logical value of the data driven to GPO2. 1 GPO1_DATA RW This bit represents the logical value of the data driven to GPO1. 0 GPO0_DATA RW This bit represents the logical value of the data driven to GPO0. Reserved. These bits return 000b when read. Writes have no effect. This bit is cleared only by the assertion of GRST. 94 SCPS110 September 2005 PC Card Controller Programming Model 4.35 Multifunction Routing Status Register The multifunction routing status register is used to configure the MFUNC6-MFUNC0 terminals. These terminals may be configured for various functions. This register is intended to be programmed once at power-on initialization. The default value for this register can also be loaded through a serial EEPROM. See Table 4-14 for a complete description of the register contents. PCI register offset: Register type: Default value: 8Ch Read/Write, Read-only 0100 1000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Table 4-14. Multifunction Routing Status Register Description BIT SIGNAL TYPE 31-28 RSVD R 27-24 23-20 MFUNC6 MFUNC5 FUNCTION Bits 31-28 return 0h when read. RW Multifunction terminal 6 configuration. These bits control the internal signal mapped to the MFUNC6 terminal as follows: 0000 = RSVD 0100 = IRQ4 1000 = IRQ8 1100 = IRQ12 0001 = CLKRUN 0101 = IRQ5 1001 = IRQ9 1101 = IRQ13 0010 = IRQ2 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 RW Multifunction terminal 5 configuration. These bits control the internal signal mapped to the MFUNC5 terminal as follows: 0000 = GPI4 0100 = SC_DBG_RX 1000 = CAUDPWM 1100 = LEDA1 0001 = GPO4 0101 = IRQ5 1001 = RSVD 1101 = LED_SKT 0010 = PCGNT 0110 = RSVD 1010 = FM_LED 1110 = GPE 0011 = RSVD 0111 = RSVD 1011 = OHCI_LED 1111 = IRQ15 Multifunction terminal 4 configuration. These bits control the internal signal mapped to the MFUNC4 terminal as follows: 19-16 15-12 11-8 MFUNC4 MFUNC3 MFUNC2 RW 0000 = GPI3 0001 = GPO3 0010 = RSVD 0011 = RSVD 0100 = IRQ4 0101 = SC_DBG_TX 0110 = RSVD 0111 = RSVD 1000 = CAUDPWM 1001 = IRQ9 1010 = INTD 1011 = FM_LED 1100 = RI_OUT 1101 = LED_SKT 1110 = GPE 1111 = IRQ15 RW Multifunction terminal 3 configuration. These bits control the internal signal mapped to the MFUNC3 terminal as follows: 0000 = RSVD 0100 = IRQ4 1000 = IRQ8 1100 = IRQ12 0001 = IRQSER 0101 = IRQ5 1001 = IRQ9 1101 = IRQ13 0010 = IRQ2 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 RW Multifunction terminal 2 configuration. These bits control the internal signal mapped to the MFUNC2 terminal as follows: 0000 = GPI2 0100 = RSVD 1000 = CAUDPWM 1100 = RI_OUT 0001 = GPO2 0101 = RSVD 1001 = FM_LED 1101 = TEST_MUX 0010 = PCREQ 0110 = RSVD 1010 = IRQ10 1110 = GPE 0011 = IRQ3 0111 = RSVD 1011 = INTC 1111 = IRQ7 These bits are cleared only by the assertion of GRST. September 2005 SCPS110 95 PC Card Controller Programming Model Table 4-14. Multifunction Routing Status Register Description (Continued) BIT SIGNAL 7-4 3-0 MFUNC1 MFUNC0 TYPE FUNCTION RW Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminal as follows: 0000 = GPI1 0100 = OHCI_LED 1000 = CAUDPWM 1100 = LEDA1 0001 = GPO1 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0110 = RSVD 1010 = IRQ10 1110 = GPE 0010 = INTB 0011 = IRQ3 0111 = RSVD 1011 = IRQ11 1111 = IRQ15 RW Multifunction terminal 0 configuration. These bits control the internal signal mapped to the MFUNC0 terminal as follows: 0000 = GPI0 0100 = IRQ4 1000 = CAUDPWM 1100 = LEDA1 0001 = GPO0 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0110 = RSVD 1010 = IRQ10 1110 = GPE 0010 = INTA 0011 = IRQ3 0111 = RSVD 1011 = IRQ11 1111 = IRQ15 These bits are cleared only by the assertion of GRST. 4.36 Retry Status Register The contents of the retry status register enable the retry time-out counters and display the retry expiration status. The flags are set when the controller, as a master, receives a retry and does not retry the request within 215 clock cycles. The flags are cleared by writing a 1b to the bit. See Table 4-15 for a complete description of the register contents. PCI register offset: Register type: Default value: 90h (Function 0) Read-only, Read/Write, Read/Clear C0h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 1 1 0 0 0 0 0 0 Table 4-15. Retry Status Register Description BIT SIGNAL TYPE FUNCTION 7 PCIRETRY RW PCI retry time-out counter enable. This bit is encoded as: 0 = PCI retry counter disabled 1 = PCI retry counter enabled (default) 6 CBRETRY RW CardBus retry time-out counter enable. This bit is encoded as: 0 = CardBus retry counter disabled 1 = CardBus retry counter enabled (default) 5 TEXP_CBB RC CardBus target B retry expired. Write a 1b to clear this bit. 0 = Inactive (default) 1 = Retry has expired 4 RSVD R 3 TEXP_CBA RC 2 RSVD R 1 TEXP_PCI RC 0 RSVD R Reserved. This bit returns 0b when read. CardBus target A retry expired. Write a 1b to clear this bit. 0 = Inactive (default) 1 = Retry has expired Reserved. This bit returns 0b when read. PCI target retry expired. Write a 1b to clear this bit. 0 = Inactive (default) 1 = Retry has expired Reserved. This bit returns 0b when read. This bit is cleared only by the assertion of GRST. These bits are global in nature and must be accessed only through function 0. 96 SCPS110 September 2005 PC Card Controller Programming Model 4.37 Card Control Register The card control register is provided for PCI1130 compatibility. The RI_OUT signal is enabled through this register. See Table 4-16 for a complete description of the register contents. PCI register offset: Register type: Default value: 91h Read-only, Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 4-16. Card Control Register Description BIT SIGNAL TYPE 7 RIENB RW Ring indicate enable. When this bit is 1b, the RI_OUT output is enabled. This bit defaults to 0b. 6-3 RSVD RW These bits are reserved. Do not change the value of these bits. 2 1 AUD2MUX SPKROUTEN 0 IFG RW RW RW FUNCTION CardBus audio-to-MFUNC. When this bit is set, the CAUDIO CardBus signal must be routed through an MFUNC terminal. 0 = CAUDIO set to CAUDPWM on MFUNC terminal (default) 1 = CAUDIO is not routed When bit 1 is set, the SPKR terminal from the PC Card is enabled and is routed to tthe SPKROUT terminal. The SPKROUT terminal drives data only when the SPKROUTEN bit is set. This bit is encoded as: 0 = SPKR to SPKROUT not enabled (default) 1 = SPKR to SPKROUT enabled Interrupt flag. This bit is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. This bit is set when a functional interrupt is signaled from a PC Card interface. Write back a 1b to clear this bit. 0 = No PC Card functional interrupt detected (default) 1 = PC Card functional interrupt detected This bit is cleared only by the assertion of GRST. This bit is global in nature and must be accessed only through function 0. September 2005 SCPS110 97 PC Card Controller Programming Model 4.38 Device Control Register The device control register is provided for PCI1130 compatibility. The interrupt mode select is programmed through this register. The socket-capable force bits are also programmed through this register. See Table 4-17 for a complete description of the register contents. PCI register offset: Register type: Default value: 92h (Function 0) Read-only, Read/Write 66h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 1 1 0 0 1 1 0 Table 4-17. Device Control Register Description BIT SIGNAL TYPE FUNCTION 7 SKTPWR_LOCK RW Socket power lock bit. When this bit is set to 1b, software cannot power down the PC Card socket while in D3. It may be necessary to lock socket power in order to support wake on LAN or RING if the operating system is programmed to power down a socket when the CardBus controller is placed in the D3 state. 6 3VCAPABLE RW 3-V socket capable force bit. 0 = Not 3-V capable 1 = 3-V capable (default) 5 IO16R2 RW Diagnostic bit. This bit defaults to 1b. PCI power management version control. This bit controls the value reported in the Version field of the power management capabilities register of the CardBus function (PCI offset A2h, see Section 4.42). 0 = Version field reports 010b for PCI Bus Power Management Interface Specification (Revision 1.1) compliance 1 = Version field reports 011b for PCI Bus Power Management Interface Specification (Revision 1.2) compliance 4 PCI_PM_ VERSION_CTL R 3 TEST RW TI test bit. Write only 0b to this bit. 2-1 INTMODE RW Interrupt mode. These bits select the interrupt signaling mode. The interrupt mode bits are encoded: 00 = Parallel PCI interrupts only 01 = Reserved 10 = IRQ serialized interrupts and parallel PCI interrupts INTA, INTB, INTC, and INTD 11 = IRQ and PCI serialized interrupts (default) 0 RSVD RW Reserved. Bit 0 is reserved for test purposes. Only a 0b must be written to this bit. This bit is cleared only by the assertion of GRST. These bits are global in nature and must be accessed only through function 0. 98 SCPS110 September 2005 PC Card Controller Programming Model 4.39 Diagnostic Register The diagnostic register is provided for internal TI test purposes. It is a read/write register, but only 00h must be written to it. See Table 4-18 for a complete description of the register contents. PCI register offset: Register type: Default value: 93h (Function 0) Read/Write 60h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 1 1 0 0 0 0 0 Table 4-18. Diagnostic Register Description BIT SIGNAL TYPE 7 TRUE_VAL RW 6 RSVD R FUNCTION This bit defaults to 0b. This bit is encoded as: 0 = Reads true values in PCI vendor ID and PCI device ID registers (default) 1 = Returns all 1s to reads from the PCI vendor ID and PCI device ID registers Reserved. This bit is read-only and returns 1b when read. 5 CSC RW CSC interrupt routing control 0 = CSC interrupts routed to PCI if ExCA 803 bit 4 = 1 1 = CSC interrupts routed to PCI if ExCA 805 bits 7-4 = 0000b (default). In this case, the setting of ExCA 803 bit 4 is a don't care. 4 DIAG4 RW Diagnostic RETRY_DIS. Delayed transaction disable. 3 DIAG3 RW 2 DIAG2 RW Diagnostic RETRY_EXT. Extends the latency from 16 to 64. Diagnostic DISCARD_TIM_SEL_CB. Set = 210, reset = 215. 1 DIAG1 RW Diagnostic DISCARD_TIM_SEL_PCI. Set = 210, reset = 215. 0 RSVD RW These bits are reserved. Do not change the value of these bits. This bit is cleared only by the assertion of GRST. This bit is global and is accessed only through function 0. 4.40 Capability ID Register The capability ID register identifies the linked list item as the register for PCI power management. The register returns 01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and the value. PCI register offset: Register type: Default value: A0h Read-only 01h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 1 4.41 Next Item Pointer Register The contents of this register indicate the next item in the linked list of the PCI power management capabilities. Because the PCIxx12 functions only include one capabilities item, this register returns 00h when read. PCI register offset: Register type: Default value: A1h Read-only 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 September 2005 SCPS110 99 PC Card Controller Programming Model 4.42 Power Management Capabilities Register The power management capabilities register contains information on the capabilities of the PC Card function related to power management. The CardBus bridge function supports D0, D1, D2, and D3 power states. Default register value is FE12h for operation in accordance with PCI Bus Power Management Interface Specification revision 1.1. See Table 4-19 for a complete description of the register contents. PCI register offset: Register type: Default value: A2h (Function 0) Read-only, Read/Write FE12h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 0 Table 4-19. Power Management Capabilities Register Description BIT SIGNAL TYPE FUNCTION This 5-bit field indicates the power states from which the controller function can assert PME. A 0b for any bit indicates that the function cannot assert the PME signal while in that power state. These 5 bits return 11111b when read. Each of these bits is described below: 15 RW PME support 14-11 R Bit 15 - defaults to a 1b indicating the PME signal can be asserted from the D3cold state. This bit is read/write because wake-up support from D3cold is contingent on the system providing an auxiliary power source to the VCC terminals. If the system designer chooses not to provide an auxiliary power source to the VCC terminals for D3cold wake-up support, then BIOS must write a 0b to this bit. Bit 14 - contains the value 1b to indicate that the PME signal can be asserted from the D3hot state. Bit 13 - contains the value 1b to indicate that the PME signal can be asserted from the D2 state. Bit 12 - contains the value 1b to indicate that the PME signal can be asserted from the D1 state. Bit 11 - contains the value 1b to indicate that the PME signal can be asserted from the D0 state. 10 D2_Support R This bit returns a 1b when read, indicating that the function supports the D2 device power state. 9 D1_Support R This bit returns a 1b when read, indicating that the function supports the D1 device power state. 8-6 RSVD R Reserved. These bits return 000b when read. 5 DSI R Device-specific initialization. This bit returns 0b when read. Auxiliary power source. This bit is meaningful only if bit 15 (D3cold supporting PME) is set. When this bit is set, it indicates that support for PME in D3cold requires auxiliary power supplied by the system by way of a proprietary delivery vehicle. 4 AUX_PWR R A 0b in this bit field indicates that the function supplies its own auxiliary power source. If the function does not support PME while in the D3cold state (bit 15 = 0), then this field must always return 0b. 3 PMECLK R When this bit is 1b, it indicates that the function relies on the presence of the PCI clock for PME operation. When this bit is 0b, it indicates that no PCI clock is required for the function to generate PME. Functions that do not support PME generation in any state must return 0b for this bit. 2-0 Version R Power management version. If bit 4 (PCI_PM_VERSION_CTRL) in the device control register (PCI offset 92h, see Section 4.38) is 0b, this field returns 010b indicating PCI Bus Power Management Interface Specification (Revision 1.1) compatibility. If bit 4 (PCI_PM_VERSION_CTRL) in the device control register is 1b, this field returns 011b indicating PCI Bus Power Management Interface Specification (Revision 1.2) compatibility. This bit is cleared only by the assertion of GRST. 100 SCPS110 September 2005 PC Card Controller Programming Model 4.43 Power Management Control/Status Register The power management control/status register determines and changes the current power state of the CardBus function. The contents of this register are not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See Table 4-20 for a complete description of the register contents. All PCI registers, ExCA registers, and CardBus registers are reset as a result of a D3hot-to-D0 state transition, with the exception of the PME context bits (if PME is enabled) and the GRST only bits. PCI register offset: Register type: Default value: A4h (Function 0) Read-only, Read/Write, Read/Write/Clear 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4-20. Power Management Control/Status Register Description BIT SIGNAL TYPE FUNCTION 15 PMESTAT RC PME status. This bit is set when the CardBus function would normally assert the PME signal, independent of the state of the PME_EN bit. This bit is cleared by a writeback of 1b, and this also clears the PME signal if PME was asserted by this function. Writing a 0b to this bit has no effect. 14-13 DATASCALE R This 2-bit field returns 00b when read. The CardBus function does not return any dynamic data. 12-9 DATASEL R Data select. This 4-bit field returns 0s when read. The CardBus function does not return any dynamic data. 8 PME_ENABLE RW This bit enables the function to assert PME. If this bit is cleared, then assertion of PME is disabled. This bit is not cleared by the assertion of PRST. It is only cleared by the assertion of GRST. 7-2 RSVD R Reserved. These bits return 00 0000b when read. Power state. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. This field is encoded as: 1-0 PWRSTATE RW 00 = D0 01 = D1 10 = D2 11 = D3hot One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or GRST. This bit is cleared only by the assertion of GRST. September 2005 SCPS110 101 PC Card Controller Programming Model 4.44 Power Management Control/Status Bridge Support Extensions Register This register supports PCI bridge-specific functionality. It is required for all PCI-to-PCI bridges. See Table 4-21 for a complete description of the register contents. PCI register offset: Register type: Default value: A6h (Function 0) Read-only C0h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 1 1 0 0 0 0 0 0 Table 4-21. Power Management Control/Status Bridge Support Extensions Register Description BIT SIGNAL TYPE FUNCTION Bus power/clock control enable. This bit returns 1b when read. This bit is encoded as: 0 = Bus power/clock control is disabled 1 = Bus power/clock control is enabled (default) 7 BPCC_EN R A 0b indicates that the bus power/clock control policies defined in the PCI Bus Power Management Interface Specification are disabled. When the bus power/clock control enable mechanism is disabled, the power state field (bits 1-0) of the power management control/status register (PCI offset A4h, see Section 4.43) cannot be used by the system software to control the power or the clock of the secondary bus. A 1b indicates that the bus power/clock control mechanism is enabled. 6 B2_B3 R B2/B3 support for D3hot. The state of this bit determines the action that is to occur as a direct result of programming the function to D3hot. This bit is only meaningful if bit 7 (BPCC_EN) is a 1b. This bit is encoded as: 0 = When the bridge is programmed to D3hot, its secondary bus has its power removed (B3) 1 = When the bridge function is programmed to D3hot, its secondary bus PCI clock is stopped (B2) (default) 5-0 RSVD R Reserved. These bits return 00 0000b when read. 4.45 Power-Management Data Register The power-management data register returns 00h when read, because the CardBus functions do not report dynamic data. PCI register offset: Register type: Default value: A7h (Function 0) Read-only 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 102 SCPS110 September 2005 PC Card Controller Programming Model 4.46 Serial Bus Data Register The serial bus data register is for programmable serial bus byte reads and writes. This register represents the data when generating cycles on the serial bus interface. To write a byte, this register must be programmed with the data, the serial bus index register must be programmed with the byte address, the serial bus slave address must be programmed with the 7-bit slave address, and the read/write indicator bit must be reset. On byte reads, the byte address is programmed into the serial bus index register, the serial bus slave address register must be programmed with both the 7-bit slave address and the read/write indicator bit, and bit 5 (REQBUSY) in the serial bus control and status register (see Section 4.49) must be polled until clear. Then the contents of this register are valid read data from the serial bus interface. See Table 4-22 for a complete description of the register contents. PCI register offset: Register type: Default value: B0h (function 0) Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 4-22. Serial Bus Data Register Description BIT 7-0 SIGNAL SBDATA TYPE FUNCTION RW Serial bus data. This bit field represents the data byte in a read or write transaction on the serial interface. On reads, the REQBUSY bit must be polled to verify that the contents of this register are valid. These bits are cleared only by the assertion of GRST. 4.47 Serial Bus Index Register The serial bus index register is for programmable serial bus byte reads and writes. This register represents the byte address when generating cycles on the serial bus interface. To write a byte, the serial bus data register must be programmed with the data, this register must be programmed with the byte address, and the serial bus slave address must be programmed with both the 7-bit slave address and the read/write indicator. On byte reads, the word address is programmed into this register, the serial bus slave address must be programmed with both the 7-bit slave address and the read/write indicator bit, and bit 5 (REQBUSY) in the serial bus control and status register (see Section 4.49) must be polled until clear. Then the contents of the serial bus data register are valid read data from the serial bus interface. See Table 4-23 for a complete description of the register contents. PCI register offset: Register type: Default value: B1h (function 0) Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 4-23. Serial Bus Index Register Description BIT SIGNAL TYPE FUNCTION 7-0 SBINDEX RW Serial bus index. This bit field represents the byte address in a read or write transaction on the serial interface. These bits are cleared only by the assertion of GRST. September 2005 SCPS110 103 PC Card Controller Programming Model 4.48 Serial Bus Slave Address Register The serial bus slave address register is for programmable serial bus byte read and write transactions. To write a byte, the serial bus data register must be programmed with the data, the serial bus index register must be programmed with the byte address, and this register must be programmed with both the 7-bit slave address and the read/write indicator bit. On byte reads, the byte address is programmed into the serial bus index register, this register must be programmed with both the 7-bit slave address and the read/write indicator bit, and bit 5 (REQBUSY) in the serial bus control and status register (see Section 4.49) must be polled until clear. Then the contents of the serial bus data register are valid read data from the serial bus interface. See Table 4-24 for a complete description of the register contents. PCI register offset: Register type: Default value: B2h (function 0) Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 4-24. Serial Bus Slave Address Register Description BIT SIGNAL 7-1 0 SLAVADDR RWCMD TYPE FUNCTION RW Serial bus slave address. This bit field represents the slave address of a read or write transaction on the serial interface. RW Read/write command. Bit 0 indicates the read/write command bit presented to the serial bus on byte read and write accesses. 0 = A byte write access is requested to the serial bus interface 1 = A byte read access is requested to the serial bus interface These bits are cleared only by the assertion of GRST. 4.49 Serial Bus Control/Status Register The serial bus control and status register communicates serial bus status information and selects the quick command protocol. Bit 5 (REQBUSY) in this register must be polled during serial bus byte reads to indicate when data is valid in the serial bus data register. See Table 4-25 for a complete description of the register contents. PCI register offset: Register type: Default value: B3h (function 0) Read-only, Read/Write, Read/Clear 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 104 SCPS110 September 2005 PC Card Controller Programming Model Table 4-25. Serial Bus Control/Status Register Description BIT SIGNAL TYPE FUNCTION 7 PROT_SEL RW Protocol select. When bit 7 is set, the send-byte protocol is used on write requests and the receive-byte protocol is used on read commands. The word address byte in the serial bus index register (see Section 4.47) is not output by the controller when bit 7 is set. 6 RSVD R Reserved. Bit 6 returns 0b when read. 5 REQBUSY R Requested serial bus access busy. Bit 5 indicates that a requested serial bus access (byte read or write) is in progress. A request is made, and bit 5 is set, by writing to the serial bus slave address register (see Section 4.48). Bit 5 must be polled on reads from the serial interface. After the byte read access has been completed, this bit is cleared and the read data is valid in the serial bus data register. R Serial EEPROM busy status. Bit 4 indicates the status of the PCIxx12 serial EEPROM circuitry. Bit 4 is set during the loading of the subsystem ID and other default values from the serial bus EEPROM. 0 = Serial EEPROM circuitry is not busy 1 = Serial EEPROM circuitry is busy 4 ROMBUSY 3 SBDETECT RW Serial bus detect. When the serial bus interface is detected through a pullup resistor on the SCL terminal after reset, this bit is set to 1b. 0 = Serial bus interface not detected 1 = Serial bus interface detected 2 SBTEST RW Serial bus test. When bit 2 is set, the serial bus clock frequency is increased for test purposes. 0 = Serial bus clock at normal operating frequency, 100 kHz (default) 1 = Serial bus clock frequency increased for test purposes 1 REQ_ERR RC Requested serial bus access error. Bit 1 indicates when a data error occurs on the serial interface during a requested cycle and may be set due to a missing acknowledge. Bit 1 is cleared by a writeback of 1b. 0 = No error detected during user-requested byte read or write cycle 1 = Data error detected during user-requested byte read or write cycle RC EEPROM data error status. Bit 0 indicates when a data error occurs on the serial interface during the auto-load from the serial bus EEPROM and may be set due to a missing acknowledge. Bit 0 is also set on invalid EEPROM data formats. See Section 3.6.4, Serial Bus EEPROM Application, for details on EEPROM data format. Bit 0 is cleared by a writeback of 1b. 0 = No error detected during autoload from serial bus EEPROM 1 = Data error detected during autoload from serial bus EEPROM 0 ROM_ERR This bit is cleared only by the assertion of GRST. September 2005 SCPS110 105 ExCA Compatibilty Registers (Function 0) 5 ExCA Compatibilty Registers (Function 0) The ExCA (exchangeable card architecture) registers implemented in the PCIxx12 controller are register-compatible with the Intel 82365SL-DF PCMCIA controller. ExCA registers are identified by an offset value, which is compatible with the legacy I/O index/data scheme used on the Intel 82365 ISA controller. The ExCA registers are accessed through this scheme by writing the register offset value into the index register (I/O base), and reading or writing the data register (I/O base + 1). The I/O base address used in the index/data scheme is programmed in the PC Card 16-bit I/F legacy mode base address register, which is shared by both card sockets. The offsets from this base address run contiguously from 00h to 3Fh for the socket. See Figure 5-1 for an ExCA I/O mapping illustration. Table 5-1 identifies each ExCA register and its respective ExCA offset. The controller also provides a memory-mapped alias of the ExCA registers by directly mapping them into PCI memory space. They are located through the CardBus socket registers/ExCA registers base address register (PCI register 10h) at memory offset 800h. Each socket has a separate base address programmable by function. See Figure 5-2 for an ExCA memory mapping illustration. This illustration also identifies the CardBus socket register mapping, which is mapped into the same 4K window at memory offset 0h. The interrupt registers in the ExCA register set, as defined by the 82365SL specification, control such card functions as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt routing registers and the host interrupt signaling method selected for the controller to ensure that all possible PCIxx12 interrupts can potentially be routed to the programmable interrupt controller. The ExCA registers that are critical to the interrupt signaling are at memory address ExCA offsets 803h and 805h. Access to I/O mapped 16-bit PC Cards is available to the host system via two ExCA I/O windows. These are regions of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this chapter. I/O windows have byte granularity. Access to memory-mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. These are regions of host memory space into which the card memory space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this chapter. Memory windows have 4-Kbyte granularity. A bit location followed by a means that this bit is not cleared by the assertion of PRST. This bit is only cleared by the assertion of GRST. This is necessary to retain device context during the transition from D3 to D0. 106 SCPS110 September 2005 ExCA Compatibilty Registers (Function 0) Host I/O Space Offset PCIxx12 Configuration Registers Offset 00h PC Card A ExCA Registers CardBus Socket/ExCA Base Address 10h Index 3Fh Data 16-Bit Legacy-Mode Base Address 40h 44h Reserved 7Fh Offset of desired register is placed in the index register and the data from that location is returned in the data register. Figure 5-1. ExCA Register Access Through I/O PCIxx12 Configuration Registers Offset Host Memory Space Offset 00h CardBus Socket/ExCA Base Address 10h 16-Bit Legacy-Mode Base Address 44h CardBus Socket A Registers 20h ExCA Registers Card A 800h 844h Offsets are from the CardBus socket/ExCA base address register's base address. Figure 5-2. ExCA Register Access Through Memory September 2005 SCPS110 107 ExCA Compatibilty Registers (Function 0) Table 5-1. ExCA Registers and Offsets PCI MEMORY ADDRESS OFFSET (HEX) EXCA OFFSET (CARD A) 800 00 Interface status 801 01 Power control 802 02 Interrupt and general control 803 03 Card status change 804 04 Card status change interrupt configuration 805 05 Address window enable 806 06 I / O window control 807 07 I / O window 0 start-address low-byte 808 08 EXCA REGISTER NAME Identification and revision I / O window 0 start-address high-byte 809 09 I / O window 0 end-address low-byte 80A 0A I / O window 0 end-address high-byte 80B 0B I / O window 1 start-address low-byte 80C 0C I / O window 1 start-address high-byte 80D 0D I / O window 1 end-address low-byte 80E 0E I / O window 1 end-address high-byte 80F 0F Memory window 0 start-address low-byte 810 10 Memory window 0 start-address high-byte 811 11 Memory window 0 end-address low-byte 812 12 Memory window 0 end-address high-byte 813 13 Memory window 0 offset-address low-byte 814 14 Memory window 0 offset-address high-byte 815 15 Card detect and general control 816 16 Reserved 817 17 Memory window 1 start-address low-byte 818 18 Memory window 1 start-address high-byte 819 19 Memory window 1 end-address low-byte 81A 1A Memory window 1 end-address high-byte 81B 1B Memory window 1 offset-address low-byte 81C 1C Memory window 1 offset-address high-byte 81D 1D Global control 81E 1E Reserved 81F 1F Memory window 2 start-address low-byte 820 20 Memory window 2 start-address high-byte 821 21 Memory window 2 end-address low-byte 822 22 Memory window 2 end-address high-byte 823 23 Memory window 2 offset-address low-byte 824 24 Memory window 2 offset-address high-byte 825 25 One or more bits in this register are cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or GRST. One or more bits in this register are cleared only by the assertion of GRST. 108 SCPS110 September 2005 ExCA Compatibilty Registers (Function 0) Table 5-1. ExCA Registers and Offsets (Continued) PCI MEMORY ADDRESS OFFSET (HEX) EXCA OFFSET (CARD A) Reserved 826 26 Reserved 827 27 Memory window 3 start-address low-byte 828 28 EXCA REGISTER NAME Memory window 3 start-address high-byte 829 29 Memory window 3 end-address low-byte 82A 2A Memory window 3 end-address high-byte 82B 2B Memory window 3 offset-address low-byte 82C 2C Memory window 3 offset-address high-byte 82D 2D Reserved 82E 2E Reserved 82F 2F Memory window 4 start-address low-byte 830 30 Memory window 4 start-address high-byte 831 31 Memory window 4 end-address low-byte 832 32 Memory window 4 end-address high-byte 833 33 Memory window 4 offset-address low-byte 834 34 Memory window 4 offset-address high-byte 835 35 I/O window 0 offset-address low-byte 836 36 I/O window 0 offset-address high-byte 837 37 I/O window 1 offset-address low-byte 838 38 I/O window 1 offset-address high-byte 839 39 Reserved 83A 3A Reserved 83B 3B Reserved 83C 3C Reserved 83D 3D Reserved 83E 3E Reserved 83F 3F Memory window page register 0 840 - Memory window page register 1 841 - Memory window page register 2 842 - Memory window page register 3 843 - Memory window page register 4 844 - September 2005 SCPS110 109 ExCA Compatibilty Registers (Function 0) 5.1 ExCA Identification and Revision Register This register provides host software with information on 16-bit PC Card support and 82365SL-DF compatibility. See Table 5-2 for a complete description of the register contents. NOTE: If bit 5 (SUBSYRW) in the system control register is 1b, then this register is read-only. ExCA register offset: Register type: Default value: CardBus Socket Address + 800h: Card A ExCA Offset 00h Read/Write, Read-only 84h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 1 0 0 0 0 1 0 0 Table 5-2. ExCA Identification and Revision Register Description BIT SIGNAL TYPE FUNCTION Interface type. These bits, which are hardwired as 10b, identify the 16-bit PC Card support provided by the controller. The controller supports both I/O and memory 16-bit PC Cards. 7-6 IFTYPE R 5-4 RSVD RW These bits can be used for 82365SL emulation. 3-0 365REV RW 82365SL-DF revision. This field stores the Intel 82365SL-DF revision supported by the controller. Host software can read this field to determine compatibility to the 82365SL-DF register set. This field defaults to 0100b upon reset. Writing 0010b to this field places the controller in the 82356SL mode. These bits are cleared only by the assertion of GRST. 110 SCPS110 September 2005 ExCA Compatibilty Registers (Function 0) 5.2 ExCA Interface Status Register This register provides information on current status of the PC Card interface. An X in the default bit values indicates that the value of the bit after reset depends on the state of the PC Card interface. See Table 5-3 for a complete description of the register contents. ExCA register offset: Register type: Default value: CardBus Socket Address + 801h: Card A ExCA Offset 01h Read-only 00XX XXXXb BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 X X X X X X Table 5-3. ExCA Interface Status Register Description BIT SIGNAL TYPE 7 RSVD R 6 CARDPWR R 5 READY R FUNCTION This bit returns 0b when read. A write has no effect. CARDPWR. Card power. This bit indicates the current power status of the PC Card socket. This bit reflects how the ExCA power control register has been programmed. The bit is encoded as: 0 = VCC and VPP to the socket are turned off (default). 1 = VCC and VPP to the socket are turned on. This bit indicates the current status of the READY signal at the PC Card interface. 4 CARDWP R 0 = PC Card is not ready for a data transfer. 1 = PC Card is ready for a data transfer. Card write protect. This bit indicates the current status of the WP signal at the PC Card interface. This signal reports to the controller whether or not the memory card is write protected. Further, write protection for an entire PCIxx12 16-bit memory window is available by setting the appropriate bit in the ExCA memory window offset-address high-byte register. 0 = WP signal is 0b. PC Card is R/W. 1 = WP signal is 1b. PC Card is read-only. 3 2 CDETECT2 CDETECT1 R R Card detect 2. This bit indicates the status of the CD2 signal at the PC Card interface. Software can use this and CDETECT1 to determine if a PC Card is fully seated in the socket. 0 = CD2 signal is 1b. No PC Card inserted. 1 = CD2 signal is 0b. PC Card at least partially inserted. Card detect 1. This bit indicates the status of the CD1 signal at the PC Card interface. Software can use this and CDETECT2 to determine if a PC Card is fully seated in the socket. 0 = CD1 signal is 1b. No PC Card inserted. 1 = CD1 signal is 0b. PC Card at least partially inserted. Battery voltage detect. When a 16-bit memory card is inserted, the field indicates the status of the battery voltage detect signals (BVD1, BVD2) at the PC Card interface, where bit 0 reflects the BVD1 status, and bit 1 reflects BVD2. 1-0 BVDSTAT R 00 = Battery is dead. 01 = Battery is dead. 10 = Battery is low; warning. 11 = Battery is good. When a 16-bit I/O card is inserted, this field indicates the status of the SPKR (bit 1) signal and the STSCHG (bit 0) at the PC Card interface. In this case, the two bits in this field directly reflect the current state of these card outputs. September 2005 SCPS110 111 ExCA Compatibilty Registers (Function 0) 5.3 ExCA Power Control Register This register provides PC Card power control. Bit 7 of this register enables the 16-bit outputs on the socket interface, and can be used for power management in 16-bit PC Card applications. See Table 5-5 for a complete description of the register contents. ExCA register offset: Register type: Default value: CardBus Socket Address + 802h: Card A ExCA Offset 02h Read-only, Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 5-4. ExCA Power Control Register Description--82365SL Support BIT SIGNAL TYPE FUNCTION 7 COE RW Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the controller. This bit is encoded as: 0 = 16-bit PC Card outputs disabled (default) 1 = 16-bit PC Card outputs enabled 6 RSVD R 5 AUTOPWRSWEN RW Auto power switch enable. 0 = Automatic socket power switching based on card detects is disabled. 1 = Automatic socket power switching based on card detects is enabled. PC Card power enable. 0 = VCC = No connection 1 = VCC is enabled and controlled by bit 2 (EXCAPOWER) of the system control register (PCI offset 80h, see Section 4.29). 4 CAPWREN RW 3-2 RSVD R 1-0 EXCAVPP RW Reserved. Bit 6 returns 0b when read. Reserved. Bits 3 and 2 return 00b when read. PC Card VPP power control. Bits 1 and 0 are used to request changes to card VPP. The controller ignores this field unless VCC to the socket is enabled. This field is encoded as: 00 = No connection (default) 10 = 12 V 01 = VCC 11 = Reserved One or more bits in this register are cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or GRST. Table 5-5. ExCA Power Control Register Description--82365SL-DF Support BIT SIGNAL TYPE FUNCTION Card output enable. This bit controls the state of all of the 16-bit outputs on the controller. This bit is encoded as: 0 = 16-bit PC Card outputs are disabled (default). 1 = 16-bit PC Card outputs are enabled. 7 COE RW 6-5 RSVD R 4-3 EXCAVCC RW 2 RSVD R 1-0 EXCAVPP RW Reserved. These bits return 00b when read. Writes have no effect. VCC. These bits are used to request changes to card VCC. This field is encoded as: 00 = 0 V (default) 10 = 5 V 01 = 0 V reserved 11 = 3.3 V This bit returns 0b when read. A write has no effect. VPP. These bits are used to request changes to card VPP. The controller ignores this field unless VCC to the socket is enabled (i.e., 5 Vdc or 3.3 Vdc). This field is encoded as: 00 = 0 V (default) 10 = 12 V 01 = VCC 11 = 0 V reserved This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or GRST. 112 SCPS110 September 2005 ExCA Compatibilty Registers (Function 0) 5.4 ExCA Interrupt and General Control Register This register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card functions. See Table 5-6 for a complete description of the register contents. ExCA register offset: Register type: Default value: CardBus Socket Address + 803h: Card A ExCA Offset 03h Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 5-6. ExCA Interrupt and General Control Register Description BIT SIGNAL TYPE FUNCTION 7 RINGEN RW Card ring indicate enable. Enables the ring indicate function of the BVD1/RI terminals. This bit is encoded as: 0 = Ring indicate disabled (default) 1 = Ring indicate enabled Card reset. This bit controls the 16-bit PC Card RESET signal, and allows host software to force a card reset. This bit affects 16-bit cards only. This bit is encoded as: 0 = RESET signal asserted (default) 1 = RESET signal deasserted. 6 RESET RW 5 CARDTYPE RW Card type. This bit indicates the PC Card type. This bit is encoded as: 4 CSCROUTE RW 0 = Memory PC Card is installed (default) 1 = I/O PC Card is installed PCI interrupt - CSC routing enable bit. This bit has meaning only if the CSC interrupt routing control bit (PCI offset 93h, bit 5) is 0b. In this case, when this bit is set (high), the card status change interrupts are routed to PCI interrupts. When low, the card status change interrupts are routed using bits 7-4 in the ExCA card status-change interrupt configuration register (ExCA offset 805h, see Section 5.6). This bit is encoded as: 0 = CSC interrupts routed by ExCA registers (default) 1 = CSC interrupts routed to PCI interrupts If the CSC interrupt routing control bit (bit 5) of the diagnostic register (PCI offset 93h, see Section 4.39) is set to 1b, this bit has no meaning, which is the default case. Card interrupt select for I/O PC Card functional interrupts. These bits select the interrupt routing for I/O PC Card functional interrupts. This field is encoded as: 3-0 INTSELECT RW 0000 = No IRQ selected (default). CSC interrupts are routed to PCI Interrupts. This bit setting is ORed with bit 4 (CSCROUTE) for backward compatibility. 0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0110 = IRQ6 enabled 0111 = IRQ7 enabled 1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or GRST. September 2005 SCPS110 113 ExCA Compatibilty Registers (Function 0) 5.5 ExCA Card Status-Change Register The ExCA card status-change register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card functions. The register enables these interrupt sources to generate an interrupt to the host. When the interrupt source is disabled, the corresponding bit in this register always reads 0b. When an interrupt source is enabled, the corresponding bit in this register is set to indicate that the interrupt source is active. After generating the interrupt to the host, the interrupt service routine must read this register to determine the source of the interrupt. The interrupt service routine is responsible for resetting the bits in this register as well. Resetting a bit is accomplished by one of two methods: a read of this register or an explicit writeback of 1b to the status bit. The choice of these two methods is based on bit 2 (interrupt flag clear mode select) in the ExCA global control register (CB offset 81Eh, see Section 5.20). See Table 5-7 for a complete description of the register contents. ExCA register offset: Register type: Default value: CardBus socket address + 804h; Read-only 00h Card A ExCA offset 04h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 5-7. ExCA Card Status-Change Register Description BIT SIGNAL TYPE 7-4 RSVD R Reserved. Bits 7-4 return 0h when read. R Card detect change. Bit 3 indicates whether a change on CD1 or CD2 occurred at the PC Card interface. This bit is encoded as: 0 = No change detected on either CD1 or CD2 1 = Change detected on either CD1 or CD2 3 2 CDCHANGE READYCHANGE R FUNCTION Ready change. When a 16-bit memory is installed in the socket, bit 2 includes whether the source of a PCIxx12 interrupt was due to a change on READY at the PC Card interface, indicating that the PC Card is now ready to accept new data. This bit is encoded as: 0 = No low-to-high transition detected on READY (default) 1 = Detected low-to-high transition on READY When a 16-bit I/O card is installed, bit 2 is always 0b. 1 BATWARN R Battery warning change. When a 16-bit memory card is installed in the socket, bit 1 indicates whether the source of a PCIxx12 interrupt was due to a battery-low warning condition. This bit is encoded as: 0 = No battery warning condition (default) 1 = Detected battery warning condition When a 16-bit I/O card is installed, bit 1 is always 0b. 0 BATDEAD R Battery dead or status change. When a 16-bit memory card is installed in the socket, bit 0 indicates whether the source of a PCIxx12 interrupt was due to a battery dead condition. This bit is encoded as: 0 = STSCHG deasserted (default) 1 = STSCHG asserted Ring indicate. When the PCIxx12 is configured for ring indicate operation, bit 0 indicates the status of RI. These are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then these bits are cleared by the assertion of PRST or GRST. 114 SCPS110 September 2005 ExCA Compatibilty Registers (Function 0) 5.6 ExCA Card Status-Change Interrupt Configuration Register This register controls interrupt routing for CSC interrupts, as well as masks/unmasks CSC interrupt sources. See Table 5-8 for a complete description of the register contents. ExCA register offset: Register type: Default value: CardBus Socket Address + 805h: Card A ExCA Offset 05h Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 5-8. ExCA Card Status-Change Interrupt Configuration Register Description BIT SIGNAL TYPE FUNCTION Interrupt select for card status change. These bits select the interrupt routing for card status-change interrupts. This field is encoded as: 7-4 CSCSELECT RW 3 CDEN RW 0000 = CSC interrupts routed to PCI interrupts if bit 5 of the diagnostic register (PCI offset 93h) is set to 1b. In this case bit 4 of ExCA 803 is a don't care. This is the default setting. 0000 = No ISA interrupt routing if bit 5 of the diagnostic register (PCI offset 93h) is set to 0b. In this case, CSC interrupts are routed to PCI interrupts by setting bit 4 of ExCA 803h to 1b. 0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0110 = IRQ6 enabled 0111 = IRQ7 enabled 1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled Card detect enable. Enables interrupts on CD1 or CD2 changes. This bit is encoded as: 2 1 0 READYEN BATWARNEN BATDEADEN RW RW RW 0 = Disables interrupts on CD1 or CD2 line changes (default) 1 = Enables interrupts on CD1 or CD2 line changes Ready enable. This bit enables/disables a low-to-high transition on the PC Card READY signal to generate a host interrupt. This interrupt source is considered a card status change. This bit is encoded as: 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation Battery warning enable. This bit enables/disables a battery warning condition to generate a CSC interrupt. This bit is encoded as: 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation Battery dead enable. This bit enables/disables a battery dead condition on a memory PC Card or assertion of the STSCHG I/O PC Card signal to generate a CSC interrupt. 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or GRST. September 2005 SCPS110 115 ExCA Compatibilty Registers (Function 0) 5.7 ExCA Address Window Enable Register The ExCA address window enable register enables/disables the memory and I/O windows to the 16-bit PC Card. By default, all windows to the card are disabled. The controller does not acknowledge PCI memory or I/O cycles to the card if the corresponding enable bit in this register is 0b, regardless of the programming of the memory or I/O window start/end/offset address registers. See Table 5-9 for a complete description of the register contents. ExCA register offset: Register type: Default value: CardBus socket address + 806h; Read-only, Read/Write 00h Card A ExCA offset 06h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 5-9. ExCA Address Window Enable Register Description BIT SIGNAL TYPE 7 IOWIN1EN RW I/O window 1 enable. Bit 7 enables/disables I/O window 1 for the PC Card. This bit is encoded as: 0 = I/O window 1 disabled (default) 1 = I/O window 1 enabled 6 IOWIN0EN RW I/O window 0 enable. Bit 6 enables/disables I/O window 0 for the PC Card. This bit is encoded as: 0 = I/O window 0 disabled (default) 1 = I/O window 0 enabled 5 RSVD R 4 Reserved. Bit 5 returns 0b when read. RW Memory window 4 enable. Bit 4 enables/disables memory window 4 for the PC Card. This bit is encoded as: 0 = Memory window 4 disabled (default) 1 = Memory window 4 enabled 3 MEMWIN3EN RW Memory window 3 enable. Bit 3 enables/disables memory window 3 for the PC Card. This bit is encoded as: 0 = Memory window 3 disabled (default) 1 = Memory window 3 enabled 2 MEMWIN2EN RW Memory window 2 enable. Bit 2 enables/disables memory window 2 for the PC Card. This bit is encoded as: 0 = Memory window 2 disabled (default) 1 = Memory window 2 enabled 1 MEMWIN1EN RW Memory window 1 enable. Bit 1 enables/disables memory window 1 for the PC Card. This bit is encoded as: 0 = Memory window 1 disabled (default) 1 = Memory window 1 enabled RW Memory window 0 enable. Bit 0 enables/disables memory window 0 for the PC Card. This bit is encoded as: 0 = Memory window 0 disabled (default) 1 = Memory window 0 enabled 0 116 MEMWIN4EN FUNCTION MEMWIN0EN SCPS110 September 2005 ExCA Compatibilty Registers (Function 0) 5.8 ExCA I/O Window Control Register The ExCA I/O window control register contains parameters related to I/O window sizing and cycle timing. See Table 5-10 for a complete description of the register contents. ExCA register offset: Register type: Default value: CardBus socket address + 807h: Read/Write 00h Card A ExCA offset 07h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 5-10. ExCA I/O Window Control Register Description BIT 7 6 5 4 3 2 1 0 SIGNAL WAITSTATE1 ZEROWS1 IOSIS16W1 DATASIZE1 WAITSTATE0 ZEROWS0 IOSIS16W0 DATASIZE0 September 2005 TYPE FUNCTION RW I/O window 1 wait state. Bit 7 controls the I/O window 1 wait state for 16-bit I/O accesses. Bit 7 has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state. RW I/O window 1 zero wait state. Bit 6 controls the I/O window 1 wait state for 8-bit I/O accesses. Bit 6 has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. RW I/O window 1 IOIS16 source. Bit 5 controls the I/O window 1 automatic data-sizing feature that uses IOIS16 from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as: 0 = Window data width determined by DATASIZE1, bit 4 (default). 1 = Window data width determined by IOIS16. RW I/O window 1 data size. Bit 4 controls the I/O window 1 data size. Bit 4 is ignored if bit 5 (IOSIS16W1) is set. This bit is encoded as: 0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits. RW I/O window 0 wait state. Bit 3 controls the I/O window 0 wait state for 16-bit I/O accesses. Bit 3 has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state. RW I/O window 0 zero wait state. Bit 2 controls the I/O window 0 wait state for 8-bit I/O accesses. Bit 2 has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. RW I/O window 0 IOIS16 source. Bit 1 controls the I/O window 0 automatic data sizing feature that uses IOIS16 from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as: 0 = Window data width is determined by DATASIZE0, bit 0 (default). 1 = Window data width is determined by IOIS16. RW I/O window 0 data size. Bit 0 controls the I/O window 0 data size. Bit 0 is ignored if bit 1 (IOSIS16W0) is set. This bit is encoded as: 0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits. SCPS110 117 ExCA Compatibilty Registers (Function 0) 5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the start address. Register: ExCA register offset: Register: ExCA register offset: Register type: Default value: ExCA I/O window 0 start-address low-byte CardBus Socket Address + 808h: Card A ExCA Offset 08h ExCA I/O window 1 start-address low-byte CardBus Socket Address + 80Ch: Card A ExCA Offset 0Ch Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers These registers contain the high byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of these registers correspond to the upper 8 bits of the start address. Register: ExCA register offset: Register: ExCA register offset: Register type: Default value: ExCA I/O window 0 start-address high-byte CardBus Socket Address + 809h: Card A ExCA Offset 09h ExCA I/O window 1 start-address high-byte CardBus Socket Address + 80Dh: Card A ExCA Offset 0Dh Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the start address. Register: ExCA register offset: Register: ExCA register offset: Register type: Default value: ExCA I/O window 0 end-address low-byte CardBus Socket Address + 80Ah: Card A ExCA Offset 0Ah ExCA I/O window 1 end-address low-byte CardBus Socket Address + 80Eh: Card A ExCA Offset 0Eh Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 118 SCPS110 September 2005 ExCA Compatibilty Registers (Function 0) 5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers These registers contain the high byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these registers correspond to the upper 8 bits of the end address. Register: ExCA register offset: Register: ExCA register offset: Register type: Default value: ExCA I/O window 0 end-address high-byte CardBus Socket Address + 80Bh: Card A ExCA Offset 0Bh ExCA I/O window 1 end-address high-byte CardBus Socket Address + 80Fh: Card A ExCA Offset 0Fh Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 5.13 ExCA Memory Windows 0-4 Start-Address Low-Byte Registers These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19-A12 of the start address. Register: ExCA register offset: Register: ExCA register offset: Register: ExCA register offset: Register: ExCA register offset: Register: ExCA register offset: Register type: Default value: ExCA memory window 0 start-address low-byte CardBus Socket Address + 810h: Card A ExCA Offset 10h ExCA memory window 1 start-address low-byte CardBus Socket Address + 818h: Card A ExCA Offset 18h ExCA memory window 2 start-address low-byte CardBus Socket Address + 820h: Card A ExCA Offset 20h ExCA memory window 3 start-address low-byte CardBus Socket Address + 828h: Card A ExCA Offset 28h ExCA memory window 4 start-address low-byte CardBus Socket Address + 830h: Card A ExCA Offset 30h Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 September 2005 SCPS110 119 ExCA Compatibilty Registers (Function 0) 5.14 ExCA Memory Windows 0-4 Start-Address High-Byte Registers These registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The lower 4 bits of these registers correspond to bits A23-A20 of the start address. In addition, the memory window data width and wait states are set in this register. See Table 5-11 for a complete description of the register contents. Register: ExCA register offset: Register: ExCA register offset: Register: ExCA register offset: Register: ExCA register offset: Register: ExCA register offset: Register type: Default value: ExCA memory window 0 start-address high-byte CardBus Socket Address + 811h: Card A ExCA Offset 11h ExCA memory window 1 start-address high-byte CardBus Socket Address + 819h: Card A ExCA Offset 19h ExCA memory window 2 start-address high-byte CardBus Socket Address + 821h: Card A ExCA Offset 21h ExCA memory window 3 start-address high-byte CardBus Socket Address + 829h: Card A ExCA Offset 29h ExCA memory window 4 start-address high-byte CardBus Socket Address + 831h: Card A ExCA Offset 31h Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 5-11. ExCA Memory Windows 0-4 Start-Address High-Byte Registers Description BIT SIGNAL TYPE 7 DATASIZE RW FUNCTION This bit controls the memory window data width. This bit is encoded as: 0 = Window data width is 8 bits (default) 1 = Window data width is 16 bits Zero wait-state. This bit controls the memory window wait state for 8- and 16-bit accesses. This wait-state timing emulates the ISA wait state used by the 82365SL-DF. This bit is encoded as: 6 ZEROWAIT RW 5-4 SCRATCH RW Scratch pad bits. These bits have no effect on memory window operation. 3-0 STAHN RW Start address high-nibble. These bits represent the upper address bits A23-A20 of the memory window start address. 0 = 8- and 16-bit cycles have standard length (default). 1 = 8-bit cycles reduced to equivalent of three ISA cycles 16-bit cycles reduced to the equivalent of two ISA cycles 5.15 ExCA Memory Windows 0-4 End-Address Low-Byte Registers These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19-A12 of the end address. Register: ExCA register offset: Register: ExCA register offset: Register: ExCA register offset: Register: ExCA register offset: Register: ExCA register offset: Register type: Default value: ExCA memory window 0 end-address low-byte CardBus Socket Address + 812h: Card A ExCA Offset 12h ExCA memory window 1 end-address low-byte CardBus Socket Address + 81Ah: Card A ExCA Offset 1Ah ExCA memory window 2 end-address low-byte CardBus Socket Address + 822h: Card A ExCA Offset 22h ExCA memory window 3 end-address low-byte CardBus Socket Address + 82Ah: Card A ExCA Offset 2Ah ExCA memory window 4 end-address low-byte CardBus Socket Address + 832h: Card A ExCA Offset 32h Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 120 SCPS110 September 2005 ExCA Compatibilty Registers (Function 0) 5.16 ExCA Memory Windows 0-4 End-Address High-Byte Registers These registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The lower 4 bits of these registers correspond to bits A23-A20 of the end address. In addition, the memory window wait states are set in this register. See Table 5-12 for a complete description of the register contents. Register: ExCA register offset: Register: ExCA register offset: Register: ExCA register offset: Register: ExCA register offset: Register: ExCA register offset: Register type: Default value: ExCA memory window 0 end-address high-byte CardBus Socket Address + 813h: Card A ExCA Offset 13h ExCA memory window 1 end-address high-byte CardBus Socket Address + 81Bh: Card A ExCA Offset 1Bh ExCA memory window 2 end-address high-byte CardBus Socket Address + 823h: Card A ExCA Offset 23h ExCA memory window 3 end-address high-byte CardBus Socket Address + 82Bh: Card A ExCA Offset 2Bh ExCA Memory window 4 end-address high-byte CardBus Socket Address + 833h: Card A ExCA Offset 33h Read/Write, Read-only 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 5-12. ExCA Memory Windows 0-4 End-Address High-Byte Registers Description BIT SIGNAL TYPE FUNCTION Wait state. These bits specify the number of equivalent ISA wait states to be added to 16-bit memory accesses. The number of wait states added is equal to the binary value of these 2 bits. 7-6 MEMWS RW 5-4 RSVD R 3-0 ENDHN RW Reserved. These bits return 00b when read. Writes have no effect. End-address high nibble. These bits represent the upper address bits A23-A20 of the memory window end address. 5.17 ExCA Memory Windows 0-4 Offset-Address Low-Byte Registers These registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19-A12 of the offset address. Register: ExCA register offset: Register: ExCA register offset: Register: ExCA register offset: Register: ExCA register offset: Register: ExCA register offset: Register type: Default value: ExCA memory window 0 offset-address low-byte CardBus Socket Address + 814h: Card A ExCA Offset 14h ExCA memory window 1 offset-address low-byte CardBus Socket Address + 81Ch: Card A ExCA Offset 1Ch ExCA memory window 2 offset-address low-byte CardBus Socket Address + 824h: Card A ExCA Offset 24h ExCA memory window 3 offset-address low-byte CardBus Socket Address + 82Ch: Card A ExCA Offset 2Ch ExCA memory window 4 offset-address low-byte CardBus Socket Address + 834h: Card A ExCA Offset 34h Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 September 2005 SCPS110 121 ExCA Compatibilty Registers (Function 0) 5.18 ExCA Memory Windows 0-4 Offset-Address High-Byte Registers These registers contain the high 6 bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. The lower 6 bits of these registers correspond to bits A25-A20 of the offset address. In addition, the write protection and common/attribute memory configurations are set in this register. See Table 5-13 for a complete description of the register contents. Register: ExCA register offset: Register: ExCA register offset: Register: ExCA register offset: Register: ExCA register offset: Register: ExCA register offset: Register type: Default value: ExCA memory window 0 offset-address high-byte CardBus Socket Address + 815h: Card A ExCA Offset 15h ExCA memory window 1 offset-address high-byte CardBus Socket Address + 81Dh: Card A ExCA Offset 1Dh ExCA memory window 2 offset-address high-byte CardBus Socket Address + 825h: Card A ExCA Offset 25h ExCA memory window 3 offset-address high-byte CardBus Socket Address + 82Dh: Card A ExCA Offset 2Dh ExCA memory window 4 offset-address high-byte CardBus Socket Address + 835h: Card A ExCA Offset 35h Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 5-13. ExCA Memory Windows 0-4 Offset-Address High-Byte Registers Description BIT 7 SIGNAL WINWP TYPE RW 6 REG RW 5-0 OFFHB RW 122 SCPS110 FUNCTION Write protect. This bit specifies whether write operations to this memory window are enabled. This bit is encoded as: 0 = Write operations are allowed (default). 1 = Write operations are not allowed. This bit specifies whether this memory window is mapped to card attribute or common memory. This bit is encoded as: 0 = Memory window is mapped to common memory (default). 1 = Memory window is mapped to attribute memory. Offset-address high byte. These bits represent the upper address bits A25-A20 of the memory window offset address. September 2005 ExCA Compatibilty Registers (Function 0) 5.19 ExCA Card Detect and General Control Register This register controls how the ExCA registers for the socket respond to card removal. It also reports the status of the VS1 and VS2 signals at the PC Card interface. Table 5-14 describes each bit in the ExCA card detect and general control register. ExCA register offset: Register type: Default value: CardBus Socket Address + 816h: Card A ExCA Offset 16h Read-only, Write-only, Read/Write XX00 0000b BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE X X 0 0 0 0 0 0 Table 5-14. ExCA Card Detect and General Control Register Description BIT 7 6 SIGNAL VS2STAT VS1STAT TYPE R R FUNCTION VS2. This bit reports the current state of the VS2 signal at the PC Card interface, and, therefore, does not have a default value. 0 = VS2 is low. 1 = VS2 is high. VS1. This bit reports the current state of the VS1 signal at the PC Card interface, and, therefore, does not have a default value. 0 = VS1 is low. 1 = VS1 is high. Software card detect interrupt. If card detect enable, bit 3 in the ExCA card status change interrupt configuration register (ExCA offset 805h, see Section 5.6) is set, then writing a 1b to this bit causes a card-detect card-status-change interrupt for the associated card socket. 5 SWCSC W If the card-detect enable bit is cleared to 0b in the ExCA card status-change interrupt configuration register (ExCA offset 805h, see Section 5.6), then writing a 1b to the software card-detect interrupt bit has no effect. This bit is write-only. A read operation of this bit always returns 0b. Writing a 1b to this bit also clears it. If bit 2 of the ExCA global control register (ExCA offset 81Eh, see Section 5.20) is set and a 1b is written to clear bit 3 of the ExCA card status change interrupt register, then this bit also is cleared. 4 CDRESUME RW Card detect resume enable. If this bit is set to 1b and a card detect change has been detected on the CD1 and CD2 inputs, then the RI_OUT output goes from high to low. The RI_OUT remains low until the card status change bit in the ExCA card status-change register (ExCA offset 804h, see Section 5.5) is cleared. If this bit is 0b, then the card detect resume functionality is disabled. 0 = Card detect resume disabled (default) 1 = Card detect resume enabled 3-2 RSVD R 1 REGCONFIG RW 0 RSVD R These bits return 00b when read. Writes have no effect. Register configuration upon card removal. This bit controls how the ExCA registers for the socket react to a card removal event. This bit is encoded as: 0 = No change to ExCA registers upon card removal (default) 1 = Reset ExCA registers upon card removal This bit returns 0b when read. A write has no effect. One or more bits in this register are cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or GRST. September 2005 SCPS110 123 ExCA Compatibilty Registers (Function 0) 5.20 ExCA Global Control Register This register controls both PC Card sockets, and is not duplicated for each socket. The host interrupt mode bits in this register are retained for 82365SL-DF compatibility. See Table 5-15 for a complete description of the register contents. ExCA register offset: Register type: Default value: CardBus Socket Address + 81Eh: Card A ExCA Offset 1Eh Read-only, Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 5-15. ExCA Global Control Register Description BIT SIGNAL TYPE 7-5 RSVD R 4 3 2 1 0 INTMODEB RW INTMODEA RW IFCMODE RW CSCMODE RW PWRDWN RW FUNCTION These bits return 000b when read. Writes have no effect. Level/edge interrupt mode select, card B. This bit selects the signaling mode for the PCIxx12 host interrupt for card B interrupts. This bit is encoded as: 0 = Host interrupt is edge mode (default). 1 = Host interrupt is level mode. Level/edge interrupt mode select, card A. This bit selects the signaling mode for the PCIxx12 host interrupt for card A interrupts. This bit is encoded as: 0 = Host interrupt is edge-mode (default). 1 = Host interrupt is level-mode. Interrupt flag clear mode select. This bit selects the interrupt flag clear mechanism for the flags in the ExCA card status change register. This bit is encoded as: 0 = Interrupt flags cleared by read of CSC register (default) 1 = Interrupt flags cleared by explicit writeback of 1 Card status change level/edge mode select. This bit selects the signaling mode for the PCIxx12 host interrupt for card status changes. This bit is encoded as: 0 = Host interrupt is edge-mode (default). 1 = Host interrupt is level-mode. Power-down mode select. When this bit is set to 1b, the controller is in power-down mode. In power-down mode the PCIxx12 card outputs are placed in a high-impedance state until an active cycle is executed on the card interface. Following an active cycle the outputs are again placed in a high-impedance state. The controller still receives functional interrupts and/or card status change interrupts; however, an actual card access is required to wake up the interface. This bit is encoded as: 0 = Power-down mode disabled (default) 1 = Power-down mode enabled One or more bits in this register are cleared only by the assertion of GRST. 5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the offset address, and bit 0 is always 0b. Register: ExCA register offset: Register: ExCA register offset: Register type: Default value: ExCA I/O window 0 offset-address low-byte CardBus Socket Address + 836h: Card A ExCA Offset 36h ExCA I/O window 1 offset-address low-byte CardBus Socket Address + 838h: Card A ExCA Offset 38h Read/Write, Read-only 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 124 SCPS110 September 2005 ExCA Compatibilty Registers (Function 0) 5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers These registers contain the high byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of these registers correspond to the upper 8 bits of the offset address. Register: ExCA register offset: Register: ExCA register offset: Register type: Default value: ExCA I/O window 0 offset-address high-byte CardBus Socket Address + 837h: Card A ExCA Offset 37h ExCA I/O window 1 offset-address high-byte CardBus Socket Address + 839h: Card A ExCA Offset 39h Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 5.23 ExCA Memory Windows 0-4 Page Registers The upper 8 bits of a 4-byte PCI memory address are compared to the contents of this register when decoding addresses for 16-bit memory windows. Each window has its own page register, all of which default to 00h. By programming this register to a nonzero value, host software can locate 16-bit memory windows in any one of 256 16-Mbyte regions in the 4-gigabyte PCI address space. These registers are only accessible when the ExCA registers are memory-mapped, that is, these registers may not be accessed using the index/data I/O scheme. ExCA register offset: Register type: Default value: CardBus Socket Address + 840h, 841h, 842h, 843h, 844h Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 September 2005 SCPS110 125 CardBus Socket Registers (Function 0) 6 CardBus Socket Registers (Function 0) The 1997 PC Card Standard requires a CardBus socket controller to provide five 32-bit registers that report and control socket-specific functions. The PCIxx12 controller provides the CardBus socket/ExCA base address register (PCI offset 10h, see Section 4.12) to locate these CardBus socket registers in PCI memory address space. Table 6-1 gives the location of the socket registers in relation to the CardBus socket/ExCA base address. In addition to the five required registers, the controller implements a register at offset 20h that provides power management control for the socket. PCIxx12 Configuration Registers Offset Host Memory Space Offset 00h CardBus Socket/ExCA Base Address 10h 16-Bit Legacy-Mode Base Address 44h CardBus Socket A Registers 20h ExCA Registers Card A 800h 844h Offsets are from the CardBus socket/ExCA base address register's base address. Figure 6-1. Accessing CardBus Socket Registers Through PCI Memory Table 6-1. CardBus Socket Registers REGISTER NAME OFFSET Socket event 00h Socket mask 04h Socket present state 08h Socket force event 0Ch Socket control 10h Reserved 14h-1Ch Socket power management 20h One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then these bits are cleared by the assertion of PRST or GRST. One or more bits in this register are cleared only by the assertion of GRST. 126 SCPS110 September 2005 CardBus Socket Registers (Function 0) 6.1 Socket Event Register This register indicates a change in socket status has occurred. These bits do not indicate what the change is, only that one has occurred. Software must read the socket present state register for current status. Each bit in this register can be cleared by writing 1b to that bit. The bits in this register can be set to 1b by software through writing 1b to the corresponding bit in the socket force event register. All bits in this register are cleared by PCI reset. They can be immediately set again, if, when coming out of PC Card reset, the bridge finds the status unchanged (i.e., CSTSCHG reasserted or card detect is still true). Software needs to clear this register before enabling interrupts. If it is not cleared and interrupts are enabled, then an unmasked interrupt is generated based on any bit that is set. See Table 6-2 for a complete description of the register contents. CardBus register offset: Register type: Default value: CardBus Socket Address + 00h Read-only, Read/Write to Clear 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6-2. Socket Event Register Description BIT SIGNAL TYPE 31-4 RSVD R 3 PWREVENT RWC Power cycle. This bit is set when the controller detects that the PWRCYCLE bit in the socket present state register (offset 08h, see Section 6.3) has changed. This bit is cleared by writing 1b. 2 CD2EVENT RWC CCD2. This bit is set when the controller detects that the CDETECT2 field in the socket present state register (offset 08h, see Section 6.3) has changed. This bit is cleared by writing 1b. 1 CD1EVENT RWC CCD1. This bit is set when the controller detects that the CDETECT1 field in the socket present state register (offset 08h, see Section 6.3) has changed. This bit is cleared by writing 1b. RWC CSTSCHG. This bit is set when the CARDSTS field in the socket present state register (offset 08h, see Section 6.3) has changed state. For CardBus cards, this bit is set on the rising edge of the CSTSCHG signal. For 16-bit PC Cards, this bit is set on both transitions of the CSTSCHG signal. This bit is reset by writing 1b. 0 CSTSEVENT FUNCTION These bits return 000 0000h when read. This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or GRST. September 2005 SCPS110 127 CardBus Socket Registers (Function 0) 6.2 Socket Mask Register This register allows software to control the CardBus card events which generate a status change interrupt. The state of these mask bits does not prevent the corresponding bits from reacting in the socket event register (offset 00h, see Section 6.1). See Table 6-3 for a complete description of the register contents. CardBus register offset: Register type: Default value: CardBus Socket Address + 04h Read-only, Read/Write 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6-3. Socket Mask Register Description BIT SIGNAL TYPE 31-4 RSVD R 3 PWRMASK RW FUNCTION These bits return 000 0000h when read. Power cycle. This bit masks the PWRCYCLE bit in the socket present state register (offset 08h, see Section 6.3) from causing a status change interrupt. 0 = PWRCYCLE event does not cause a CSC interrupt (default). 1 = PWRCYCLE event causes a CSC interrupt. Card detect mask. These bits mask the CDETECT1 and CDETECT2 bits in the socket present state register (offset 08h, see Section 6.3) from causing a CSC interrupt. 2-1 0 CDMASK CSTSMASK RW RW 00 = Insertion/removal does not cause a CSC interrupt (default). 01 = Reserved (undefined) 10 = Reserved (undefined) 11 = Insertion/removal causes a CSC interrupt. CSTSCHG mask. This bit masks the CARDSTS field in the socket present state register (offset 08h, see Section 6.3) from causing a CSC interrupt. 0 = CARDSTS event does not cause a CSC interrupt (default). 1 = CARDSTS event causes a CSC interrupt. This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or GRST. 128 SCPS110 September 2005 CardBus Socket Registers (Function 0) 6.3 Socket Present State Register This register reports information about the socket interface. Writes to the socket force event register (offset 0Ch, see Section 6.4), as well as general socket interface status, are reflected here. Information about PC Card VCC support and card type is only updated at each insertion. Also note that the PCIxx12 controller uses the CCD1 and CCD2 signals during card identification, and changes on these signals during this operation are not reflected in this register. CardBus register offset: Register type: Default value: CardBus Socket Address + 08h Read-only 3000 00XXh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 X 0 0 0 X X X Table 6-4. Socket Present State Register Description BIT SIGNAL TYPE FUNCTION 31 YVSOCKET R YV socket. This bit indicates whether or not the socket can supply VCC = Y.Y V to PC Cards. The controller does not support Y.Y-V VCC; therefore, this bit is always reset unless overridden by the socket force event register (offset 0Ch, see Section 6.4). This bit defaults to 0b. 30 XVSOCKET R XV socket. This bit indicates whether or not the socket can supply VCC = X.X V to PC Cards. The controller does not support X.X-V VCC; therefore, this bit is always reset unless overridden by the socket force event register (offset 0Ch, see Section 6.4). This bit defaults to 0b. 29 3VSOCKET R 3-V socket. This bit indicates whether or not the socket can supply VCC = 3.3 Vdc to PC Cards. The controller does support 3.3-V VCC; therefore, this bit is always set unless overridden by the socket force event register (offset 0Ch, see Section 6.4). 28 5VSOCKET R 5-V socket. This bit indicates whether or not the socket can supply VCC = 5 Vdc to PC Cards. The PCI712 controller does support 5-V VCC; therefore, this bit is always set unless overridden by bit 6 of the device control register (PCI offset 92h, see Section 4.38). 27-14 RSVD R These bits return 0s when read. 13 YVCARD R YV card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = Y.Y Vdc. This bit can be set by writing a 1b to the corresponding bit in the socket force event register (offset 0Ch, see Section 6.4). 12 XVCARD R XV card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = X.X Vdc. This bit can be set by writing a 1b to the corresponding bit in the socket force event register (offset 0Ch, see Section 6.4). 11 3VCARD R 3-V card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = 3.3 Vdc. This bit can be set by writing a 1b to the corresponding bit in the socket force event register (offset 0Ch, see Section 6.4). 10 5VCARD R 5-V card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = 5 Vdc. This bit can be set by writing a 1b to the corresponding bit in the socket force event register (offset 0Ch, see Section 6.4). 9 BADVCCREQ R 8 DATALOST R Bad VCC request. This bit indicates that the host software has requested that the socket be powered at an invalid voltage. 0 = Normal operation (default) 1 = Invalid VCC request by host software Data lost. This bit indicates that a PC Card removal event may have caused lost data because the cycle did not terminate properly or because write data still resides in the controller. 0 = Normal operation (default) 1 = Potential data loss due to card removal One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then these bits are cleared by the assertion of PRST or GRST. September 2005 SCPS110 129 CardBus Socket Registers (Function 0) Table 6-4. Socket Present State Register Description (Continued) BIT SIGNAL TYPE FUNCTION 7 NOTACARD R Not a card. This bit indicates that an unrecognizable PC Card has been inserted in the socket. This bit is not updated until a valid PC Card is inserted into the socket. 0 = Normal operation (default) 1 = Unrecognizable PC Card detected 6 IREQCINT R READY(IREQ)//CINT. This bit indicates the current status of the READY(IREQ)//CINT signal at the PC Card interface. 0 = READY(IREQ)//CINT is low. 1 = READY(IREQ)//CINT is high. 5 CBCARD R CardBus card detected. This bit indicates that a CardBus PC Card is inserted in the socket. This bit is not updated until another card interrogation sequence occurs (card insertion). 4 16BITCARD R 16-bit card detected. This bit indicates that a 16-bit PC Card is inserted in the socket. This bit is not updated until another card interrogation sequence occurs (card insertion). 3 PWRCYCLE R Power cycle. This bit indicates the status of each card powering request. This bit is encoded as: 0 = Socket is powered down (default). 1 = Socket is powered up. R CCD2. This bit reflects the current status of the CCD2 signal at the PC Card interface. Changes to this signal during card interrogation are not reflected here. 0 = CCD2 is low (PC Card may be present) 1 = CCD2 is high (PC Card not present) 2 CDETECT2 1 CDETECT1 R CCD1. This bit reflects the current status of the CCD1 signal at the PC Card interface. Changes to this signal during card interrogation are not reflected here. 0 = CCD1 is low (PC Card may be present). 1 = CCD1 is high (PC Card not present). 0 CARDSTS R CSTSCHG. This bit reflects the current status of the CSTSCHG signal at the PC Card interface. 0 = CSTSCHG is low. 1 = CSTSCHG is high. One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then these bits are cleared by the assertion of PRST or GRST. 130 SCPS110 September 2005 CardBus Socket Registers (Function 0) 6.4 Socket Force Event Register This register forces changes to the socket event register (offset 00h, see Section 6.1) and the socket present state register (offset 08h, see Section 6.3). The CVSTEST bit (bit 14) in this register must be written when forcing changes that require card interrogation. See Table 6-5 for a complete description of the register contents. CardBus register offset: Register type: Default value: CardBus Socket Address + 0Ch Read-only, Write-only 0000 XXXXh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE X X X X X X X X X X X X X X X X Table 6-5. Socket Force Event Register Description BIT SIGNAL TYPE 31-15 RSVD R Reserved. These bits return 0s when read. 14 CVSTEST W Card VS test. When this bit is set, the PCIxx12 controller reinterrogates the PC Card, updates the socket present state register (offset 08h, see Section 6.3), and re-enables the socket power control. 13 FYVCARD W Force YV card. Writes to this bit cause the YVCARD bit in the socket present state register (offset 08h, see Section 6.3) to be written. When set, this bit disables the socket power control. 12 FXVCARD W Force XV card. Writes to this bit cause the XVCARD bit in the socket present state register (offset 08h, see Section 6.3) to be written. When set, this bit disables the socket power control. 11 F3VCARD W Force 3-V card. Writes to this bit cause the 3VCARD bit in the socket present state register (offset 08h, see Section 6.3) to be written. When set, this bit disables the socket power control. 10 F5VCARD W Force 5-V card. Writes to this bit cause the 5VCARD bit in the socket present state register (offset 08h, see Section 6.3) to be written. When set, this bit disables the socket power control. 9 FBADVCCREQ W Force BadVccReq. Changes to the BADVCCREQ bit in the socket present state register (offset 08h, see Section 6.3) can be made by writing this bit. 8 FDATALOST W Force data lost. Writes to this bit cause the DATALOST bit in the socket present state register (offset 08h, see Section 6.3) to be written. 7 FNOTACARD W Force not a card. Writes to this bit cause the NOTACARD bit in the socket present state register (offset 08h, see Section 6.3) to be written. 6 RSVD R This bit returns 0b when read. 5 FCBCARD W Force CardBus card. Writes to this bit cause the CBCARD bit in the socket present state register (offset 08h, see Section 6.3) to be written. 4 F16BITCARD W Force 16-bit card. Writes to this bit cause the 16BITCARD bit in the socket present state register (offset 08h, see Section 6.3) to be written. 3 FPWRCYCLE W Force power cycle. Writes to this bit cause the PWREVENT bit in the socket event register (offset 00h, see Section 6.1) to be written, and the PWRCYCLE bit in the socket present state register (offset 08h, see Section 6.3) is unaffected. 2 FCDETECT2 W Force CCD2. Writes to this bit cause the CD2EVENT bit in the socket event register (offset 00h, see Section 6.1) to be written, and the CDETECT2 bit in the socket present state register (offset 08h, see Section 6.3) is unaffected. 1 FCDETECT1 W Force CCD1. Writes to this bit cause the CD1EVENT bit in the socket event register (offset 00h, see Section 6.1) to be written, and the CDETECT1 bit in the socket present state register (offset 08h, see Section 6.3) is unaffected. 0 FCARDSTS W Force CSTSCHG. Writes to this bit cause the CSTSEVENT bit in the socket event register (offset 00h, see Section 6.1) to be written. The CARDSTS bit in the socket present state register (offset 08h, see Section 6.3) is unaffected. September 2005 FUNCTION SCPS110 131 CardBus Socket Registers (Function 0) 6.5 Socket Control Register This register provides control of the voltages applied to the socket VPP and VCC. The PCIxx12 controller ensures that the socket is powered up only at acceptable voltages when a CardBus card is inserted. See Table 6-6 for a complete description of the register contents. CardBus register offset: Register type: Default value: CardBus Socket Address + 10h Read-only, Read/Write 0000 0400h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Table 6-6. Socket Control Register Description BIT SIGNAL TYPE FUNCTION 31-11 RSVD R These bits return 0s when read. 10 RSVD R This bit returns 1b when read. 9-8 RSVD R These bits return 00b when read. This bit controls how the CardBus clock run state machine decides when to stop the CardBus clock to the CardBus card: 7 STOPCLK RW 0 = The CardBus CLKRUN protocol can only attempt to stop/slow the CaredBus clock if the sockethas been idle for 8 clocks and the PCI CLKRUN protocol is preparing to stop/slow the PCI bus clock. 1 = The CardBus CLKRUN protocol can only attempt to stop/slow the CaredBus clock if the socket has been idle for 8 clocks, regardless of the state of the PCI CLKRUN signal. 6-4 VCCCTRL RW 3 RSVD R VCC control. These bits are used to request card VCC changes. 000 = Request power off (default) 100 = Request VCC = X.X V 001 = Reserved 101 = Request VCC = Y.Y V 010 = Request VCC = 5 V 110 = Reserved 011 = Request VCC = 3.3 V 111 = Reserved This bit returns 0b when read. VPP control. These bits request card VPP changes. 000 = Request power off (default) 100 = Request VPP = X.X V 2-0 VPPCTRL RW 001 = Request VPP = 12 V 101 = Request VPP = Y.Y V 010 = Request VPP = 5 V 110 = Reserved 011 = Request VPP = 3.3 V 111 = Reserved One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or GRST. 132 SCPS110 September 2005 CardBus Socket Registers (Function 0) 6.6 Socket Power Management Register This register provides power management control over the socket through a mechanism for slowing or stopping the clock on the card interface when the card is idle. See Table 6-7 for a complete description of the register contents. CardBus register offset: Register type: Default value: CardBus Socket Address + 20h Read-only, Read/Write 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6-7. Socket Power Management Register Description BIT SIGNAL TYPE 31-26 RSVD R FUNCTION Reserved. These bits return 00 0000b when read. Socket access status. This bit provides information on whether a socket access has occurred. This bit is cleared by a read access. 25 SKTACCES R 24 SKTMODE R 0 = Normal clock operation 1 = Clock frequency has changed. 23-17 RSVD R These bits return 000 0000b when read. 16 CLKCTRLEN RW 15-1 RSVD R 0 = No PC Card access has occurred (default). 1 = PC Card has been accessed. Socket mode status. This bit provides clock mode information. CardBus clock control enable. This bit, when set, enables clock control according to bit 0 (CLKCTRL). 0 CLKCTRL RW 0 = Clock control disabled (default) 1 = Clock control enabled These bits return 0s when read. CardBus clock control. This bit determines whether the CardBus CLKRUN protocol attempts to stop or slow the CardBus clock during idle states. The CLKCTRLEN bit enables this bit. 0 = Allows the CardBus CLKRUN protocol to attempt to stop the CardBus clock (default) 1 = Allows the CardBus CLKRUN protocol to attempt to slow the CardBus clock by a factor of 16. This bit is cleared only by the assertion of GRST. September 2005 SCPS110 133 OHCI Controller Programming Model 7 OHCI Controller Programming Model This section describes the internal PCI configuration registers used to program the PCIxx12 1394 open host controller interface. All registers are detailed in the same format: a brief description for each register is followed by the register offset and a bit table describing the reset state for each register. A bit description table, typically included when the register contains bits of more than one type or purpose, indicates bit field names, a detailed field description, and field access tags which appear in the type column. Table 4-1 describes the field access tags. The controller is a multifunction PCI device. The 1394 OHCI is integrated as PCI function 1. The function 1 configuration header is compliant with the PCI Local Bus Specification as a standard header. Table 7-1 illustrates the configuration header that includes both the predefined portion of the configuration space and the user-definable registers. Table 7-1. Function 1 Configuration Register Map REGISTER NAME OFFSET Device ID Vendor ID 00h Status Command 04h Class code BIST Header type Latency timer Revision ID 08h Cache line size 0Ch OHCI base address 10h TI extension base address 14h CardBus CIS base address 18h Reserved 1Ch-27h CardBus CIS pointer Subsystem ID 28h Subsystem vendor ID Reserved 30h PCI power management capabilities pointer Reserved Reserved Maximum latency Minimum grant Interrupt pin PM data Next item pointer PMCSR_BSE 34h 38h Interrupt line PCI OHCI control Power management capabilities 2Ch 3Ch 40h Capability ID Power management control and status 44h 48h Reserved 4Ch-EBh PCI PHY control ECh PCI miscellaneous configuration F0h Link enhancement control F4h Subsystem access F8h GPIO control FCh One or more bits in this register are cleared only by the assertion of GRST. 134 SCPS110 September 2005 OHCI Controller Programming Model 7.1 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch. Function 1 register offset: 00h Register type: Read-only Default value: 104Ch BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 7.2 Device ID Register The device ID register contains a value assigned to the controller by Texas Instruments. The device identification for the controller is 803Ah. Function 1 register offset: 02h Register type: Read-only Default value: 803Ah BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 September 2005 SCPS110 135 OHCI Controller Programming Model 7.3 Command Register The command register provides control over the interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 7-2 for a complete description of the register contents. Function 1 register offset: 04h Register type: Read/Write, Read-only Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 7-2. Command Register Description BIT FIELD NAME TYPE 15-11 RSVD R 10 INT_DISABLE RW INTx disable. When set to 1b, this bit disables the function from asserting interrupts on the INTx signals. 0 = INTx assertion is enabled (default) 1 = INTx assertion is disabled 9 FBB_ENB R Fast back-to-back enable. The controller does not generate fast back-to-back transactions; therefore, bit 9 returns 0b when read. 8 SERR_ENB RW SERR enable. When bit 8 is set to 1b, the SERR driver is enabled. SERR can be asserted after detecting an address parity error on the PCI bus. The default value for this bit is 0b. 7 RSVD R 6 PERR_ENB RW Parity error enable. When bit 6 is set to 1b, the controller is enabled to drive PERR response to parity errors through the PERR signal. The default value for this bit is 0b. 5 VGA_ENB R VGA palette snoop enable. The controller does not feature VGA palette snooping; therefore, bit 5 returns 0b when read. 4 MWI_ENB RW Memory write and invalidate enable. When bit 4 is set to 1b, the controller is enabled to generate MWI PCI bus commands. If this bit is cleared, then the controller generates memory write commands instead. The default value for this bit is 0b. 3 SPECIAL R Special cycle enable. The PCIxx12 function does not respond to special cycle transactions; therefore, bit 3 returns 0b when read. 2 MASTER_ENB RW Bus master enable. When bit 2 is set to 1b, the controller is enabled to initiate cycles on the PCI bus. The default value for this bit is 0b. 1 MEMORY_ENB RW Memory response enable. Setting bit 1 to 1b enables the controller to respond to memory cycles on the PCI bus. This bit must be set to access OHCI registers. The default value for this bit is 0b. 0 IO_ENB R I/O space enable. The controller does not implement any I/O-mapped functionality; therefore, bit 0 returns 0b when read. 136 SCPS110 DESCRIPTION Reserved. Bits 15-11 return 00000b when read. Reserved. Bit 7 returns 0b when read. September 2005 OHCI Controller Programming Model 7.4 Status Register The status register provides status over the interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 7-3 for a complete description of the register contents. Function 1 register offset: 06h Register type: Read/Clear/Update, Read-only Default value: 0210h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 Table 7-3. Status Register Description BIT FIELD NAME TYPE DESCRIPTION 15 PAR_ERR RCU Detected parity error. Bit 15 is set to 1b when either an address parity or data parity error is detected. 14 SYS_ERR RCU Signaled system error. Bit 14 is set to 1b when SERR is enabled and the controller has signaled a system error to the host. 13 MABORT RCU Received master abort. Bit 13 is set to 1b when a cycle initiated by the controller on the PCI bus has been terminated by a master abort. 12 TABORT_REC RCU Received target abort. Bit 12 is set to 1b when a cycle initiated by the controller on the PCI bus was terminated by a target abort. 11 TABORT_SIG RCU Signaled target abort. Bit 11 is set to 1b by the controller when it terminates a transaction on the PCI bus with a target abort. 10-9 PCI_SPEED R DEVSEL timing. Bits 10 and 9 encode the timing of DEVSEL and are hardwired to 01b, indicating that the controller asserts this signal at a medium speed on nonconfiguration cycle accesses. Data parity error detected. Bit 8 is set to 1b when the following conditions have been met: a. PERR was asserted by any PCI device including the controller. b. The controller was the bus master during the data parity error. c. Bit 6 (PERR_EN) in the command register at offset 04h in the PCI configuration space (see Section 7.3) is set to 1b. 8 DATAPAR RCU 7 FBB_CAP R Fast back-to-back capable. The controller cannot accept fast back-to-back transactions; therefore, bit 7 is hardwired to 0b. 6 UDF R User-definable features (UDF) supported. The controller does not support the UDF; therefore, bit 6 is hardwired to 0b. 5 66MHZ R 66-MHz capable. The controller operates at a maximum PCLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0b. 4 CAPLIST R Capabilities list. Bit 4 returns 1b when read, indicating that capabilities additional to standard PCI are implemented. The linked list of PCI power-management capabilities is implemented in this function. 3 INT_STATUS RU Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE) in the command register (see Section 7.3) is 0b and this bit is 1b, is the function's INTx signal asserted. Setting the INT_DISABLE bit to 1b has no effect on the state of this bit. 2-0 RSVD R September 2005 Reserved. Bits 2-0 return 000b when read. SCPS110 137 OHCI Controller Programming Model 7.5 Class Code and Revision ID Register The class code and revision ID register categorizes the controller as a serial bus controller (0Ch), controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the least significant byte. See Table 7-4 for a complete description of the register contents. Function 1 register offset: 08h Register type: Read-only Default value: 0C00 1000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Table 7-4. Class Code and Revision ID Register Description BIT FIELD NAME TYPE DESCRIPTION 31-24 BASECLASS R Base class. This field returns 0Ch when read, which broadly classifies the function as a serial bus controller. 23-16 SUBCLASS R Subclass. This field returns 00h when read, which specifically classifies the function as controlling an IEEE 1394 serial bus. 15-8 PGMIF R Programming interface. This field returns 10h when read, which indicates that the programming model is compliant with the 1394 Open Host Controller Interface Specification. 7-0 CHIPREV R Silicon revision. This field returns 00h when read, which indicates the silicon revision of the controller. 7.6 Latency Timer and Class Cache Line Size Register The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the controller. See Table 7-5 for a complete description of the register contents. Function 1 register offset: 0Ch Register type: Read/Write Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 7-5. Latency Timer and Class Cache Line Size Register Description BIT FIELD NAME TYPE DESCRIPTION 15-8 LATENCY_TIMER RW PCI latency timer. The value in this register specifies the latency timer for the controller, in units of PCI clock cycles. When the controller is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires before the transaction has terminated, then the controller terminates the transaction when its GNT is deasserted. The default value for this field is 00h. 7-0 CACHELINE_SZ RW Cache line size. This value is used by the controller during memory write and invalidate, memory-read line, and memory-read multiple transactions. The default value for this field is 00h. 138 SCPS110 September 2005 OHCI Controller Programming Model 7.7 Header Type and BIST Register The header type and built-in self-test (BIST) register indicates the PCI header type and no built-in self-test. See Table 7-6 for a complete description of the register contents. Function 1 register offset: 0Eh Register type: Read-only Default value: 0080h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Table 7-6. Header Type and BIST Register Description BIT FIELD NAME TYPE DESCRIPTION 15-8 BIST R Built-in self-test. The controller does not include a BIST; therefore, this field returns 00h when read. 7-0 HEADER_TYPE R PCI header type. The controller includes the standard PCI header, which is communicated by returning 80h when this field is read. 7.8 OHCI Base Address Register The OHCI base address register is programmed with a base address referencing the memory-mapped OHCI control. When BIOS writes FFFF FFFFh to this register, the value read back is FFFF F800h, indicating that at least 2K bytes of memory address space are required for the OHCI registers. See Table 7-7 for a complete description of the register contents. Function 1 register offset: 10h Register type: Read/Write, Read-only Default value: 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 7-7. OHCI Base Address Register Description BIT FIELD NAME TYPE DESCRIPTION 31-11 OHCIREG_PTR RW OHCI register pointer. This field specifies the upper 21 bits of the 32-bit OHCI base address register. The default value for this field is all 0s. 10-4 OHCI_SZ R OHCI register size. This field returns 000 0000b when read, indicating that the OHCI registers require a 2K-byte region of memory. 3 OHCI_PF R OHCI register prefetch. Bit 3 returns 0b when read, indicating that the OHCI registers are nonprefetchable. 2-1 OHCI_MEMTYPE R OHCI memory type. This field returns 00b when read, indicating that the OHCI base address register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. 0 OHCI_MEM R OHCI memory indicator. Bit 0 returns 0b when read, indicating that the OHCI registers are mapped into system memory space. September 2005 SCPS110 139 OHCI Controller Programming Model 7.9 TI Extension Base Address Register The TI extension base address register is programmed with a base address referencing the memory-mapped TI extension registers. When BIOS writes FFFF FFFFh to this register, the value read back is FFFF C000h, indicating that at least 16K bytes of memory address space are required for the TI registers. See Table 7-8 for a complete description of the register contents. Function 1 register offset: 14h Register type: Read/Write, Read-only Default value: 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 7-8. TI Base Address Register Description BIT FIELD NAME TYPE DESCRIPTION 31-14 TIREG_PTR RW TI register pointer. This field specifies the upper 18 bits of the 32-bit TI base address register. The default value for this field is all 0s. 13-4 TI_SZ R TI register size. This field returns 0s when read, indicating that the TI registers require a 16K-byte region of memory. 3 TI_PF R TI register prefetch. Bit 3 returns 0b when read, indicating that the TI registers are nonprefetchable. 2-1 TI_MEMTYPE R TI memory type. This field returns 00b when read, indicating that the TI base address register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. 0 TI_MEM R TI memory indicator. Bit 0 returns 0b when read, indicating that the TI registers are mapped into system memory space. 7.10 CardBus CIS Base Address Register The internal CARDBUS input to the 1394 OHCI core is tied high such that this register returns 0s when read. See Table 7-9 for a complete description of the register contents. Function 1 register offset: 18h Register type: Read/Write, Read-only Default value: 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 7-9. CardBus CIS Base Address Register Description BIT FIELD NAME TYPE DESCRIPTION 31-11 CIS_BASE RW CIS base address. This field specifies the upper 21 bits of the 32-bit CIS base address. If CARDBUS is sampled high on a GRST, then this field is read-only, returning 0s when read. 10-4 CIS_SZ R CIS address space size. This field returns 000 0000b when read, indicating that the CIS space requires a 2K-byte region of memory. 3 CIS_PF R CIS prefetch. Bit 3 returns 0b when read, indicating that the CIS is nonprefetchable. Furthermore, the CIS is a byte-accessible address space, and either a doubleword or 16-bit word access yields indeterminate results. 2-1 CIS_MEMTYPE R CIS memory type. This field returns 00b when read, indicating that the CardBus CIS base address register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. 0 CIS_MEM R CIS memory indicator. Bit 0 returns 0b when read, indicating that the CIS is mapped into system memory space. 140 SCPS110 September 2005 OHCI Controller Programming Model 7.11 CardBus CIS Pointer Register The internal CARDBUS input to the 1394 OHCI core is tied high such that this register returns 0000 0000h when read. Function 1 register offset: 28h Register type: Read-only Default value: 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7.12 Subsystem Identification Register The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCI configuration space (see Section 7.25). See Table 7-10 for a complete description of the register contents. Function 1 register offset: 2Ch Register type: Read/Update Default value: 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 7-10. Subsystem Identification Register Description BIT FIELD NAME TYPE 31-16 OHCI_SSID RU DESCRIPTION Subsystem device ID. This field indicates the subsystem device ID. 15-0 OHCI_SSVID RU Subsystem vendor ID. This field indicates the subsystem vendor ID. These bits are cleared only by the assertion of GRST. 7.13 Power Management Capabilities Pointer Register The power management capabilities pointer register provides a pointer into the PCI configuration header where the power-management register block resides. The configuration header doublewords at offsets 44h and 48h provide the power-management registers. This register is read-only and returns 44h when read. Function 1 register offset: 34h Register type: Read-only Default value: 44h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 1 0 0 0 1 0 0 September 2005 SCPS110 141 OHCI Controller Programming Model 7.14 Interrupt Line Register The interrupt line register communicates interrupt line routing information. See Table 7-11 for a complete description of the register contents. Function 1 register offset: 3Ch Register type: Read/Write Default value: FFh BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 1 1 1 1 1 1 1 1 Table 7-11. Interrupt Line Register Description BIT FIELD NAME TYPE DESCRIPTION 7-0 INTR_LINE RW Interrupt line. This field is programmed by the system and indicates to software which interrupt line the interrupt pin is connected to. The default value for this field is 00h. 7.15 Interrupt Pin Register The value read from this register is function dependent and depends on the values of bits 28, the tie-all bit (TIEALL), and 29, the interrupt tie bit (INTRTIE), in the system control register (PCI offset 80h, see Section 4.29). The INTRTIE bit is compatible with previous TI CardBus controllers, and when set to 1b, ties INTB to INTA internally. The TIEALL bit ties INTA, INTB, INTC, and INTD together internally. The internal interrupt connections set by INTRTIE and TIEALL are communicated to host software through this standard register interface. This read-only register is described for all PCIxx12 functions in Table 7-12. Function 1 register offset: 3Dh Register type: Read-only Default value: 02h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 1 0 INTRTIE BIT (BIT 29, OFFSET 80H) TIEALL BIT (BIT 28, OFFSET 80H) 0 0 01h (INTA) 02h (INTB) 1 0 01h (INTA) 01h (INTA) X 1 01h (INTA) 01h (INTA) Table 7-12. PCI Interrupt Pin Register--Read-Only INTPIN Per Function INTPIN INTPIN FUNCTION 0 FUNCTION 1 (CARDBUS) (1394 OHCI) INTPIN FUNCTION 2 (FLASH MEDIA) INTPIN FUNCTION 3 (SD HOST) INTPIN FUNCTION 4 (SMART CARD) Determined by bits 6-5 (INT_SEL) in the flash media general control register (see Section 11.21) Determined by bits 6-5 (INT_SEL) in the SD host general control register (see Section 12.22) Determined by bits 6-5 (INT_SEL) in the Smart Card general control register (see Section 13.22) 01h (INTA) 01h (INTA) 01h (INTA) NOTE: When configuring the controller functions to share PCI interrupts, multifunction terminal MFUNC3 must be configured as IRQSER prior to setting the INTRTIE bit. 142 SCPS110 September 2005 OHCI Controller Programming Model 7.16 Minimum Grant and Maximum Latency Register The minimum grant and maximum latency register communicates to the system the desired setting of bits 15-8 in the latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see Section 7.6). If a serial EEPROM is detected, then the contents of this register are loaded through the serial EEPROM interface after a GRST. If no serial EEPROM is detected, then this register returns a default value that corresponds to the MAX_LAT = 4, MIN_GNT = 2. See Table 7-13 for a complete description of the register contents. Function 1 register offset: 3Eh Register type: Read/Update Default value: 0402h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 Table 7-13. Minimum Grant and Maximum Latency Register Description BIT FIELD NAME TYPE DESCRIPTION 15-8 MAX_LAT RU Maximum latency. The contents of this field may be used by host BIOS to assign an arbitration priority level to the controller. The default for this register indicates that the controller may need to access the PCI bus as often as every 0.25 s; thus, an extremely high priority level is requested. Bits 11-8 of this field may also be loaded through the serial EEPROM. RU Minimum grant. The contents of this field may be used by host BIOS to assign a latency timer register value to the controller. The default for this register indicates that the controller may need to sustain burst transfers for nearly 64 s and thus request a large value be programmed in bits 15-8 of the latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see Section 7.6). Bits 3-0 of this field may also be loaded through the serial EEPROM. 7-0 MIN_GNT These bits are cleared only by the assertion of GRST. 7.17 OHCI Control Register The PCI OHCI control register is defined by the 1394 Open Host Controller Interface Specification and provides a bit for big endian PCI support. See Table 7-14 for a complete description of the register contents. Function 1 register offset: 40h Register type: Read/Write, Read-only Default value: 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 7-14. OHCI Control Register Description BIT FIELD NAME TYPE 31-1 RSVD R 0 GLOBAL_SWAP RW September 2005 DESCRIPTION Reserved. Bits 31-1 return 0s when read. When bit 0 is set to 1b, all quadlets read from and written to the PCI interface are byte-swapped (big endian). The default value for this bit is 0b which is little endian mode. SCPS110 143 OHCI Controller Programming Model 7.18 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the next capability item. See Table 7-15 for a complete description of the register contents. Function 1 register offset: 44h Register type: Read-only Default value: 0001h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Table 7-15. Capability ID and Next Item Pointer Registers Description BIT FIELD NAME TYPE DESCRIPTION 15-8 NEXT_ITEM R Next item pointer. The controller supports only one additional capability that is communicated to the system through the extended capabilities list; therefore, this field returns 00h when read. 7-0 CAPABILITY_ID R Capability identification. This field returns 01h when read, which is the unique ID assigned by the PCI SIG for PCI power-management capability. 144 SCPS110 September 2005 OHCI Controller Programming Model 7.19 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the controller related to PCI power management. See Table 7-16 for a complete description of the register contents. Function 1 register offset: 46h Register type: Read/Update, Read-only Default value: 7E02h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 Table 7-16. Power Management Capabilities Register Description BIT FIELD NAME TYPE DESCRIPTION 15 PME_D3COLD RU PME support from D3cold. This bit can be set to 1b or cleared to 0b via bit 15 (PME_D3COLD) in the PCI miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 7.23). The PCI miscellaneous configuration register is loaded from ROM. When this bit is set to 1b, it indicates that the controller is capable of generating a PME wake event from D3cold. This bit state is dependent upon the VAUX implementation and may be configured by using bit 15 (PME_D3COLD) in the PCI miscellaneous configuration register (see Section 7.23). 14-11 PME_SUPPORT R PME support. This 4-bit field indicates the power states from which the controller may assert PME. This field returns a value of 1111b by default, indicating that PME may be asserted from the D3hot, D2, D1, and D0 power states. 10 D2_SUPPORT R D2 support. Bit 10 is hardwired to 1b, indicating that the controller supports the D2 power state. 9 D1_SUPPORT R D1 support. Bit 9 is hardwired to 1b, indicating that the controller supports the D1 power state. 8-6 AUX_CURRENT R 5 DSI R 4 RSVD R Reserved. Bit 4 returns 0b when read. 3 PME_CLK R PME clock. This bit returns 0b when read, indicating that no host bus clock is required for the controller to generate PME. RU Power-management version. If bit 7 (PCI_PM_VERSION_CTRL) in the PCI miscellaneous configuration register (offset F0h, see Section 7.23) is 0b, this field returns 010b indicating PCI Bus Power Management Interface Specification (Revision 1.1) compatibility. If the PCI_PM_VERSION_CTRL bit is 1b, this field returns 011b indicating PCI Bus Power Management Interface Specification (Revision 1.2) compatibility. 2-0 PM_VERSION September 2005 Auxiliary current. This 3-bit field reports the 3.3-VAUX auxiliary current requirements. When bit 15 (PME_D3COLD) is cleared, this field returns 000b; otherwise, it returns 001b. 000b = Self-powered 001b = 55 mA (3.3-VAUX maximum current required) Device-specific initialization. This bit returns 0b when read, indicating that the controller does not require special initialization beyond the standard PCI configuration header before a generic class driver is able to use it. SCPS110 145 OHCI Controller Programming Model 7.20 Power Management Control and Status Register The power management control and status register implements the control and status of the PCI power-management function. This register is not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See Table 7-17 for a complete description of the register contents. Function 1 register offset: 48h Register type: Read/Clear, Read/Write, Read-only Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 7-17. Power Management Control and Status Register Description BIT FIELD NAME TYPE DESCRIPTION 15 PME_STS RWC Bit 15 is set to 1b when the controller normally asserts the PME signal independent of the state of bit 8 (PME_ENB). This bit is cleared by a writeback of 1b, which also clears the PME signal driven by the controller. Writing 0b to this bit has no effect. 14-13 DATA_SCALE R This field returns 00b, because the data register is not implemented. 12-9 DATA_SELECT R This field returns 0h, because the data register is not implemented. 8 PME_ENB RW 7-2 RSVD R When bit 8 is set to 1b, PME assertion is enabled. When bit 8 is cleared, PME assertion is disabled. This bit defaults to 0b if the function does not support PME generation from D3cold. If the function supports PME from D3cold, then this bit is sticky and must be explicitly cleared by the operating system each time it is initially loaded. Reserved. Bits 7-2 return 00 0000b when read. Power state. This 2-bit field sets the controller power state and is encoded as follows: 1-0 PWR_STATE RW 00 = Current power state is D0. 01 = Current power state is D1. 10 = Current power state is D2. 11 = Current power state is D3. These bits are cleared only by the assertion of GRST. 7.21 Power Management Extension Registers The power management extension register provides extended power-management features not applicable to the controller; thus, it is read-only and returns 0000h when read. See Table 7-18 for a complete description of the register contents. Function 1 register offset: 4Ah Register type: Read-only Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 7-18. Power Management Extension Registers Description BIT FIELD NAME TYPE 15-0 RSVD R 146 SCPS110 DESCRIPTION Reserved. Bits 15-0 return 0000h when read. September 2005 OHCI Controller Programming Model 7.22 PCI PHY Control Register The PCI PHY control register provides a method for enabling the PHY CNA output. See Table 7-19 for a complete description of the register contents. Function 1 register offset: ECh Register type: Read/Write, Read-only Default value: 0000 0008h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Table 7-19. PCI PHY Control Register Description BIT FIELD NAME TYPE 31-8 RSVD R 7 CNAOUT RW DESCRIPTION Reserved. Bits 31-8 return 00 0000h when read. When bit 7 is set to 1b, the PHY CNA output is routed to terminal P18. When implementing a serial EEPROM, this bit is loaded via the serial EEPROM as defined by Table 3-9 and must be 1b for normal operation. 6-5 RSVD R 4 PHYRST RW Reserved. Bits 6-5 return 00b when read. These bits must be 00b for normal operation. PHY reset. This bit controls the RST input to the PHY. When bit 4 is set, the PHY reset is asserted. The default value is 0b. This bit must be 0b for normal operation. 3 RSVD RW Reserved. Bit 3 defaults to 1b to indicate compliance with IEEE Std 1394a-2000. This bit is loaded via the serial EEPROM as defined by Table 3-9 and must be 1b for normal operation. 2 PD RW This bit controls the power-down input to the PHY. When bit 2 is set, the PHY is in the power-down mode and enters the ULP mode if the LPS is disabled. If PD is asserted, then a reset to the physical layer must be initiated via bit 4 (PHYRST) after PD is cleared. The default value is 0b. This bit must be 0b for normal operation. 1-0 RSVD RW Reserved. Bits 1-0 return 00b when read. These bits are affected when implementing a serial EEPROM; thus, bits 1-0 are loaded via the serial EEPROM as defined by Table 3-9 and must be 00b for normal operation. These bits are cleared only by the assertion of GRST. September 2005 SCPS110 147 OHCI Controller Programming Model 7.23 PCI Miscellaneous Configuration Register The PCI miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 7-20 for a complete description of the register contents. Function 1 register offset: F0h Register type: Read/Write, Read-only Default value: 0000 0800h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Table 7-20. PCI Miscellaneous Configuration Register Description BIT FIELD NAME TYPE 31-16 RSVD R 15 PME_D3COLD RW PME support from D3cold. This bit programs bit 15 (PME_D3COLD) in the power management capabilities register at offset 46h in the PCI configuration space (see Section 7.19). 14-12 POWER_CLASS RW Power Class. This field sets the power class for the controller. These three bits are routed to signals in the controller design that are then connected to the power class terminals on the 1394 OHCI core. Bit 14 corresponds to PC2, bit 13 corresponds to PC1, and bit 12 corresponds to PC0. 11 PCI2_3_EN R PCI 2.3 enable. The 1394 OHCI function always conforms to the PCI 2.3 specification. Therefore, this bit is tied to 1b. 10 ignore_ mstrIntEna_ for_pme RW Ignore IntMask.msterIntEnable bit for PME generation. When set, this bit causes the PME generation behavior to be changed as described in Section 3.8. When set, this bit also causes bit 26 of the OHCI vendor ID register at OHCI offset 40h (see Section 8.15) to read 1b; otherwise, bit 26 reads 0b. 0 = PME behavior generated from unmasked interrupt bits and IntMask.masterIntEnable bit (default) 1 = PME generation does not depend on the value of IntMask.masterIntEnable RW This field selects the read command behavior of the PCI master for read transactions of greater than two data phases. For read transactions of one or two data phases, a memory read command is used. The default of this field is 00b. This register is loaded by the serial EEPROM word 12, bits 1-0. 00 = Memory read line (default) 01 = Memory read 10 = Memory read multiple 11 = Reserved, behavior reverts to default PCI power-management version control. This bit controls the value reported in bits 2-0 (PM_VERSION) of the power management capabilities register (offset 46h, see Section 7.19) of the 1394 OHCI function. 0 = PM_VERSION reports 010b for PCI Bus Power Management Interface Specification (Revision 1.1) compatability. 1 = PM_VERSION reports 011b for PCI Bus Power Management Interface Specification (Revision 1.2) compatability. 9-8 MR_ENHANCE DESCRIPTION Reserved. Bits 31-16 return 0000h when read. 7 PCI_PM_ VERSION_CTRL RW 6 RSVD R Reserved. Bit 6 returns 0b when read. 5 RSVD R Reserved. Bit 5 returns 0b when read. 4 DIS_TGT_ABT RW Bit 4 defaults to 0b, which provides OHCI-Lynx compatible target abort signaling. When this bit is set to 1b, it enables the no-target-abort mode, in which the controller returns indeterminate data instead of signaling target abort. The LLC is divided into the PCLK and SCLK domains. If software tries to access registers in the link that are not active because the SCLK is disabled, then a target abort is issued by the link. On some systems, this can cause a problem resulting in a fatal system error. Enabling this bit allows the link to respond to these types of requests by returning FFh. It is recommended that this bit be cleared to 0b. 3 GP2IIC RW When bit 3 is set to 1b, the GPIO3 and GPIO2 signals are internally routed to the SCL and SDA, respectively. The GPIO3 and GPIO2 terminals are also placed in the high-impedance state. This bit is cleared only by the assertion of GRST. 148 SCPS110 September 2005 OHCI Controller Programming Model Table 7-20. PCI Miscellaneous Configuration Register Description (Continued) 2 DISABLE_ SCLKGATE RW When bit 2 is set to 1b, the internal SCLK runs identically with the chip input. This is a test feature only and must be cleared to 0b (all applications). 1 DISABLE_ PCIGATE RW When bit 1 is set to 1b, the internal PCI clock runs identically with the chip input. This is a test feature only and must be cleared to 0b (all applications). 0 KEEP_PCLK RW When bit 0 is set to 1b, the PCI clock is always kept running through the CLKRUN protocol. When this bit is cleared, the PCI clock can be stopped using CLKRUN on MFUNC6. This bit is cleared only by the assertion of GRST. 7.24 Link Enhancement Control Register The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial EEPROM, if present. After these bits are set to 1, their functionality is enabled only if bit 22 (aPhyEnhanceEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1b. See Table 7-21 for a complete description of the register contents. Function 1 register offset: F4h Register type: Read/Write, Read-only Default value: 0000 1000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Table 7-21. Link Enhancement Control Register Description BIT FIELD NAME TYPE 31-16 RSVD R 15 dis_at_pipeline RW 14 RSVD R 13-12 atx_thresh RW DESCRIPTION Reserved. Bits 31-16 return 0000h when read. Disable AT pipelining. When bit 15 is set to 1b, out-of-order AT pipelining is disabled. The default value for this bit is 0b. Reserved. Bit 14 defaults to 0b and must remain 0b for normal operation of the OHCI core. This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the controller retries the packet, it uses a 2K-byte threshold, resulting in a store-and-forward operation. 00 = Threshold ~ 2K bytes resulting in a store-and-forward operation 01 = Threshold ~ 1.7K bytes (default) 10 = Threshold ~ 1K bytes 11 = Threshold ~ 512 bytes These bits fine-tune the asynchronous transmit threshold. For most applications the 1.7K-byte threshold is optimal. Changing this value may increase or decrease the 1394 latency depending on the average PCI bus latency. Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds or when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger than the AT threshold, then the remaining data must be received before the AT FIFO is emptied; otherwise, an underrun condition occurs, resulting in a packet error at the receiving node. As a result, the link then commences a store-and-forward operation. It waits until it has the complete packet in the FIFO before retransmitting it on the second attempt to ensure delivery. An AT threshold of 2K results in a store-and-forward operation, which means that asynchronous data is not transmitted until an end-of-packet token is received. Restated, setting the AT threshold to 2K results in only complete packets being transmitted. Note that this controller always uses a store-and-forward operation when the asynchronous transmit retries register at OHCI offset 08h (see Section 8.3) is cleared. 11 RSVD R 10 enab_mpeg_ts RW Reserved. Bit 11 returns 0b when read. Enable MPEG CIP timestamp enhancement. When bit 9 is set to 1b, the enhancement is enabled for MPEG CIP transmit streams (FMT = 20h). The default value for this bit is 0b. These bits are cleared only by the assertion of GRST. September 2005 SCPS110 149 OHCI Controller Programming Model Table 7-21. Link Enhancement Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 9 RSVD R 8 enab_dv_ts RW Enable DV CIP timestamp enhancement. When bit 8 is set to 1b, the enhancement is enabled for DV CIP transmit streams (FMT = 00h). The default value for this bit is 0b. 7 enab_unfair RW Enable asynchronous priority requests. OHCI-Lynx compatible. Setting bit 7 to 1b enables the link to respond to requests with priority arbitration. It is recommended that this bit be set to 1b. The default value for this bit is 0b. 6 RSVD R This bit is not assigned in the PCIxx12 follow-on products, because this bit location loaded by the serial EEPROM from the enhancements field corresponds to bit 23 (programPhyEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16). 5-3 RSVD R Reserved. Bits 5-3 return 000b when read. 2 RSVD R Reserved. Bit 2 returns 0b when read. Reserved. Bit 9 returns 0b when read. 1 enab_accel RW 0 RSVD R Enable acceleration enhancements. OHCI-Lynx compatible. When bit 1 is set to 1b, the PHY layer is notified that the link supports the IEEE Std 1394a-2000 acceleration enhancements, that is, ack-accelerated, fly-by concatenation, etc. It is recommended that this bit be set to 1b. The default value for this bit is 0b. Reserved. Bit 0 returns 0b when read. This bit is cleared only by the assertion of GRST. 7.25 Subsystem Access Register Write access to the subsystem access register updates the subsystem identification registers identically to OHCI-Lynx. The system ID value written to this register may also be read back from this register. See Table 7-22 for a complete description of the register contents. Function 1 register offset: F8h Register type: Read/Write Default value: 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 7-22. Subsystem Access Register Description BIT FIELD NAME TYPE 31-16 SUBDEV_ID RW Subsystem device ID alias. This field indicates the subsystem device ID. DESCRIPTION 15-0 SUBVEN_ID RW Subsystem vendor ID alias. This field indicates the subsystem vendor ID. These bits are cleared only by the assertion of GRST. 150 SCPS110 September 2005 OHCI Controller Programming Model 7.26 GPIO Control Register The GPIO control register has the control and status bits for GPIO0, GPIO1, GPIO2, and GPIO3 ports. Upon reset, GPIO0 and GPIO1 default to bus manager contender (BMC) and link power status terminals, respectively. The BMC terminal can be configured as GPIO0 by setting bit 7 (DISABLE_BMC) to 1b. The LPS terminal can be configured as GPIO1 by setting bit 15 (DISABLE_LPS) to 1b. See Table 7-23 for a complete description of the register contents. Function 1 register offset: FCh Register type: Read-only, Read/Write Default value: 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 7-23. GPIO Control Register Description BIT SIGNAL TYPE 31-30 RSVD R 29 GPIO_INV3 R/W GPIO3 polarity invert. This bit controls the input/output polarity control of GPIO3. 0 = Noninverted (default) 1 = Inverted 28 GPIO_ENB3 R/W GPIO3 enable control. This bit controls the output enable for GPIO3. 0 = High-impedance output (default) 1 = Output is enabled 27-25 RSVD R 24 GPIO_DATA3 R/W 23-22 RSVD R 21 GPIO_INV2 R/W GPIO2 polarity invert. This bit controls the input/output polarity control of GPIO2. 0 = Noninverted (default) 1 = Inverted 20 GPIO_ENB2 R/W GPIO2 enable control. This bit controls the output enable for GPIO2. 0 = High-impedance output (default) 1 = Output is enabled 19-17 RSVD R 16 GPIO_DATA2 R/W GPIO2 data. When GPIO2 output is enabled, the value written to this bit represents the logical data driven to the GPIO2 terminal. 15 DISABLE_LPS R/W Disable link power status (LPS). This bit configures this terminal as 0 = LPS (default) 1 = GPIO1 14 RSVD R 13 GPIO_INV1 Reserved. Bits 31 and 30 return 00b when read. Reserved. Bits 27-25 return 000b when read. GPIO3 data. When GPIO3 output is enabled, the value written to this bit represents the logical data driven to the GPIO3 terminal. Reserved. Bits 23 and 22 return 00b when read. Reserved. Bits 19-17 return 000b when read. Reserved. Bit 14 returns 0b when read. R/W GPIO1 polarity invert. When bit 15 (DISABLE_LPS) is set to 1b, this bit controls the input/output polarity control of GPIO1. 0 = Noninverted (default) 1 = Inverted GPIO1 enable control. When bit 15 (DISABLE_LPS) is set to 1b, this bit controls the output enable for GPIO1. 0 = High-impedance output (default) 1 = Output is enabled 12 GPIO_ENB1 R/W 11-9 RSVD R September 2005 FUNCTION Reserved. Bits 11-9 return 000b when read. SCPS110 151 OHCI Controller Programming Model Table 7-23. GPIO Control Register Description (Continued) BIT SIGNAL TYPE FUNCTION 8 GPIO_DATA1 R/W GPIO1 data. When bit 15 (DISABLE_LPS) is set to 1b and GPIO1 output is enabled, the value written to this bit represents the logical data driven to the GPIO1 terminal. Disable bus manager contender (BMC). This bit configures this terminal as bus manager contender or GPIO0. 0 = BMC (default) 1 = GPIO0 7 DISABLE_BMC R/W 6 RSVD R 5 GPIO_INV0 R/W GPIO0 polarity invert. When bit 7 (DISABLE_BMC) is set to 1b, this bit controls the input/output polarity control for GPIO0. 0 = Noninverted (default) 1 = Inverted GPIO0 enable control. When bit 7 (DISABLE_BMC) is set to 1b, this bit controls the output enable for GPIO0. 0 = High-impedance output (default) 1 = Output is enabled 4 GPIO_ENB0 R/W 3-1 RSVD R 0 GPIO_DATA0 R/W 152 SCPS110 Reserved. Bit 6 returns 0b when read. Reserved. Bits 3-1 return 000b when read. GPIO0 data. When bit 7 (DISABLE_BMC) is set to 1b and GPIO0 output is enabled, the value written to this bit represents the logical data driven to the GPIO0 terminal. September 2005 OHCI Registers 8 OHCI Registers The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a 2K-byte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see Section 7.8). These registers are the primary interface for controlling the PCIxx12 IEEE 1394 link function. This section provides the register interface and bit descriptions. Several set/clear register pairs in this programming model are implemented to solve various issues with typical read-modify-write control registers. There are two addresses for a set/clear register: RegisterSet and RegisterClear. See Table 8-1 for a register listing. A 1b written to RegisterSet causes the corresponding bit in the set/clear register to be set to 1b; a 0b leaves the corresponding bit unaffected. A 1b written to RegisterClear causes the corresponding bit in the set/clear register to be cleared; a 0b leaves the corresponding bit in the set/clear register unaffected. Typically, a read from either RegisterSet or RegisterClear returns the contents of the set or clear register, respectively. However, sometimes reading the RegisterClear provides a masked version of the set or clear register. The interrupt event register is an example of this behavior. Table 8-1. OHCI Register Map DMA CONTEXT -- REGISTER NAME ABBREVIATION OFFSET OHCI version Version 00h GUID ROM GUID_ROM 04h Asynchronous transmit retries ATRetries 08h CSR data CSRData 0Ch CSR compare CSRCompareData 10h CSR control CSRControl 14h Configuration ROM header ConfigROMhdr 18h Bus identification BusID 1Ch Bus options BusOptions 20h GUID high GUIDHi 24h GUID low GUIDLo 28h Reserved -- Configuration ROM mapping ConfigROMmap 34h Posted write address low PostedWriteAddressLo 38h Posted write address high PostedWriteAddressHi 3Ch Vendor ID VendorID 40h Reserved -- Host controller control Reserved 2Ch-30h 44h-4Ch HCControlSet 50h HCControlClr 54h -- 58h-5Ch One or more bits in this register are cleared only by the assertion of GRST. September 2005 SCPS110 153 OHCI Registers Table 8-1. OHCI Register Map (Continued) DMA CONTEXT Self-ID REGISTER NAME ABBREVIATION OFFSET Reserved -- 60h Self-ID buffer pointer SelfIDBuffer 64h Self-ID count SelfIDCount 68h Reserved -- 6Ch IRChannelMaskHiSet 70h IRChannelMaskHiClear 74h -- Isochronous receive channel mask high Isochronous receive channel mask low Interrupt event Interrupt mask Isochronous transmit interrupt event Isochronous transmit interrupt mask -- Isochronous receive interrupt event Isochronous receive interrupt mask IRChannelMaskLoSet 78h IRChannelMaskLoClear 7Ch IntEventSet 80h IntEventClear 84h IntMaskSet 88h IntMaskClear 8Ch IsoXmitIntEventSet 90h IsoXmitIntEventClear 94h IsoXmitIntMaskSet 98h IsoXmitIntMaskClear 9Ch IsoRecvIntEventSet A0h IsoRecvIntEventClear A4h IsoRecvIntMaskSet A8h IsoRecvIntMaskClear ACh Initial bandwidth available InitialBandwidthAvailable B0h Initial channels available high InitialChannelsAvailableHi B4h Initial channels available low InitialChannelsAvailableLo B8h Reserved -- Fairness control FairnessControl DCh LinkControlSet E0h Link control BCh-D8h LinkControlClear E4h Node identification NodeID E8h PHY layer control PhyControl ECh Isochronous cycle timer Isocyctimer F0h Reserved -- Asynchronous request filter high Asynchronous request filter low Physical request filter high Physical request filter low F4h-FCh AsyncRequestFilterHiSet 100h AsyncRequestFilterHiClear 104h AsyncRequestFilterLoSet 108h AsyncRequestFilterLoClear 10Ch PhysicalRequestFilterHiSet 110h PhysicalRequestFilterHiClear 114h PhysicalRequestFilterLoSet 118h PhysicalRequestFilterLoClear 11Ch Physical upper bound PhysicalUpperBound 120h Reserved -- 124h-17Ch One or more bits in this register are cleared only by the assertion of GRST. 154 SCPS110 September 2005 OHCI Registers Table 8-1. OHCI Register Map (Continued) DMA CONTEXT Asynchronous Request Transmit [ ATRQ ] Asynchronous Response Transmit [ ATRS ] Asynchronous Request Receive [ ARRQ ] Asynchronous Response Receive [ ARRS ] REGISTER NAME Asynchronous context control Transmit Context n n = 0, 1, 2, 3, ..., 7 September 2005 180h ContextControlClear 184h -- 188h CommandPtr 18Ch Reserved -- 190h-19Ch ContextControlSet 1A0h ContextControlClear 1A4h Reserved -- 1A8h Asynchronous context command pointer CommandPtr Reserved -- Asynchronous context control Asynchronous context control 1ACh 1B0h-1BCh ContextControlSet 1C0h ContextControlClear 1C4h Reserved -- 1C8h Asynchronous context command pointer CommandPtr Reserved -- Asynchronous context control 1CCh 1D0h-1DCh ContextControlSet 1E0h ContextControlClear 1E4h Reserved -- 1E8h Asynchronous context command pointer CommandPtr 1ECh Reserved -- 1F0h-1FCh ContextControlSet 200h + 16*n ContextControlClear 204h + 16*n Reserved -- 208h + 16*n Isochronous transmit context command pointer CommandPtr 20Ch + 16*n Reserved -- 210h-3FCh ContextControlSet 400h + 32*n ContextControlClear 404h + 32*n Reserved -- 408h + 32*n Isochronous receive context command pointer CommandPtr 40Ch + 32*n Isochronous receive context match ContextMatch 410h + 32*n Isochronous n = 0, 1, 2, 3 ContextControlSet Asynchronous context command pointer Isochronous receive context control Receive Context n OFFSET Reserved Isochronous transmit context control Isochronous ABBREVIATION SCPS110 155 OHCI Registers 8.1 OHCI Version Register The OHCI version register indicates the OHCI version support and whether or not the serial EEPROM is present. See Table 8-2 for a complete description of the register contents. OHCI register offset: Register type: Default value: 00h Read-only 0X01 0010h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 X 0 0 0 0 0 0 0 1 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Table 8-2. OHCI Version Register Description BIT FIELD NAME TYPE DESCRIPTION 31-25 RSVD R 24 GUID_ROM RU Reserved. Bits 31-25 return 000 0000b when read. The controller sets bit 24 to 1b if the serial EEPROM is detected. If the serial EEPROM is present, then the Bus_Info_Block is automatically loaded on system (hardware) reset. The default value for this bit is 0b. 23-16 version R Major version of the OHCI. The controller is compliant with the 1394 Open Host Controller Interface Specification (Release 1.1); thus, this field reads 01h. 15-8 RSVD R Reserved. Bits 15-8 return 00h when read. 7-0 revision R Minor version of the OHCI. The controller is compliant with the 1394 Open Host Controller Interface Specification (Release 1.1); thus, this field reads 10h. This bit is cleared only by the assertion of GRST. 8.2 GUID ROM Register The GUID ROM register accesses the serial EEPROM, and is only applicable if bit 24 (GUID_ROM) in the OHCI version register at OHCI offset 00h (see Section 8.1) is set to 1b. See Table 8-3 for a complete description of the register contents. OHCI register offset: Register type: Default value: BIT NUMBER 31 30 04h Read/Set/Update, Read/Update, Read-only 00XX 0000h 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 X X X X X X X X BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 8-3. GUID ROM Register Description BIT FIELD NAME TYPE DESCRIPTION 31 addrReset RSU Software sets bit 31 to 1b to reset the GUID ROM address to 0. When the controller completes the reset, it clears this bit. The controller does not automatically fill bits 23-16 (rdData field) with the 0th byte. 30-26 RSVD R 25 rdStart RSU 24 RSVD R 23-16 rdData RU 15-8 RSVD R Reserved. Bits 15-8 return 00h when read. 7-0 miniROM R The miniROM field defaults to 00h indicating that no mini-ROM is implemented. If an EEPROM is implemented, then all 8 bits of this miniROM field are downloaded from EEPROM word offset 28h. For this device, the miniROM field must be greater than 61h to indicate a valid miniROM offset into the EEPROM. 156 SCPS110 Reserved. Bits 30-26 return 00000b when read. A read of the currently addressed byte is started when bit 25 is set to 1b. This bit is automatically cleared when the controller completes the read of the currently addressed GUID ROM byte. Reserved. Bit 24 returns 0b when read. This field contains the data read from the GUID ROM. September 2005 OHCI Registers 8.3 Asynchronous Transmit Retries Register The asynchronous transmit retries register indicates the number of times the controller attempts a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See Table 8-4 for a complete description of the register contents. OHCI register offset: Register type: Default value: 08h Read/Write, Read-only 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 8-4. Asynchronous Transmit Retries Register Description BIT FIELD NAME TYPE DESCRIPTION 31-29 secondLimit R The second limit field returns 000b when read, because outbound dual-phase retry is not implemented. 28-16 cycleLimit R The cycle limit field returns 0s when read, because outbound dual-phase retry is not implemented. Reserved. Bits 15-12 return 0h when read. 15-12 RSVD R 11-8 maxPhysRespRetries RW This field tells the physical response unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. The default value for this field is 0h. 7-4 maxATRespRetries RW This field tells the asynchronous transmit response unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. The default value for this field is 0h. 3-0 maxATReqRetries RW This field tells the asynchronous transmit DMA request unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. The default value for this field is 0h. 8.4 CSR Data Register The CSR data register accesses the bus management CSR registers from the host through compare-swap operations. This register contains the data to be stored in a CSR if the compare is successful. OHCI register offset: Register type: Default value: BIT NUMBER 31 30 29 0Ch Read-only XXXX XXXXh 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE X X X X X X X X X X X X X X X X BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE X X X X X X X X X X X X X X X X September 2005 SCPS110 157 OHCI Registers 8.5 CSR Compare Register The CSR compare register accesses the bus management CSR registers from the host through compare-swap operations. This register contains the data to be compared with the existing value of the CSR resource. OHCI register offset: Register type: Default value: 10h Read-only XXXX XXXXh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE X X X X X X X X X X X X X X X X BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE X X X X X X X X X X X X X X X X 8.6 CSR Control Register The CSR control register accesses the bus management CSR registers from the host through compare-swap operations. This register controls the compare-swap operation and selects the CSR resource. See Table 8-5 for a complete description of the register contents. OHCI register offset: Register type: Default value: BIT NUMBER 31 30 29 14h Read/Write, Read/Update, Read-only 8000 000Xh 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X Table 8-5. CSR Control Register Description BIT FIELD NAME TYPE DESCRIPTION 31 csrDone RU Bit 31 is set to 1b by the controller when a compare-swap operation is complete. It is cleared whenever this register is written. 30-2 RSVD R 1-0 csrSel RW Reserved. Bits 30-2 return 0s when read. This field selects the CSR resource as follows: 00 = BUS_MANAGER_ID 01 = BANDWIDTH_AVAILABLE 10 = CHANNELS_AVAILABLE_HI 11 = CHANNELS_AVAILABLE_LO 158 SCPS110 September 2005 OHCI Registers 8.7 Configuration ROM Header Register The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset FFFF F000 0400h. See Table 8-6 for a complete description of the register contents. OHCI register offset: Register type: Default value: 18h Read/Write 0000 XXXXh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE X X X X X X X X X X X X X X X X Table 8-6. Configuration ROM Header Register Description BIT FIELD NAME TYPE DESCRIPTION 31-24 info_length RW IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1b. The default value for this field is 00h. 23-16 crc_length RW IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1b. The default value for this field is 00h. 15-0 rom_crc_value RW IEEE 1394 bus-management field. Must be valid at any time bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1b. 8.8 Bus Identification Register The bus identification register externally maps to the first quadlet in the Bus_Info_Block and contains the constant 3133 3934h, which is the ASCII value of 1394. OHCI register offset: Register type: Default value: BIT NUMBER 31 30 29 1Ch Read-only 3133 3934h 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 1 1 0 0 0 1 0 0 1 1 0 0 1 1 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 1 1 1 0 0 1 0 0 1 1 0 1 0 0 September 2005 SCPS110 159 OHCI Registers 8.9 Bus Options Register The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 8-7 for a complete description of the register contents. OHCI register offset: Register type: Default value: 20h Read/Write, Read-only X0XX A0X2h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE X X X X 0 0 0 0 X X X X X X X X BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 1 0 1 0 0 0 0 0 X X 0 0 0 0 1 0 Table 8-7. Bus Options Register Description BIT FIELD NAME TYPE DESCRIPTION 31 irmc RW Isochronous resource-manager capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1b. The default value for this bit is 0b. 30 cmc RW Cycle master capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1b. The default value for this bit is 0b. 29 isc RW Isochronous support capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1b. The default value for this bit is 0b. 28 bmc RW Bus manager capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1b. The default value for this bit is 0b. 27 pmc RW Power-management capable. IEEE 1394 bus-management field. When bit 27 is set to 1b, this indicates that the node is power-management capable. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1b. The default value for this bit is 0b. 26-24 RSVD R 23-16 cyc_clk_acc RW Reserved. Bits 26-24 return 000b when read. Cycle master clock accuracy, in parts per million. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1b. The default value for this field is 00h. 15-12 max_rec RW Maximum request. IEEE 1394 bus-management field. Hardware initializes this field to indicate the maximum number of bytes in a block request packet that is supported by the implementation. This value, max_rec_bytes, must be 512 or greater, and is calculated by 2^(max_rec + 1). Software may change this field; however, this field must be valid at any time bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1b. A received block write request packet with a length greater than max_rec_bytes may generate an ack_type_error. This field is not affected by a software reset, and defaults to value indicating 2048 bytes on a system (hardware) reset. The default value for this field is Ah. 11-8 RSVD R 7-6 g RW 5-3 RSVD R Reserved. Bits 5-3 return 000b when read. 2-0 Lnk_spd R Link speed. This field returns 010b, indicating that the link speeds of 100M bits/s, 200M bits/s, and 400M bits/s are supported. Reserved. Bits 11-8 return 0h when read. Generation counter. This field is incremented if any portion of the configuration ROM has been incremented since the prior bus reset. These bits are cleared only by the assertion of GRST. 160 SCPS110 September 2005 OHCI Registers 8.10 GUID High Register The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the third quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes to 0000 0000h on a system (hardware) reset, which is an illegal GUID value. If a serial EEPROM is detected, then the contents of this register are loaded through the serial EEPROM interface after a GRST. At that point, the contents of this register cannot be changed. If no serial EEPROM is detected, then the contents of this register are loaded by the BIOS. At that point, the contents of this register cannot be changed. All bits in this register are reset by GRST only. OHCI register offset: Register type: Default value: 24h Read-only 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8.11 GUID Low Register The GUID low register represents the lower quadlet in a 64-bit global unique ID (GUID) which maps to chip_ID_lo in the Bus_Info_Block. This register initializes to 0000 0000h on a system (hardware) reset and behaves identical to the GUID high register at OHCI offset 24h (see Section 8.10). All bits in this register are reset by GRST only. OHCI register offset: Register type: Default value: 28h Read-only 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8.12 Configuration ROM Mapping Register The configuration ROM mapping register contains the start address within system memory that maps to the start address of 1394 configuration ROM for this node. See Table 8-8 for a complete description of the register contents. OHCI register offset: Register type: Default value: BIT NUMBER 31 30 29 34h Read/Write 0000 0000h 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 8-8. Configuration ROM Mapping Register Description BIT FIELD NAME TYPE DESCRIPTION 31-10 configROMaddr RW If a quadlet read request to 1394 offset FFFF F000 0400h through offset FFFF F000 07FFh is received, then the low-order 10 bits of the offset are added to this register to determine the host memory address of the read request. 9-0 RSVD R September 2005 Reserved. Bits 9-0 return 0s when read. SCPS110 161 OHCI Registers 8.13 Posted Write Address Low Register The posted write address low register communicates error information if a write request is posted and an error occurs while the posted data packet is being written. See Table 8-9 for a complete description of the register contents. OHCI register offset: Register type: Default value: 38h Read/Update XXXX XXXXh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE X X X X X X X X X X X X X X X X BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE X X X X X X X X X X X X X X X X Table 8-9. Posted Write Address Low Register Description BIT FIELD NAME TYPE 31-0 offsetLo RU DESCRIPTION The lower 32 bits of the 1394 destination offset of the write request that failed. 8.14 Posted Write Address High Register The posted write address high register communicates error information if a write request is posted and an error occurs while writing the posted data packet. See Table 8-10 for a complete description of the register contents. OHCI register offset: Register type: Default value: 3Ch Read/Update XXXX XXXXh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE X X X X X X X X X X X X X X X X BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE X X X X X X X X X X X X X X X X Table 8-10. Posted Write Address High Register Description BIT FIELD NAME TYPE DESCRIPTION 31-16 sourceID RU This field is the 10-bit bus number (bits 31-22) and 6-bit node number (bits 21-16) of the node that issued the write request that failed. 15-0 offsetHi RU The upper 16 bits of the 1394 destination offset of the write request that failed. 8.15 Vendor ID Register The vendor ID register holds the company ID of an organization that specifies any vendor-unique registers. The controller implements Texas Instruments unique behavior with regards to OHCI. Thus, this register is read-only and returns 0108 0028h when read. OHCI register offset: Register type: Default value: 40h Read-only 0108 0028h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 162 SCPS110 September 2005 OHCI Registers 8.16 Host Controller Control Register The host controller control set/clear register pair provides flags for controlling the controller. See Table 8-11 for a complete description of the register contents. OHCI register offset: 50h set register 54h clear register Read/Set/Clear/Update, Read/Set/Clear, Read/Clear, Read-only X08X 0000h Register type: Default value: BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 X 0 0 0 0 0 0 1 0 0 0 0 X 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 8-11. Host Controller Control Register Description BIT FIELD NAME TYPE DESCRIPTION 31 BIBimage Valid RSU When bit 31 is set to 1b, the PCIxx12 physical response unit is enabled to respond to block read requests to host configuration ROM and to the mechanism for atomically updating configuration ROM. Software creates a valid image of the bus_info_block in host configuration ROM before setting this bit. When this bit is cleared, the controller returns ack_type_error on block read requests to host configuration ROM. Also, when this bit is cleared and a 1394 bus reset occurs, the configuration ROM mapping register at OHCI offset 34h (see Section 8.12), configuration ROM header register at OHCI offset 18h (see Section 8.7), and bus options register at OHCI offset 20h (see Section 8.9) are not updated. Software can set this bit only when bit 17 (linkEnable) is 0b. Once bit 31 is set to 1b, it can be cleared by a system (hardware) reset, a software reset, or if a fetch error occurs when the controller loads bus_info_block registers from host memory. 30 noByteSwapData RSC Bit 30 controls whether physical accesses to locations outside the controller itself, as well as any other DMA data accesses are byte swapped. 29 AckTardyEnable RSC Bit 29 controls the acknowledgement of ack_tardy. When bit 29 is set to 1b, ack_tardy may be returned as an acknowledgment to accesses from the 1394 bus to the controller, including accesses to the bus_info_block. The controller returns ack_tardy to all other asynchronous packets addressed to the PCIxx12 node. When the controller sends ack_tardy, bit 27 (ack_tardy) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) is set to 1b to indicate the attempted asynchronous access. Software ensures that bit 27 (ack_tardy) in the interrupt event register is 0b. Software also unmasks wake-up interrupt events such as bit 19 (phy) and bit 27 (ack_tardy) in the interrupt event register before placing the controller into the D1 power mode. Software must not set this bit if the PCIxx12 node is the 1394 bus manager. 28-24 RSVD R Reserved. Bits 28-24 return 00000b when read. 23 programPhyEnable R Bit 23 informs upper-level software that lower-level software has consistently configured the IEEE 1394a-2000 enhancements in the link and PHY layers. When this bit is 1b, generic software such as the OHCI driver is responsible for configuring IEEE 1394a-2000 enhancements in the PHY layer and bit 22 (aPhyEnhanceEnable). When this bit is 0b, the generic software may not modify the IEEE 1394a-2000 enhancements in the PHY layer and cannot interpret the setting of bit 22 (aPhyEnhanceEnable). This bit is initialized from serial EEPROM. This bit defaults to 1b. 22 aPhyEnhanceEnable RSC When bits 23 (programPhyEnable) and 17 (linkEnable) are 11b, the OHCI driver can set bit 22 to 1b to use all IEEE 1394a-2000 enhancements. When bit 23 (programPhyEnable) is cleared to 0b, the software does not change PHY enhancements or this bit. 21-20 RSVD R Reserved. Bits 21 and 20 return 00b when read. This bit is cleared only by the assertion of GRST. September 2005 SCPS110 163 OHCI Registers Table 8-11. Host Controller Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 19 LPS RSC Bit 19 controls the link power status. Software must set this bit to 1b to permit the link-PHY communication. A prevents link-PHY communication. The OHCI-link is divided into two clock domains (PCLK and PHY_SCLK). If software tries to access any register in the PHY_SCLK domain while the PHY_SCLK is disabled, then a target abort is issued by the link. This problem can be avoided by setting bit 4 (DIS_TGT_ABT) to 1b in the PCI miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 7.23). This allows the link to respond to these types of request by returning all Fs (hex). OHCI registers at offsets DCh-F0h and 100h-11Ch are in the PHY_SCLK domain. After setting LPS, software must wait approximately 10 ms before attempting to access any of the OHCI registers. This gives the PHY_SCLK time to stabilize. 18 postedWriteEnable RSC Bit 18 enables (1b) or disables (0b) posted writes. Software changes this bit only when bit 17 (linkEnable) is 0b. 17 linkEnable RSC Bit 17 is cleared to 0b by either a system (hardware) or software reset. Software must set this bit to 1b when the system is ready to begin operation and then force a bus reset. This bit is necessary to keep other nodes from sending transactions before the local system is ready. When this bit is cleared, the controller is logically and immediately disconnected from the 1394 bus, no packets are received or processed, nor are packets transmitted. 16 SoftReset RSCU When bit 16 is set to 1b, all PCIxx12 states are reset, all FIFOs are flushed, and all OHCI registers are set to their system (hardware) reset values, unless otherwise specified. PCI registers are not affected by this bit. This bit remains set to 1b while the software reset is in progress and reverts back to when the reset has completed. 15-0 RSVD R Reserved. Bits 15-0 return 0000h when read. 8.17 Self-ID Buffer Pointer Register The self-ID buffer pointer register points to the 2K-byte aligned base address of the buffer in host memory where the self-ID packets are stored during bus initialization. Bits 31-11 are read/write accessible. Bits 10-0 are reserved, and return 0s when read. OHCI register offset: Register type: Default value: 64h Read/Write, Read-only XXXX XX00h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE X X X X X X X X X X X X X X X X BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE X X X X X 0 0 0 0 0 0 0 0 0 0 0 164 SCPS110 September 2005 OHCI Registers 8.18 Self-ID Count Register The self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags self-ID packet errors, and keeps a count of the self-ID data in the self-ID buffer. See Table 8-12 for a complete description of the register contents. OHCI register offset: Register type: Default value: 68h Read/Update, Read-only X0XX 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE X 0 0 0 0 0 0 0 X X X X X X X X BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 8-12. Self-ID Count Register Description BIT FIELD NAME TYPE DESCRIPTION 31 selfIDError RU When bit 31 is set to 1b, an error was detected during the most recent self-ID packet reception. The contents of the self-ID buffer are undefined. This bit is cleared after a self-ID reception in which no errors are detected. Note that an error can be a hardware error or a host bus write error. 30-24 RSVD R 23-16 selfIDGeneration RU 15-11 RSVD R 10-2 selfIDSize RU 1-0 RSVD R September 2005 Reserved. Bits 30-24 return 000 0000b when read. The value in this field increments each time a bus reset is detected. This field rolls over to 0 after reaching 255. Reserved. Bits 15-11 return 00000b when read. This field indicates the number of quadlets that have been written into the self-ID buffer for the current bits 23-16 (selfIDGeneration field). This includes the header quadlet and the self-ID data. This field is cleared to 0s when the self-ID reception begins. Reserved. Bits 1 and 0 return 00b when read. SCPS110 165 OHCI Registers 8.19 Isochronous Receive Channel Mask High Register The isochronous receive channel mask high set/clear register enables packet receives from the upper 32 isochronous data channels. A read from either the set register or clear register returns the content of the isochronous receive channel mask high register. See Table 8-13 for a complete description of the register contents. OHCI register offset: Register type: Default value: 70h set register 74h clear register Read/Set/Clear XXXX XXXXh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE X X X X X X X X X X X X X X X X BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE X X X X X X X X X X X X X X X X Table 8-13. Isochronous Receive Channel Mask High Register Description BIT FIELD NAME TYPE 31 isoChannel63 RSC When bit 31 is set to 1b, the controller is enabled to receive from isochronous channel number 63. 30 isoChannel62 RSC When bit 30 is set to 1b, the controller is enabled to receive from isochronous channel number 62. 29 isoChannel61 RSC When bit 29 is set to 1b, the controller is enabled to receive from isochronous channel number 61. 28 isoChannel60 RSC When bit 28 is set to 1b, the controller is enabled to receive from isochronous channel number 60. 27 isoChannel59 RSC When bit 27 is set to 1b, the controller is enabled to receive from isochronous channel number 59. 26 isoChannel58 RSC When bit 26 is set to 1b, the controller is enabled to receive from isochronous channel number 58. 25 isoChannel57 RSC When bit 25 is set to 1b, the controller is enabled to receive from isochronous channel number 57. 24 isoChannel56 RSC When bit 24 is set to 1b, the controller is enabled to receive from isochronous channel number 56. 23 isoChannel55 RSC When bit 23 is set to 1b, the controller is enabled to receive from isochronous channel number 55. 22 isoChannel54 RSC When bit 22 is set to 1b, the controller is enabled to receive from isochronous channel number 54. 21 isoChannel53 RSC When bit 21 is set to 1b, the controller is enabled to receive from isochronous channel number 53. 20 isoChannel52 RSC When bit 20 is set to 1b, the controller is enabled to receive from isochronous channel number 52. 19 isoChannel51 RSC When bit 19 is set to 1b, the controller is enabled to receive from isochronous channel number 51. 18 isoChannel50 RSC When bit 18 is set to 1b, the controller is enabled to receive from isochronous channel number 50. 17 isoChannel49 RSC When bit 17 is set to 1b, the controller is enabled to receive from isochronous channel number 49. 16 isoChannel48 RSC When bit 16 is set to 1b, the controller is enabled to receive from isochronous channel number 48. 15 isoChannel47 RSC When bit 15 is set to 1b, the controller is enabled to receive from isochronous channel number 47. 14 isoChannel46 RSC When bit 14 is set to 1b, the controller is enabled to receive from isochronous channel number 46. 13 isoChannel45 RSC When bit 13 is set to 1b, the controller is enabled to receive from isochronous channel number 45. 12 isoChannel44 RSC When bit 12 is set to 1b, the controller is enabled to receive from isochronous channel number 44. 11 isoChannel43 RSC When bit 11 is set to 1b, the controller is enabled to receive from isochronous channel number 43. 10 isoChannel42 RSC When bit 10 is set to 1b, the controller is enabled to receive from isochronous channel number 42. 9 isoChannel41 RSC When bit 9 is set to 1b, the controller is enabled to receive from isochronous channel number 41. 8 isoChannel40 RSC When bit 8 is set to 1b, the controller is enabled to receive from isochronous channel number 40. 7 isoChannel39 RSC When bit 7 is set to 1b, the controller is enabled to receive from isochronous channel number 39. 6 isoChannel38 RSC When bit 6 is set to 1b, the controller is enabled to receive from isochronous channel number 38. 5 isoChannel37 RSC When bit 5 is set to 1b, the controller is enabled to receive from isochronous channel number 37. 4 isoChannel36 RSC When bit 4 is set to 1b, the controller is enabled to receive from isochronous channel number 36. 3 isoChannel35 RSC When bit 3 is set to 1b, the controller is enabled to receive from isochronous channel number 35. 2 isoChannel34 RSC When bit 2 is set to 1b, the controller is enabled to receive from isochronous channel number 34. 166 SCPS110 DESCRIPTION September 2005 OHCI Registers Table 8-13. Isochronous Receive Channel Mask High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 1 isoChannel33 RSC When bit 1 is set to 1b, the controller is enabled to receive from isochronous channel number 33. 0 isoChannel32 RSC When bit 0 is set to 1b, the controller is enabled to receive from isochronous channel number 32. 8.20 Isochronous Receive Channel Mask Low Register The isochronous receive channel mask low set/clear register enables packet receives from the lower 32 isochronous data channels. See Table 8-14 for a complete description of the register contents. OHCI register offset: 78h set register 7Ch clear register Read/Set/Clear XXXX XXXXh Register type: Default value: BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE X X X X X X X X X X X X X X X X BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE X X X X X X X X X X X X X X X X Table 8-14. Isochronous Receive Channel Mask Low Register Description BIT FIELD NAME TYPE 31 isoChannel31 RSC When bit 31 is set to 1b, the controller is enabled to receive from isochronous channel number 31. 30 isoChannel30 RSC When bit 30 is set to 1b, the controller is enabled to receive from isochronous channel number 30. 29-2 isoChanneln RSC Bits 29 through 2 (isoChanneln, where n = 29, 28, 27, ..., 2) follow the same pattern as bits 31 and 30. 1 isoChannel1 RSC When bit 1 is set to 1b, the controller is enabled to receive from isochronous channel number 1. 0 isoChannel0 RSC When bit 0 is set to 1b, the controller is enabled to receive from isochronous channel number 0. September 2005 DESCRIPTION SCPS110 167 OHCI Registers 8.21 Interrupt Event Register The interrupt event set/clear register reflects the state of the various PCIxx12 interrupt sources. The interrupt bits are set to 1b by an asserting edge of the corresponding interrupt signal or by writing a 1b in the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1b to the corresponding bit in the clear register. This register is fully compliant with the 1394 Open Host Controller Interface Specification, and the controller adds a vendor-specific interrupt function to bit 30. When the interrupt event register is read, the return value is the bit-wise AND function of the interrupt event and interrupt mask registers. See Table 8-15 for a complete description of the register contents. OHCI register offset: 80h 84h set register clear register [returns the content of the interrupt event register bit-wise ANDed with the interrupt mask register when read] Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only XXXX 0XXXh Register type: Default value: BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 X 0 0 0 X X X X X X X X 0 X X BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 X X X X X X X X X X Table 8-15. Interrupt Event Register Description BIT FIELD NAME TYPE 31-30 RSVD R 29 SoftInterrupt RSC 28 RSVD R 27 ack_tardy RSCU DESCRIPTION Reserved. Bits 31 and 30 return 00b when read. Bit 29 is used by software to generate a PCIxx12 interrupt for its own use. Reserved. Bit 28 returns 0b when read. Bit 27 is set to 1b when bit 29 (AckTardyEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1b and any of the following conditions occur: a. Data is present in a receive FIFO that is to be delivered to the host. b. The physical response unit is busy processing requests or sending responses. c. The controller sent an ack_tardy acknowledgment. 168 26 phyRegRcvd RSCU The controller has received a PHY register data byte which can be read from bits 23-16 in the PHY layer control register at OHCI offset ECh (see Section 8.33). 25 cycleTooLong RSCU If bit 21 (cycleMaster) in the link control register at OHCI offset E0h/E4h (see Section 8.31) is set to 1b, then this indicates that over 125 s has elapsed between the start of sending a cycle start packet and the end of a subaction gap. Bit 21 (cycleMaster) in the link control register is cleared by this event. 24 unrecoverableError RSCU This event occurs when the controller encounters any error that forces it to stop operations on any or all of its subunits, for example, when a DMA context sets its dead bit to 1b. While bit 24 is set to 1b, all normal interrupts for the context(s) that caused this interrupt are blocked from being set to 1b. 23 cycleInconsistent RSCU A cycle start was received that had values for the cycleSeconds and cycleCount fields that are different from the values in bits 31-25 (cycleSeconds field) and bits 24-12 (cycleCount field) in the isochronous cycle timer register at OHCI offset F0h (see Section 8.34). 22 cycleLost RSCU A lost cycle is indicated when no cycle_start packet is sent or received between two successive cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected after a cycleSynch event without an intervening cycle start. Bit 22 may be set to 1b either when a lost cycle occurs or when logic predicts that one will occur. 21 cycle64Seconds RSCU Indicates that the seventh bit of the cycle second counter has changed. 20 cycleSynch RSCU Indicates that a new isochronous cycle has started. Bit 20 is set to 1b when the low-order bit of the cycle count toggles. SCPS110 September 2005 OHCI Registers Table 8-15. Interrupt Event Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 19 phy RSCU Indicates that the PHY layer requests an interrupt through a status transfer. 18 regAccessFail RSCU Indicates that a PCIxx12 register access has failed due to a missing SCLK clock signal from the PHY layer. When a register access fails, bit 18 is set to 1b before the next register access. 17 busReset RSCU Indicates that the PHY layer has entered bus reset mode. 16 selfIDcomplete RSCU A self-ID packet stream has been received. It is generated at the end of the bus initialization process. Bit 16 is turned off simultaneously when bit 17 (busReset) is turned on. 15 selfIDcomplete2 RSCU Secondary indication of the end of a self-ID packet stream. Bit 15 is set to 1b by the controller when it sets bit 16 (selfIDcomplete), and retains the state, independent of bit 17 (busReset). 14-10 RSVD R 9 lockRespErr RSCU Indicates that the controller sent a lock response for a lock request to a serial bus register, but did not receive an ack_complete. 8 postedWriteErr RSCU Indicates that a host bus error occurred while the controller was trying to write a 1394 write request, which had already been given an ack_complete, into system memory. 7 isochRx RU Isochronous receive DMA interrupt. Indicates that one or more isochronous receive contexts have generated an interrupt. This is not a latched event; it is the logical OR of all bits in the isochronous receive interrupt event register at OHCI offset A0h/A4h (see Section 8.25) and isochronous receive interrupt mask register at OHCI offset A8h/ACh (see Section 8.26). The isochronous receive interrupt event register indicates which contexts have been interrupted. 6 isochTx RU Isochronous transmit DMA interrupt. Indicates that one or more isochronous transmit contexts have generated an interrupt. This is not a latched event; it is the logical OR of all bits in the isochronous transmit interrupt event register at OHCI offset 90h/94h (see Section 8.23) and isochronous transmit interrupt mask register at OHCI offset 98h/9Ch (see Section 8.24). The isochronous transmit interrupt event register indicates which contexts have been interrupted. 5 RSPkt RSCU Indicates that a packet was sent to an asynchronous receive response context buffer and the descriptor xferStatus and resCount fields have been updated. 4 RQPkt RSCU Indicates that a packet was sent to an asynchronous receive request context buffer and the descriptor xferStatus and resCount fields have been updated. 3 ARRS RSCU Asynchronous receive response DMA interrupt. Bit 3 is conditionally set to 1b upon completion of an ARRS DMA context command descriptor. 2 ARRQ RSCU Asynchronous receive request DMA interrupt. Bit 2 is conditionally set to 1b upon completion of an ARRQ DMA context command descriptor. 1 respTxComplete RSCU Asynchronous response transmit DMA interrupt. Bit 1 is conditionally set to 1b upon completion of an ATRS DMA command. 0 reqTxComplete RSCU Asynchronous request transmit DMA interrupt. Bit 0 is conditionally set to 1b upon completion of an ATRQ DMA command. September 2005 Reserved. Bits 14-10 return 00000b when read. SCPS110 169 OHCI Registers 8.22 Interrupt Mask Register The interrupt mask set/clear register enables the various PCIxx12 interrupt sources. Reads from either the set register or the clear register always return the contents of the interrupt mask register. In all cases except masterIntEnable (bit 31) and vendorSpecific (bit 30), the enables for each interrupt event align with the interrupt event register bits detailed in Table 8-15. This register is fully compliant with the 1394 Open Host Controller Interface Specification and the controller adds an interrupt function to bit 30. See Table 8-16 for a complete description of bits 31 and 30. OHCI register offset: 88h set register 8Ch clear register Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only XXXX 0XXXh Register type: Default value: BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE X X 0 0 0 X X X X X X X X 0 X X BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 X X X X X X X X X X Table 8-16. Interrupt Mask Register Description BIT FIELD NAME TYPE DESCRIPTION 31 masterIntEnable RSCU Master interrupt enable. If bit 31 is set to 1b, then external interrupts are generated in accordance with the interrupt mask register. If this bit is cleared, then external interrupts are not generated regardless of the interrupt mask register settings. 30 VendorSpecific RSC When this bit and bit 30 (vendorSpecific) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this vendor-specific interrupt mask enables interrupt generation. 29 SoftInterrupt RSC When this bit and bit 29 (SoftInterrupt) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this soft-interrupt mask enables interrupt generation. 28 RSVD R 27 ack_tardy RSC When this bit and bit 27 (ack_tardy) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this acknowledge-tardy interrupt mask enables interrupt generation. 26 phyRegRcvd RSC When this bit and bit 26 (phyRegRcvd) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this PHY-register interrupt mask enables interrupt generation. 25 cycleTooLong RSC When this bit and bit 25 (cycleTooLong) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this cycle-too-long interrupt mask enables interrupt generation. 24 unrecoverableError RSC When this bit and bit 24 (unrecoverableError) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this unrecoverable-error interrupt mask enables interrupt generation. 23 cycleInconsistent RSC When this bit and bit 23 (cycleInconsistent) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this inconsistent-cycle interrupt mask enables interrupt generation. 22 cycleLost RSC When this bit and bit 22 (cycleLost) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this lost-cycle interrupt mask enables interrupt generation. 21 cycle64Seconds RSC When this bit and bit 21 (cycle64Seconds) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this 64-second-cycle interrupt mask enables interrupt generation. 20 cycleSynch RSC When this bit and bit 20 (cycleSynch) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this isochronous-cycle interrupt mask enables interrupt generation. 19 phy RSC When this bit and bit 19 (phy) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this PHY-status-transfer interrupt mask enables interrupt generation. 18 regAccessFail RSC When this bit and bit 18 (regAccessFail) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this register-access-failed interrupt mask enables interrupt generation. 17 busReset RSC When this bit and bit 17 (busReset) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this bus-reset interrupt mask enables interrupt generation. 170 SCPS110 Reserved. Bit 28 returns 0b when read. September 2005 OHCI Registers Table 8-16. Interrupt Mask Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 16 selfIDcomplete RSC When this bit and bit 16 (selfIDcomplete) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this self-ID-complete interrupt mask enables interrupt generation. 15 selfIDcomplete2 RSC When this bit and bit 15 (selfIDcomplete2) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this second-self-ID-complete interrupt mask enables interrupt generation. 14-10 RSVD R 9 lockRespErr RSC When this bit and bit 9 (lockRespErr) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this lock-response-error interrupt mask enables interrupt generation. 8 postedWriteErr RSC When this bit and bit 8 (postedWriteErr) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this posted-write-error interrupt mask enables interrupt generation. 7 isochRx RSC When this bit and bit 7 (isochRx) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this isochronous-receive-DMA interrupt mask enables interrupt generation. 6 isochTx RSC When this bit and bit 6 (isochTx) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this isochronous-transmit-DMA interrupt mask enables interrupt generation. 5 RSPkt RSC When this bit and bit 5 (RSPkt) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this receive-response-packet interrupt mask enables interrupt generation. 4 RQPkt RSC When this bit and bit 4 (RQPkt) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this receive-request-packet interrupt mask enables interrupt generation. 3 ARRS RSC When this bit and bit 3 (ARRS) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this asynchronous-receive-response-DMA interrupt mask enables interrupt generation. 2 ARRQ RSC When this bit and bit 2 (ARRQ) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this asynchronous-receive-request-DMA interrupt mask enables interrupt generation. 1 respTxComplete RSC When this bit and bit 1 (respTxComplete) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this response-transmit-complete interrupt mask enables interrupt generation. 0 reqTxComplete RSC When this bit and bit 0 (reqTxComplete) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this request-transmit-complete interrupt mask enables interrupt generation. September 2005 Reserved. Bits 14-10 return 00000b when read. SCPS110 171 OHCI Registers 8.23 Isochronous Transmit Interrupt Event Register The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST* command completes and its interrupt bits are set to 1b. Upon determining that the isochTx (bit 6) interrupt has occurred in the interrupt event register at OHCI offset 80h/84h (see Section 8.21), software can check this register to determine which context(s) caused the interrupt. The interrupt bits are set to 1b by an asserting edge of the corresponding interrupt signal, or by writing a 1b in the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1b to the corresponding bit in the clear register. See Table 8-17 for a complete description of the register contents. OHCI register offset: Register type: Default value: 90h 94h set register clear register [returns the contents of the isochronous transmit interrupt event register bit-wise ANDed with the isochronous transmit interrupt mask register when read] Read/Set/Clear, Read-only 0000 00XXh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 X X X X X X X X Table 8-17. Isochronous Transmit Interrupt Event Register Description BIT FIELD NAME TYPE 31-8 RSVD R DESCRIPTION 7 isoXmit7 RSC Isochronous transmit channel 7 caused the interrupt event register bit 6 (isochTx) interrupt. 6 isoXmit6 RSC Isochronous transmit channel 6 caused the interrupt event register bit 6 (isochTx) interrupt. 5 isoXmit5 RSC Isochronous transmit channel 5 caused the interrupt event register bit 6 (isochTx) interrupt. 4 isoXmit4 RSC Isochronous transmit channel 4 caused the interrupt event register bit 6 (isochTx) interrupt. 3 isoXmit3 RSC Isochronous transmit channel 3 caused the interrupt event register bit 6 (isochTx) interrupt. 2 isoXmit2 RSC Isochronous transmit channel 2 caused the interrupt event register bit 6 (isochTx) interrupt. 1 isoXmit1 RSC Isochronous transmit channel 1 caused the interrupt event register bit 6 (isochTx) interrupt. 0 isoXmit0 RSC Isochronous transmit channel 0 caused the interrupt event register bit 6 (isochTx) interrupt. Reserved. Bits 31-8 return 00 0000h when read. 8.24 Isochronous Transmit Interrupt Mask Register The isochronous transmit interrupt mask set/clear register enables the isochTx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register. In all cases the enables for each interrupt event align with the isochronous transmit interrupt event register bits detailed in Table 8-17. OHCI register offset: Register type: Default value: 98h set register 9Ch clear register Read/Set/Clear, Read-only 0000 00XXh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 X X X X X X X X 172 SCPS110 September 2005 OHCI Registers 8.25 Isochronous Receive Interrupt Event Register The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes and its interrupt bits are set to 1b. Upon determining that the isochRx (bit 7) interrupt in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) has occurred, software can check this register to determine which context(s) caused the interrupt. The interrupt bits are set to 1b by an asserting edge of the corresponding interrupt signal or by writing a 1b in the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1b to the corresponding bit in the clear register. See Table 8-18 for a complete description of the register contents. OHCI register offset: Register type: Default value: A0h A4h set register clear register [returns the contents of isochronous receive interrupt event register bit-wise ANDed with the isochronous receive mask register when read] Read/Set/Clear, Read-only 0000 000Xh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 X X X X Table 8-18. Isochronous Receive Interrupt Event Register Description BIT FIELD NAME TYPE 31-4 RSVD R DESCRIPTION 3 isoRecv3 RSC Isochronous receive channel 3 caused the interrupt event register bit 7 (isochRx) interrupt. 2 isoRecv2 RSC Isochronous receive channel 2 caused the interrupt event register bit 7 (isochRx) interrupt. 1 isoRecv1 RSC Isochronous receive channel 1 caused the interrupt event register bit 7 (isochRx) interrupt. 0 isoRecv0 RSC Isochronous receive channel 0 caused the interrupt event register bit 7 (isochRx) interrupt. Reserved. Bits 31-4 return 000 0000h when read. 8.26 Isochronous Receive Interrupt Mask Register The isochronous receive interrupt mask set/clear register enables the isochRx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the isochronous receive interrupt mask register. In all cases the enables for each interrupt event align with the isochronous receive interrupt event register bits detailed in Table 8-18. OHCI register offset: Register type: Default value: A8h set register ACh clear register Read/Set/Clear, Read-only 0000 000Xh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 X X X X September 2005 SCPS110 173 OHCI Registers 8.27 Initial Bandwidth Available Register The initial bandwidth available register value is loaded into the corresponding bus management CSR register on a system (hardware) or software reset. See Table 8-19 for a complete description of the register contents. OHCI register offset: Register type: Default value: B0h Read-only, Read/Write 0000 1333h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 Table 8-19. Initial Bandwidth Available Register Description BIT FIELD NAME TYPE 31-13 RSVD R 12-0 InitBWAvailable RW DESCRIPTION Reserved. Bits 31-13 return 0s when read. This field is reset to 1333h on a system (hardware) or software reset, and is not affected by a 1394 bus reset. The value of this field is loaded into the BANDWIDTH_AVAILABLE CSR register upon a GRST, PRST, or a 1394 bus reset. 8.28 Initial Channels Available High Register The initial channels available high register value is loaded into the corresponding bus management CSR register on a system (hardware) or software reset. See Table 8-20 for a complete description of the register contents. OHCI register offset: Register type: Default value: B4h Read/Write FFFF FFFFh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 8-20. Initial Channels Available High Register Description BIT FIELD NAME TYPE DESCRIPTION 31-0 InitChanAvailHi RW This field is reset to FFFF_FFFFh on a system (hardware) or software reset, and is not affected by a 1394 bus reset. The value of this field is loaded into the CHANNELS_AVAILABLE_HI CSR register upon a GRST, PRST, or a 1394 bus reset. 174 SCPS110 September 2005 OHCI Registers 8.29 Initial Channels Available Low Register The initial channels available low register value is loaded into the corresponding bus management CSR register on a system (hardware) or software reset. See Table 8-21 for a complete description of the register contents. OHCI register offset: Register type: Default value: B8h Read/Write FFFF FFFFh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 8-21. Initial Channels Available Low Register Description BIT FIELD NAME TYPE DESCRIPTION 31-0 InitChanAvailLo RW This field is reset to FFFF_FFFFh on a system (hardware) or software reset, and is not affected by a 1394 bus reset. The value of this field is loaded into the CHANNELS_AVAILABLE_LO CSR register upon a GRST, PRST, or a 1394 bus reset. 8.30 Fairness Control Register The fairness control register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous requests during a fairness interval. See Table 8-22 for a complete description of the register contents. OHCI register offset: Register type: Default value: DCh Read-only 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 8-22. Fairness Control Register Description BIT FIELD NAME TYPE 31-8 RSVD R 7-0 pri_req RW September 2005 DESCRIPTION Reserved. Bits 31-8 return 00 0000h when read. This field specifies the maximum number of priority arbitration requests for asynchronous request packets that the link is permitted to make of the PHY layer during a fairness interval. The default value for this field is 00h. SCPS110 175 OHCI Registers 8.31 Link Control Register The link control set/clear register provides the control flags that enable and configure the link core protocol portions of the controller. It contains controls for the receiver and cycle timer. See Table 8-23 for a complete description of the register contents. OHCI register offset: E0h set register E4h clear register Read/Set/Clear/Update, Read/Set/Clear, Read-only 00X0 0X00h Register type: Default value: BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 X X X 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 X X 0 0 0 0 0 0 0 0 0 Table 8-23. Link Control Register Description BIT FIELD NAME TYPE 31-23 RSVD R 22 cycleSource RSC When bit 22 is set to 1b, the cycle timer uses an external source (CYCLEIN) to determine when to roll over the cycle timer. When this bit is cleared, the cycle timer rolls over when the timer reaches 3072 cycles of the 24.576-MHz clock (125 s). 21 cycleMaster RSCU When bit 21 is set to 1b, the controller is root and it generates a cycle start packet every time the cycle timer rolls over, based on the setting of bit 22 (cycleSource). When bit 21 is cleared, the OHCI-Lynx accepts received cycle start packets to maintain synchronization with the node which is sending them. Bit 21 is automatically cleared when bit 25 (cycleTooLong) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) is set to 1b. Bit 21 cannot be set to 1b until bit 25 (cycleTooLong) is cleared. 20 CycleTimerEnable RSC When bit 20 is set to 1b, the cycle timer offset counts cycles of the 24.576-MHz clock and rolls over at the appropriate time, based on the settings of the above bits. When this bit is cleared, the cycle timer offset does not count. 19-11 RSVD R 10 RcvPhyPkt RSC When bit 10 is set to 1b, the receiver accepts incoming PHY packets into the AR request context if the AR request context is enabled. This bit does not control receipt of self-identification packets. 9 RcvSelfID RSC When bit 9 is set to 1b, the receiver accepts incoming self-identification packets. Before setting this bit to 1b, software must ensure that the self-ID buffer pointer register contains a valid address. 8-7 RSVD R 6 tag1SyncFilterLock RS 5-0 RSVD R DESCRIPTION Reserved. Bits 31-23 return 0 0000 0000b when read. Reserved. Bits 19-11 return 0 0000 0000b when read. Reserved. Bits 8 and 7 return 00b when read. When bit 6 is set to 1b, bit 6 (tag1SyncFilter) in the isochronous receive context match register (see Section 8.46) is set to 1b for all isochronous receive contexts. When bit 6 is cleared, bit 6 (tag1SyncFilter) in the isochronous receive context match register has read/write access. This bit is cleared when GRST is asserted. Reserved. Bits 5-0 return 00 0000b when read. This bit is cleared only by the assertion of GRST. 176 SCPS110 September 2005 OHCI Registers 8.32 Node Identification Register The node identification register contains the address of the node on which the OHCI-Lynx chip resides, and indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15-6) and the NodeNumber field (bits 5-0) is referred to as the node ID. See Table 8-24 for a complete description of the register contents. OHCI register offset: Register type: Default value: E8h Read/Write/Update, Read/Update, Read-only 0000 FFXXh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 1 1 1 1 1 1 1 1 1 1 X X X X X X Table 8-24. Node Identification Register Description BIT FIELD NAME TYPE DESCRIPTION 31 iDValid RU Bit 31 indicates whether or not the controller has a valid node number. It is cleared when a 1394 bus reset is detected and set to 1b when the controller receives a new node number from its PHY layer. 30 root RU Bit 30 is set to 1b during the bus reset process if the attached PHY layer is root. 29-28 RSVD R 27 CPS RU Reserved. Bits 29 and 28 return 00b when read. Bit 27 is set to 1b if the PHY layer is reporting that cable power status is OK. 26-16 RSVD R 15-6 busNumber RWU This field identifies the specific 1394 bus the controller belongs to when multiple 1394-compatible buses are connected via a bridge. The default value for this field is 11 1111 1111b. 5-0 NodeNumber RU This field is the physical node number established by the PHY layer during self-identification. It is automatically set to the value received from the PHY layer after the self-identification phase. If the PHY layer sets the nodeNumber to 63, then software must not set bit 15 (run) in the asynchronous context control register (see Section 8.40) for either of the AT DMA contexts. September 2005 Reserved. Bits 26-16 return 0s when read. SCPS110 177 OHCI Registers 8.33 PHY Layer Control Register The PHY layer control register reads from or writes to a PHY register. See Table 8-25 for a complete description of the register contents. OHCI register offset: Register type: Default value: ECh Read/Write/Update, Read/Write, Read/Update, Read-only 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 8-25. PHY Control Register Description BIT FIELD NAME TYPE DESCRIPTION 31 rdDone RU Bit 31 is cleared to 0b by the controller when either bit 15 (rdReg) or bit 14 (wrReg) is set to 1b. This bit is set to 1b when a register transfer is received from the PHY layer. 30-28 RSVD R 27-24 rdAddr RU This field is the address of the register most recently received from the PHY layer. 23-16 rdData RU This field is the contents of a PHY register that has been read. 15 rdReg RWU Bit 15 is set to 1b by software to initiate a read request to a PHY register, and is cleared by hardware when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both be set to 1b simultaneously. 14 wrReg RWU Bit 14 is set to 1b by software to initiate a write request to a PHY register, and is cleared by hardware when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both be set to 1b simultaneously. 13-12 RSVD R 11-8 regAddr RW This field is the address of the PHY register to be written or read. The default value for this field is 0h. 7-0 wrData RW This field is the data to be written to a PHY register and is ignored for reads. The default value for this field is 00h. Reserved. Bits 30-28 return 000b when read. Reserved. Bits 13 and 12 return 00b when read. 8.34 Isochronous Cycle Timer Register The isochronous cycle timer register indicates the current cycle number and offset. When the controller is cycle master, this register is transmitted with the cycle start message. When the controller is not cycle master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start message is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference. See Table 8-26 for a complete description of the register contents. OHCI register offset: Register type: Default value: F0h Read/Write/Update XXXX XXXXh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE X X X X X X X X X X X X X X X X BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE X X X X X X X X X X X X X X X X Table 8-26. Isochronous Cycle Timer Register Description BIT FIELD NAME TYPE 31-25 cycleSeconds RWU This field counts seconds [rollovers from bits 24-12 (cycleCount field)] modulo 128. 24-12 cycleCount RWU This field counts cycles [rollovers from bits 11-0 (cycleOffset field)] modulo 8000. 11-0 cycleOffset RWU This field counts 24.576-MHz clocks modulo 3072, that is, 125 s. If an external 8-kHz clock configuration is being used, then this field must be cleared to 000h at each tick of the external clock. 178 SCPS110 DESCRIPTION September 2005 OHCI Registers 8.35 Asynchronous Request Filter High Register The asynchronous request filter high set/clear register enables asynchronous receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for either the physical request context or the ARRQ context, the source node ID is examined. If the bit corresponding to the node ID is not set to 1b in this register, then the packet is not acknowledged and the request is not queued. The node ID comparison is done if the source node is on the same bus as the controller. Nonlocal bus-sourced packets are not acknowledged unless bit 31 in this register is set to 1b. See Table 8-27 for a complete description of the register contents. OHCI register offset: Register type: Default value: 100h set register 104h clear register Read/Set/Clear 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 8-27. Asynchronous Request Filter High Register Description BIT FIELD NAME TYPE DESCRIPTION 31 asynReqAllBuses RSC If bit 31 is set to 1b, all asynchronous requests received by the controller from nonlocal bus nodes are accepted. 30 asynReqResource62 RSC If bit 30 is set to 1b for local bus node number 62, asynchronous requests received by the controller from that node are accepted. 29 asynReqResource61 RSC If bit 29 is set to 1b for local bus node number 61, asynchronous requests received by the controller from that node are accepted. 28 asynReqResource60 RSC If bit 28 is set to 1b for local bus node number 60, asynchronous requests received by the controller from that node are accepted. 27 asynReqResource59 RSC If bit 27 is set to 1b for local bus node number 59, asynchronous requests received by the controller from that node are accepted. 26 asynReqResource58 RSC If bit 26 is set to 1b for local bus node number 58, asynchronous requests received by the controller from that node are accepted. 25 asynReqResource57 RSC If bit 25 is set to 1b for local bus node number 57, asynchronous requests received by the controller from that node are accepted. 24 asynReqResource56 RSC If bit 24 is set to 1b for local bus node number 56, asynchronous requests received by the controller from that node are accepted. 23 asynReqResource55 RSC If bit 23 is set to 1b for local bus node number 55, asynchronous requests received by the controller from that node are accepted. 22 asynReqResource54 RSC If bit 22 is set to 1b for local bus node number 54, asynchronous requests received by the controller from that node are accepted. 21 asynReqResource53 RSC If bit 21 is set to 1b for local bus node number 53, asynchronous requests received by the controller from that node are accepted. 20 asynReqResource52 RSC If bit 20 is set to 1b for local bus node number 52, asynchronous requests received by the controller from that node are accepted. 19 asynReqResource51 RSC If bit 19 is set to 1b for local bus node number 51, asynchronous requests received by the controller from that node are accepted. 18 asynReqResource50 RSC If bit 18 is set to 1b for local bus node number 50, asynchronous requests received by the controller from that node are accepted. 17 asynReqResource49 RSC If bit 17 is set to 1b for local bus node number 49, asynchronous requests received by the controller from that node are accepted. September 2005 SCPS110 179 OHCI Registers Table 8-27. Asynchronous Request Filter High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 16 asynReqResource48 RSC If bit 16 is set to 1b for local bus node number 48, asynchronous requests received by the controller from that node are accepted. 15 asynReqResource47 RSC If bit 15 is set to 1b for local bus node number 47, asynchronous requests received by the controller from that node are accepted. 14 asynReqResource46 RSC If bit 14 is set to 1b for local bus node number 46, asynchronous requests received by the controller from that node are accepted. 13 asynReqResource45 RSC If bit 13 is set to 1b for local bus node number 45, asynchronous requests received by the controller from that node are accepted. 12 asynReqResource44 RSC If bit 12 is set to 1b for local bus node number 44, asynchronous requests received by the controller from that node are accepted. 11 asynReqResource43 RSC If bit 11 is set to 1b for local bus node number 43, asynchronous requests received by the controller from that node are accepted. 10 asynReqResource42 RSC If bit 10 is set to 1b for local bus node number 42, asynchronous requests received by the controller from that node are accepted. 9 asynReqResource41 RSC If bit 9 is set to 1b for local bus node number 41, asynchronous requests received by the controller from that node are accepted. 8 asynReqResource40 RSC If bit 8 is set to 1b for local bus node number 40, asynchronous requests received by the controller from that node are accepted. 7 asynReqResource39 RSC If bit 7 is set to 1b for local bus node number 39, asynchronous requests received by the controller from that node are accepted. 6 asynReqResource38 RSC If bit 6 is set to 1b for local bus node number 38, asynchronous requests received by the controller from that node are accepted. 5 asynReqResource37 RSC If bit 5 is set to 1b for local bus node number 37, asynchronous requests received by the controller from that node are accepted. 4 asynReqResource36 RSC If bit 4 is set to 1b for local bus node number 36, asynchronous requests received by the controller from that node are accepted. 3 asynReqResource35 RSC If bit 3 is set to 1b for local bus node number 35, asynchronous requests received by the controller from that node are accepted. 2 asynReqResource34 RSC If bit 2 is set to 1b for local bus node number 34, asynchronous requests received by the controller from that node are accepted. 1 asynReqResource33 RSC If bit 1 is set to 1b for local bus node number 33, asynchronous requests received by the controller from that node are accepted. 0 asynReqResource32 RSC If bit 0 is set to 1b for local bus node number 32, asynchronous requests received by the controller from that node are accepted. 180 SCPS110 September 2005 OHCI Registers 8.36 Asynchronous Request Filter Low Register The asynchronous request filter low set/clear register enables asynchronous receive requests on a per-node basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to the asynchronous request filter high register. See Table 8-28 for a complete description of the register contents. OHCI register offset: Register type: Default value: 108h set register 10Ch clear register Read/Set/Clear 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 8-28. Asynchronous Request Filter Low Register Description BIT FIELD NAME TYPE DESCRIPTION 31 asynReqResource31 RSC If bit 31 is set to 1b for local bus node number 31, asynchronous requests received by the controller from that node are accepted. 30 asynReqResource30 RSC If bit 30 is set to 1b for local bus node number 30, asynchronous requests received by the controller from that node are accepted. 29-2 asynReqResourcen RSC Bits 29 through 2 (asynReqResourcen, where n = 29, 28, 27, ..., 2) follow the same pattern as bits 31 and 30. 1 asynReqResource1 RSC If bit 1 is set to 1b for local bus node number 1, asynchronous requests received by the controller from that node are accepted. 0 asynReqResource0 RSC If bit 0 is set to 1b for local bus node number 0, asynchronous requests received by the controller from that node are accepted. September 2005 SCPS110 181 OHCI Registers 8.37 Physical Request Filter High Register The physical request filter high set/clear register enables physical receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for the physical request context, and the node ID has been compared against the ARRQ registers, then the comparison is done again with this register. If the bit corresponding to the node ID is not set to 1b in this register, then the request is handled by the ARRQ context instead of the physical request context. The node ID comparison is done if the source node is on the same bus as the controller. Nonlocal bus-sourced packets are not acknowledged unless bit 31 in this register is set to 1b. See Table 8-29 for a complete description of the register contents. OHCI register offset: 110h set register 114h clear register Read/Set/Clear 0000 0000h Register type: Default value: BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 8-29. Physical Request Filter High Register Description BIT FIELD NAME TYPE DESCRIPTION 31 physReqAllBusses RSC If bit 31 is set to 1b, all asynchronous requests received by the controller from nonlocal bus nodes are accepted. Bit 31 is not cleared by a PRST. 30 physReqResource62 RSC If bit 30 is set to 1b for local bus node number 62, physical requests received by the controller from that node are handled through the physical request context. 29 physReqResource61 RSC If bit 29 is set to 1b for local bus node number 61, physical requests received by the controller from that node are handled through the physical request context. 28 physReqResource60 RSC If bit 28 is set to 1b for local bus node number 60, physical requests received by the controller from that node are handled through the physical request context. 27 physReqResource59 RSC If bit 27 is set to 1b for local bus node number 59, physical requests received by the controller from that node are handled through the physical request context. 26 physReqResource58 RSC If bit 26 is set to 1b for local bus node number 58, physical requests received by the controller from that node are handled through the physical request context. 25 physReqResource57 RSC If bit 25 is set to 1b for local bus node number 57, physical requests received by the controller from that node are handled through the physical request context. 24 physReqResource56 RSC If bit 24 is set to 1b for local bus node number 56, physical requests received by the controller from that node are handled through the physical request context. 23 physReqResource55 RSC If bit 23 is set to 1b for local bus node number 55, physical requests received by the controller from that node are handled through the physical request context. 22 physReqResource54 RSC If bit 22 is set to 1b for local bus node number 54, physical requests received by the controller from that node are handled through the physical request context. 21 physReqResource53 RSC If bit 21 is set to 1b for local bus node number 53, physical requests received by the controller from that node are handled through the physical request context. 20 physReqResource52 RSC If bit 20 is set to 1b for local bus node number 52, physical requests received by the controller from that node are handled through the physical request context. 19 physReqResource51 RSC If bit 19 is set to 1b for local bus node number 51, physical requests received by the controller from that node are handled through the physical request context. 18 physReqResource50 RSC If bit 18 is set to 1b for local bus node number 50, physical requests received by the controller from that node are handled through the physical request context. 17 physReqResource49 RSC If bit 17 is set to 1b for local bus node number 49, physical requests received by the controller from that node are handled through the physical request context. 182 SCPS110 September 2005 OHCI Registers Table 8-29. Physical Request Filter High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 16 physReqResource48 RSC If bit 16 is set to 1b for local bus node number 48, physical requests received by the controller from that node are handled through the physical request context. 15 physReqResource47 RSC If bit 15 is set to 1b for local bus node number 47, physical requests received by the controller from that node are handled through the physical request context. 14 physReqResource46 RSC If bit 14 is set to 1b for local bus node number 46, physical requests received by the controller from that node are handled through the physical request context. 13 physReqResource45 RSC If bit 13 is set to 1b for local bus node number 45, physical requests received by the controller from that node are handled through the physical request context. 12 physReqResource44 RSC If bit 12 is set to 1b for local bus node number 44, physical requests received by the controller from that node are handled through the physical request context. 11 physReqResource43 RSC If bit 11 is set to 1b for local bus node number 43, physical requests received by the controller from that node are handled through the physical request context. 10 physReqResource42 RSC If bit 10 is set to 1b for local bus node number 42, physical requests received by the controller from that node are handled through the physical request context. 9 physReqResource41 RSC If bit 9 is set to 1b for local bus node number 41, physical requests received by the controller from that node are handled through the physical request context. 8 physReqResource40 RSC If bit 8 is set to 1b for local bus node number 40, physical requests received by the controller from that node are handled through the physical request context. 7 physReqResource39 RSC If bit 7 is set to 1b for local bus node number 39, physical requests received by the controller from that node are handled through the physical request context. 6 physReqResource38 RSC If bit 6 is set to 1b for local bus node number 38, physical requests received by the controller from that node are handled through the physical request context. 5 physReqResource37 RSC If bit 5 is set to 1b for local bus node number 37, physical requests received by the controller from that node are handled through the physical request context. 4 physReqResource36 RSC If bit 4 is set to 1b for local bus node number 36, physical requests received by the controller from that node are handled through the physical request context. 3 physReqResource35 RSC If bit 3 is set to 1b for local bus node number 35, physical requests received by the controller from that node are handled through the physical request context. 2 physReqResource34 RSC If bit 2 is set to 1b for local bus node number 34, physical requests received by the controller from that node are handled through the physical request context. 1 physReqResource33 RSC If bit 1 is set to 1b for local bus node number 33, physical requests received by the controller from that node are handled through the physical request context. 0 physReqResource32 RSC If bit 0 is set to 1b for local bus node number 32, physical requests received by the controller from that node are handled through the physical request context. September 2005 SCPS110 183 OHCI Registers 8.38 Physical Request Filter Low Register The physical request filter low set/clear register enables physical receive requests on a per-node basis, and handles the lower node IDs. When a packet is destined for the physical request context, and the node ID has been compared against the asynchronous request filter registers, then the node ID comparison is done again with this register. If the bit corresponding to the node ID is not set to 1b in this register, then the request is handled by the asynchronous request context instead of the physical request context. See Table 8-30 for a complete description of the register contents. OHCI register offset: 118h set register 11Ch clear register Read/Set/Clear 0000 0000h Register type: Default value: BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 8-30. Physical Request Filter Low Register Description BIT FIELD NAME TYPE DESCRIPTION 31 physReqResource31 RSC If bit 31 is set to 1b for local bus node number 31, physical requests received by the controller from that node are handled through the physical request context. 30 physReqResource30 RSC If bit 30 is set to 1b for local bus node number 30, physical requests received by the controller from that node are handled through the physical request context. 29-2 physReqResourcen RSC Bits 29 through 2 (physReqResourcen, where n = 29, 28, 27, ..., 2) follow the same pattern as bits 31 and 30. 1 physReqResource1 RSC If bit 1 is set to 1b for local bus node number 1, physical requests received by the controller from that node are handled through the physical request context. 0 physReqResource0 RSC If bit 0 is set to 1b for local bus node number 0, physical requests received by the controller from that node are handled through the physical request context. 8.39 Physical Upper Bound Register (Optional Register) The physical upper bound register is an optional register and is not implemented. This register returns 0000 0000h when read. OHCI register offset: Register type: Default value: 120h Read-only 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 184 SCPS110 September 2005 OHCI Registers 8.40 Asynchronous Context Control Register The asynchronous context control set/clear register controls the state and indicates status of the DMA context. See Table 8-31 for a complete description of the register contents. OHCI register offset: Register type: Default value: 180h set register [ATRQ] 184h clear register [ATRQ] 1A0h set register [ATRS] 1A4h clear register [ATRS] 1C0h set register [ARRQ] 1C4h clear register [ARRQ] 1E0h set register [ARRS] 1E4h clear register [ARRS] Read/Set/Clear/Update, Read/Set/Update, Read/Update, Read-only 0000 X0XXh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 X 0 0 0 0 X X X X X X X X Table 8-31. Asynchronous Context Control Register Description BIT FIELD NAME TYPE 31-16 RSVD R DESCRIPTION 15 run RSCU 14-13 RSVD R 12 wake RSU Software sets bit 12 to 1b to cause the controller to continue or resume descriptor processing. The controller clears this bit on every descriptor fetch. 11 dead RU The controller sets bit 11 to 1b when it encounters a fatal error, and clears the bit when software clears bit 15 (run). Asynchronous contexts supporting out-of-order pipelining provide unique ContextControl.dead functionality. See Section 7.7 in the 1394 Open Host Controller Interface Specification (Release 1.1) for more information. 10 active RU The controller sets bit 10 to 1b when it is processing descriptors. 9-8 RSVD R 7-5 spd RU Reserved. Bits 31-16 return 0000h when read. Bit 15 is set to 1b by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. The controller changes this bit only on a system (hardware) or software reset. Reserved. Bits 14 and 13 return 00b when read. Reserved. Bits 9 and 8 return 00b when read. This field indicates the speed at which a packet was received or transmitted and only contains meaningful information for receive contexts. This field is encoded as: 000 = 100M bits/sec 001 = 200M bits/sec 010 = 400M bits/sec All other values are reserved. 4-0 eventcode September 2005 RU This field holds the acknowledge sent by the link core for this packet or an internally generated error code if the packet was not transferred successfully. SCPS110 185 OHCI Registers 8.41 Asynchronous Context Command Pointer Register The asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the controller accesses when software enables the context by setting bit 15 (run) in the asynchronous context control register (see Section 8.40) to 1b. See Table 8-32 for a complete description of the register contents. OHCI register offset: Register type: Default value: 18Ch [ATRQ] 1ACh [ATRS] 1CCh [ARRQ] 1ECh [ARRS] Read/Write/Update XXXX XXXXh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE X X X X X X X X X X X X X X X X BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE X X X X X X X X X X X X X X X X Table 8-32. Asynchronous Context Command Pointer Register Description BIT FIELD NAME TYPE 31-4 descriptorAddress RWU Contains the upper 28 bits of the address of a 16-byte aligned descriptor block. 3-0 Z RWU Indicates the number of contiguous descriptors at the address pointed to by the descriptor address. If Z is 0h, then it indicates that the descriptorAddress field (bits 31-4) is not valid. 186 SCPS110 DESCRIPTION September 2005 OHCI Registers 8.42 Isochronous Transmit Context Control Register The isochronous transmit context control set/clear register controls options, state, and status for the isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, ..., 7). See Table 8-33 for a complete description of the register contents. OHCI register offset: Register type: Default value: 200h + (16 * n) set register 204h + (16 * n) clear register Read/Set/Clear/Update, Read/Set/Clear, Read/Set/Update, Read/Update, Read-only XXXX X0XXh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE X X X X X X X X X X X X X X X X BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 X 0 0 0 0 X X X X X X X X Table 8-33. Isochronous Transmit Context Control Register Description BIT FIELD NAME TYPE DESCRIPTION 31 cycleMatchEnable RSCU When bit 31 is set to 1b, processing occurs such that the packet described by the context first descriptor block is transmitted in the cycle whose number is specified in the cycleMatch field (bits 30-16). The cycleMatch field (bits 30-16) must match the low-order two bits of cycleSeconds and the 13-bit cycleCount field in the cycle start packet that is sent or received immediately before isochronous transmission begins. Since the isochronous transmit DMA controller may work ahead, the processing of the first descriptor block may begin slightly in advance of the actual cycle in which the first packet is transmitted. The effects of this bit, however, are impacted by the values of other bits in this register and are explained in the 1394 Open Host Controller Interface Specification. Once the context has become active, hardware clears this bit. 30-16 cycleMatch RSC This field contains a 15-bit value, corresponding to the low-order two bits of the isochronous cycle timer register at OHCI offset F0h (see Section 8.34) cycleSeconds field (bits 31-25) and the cycleCount field (bits 24-12). If bit 31 (cycleMatchEnable) is set to 1b, then this isochronous transmit DMA context becomes enabled for transmits when the low-order two bits of the isochronous cycle timer register at OHCI offset F0h cycleSeconds field (bits 31-25) and the cycleCount field (bits 24-12) value equal this field (cycleMatch) value. 15 run RSC Bit 15 is set to 1b by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. The controller changes this bit only on a system (hardware) or software reset. 14-13 RSVD R 12 wake RSU Software sets bit 12 to 1b to cause the controller to continue or resume descriptor processing. The controller clears this bit on every descriptor fetch. 11 dead RU The controller sets bit 11 to 1b when it encounters a fatal error, and clears the bit when software clears bit 15 (run) to 0b. 10 active RU The controller sets bit 10 to 1b when it is processing descriptors. 9-8 RSVD R 7-5 spd RU This field in not meaningful for isochronous transmit contexts. 4-0 event code RU Following an OUTPUT_LAST* command, the error code is indicated in this field. Possible values are: ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown. Reserved. Bits 14 and 13 return 00b when read. Reserved. Bits 9 and 8 return 00b when read. On an overflow for each running context, the isochronous transmit DMA supports up to 7 cycle skips, when the following are true: 1. Bit 11 (dead) in either the isochronous transmit or receive context control register is set to 1b. 2. Bits 4-0 (eventcode field) in either the isochronous transmit or receive context control register is set to evt_timeout. 3. Bit 24 (unrecoverableError) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) is set to 1b. September 2005 SCPS110 187 OHCI Registers 8.43 Isochronous Transmit Context Command Pointer Register The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the controller accesses when software enables an isochronous transmit context by setting bit 15 (run) in the isochronous transmit context control register (see Section 8.42) to 1b. The isochronous transmit DMA context command pointer can be read when a context is active. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, ..., 7). OHCI register offset: Register type: Default value: 20Ch + (16 * n) Read-only XXXX XXXXh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE X X X X X X X X X X X X X X X X BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE X X X X X X X X X X X X X X X X 8.44 Isochronous Receive Context Control Register The isochronous receive context control set/clear register controls options, state, and status for the isochronous receive DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). See Table 8-34 for a complete description of the register contents. OHCI register offset: Register type: Default value: 400h + (32 * n) set register 404h + (32 * n) clear register Read/Set/Clear/Update, Read/Set/Clear, Read/Set/Update, Read/Update, Read-only XX00 X0XXh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE X X X X X 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 X 0 0 0 0 X X X X X X X X Table 8-34. Isochronous Receive Context Control Register Description BIT FIELD NAME TYPE DESCRIPTION 31 bufferFill RSC When bit 31 is set to 1b, received packets are placed back-to-back to completely fill each receive buffer. When this bit is cleared, each received packet is placed in a single buffer. If bit 28 (multiChanMode) is set to 1b, then this bit must also be set to 1b. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1b. 30 isochHeader RSC When bit 30 is set to 1b, received isochronous packets include the complete 4-byte isochronous packet header seen by the link layer. The end of the packet is marked with a xferStatus in the first doublet, and a 16-bit timeStamp indicating the time of the most recently received (or sent) cycleStart packet. When this bit is cleared, the packet header is stripped from received isochronous packets. The packet header, if received, immediately precedes the packet payload. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1b. 29 188 cycleMatchEnable SCPS110 RSCU When bit 29 is set to 1b and the 13-bit cycleMatch field (bits 24-12) in the isochronous receive context match register (See Section 8.46) matches the 13-bit cycleCount field in the cycleStart packet, the context begins running. The effects of this bit, however, are impacted by the values of other bits in this register. Once the context has become active, hardware clears this bit. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1b. September 2005 OHCI Registers Table 8-34. Isochronous Receive Context Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 28 multiChanMode RSC When bit 28 is set to 1b, the corresponding isochronous receive DMA context receives packets for all isochronous channels enabled in the isochronous receive channel mask high register at OHCI offset 70h/74h (see Section 8.19) and isochronous receive channel mask low register at OHCI offset 78h/7Ch (see Section 8.20). The isochronous channel number specified in the isochronous receive context match register (see Section 8.46) is ignored. When this bit is cleared, the isochronous receive DMA context receives packets for the single channel specified in the isochronous receive context match register (see Section 8.46). Only one isochronous receive DMA context may use the isochronous receive channel mask registers (see Sections 8.19, and 8.20). If more than one isochronous receive context control register has this bit set, then the results are undefined. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1b. 27 dualBufferMode RSC 26-16 RSVD R 15 run RSCU 14-13 RSVD R 12 wake RSU Software sets bit 12 to 1b to cause the controller to continue or resume descriptor processing. The controller clears this bit on every descriptor fetch. 11 dead RU The controller sets bit 11 to 1b when it encounters a fatal error, and clears the bit when software clears bit 15 (run). The controller sets bit 10 to 1b when it is processing descriptors. 10 active RU 9-8 RSVD R 7-5 spd RU When bit 27 is set to 1b, receive packets are separated into first and second payload and streamed independently to the firstBuffer series and secondBuffer series as described in Section 10.2.3 in the 1394 Open Host Controller Interface Specification. Also, when bit 27 is set to 1b, both bits 28 (multiChanMode) and 31 (bufferFill) are cleared to 00b. The value of this bit does not change when either bit 10 (active) or bit 15 (run) is set to 1b. Reserved. Bits 26-16 return 0s when read. Bit 15 is set to 1b by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. The controller changes this bit only on a system (hardware) or software reset. Reserved. Bits 14 and 13 return 00b when read. Reserved. Bits 9 and 8 return 00b when read. This field indicates the speed at which the packet was received. 000 = 100M bits/sec 001 = 200M bits/sec 010 = 400M bits/sec All other values are reserved. 4-0 event code RU For bufferFill mode, possible values are: ack_complete, evt_descriptor_read, evt_data_write, and evt_unknown. Packets with data errors (either dataLength mismatches or dataCRC errors) and packets for which a FIFO overrun occurred are backed out. For packet-per-buffer mode, possible values are: ack_complete, ack_data_error, evt_long_packet, evt_overrun, evt_descriptor_read, evt_data_write, and evt_unknown. 8.45 Isochronous Receive Context Command Pointer Register The isochronous receive context command pointer register contains a pointer to the address of the first descriptor block that the controller accesses when software enables an isochronous receive context by setting bit 15 (run) in the isochronous receive context control register (see Section 8.44) to 1b. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). OHCI register offset: Register type: Default value: 40Ch + (32 * n) Read-only XXXX XXXXh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE X X X X X X X X X X X X X X X X BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE X X X X X X X X X X X X X X X X September 2005 SCPS110 189 OHCI Registers 8.46 Isochronous Receive Context Match Register The isochronous receive context match register starts an isochronous receive context running on a specified cycle number, filters incoming isochronous packets based on tag values, and waits for packets with a specified sync value. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). See Table 8-35 for a complete description of the register contents. OHCI register offset: Register type: Default value: 410Ch + (32 * n) Read/Write, Read-only XXXX XXXXh BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE X X X X 0 0 0 X X X X X X X X X BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE X X X X X X X X 0 X X X X X X X Table 8-35. Isochronous Receive Context Match Register Description BIT FIELD NAME TYPE 31 tag3 RW If bit 31 is set to 1b, this context matches on isochronous receive packets with a tag field of 11b. DESCRIPTION 30 tag2 RW If bit 30 is set to 1b, this context matches on isochronous receive packets with a tag field of 10b. 29 tag1 RW If bit 29 is set to 1b, this context matches on isochronous receive packets with a tag field of 01b. 28 tag0 RW If bit 28 is set to 1b, this context matches on isochronous receive packets with a tag field of 00b. 27 RSVD R 26-12 cycleMatch RW This field contains a 15-bit value corresponding to the two low-order bits of cycleSeconds and the 13-bit cycleCount field in the cycleStart packet. If cycleMatchEnable (bit 29) in the isochronous receive context control register (see Section 8.44) is set to 1b, then this context is enabled for receives when the two low-order bits of the isochronous cycle timer register at OHCI offset F0h (see Section 8.34) cycleSeconds field (bits 31-25) and cycleCount field (bits 24-12) value equal this field (cycleMatch) value. 11-8 sync RW This 4-bit field is compared to the sync field of each isochronous packet for this channel when the command descriptor w field is set to 11b. 7 RSVD R 6 tag1SyncFilter RW Reserved. Bit 27 returns 0b when read. Reserved. Bit 7 returns 0b when read. If bit 6 and bit 29 (tag1) are set to 1b, then packets with tag 01b are accepted into the context if the two most significant bits of the packet sync field are 00b. Packets with tag values other than 01b are filtered according to bit 28 (tag0), bit 30 (tag2), and bit 31 (tag3) without any additional restrictions. If this bit is cleared, then this context matches on isochronous receive packets as specified in bits 28-31 (tag0-tag3) with no additional restrictions. 5-0 190 channelNumber SCPS110 RW This 6-bit field indicates the isochronous channel number for which this isochronous receive DMA context accepts packets. September 2005 TI Extension Registers 9 TI Extension Registers The TI extension base address register provides a method of accessing memory-mapped TI extension registers. See Section 7.9, TI Extension Base Address Register, for register bit field details. See Table 9-1 for the TI extension register listing. Table 9-1. TI Extension Register Map 9.1 REGISTER NAME OFFSET Reserved 00h-A7Fh Isochronous Receive DV Enhancement Set A80h Isochronous Receive DV Enhancement Clear A84h Link Enhancement Control Set A88h Link Enhancement Control Clear A8Ch Isochronous Transmit Context 0 Timestamp Offset A90h Isochronous Transmit Context 1 Timestamp Offset A94h Isochronous Transmit Context 2 Timestamp Offset A98h Isochronous Transmit Context 3 Timestamp Offset A9Ch Isochronous Transmit Context 4 Timestamp Offset AA0h Isochronous Transmit Context 5 Timestamp Offset AA4h Isochronous Transmit Context 6 Timestamp Offset AA8h Isochronous Transmit Context 7 Timestamp Offset AACh DV and MPEG2 Timestamp Enhancements The DV timestamp enhancements are enabled by bit 8 (enab_dv_ts) in the link enhancement control register located at PCI offset F4h and are aliased in TI extension register space at offset A88h (set) and A8Ch (clear). The DV and MPEG transmit enhancements are enabled separately by bits in the link enhancement control register located in PCI configuration space at PCI offset F4h. The link enhancement control register is also aliased as a set/clear register in TI extension space at offset A88h (set) and A8Ch (clear). Bit 8 (enab_dv_ts) of the link enhancement control register enables DV timestamp support. When enabled, the link calculates a timestamp based on the cycle timer and the timestamp offset register and substitutes it in the SYT field of the CIP once per DV frame. Bit 10 (enab_mpeg_ts) of the link enhancement control register enables MPEG timestamp support. Two MPEG time stamp modes are supported. The default mode calculates an initial delta that is added to the calculated timestamp in addition to a user-defined offset. The initial offset is calculated as the difference in the intended transmit cycle count and the cycle count field of the timestamp in the first TSP of the MPEG2 stream. The use of the initial delta can be controlled by bit 31 (DisableInitialOffset) in the timestamp offset register (see Section 9.5). The MPEG2 timestamp enhancements are enabled by bit 10 (enab_mpeg_ts) in the link enhancement control register located at PCI offset F4h and aliased in TI extension register space at offset A88h (set) and A8Ch (clear). When bit 10 (enab_mpeg_ts) is set to 1b, the hardware applies the timestamp enhancements to isochronous transmit packets that have the tag field equal to 01b in the isochronous packet header and a FMT field equal to 10h. September 2005 SCPS110 191 TI Extension Registers 9.2 Isochronous Receive Digital Video Enhancements The DV frame sync and branch enhancement provides a mechanism in buffer-fill mode to synchronize 1394 DV data that is received in the correct order to DV frame-sized data buffers described by several INPUT_MORE descriptors (see 1394 Open Host Controller Interface Specification, Release 1.1). This is accomplished by waiting for the start-of-frame packet in a DV stream before transferring the received isochronous stream into the memory buffer described by the INPUT_MORE descriptors. This can improve the DV capture application performance by reducing the amount of processing overhead required to strip the CIP header and copy the received packets into frame-sized buffers. The start of a DV frame is represented in the 1394 packet as a 16-bit pattern of 1FX7h (first byte 1Fh and second byte X7h) received as the first two bytes of the third quadlet in a DV isochronous packet. 9.3 Isochronous Receive Digital Video Enhancements Register The isochronous receive digital video enhancements register enables the DV enhancements in the PCIxx12 controller. The bits in this register may only be modified when both the active (bit 10) and run (bit 15) bits of the corresponding context control register are 00b. See Table 9-2 for a complete description of the register contents. TI extension register offset: Register type: Default value: A80h set register A84h clear register Read/Set/Clear, Read-only 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 9-2. Isochronous Receive Digital Video Enhancements Register Description BIT FIELD NAME TYPE 31-14 RSVD R 13 DV_Branch3 RSC When bit 13 is set to 1b, the isochronous receive context 3 synchronizes reception to the DV frame start tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 12 (CIP_Strip3) is set to 1b and bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 460h/464h (see Section 8.44) is cleared to 0b. 12 CIP_Strip3 RSC When bit 12 is set to 1b, the isochronous receive context 3 strips the first two quadlets of payload. This bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 460h/464h (see Section 8.44) is cleared to 0b. 11-10 RSVD R 9 DV_Branch2 RSC When bit 9 is set to 1b, the isochronous receive context 2 synchronizes reception to the DV frame start tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 8 (CIP_Strip2) is set to 1b and bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 440h/444h (see Section 8.44) is cleared to 0b. 8 CIP_Strip2 RSC When bit 8 is set to 1b, the isochronous receive context 2 strips the first two quadlets of payload. This bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 440h/444h (see Section 8.44) is cleared to 0b. 7-6 RSVD R 5 DV_Branch1 RSC 192 SCPS110 DESCRIPTION Reserved. Bits 31-14 return 0s when read. Reserved. Bits 11 and 10 return 00b when read. Reserved. Bits 7 and 6 return 00b when read. When bit 5 is set to 1b, the isochronous receive context 1 synchronizes reception to the DV frame start tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 4 (CIP_Strip1) is set to 1b and bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 420h/424h (see Section 8.44) is cleared to 0b. September 2005 TI Extension Registers Table 9-2. Isochronous Receive Digital Video Enhancements Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 4 CIP_Strip1 RSC When bit 4 is set to 1b, the isochronous receive context 1 strips the first two quadlets of payload. This bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 420h/424h (see Section 8.44) is cleared to 0b. 3-2 RSVD R 1 DV_Branch0 RSC When bit 1 is set to 1b, the isochronous receive context 0 synchronizes reception to the DV frame start tag in bufferfill mode if input_more.b = 01b and jumps to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 0 (CIP_Strip0) is set to 1b and bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 400h/404h (see Section 8.44) is cleared to 0b. 0 CIP_Strip0 RSC When bit 0 is set to 1b, the isochronous receive context 0 strips the first two quadlets of payload. This bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 400h/404h (see Section 8.44) is cleared to 0b. September 2005 Reserved. Bits 3 and 2 return 00b when read. SCPS110 193 TI Extension Registers 9.4 Link Enhancement Register This register is a memory-mapped set/clear register that is an alias of the link enhancement control register at PCI offset F4h. These bits may be initialized by software. Some of the bits may also be initialized by a serial EEPROM, if one is present, as noted in the bit descriptions below. If the bits are to be initialized by software, then the bits must be initialized prior to setting bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see Section 8.16). See Table 9-3 for a complete description of the register contents. TI extension register offset: Register type: Default value: A88h set register A8Ch clear register Read/Set/Clear, Read-only 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Table 9-3. Link Enhancement Register Description BIT FIELD NAME TYPE 31-16 RSVD R 15 dis_at_pipeline RW 14 RSVD R 13-12 atx_thresh RW DESCRIPTION Reserved. Bits 31-16 return 0000h when read. Disable AT pipelining. When bit 15 is set to 1b, out-of-order AT pipelining is disabled. The default value for this bit is 0b. Reserved. Bit 14 defaults to 0b and must remain 0b for normal operation of the OHCI core. This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the controller retries the packet, it uses a 2K-byte threshold, resulting in a store-and-forward operation. 00 = Threshold ~ 2K bytes resulting in a store-and-forward operation 01 = Threshold ~ 1.7K bytes (default) 10 = Threshold ~ 1K bytes 11 = Threshold ~ 512 bytes These bits fine-tune the asynchronous transmit threshold. For most applications the 1.7K-byte threshold is optimal. Changing this value may increase or decrease the 1394 latency depending on the average PCI bus latency. Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds or when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger than the AT threshold, then the remaining data must be received before the AT FIFO is emptied; otherwise, an underrun condition occurs, resulting in a packet error at the receiving node. As a result, the link then commences a store-and-forward operation. It waits until it has the complete packet in the FIFO before retransmitting it on the second attempt to ensure delivery. An AT threshold of 2K results in a store-and-forward operation, which means that asynchronous data is not transmitted until an end-of-packet token is received. Restated, setting the AT threshold to 2K results in only complete packets being transmitted. Note that this controller always uses a store-and-forward operation when the asynchronous transmit retries register at OHCI offset 08h (see Section 8.3) is cleared. 11 RSVD R Reserved. Bit 11 returns 0b when read. 10 enab_mpeg_ts RW 9 RSVD R 8 enab_dv_ts RW Enable DV CIP timestamp enhancement. When bit 8 is set to 1b, the enhancement is enabled for DV CIP transmit streams (FMT = 00h). The default value for this bit is 0b. 7 enab_unfair RW Enable asynchronous priority requests. OHCI-Lynx compatible. Setting bit 7 to 1b enables the link to respond to requests with priority arbitration. It is recommended that this bit be set to 1b. The default value for this bit is 0b. Enable MPEG CIP timestamp enhancement. When bit 9 is set to 1b, the enhancement is enabled for MPEG CIP transmit streams (FMT = 20h). The default value for this bit is 0b. Reserved. Bit 9 returns 0b when read. This bit is cleared only by the assertion of GRST. 194 SCPS110 September 2005 TI Extension Registers Table 9-3. Link Enhancement Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 6 RSVD R This bit is not assigned in the PCIxx12 follow-on products, because this bit location loaded by the serial EEPROM from the enhancements field corresponds to bit 23 (programPhyEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16). 5-3 RSVD R Reserved. Bits 5-3 return 000b when read. 2 RSVD R Reserved. Bit 2 returns 0b when read. 1 enab_accel RW 0 RSVD R Enable acceleration enhancements. OHCI-Lynx compatible. When bit 1 is set to 1b, the PHY layer is notified that the link supports the IEEE Std 1394a-2000 acceleration enhancements, that is, ack-accelerated, fly-by concatenation, etc. It is recommended that this bit be set to 1b. The default value for this bit is 0b. Reserved. Bit 0 returns 0b when read. This bit is cleared only by the assertion of GRST. 9.5 Timestamp Offset Register The value of this register is added as an offset to the cycle timer value when using the MPEG, DV, and CIP enhancements. A timestamp offset register is implemented per isochronous transmit context. The n value following the offset indicates the context number (n = 0, 1, 2, 3, ..., 7). These registers are programmed by software as appropriate. See Table 9-4 for a complete description of the register contents. TI extension register offset: Register type: Default value: A90h + (4*n) Read/Write, Read-only 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 9-4. Timestamp Offset Register Description BIT FIELD NAME TYPE DESCRIPTION 31 DisableInitialOffset RW Bit 31 disables the use of the initial timestamp offset when the MPEG2 enhancements are enabled. A value of 0b indicates the use of the initial offset, a value of 1b indicates that the initial offset must not be applied to the calculated timestamp. This bit has no meaning for the DV timestamp enhancements. The default value for this bit is 0b. 30-25 RSVD R 24-12 CycleCount RW This field adds an offset to the cycle count field in the timestamp when the DV or MPEG2 enhancements are enabled. The cycle count field is incremented modulo 8000; therefore, values in this field must be limited between 0 and 7999. The default value for this field is all 0b.. 11-0 CycleOffset RW This field adds an offset to the cycle offset field in the timestamp when the DV or MPEG2 enhancements are enabled. The cycle offset field is incremented modulo 3072; therefore, values in this field must be limited between 0 and 3071. The default value for this field is 000h. September 2005 Reserved. Bits 30-25 return 000000b when read. SCPS110 195 PHY Register Configuration 10 PHY Register Configuration There are 16 accessible internal registers in the PCIxx12 controller. The configuration of the registers at addresses 0h through 7h (the base registers) is fixed, whereas the configuration of the registers at addresses 8h through Fh (the paged registers) is dependent upon which one of eight pages, numbered 0h through 7h, is currently selected. The selected page is set in base register 7h. 10.1 Base Registers Table 10-1 shows the configuration of the base registers, and Table 10-2 shows the corresponding field descriptions. The base register field definitions are unaffected by the selected page number. A reserved register or register field (marked as Reserved in the following register configuration tables) is read as 0, but is subject to future usage. All registers in address pages 2 through 6 are reserved. Table 10-1. Base Register Configuration BIT POSITION ADDRESS 0 1 0000 0001 3 4 5 Physical ID RHB IBR 6 7 R CPS Gap_Count 0010 Extended (111b) Reserved Total_Ports (0010b) 0011 Max_Speed (010b) Reserved Delay (0000b) 0100 LCtrl C 0101 Watchdog ISBR 0110 0111 196 2 SCPS110 Jitter (000b) Loop Pwr_fail Pwr_Class Timeout Port_event Enab_accel Enab_multi Reserved Page_Select Reserved Port_Select September 2005 PHY Register Configuration Table 10-2. Base Register Field Descriptions FIELD SIZE TYPE DESCRIPTION Physical ID 6 R This field contains the physical address ID of this node determined during self-ID. The physical ID is invalid after a bus reset until self-ID has completed as indicated by an unsolicited register-0 status transfer. R 1 R Root. This bit indicates that this node is the root node. The R bit is cleared to 0b by bus reset and is set to 1b during tree-ID if this node becomes root. CPS 1 R Cable-power-status. This bit indicates the state of the CPS input terminal. The CPS terminal is normally tied to serial bus cable power through a 400-k resistor. A 0b in this bit indicates that the cable power voltage has dropped below its threshold for ensured reliable operation. RHB 1 R/W Root-holdoff bit. This bit instructs the PHY layer to attempt to become root after the next bus reset. The RHB bit is cleared to 0b by a system (hardware) reset and is unaffected by a bus reset. IBR 1 R/W Initiate bus reset. This bit instructs the PHY layer to initiate a long (166 s) bus reset at the next opportunity. Any receive or transmit operation in progress when this bit is set completes before the bus reset is initiated. The IBR bit is cleared to 0b after a system (hardware) reset or a bus reset. Gap_Count 6 R/W Arbitration gap count. This value sets the subaction (fair) gap, arb-reset gap, and arb-delay times. The gap count can be set either by a write to the register, or by reception or transmission of a PHY_CONFIG packet. The gap count is reset to 3Fh by system (hardware) reset or after two consecutive bus resets without an intervening write to the gap count register (either by a write to the PHY register or by a PHY_CONFIG packet). Extended 3 R Extended register definition. For the controller, this field is 111b, indicating that the extended register set is implemented. Total_Ports 4 R Number of ports. This field indicates the number of ports implemented in the PHY layer. For the controller this field is 2. Max_Speed 3 R PHY speed capability. For the PCIxx12 PHY layer this field is 010b, indicating S400 speed capability. Delay 4 R PHY repeater data delay. This field indicates the worst case repeater data delay of the PHY layer, expressed as 144+(delay x 20) ns. For the controller this field is 0h. LCtrl 1 R/W Link-active status control. This bit controls the active status of the LLC as indicated during self-ID. The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID packet. The LLC is considered active only if both the LPS input is active and the LCtrl bit is set. The LCtrl bit provides a software controllable means to indicate the LLC active/status in lieu of using the LPS input. The LCtrl bit is set to 1b by a system (hardware) reset and is unaffected by a bus reset. NOTE: The state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state of the LCtrl bit. If the PHY-LLC interface is operational as determined by the LPS input being active, received packets and status information continue to be presented on the interface, and any requests indicated on the LREQ input are processed, even if the LCtrl bit is cleared to 0b. C 1 R/W Contender status. This bit indicates that this node is a contender for the bus or isochronous resource manager. This bit is replicated in the c field (bit 20) of the self-ID packet. Jitter 3 R PHY repeater jitter. This field indicates the worst case difference between the fastest and slowest repeater data delay, expressed as (Jitter+1) x 20 ns. For the controller, this field is 000b. Pwr_Class 3 R/W Node power class. This field indicates this node power consumption and source characteristics and is replicated in the pwr field (bits 21-23) of the self-ID packet. This field is reset to the state specified by the PC0-PC2 input terminals upon a system (hardware) reset and is unaffected by a bus reset. See Table 10-9. Watchdog 1 R/W Watchdog enable. This bit, if set to 1b, enables the port event interrupt (Port_event) bit to be set whenever resume operations begin on any port. This bit is cleared to 0b by system (hardware) reset and is unaffected by bus reset. September 2005 SCPS110 197 PHY Register Configuration Table 10-2. Base Register Field Descriptions (Continued) FIELD ISBR SIZE TYPE DESCRIPTION 1 R/W Initiate short arbitrated bus reset. This bit, if set to 1b, instructs the PHY layer to initiate a short (1.3 s) arbitrated bus reset at the next opportunity. This bit is cleared to 0b by a bus reset. NOTE: Legacy IEEE Std 1394-1995 compliant PHY layers can not be capable of performing short bus resets. Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long bus reset being performed. Loop 1 R/W Loop detect. This bit is set to 1b when the arbitration controller times out during tree-ID start and may indicate that the bus is configured in a loop. This bit is cleared to 0b by system (hardware) reset or by writing a 1b to this register bit. If the Loop and Watchdog bits are both set and the LLC is or becomes inactive, the PHY layer activates the LLC to service the interrupt. NOTE: If the network is configured in a loop, only those nodes which are part of the loop generate a configuration-timeout interrupt. All other nodes instead time out waiting for the tree-ID and/or self-ID process to complete and then generate a state time-out interrupt and bus-reset. Pwr_fail 1 R/W Cable power failure detect. This bit is set to 1b whenever the CPS input transitions from high to low indicating that cable power may be too low for reliable operation. This bit is cleared to 0b by system (hardware) reset or by writing a 1b to this register bit. Timeout 1 R/W State time-out interrupt. This bit indicates that a state time-out has occurred (which also causes a bus reset to occur). This bit is cleared to 0b by system (hardware) reset or by writing a 1b to this register bit. Port_event 1 R/W Port event detect. This bit is set to 1b upon a change in the bias (unless disabled) connected, disabled, or fault bits for any port for which the port interrupt enable (Int_enable) bit is set. Additionally, if the Watchdog bit is set, the Port_event bit is set to 1b at the start of resume operations on any port. This bit is cleared to 0b by system (hardware) reset or by writing a 1b to this register bit. Enab_accel 1 R/W Enable accelerated arbitration. This bit enables the PHY layer to perform the various arbitration acceleration enhancements defined in IEEE Std 1394a-2000 (ACK-accelerated arbitration, asynchronous fly-by concatenation, and isochronous fly-by concatenation). This bit is cleared to 0b by system (hardware) reset and is unaffected by bus reset. Enab_multi 1 R/W Enable multispeed concatenated packets. This bit enables the PHY layer to transmit concatenated packets of differing speeds in accordance with the protocols defined in IEEE Std 1394a-2000. This bit is cleared to 0b by system (hardware) reset and is unaffected by bus reset. Page_Select 3 R/W Page_Select. This field selects the register page to use when accessing register addresses 8 through 15. This field is cleared to 000b by a system (hardware) reset and is unaffected by bus reset. Port_Select 4 R/W Port_Select. This field selects the port when accessing per-port status or control (for example, when one of the port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is cleared to 0h by system (hardware) reset and is unaffected by bus reset. 198 SCPS110 September 2005 PHY Register Configuration 10.2 Port Status Register The port status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. Table 10-3 shows the configuration of the port status page registers and Table 10-4 shows the corresponding field descriptions. If the selected port is not implemented, all registers in the port status page are read as 0. Table 10-3. Page 0 (Port Status) Register Configuration BIT POSITION ADDRESS 0 1 1000 AStat 1001 Peer_Speed 2 3 BStat Int_enable 4 5 6 7 Ch Con Bias Dis Fault 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved Reserved Table 10-4. Page 0 (Port Status) Register Field Descriptions FIELD SIZE TYPE DESCRIPTION AStat 2 R TPA line state. This field indicates the TPA line state of the selected port, encoded as follows: Code Arb Value 11 Z 10 0 01 1 00 invalid BStat 2 R TPB line state. This field indicates the TPB line state of the selected port. This field has the same encoding as the AStat field. Ch 1 R Child/parent status. A 1b indicates that the selected port is a child port. A 0b indicates that the selected port is the parent port. A disconnected, disabled, or suspended port is reported as a child port. The Ch bit is invalid after a bus reset until tree-ID has completed. Con 1 R Debounced port connection status. This bit indicates that the selected port is connected. The connection must be stable for the debounce time of approximately 341 ms for the Con bit to be set to 1b. The Con bit is cleared to 0b by system (hardware) reset and is unaffected by bus reset. NOTE: The Con bit indicates that the port is physically connected to a peer PHY device, but the port is not necessarily active. Bias 1 R Debounced incoming cable bias status. A 1b indicates that the selected port is detecting incoming cable bias. The incoming cable bias must be stable for the debounce time of 52 s for the Bias bit to be set to 1b. Dis 1 RW Port disabled control. If the Dis bit is set to 1b, the selected port is disabled. The Dis bit is cleared to 0b by system (hardware) reset (all ports are enabled for normal operation following system (hardware) reset). The Dis bit is not affected by bus reset. Peer_Speed 3 R Port peer speed. This field indicates the highest speed capability of the peer PHY device connected to the selected port, encoded as follows: Peer Speed Code 000 S100 001 S200 010 S400 011-111 invalid The Peer_Speed field is invalid after a bus reset until self-ID has completed. NOTE: Peer speed codes higher than 010b (S400) are defined in IEEE Std 1394a-2000. However, the controller is only capable of detecting peer speeds up to S400. September 2005 SCPS110 199 PHY Register Configuration Table 10-4. Page 0 (Port Status) Register Field Descriptions (Continued) FIELD SIZE TYPE DESCRIPTION Int_enable 1 RW Port event interrupt enable. When the Int_enable bit is set to 1b, a port event on the selected port sets the port event interrupt (Port_event) bit and notifies the link. This bit is cleared to 0b by a system (hardware) reset and is unaffected by bus reset. Fault 1 RW Fault. This bit indicates that a resume-fault or suspend-fault has occurred on the selected port, and that the port is in the suspended state. A resume-fault occurs when a resuming port fails to detect incoming cable bias from its attached peer. A suspend-fault occurs when a suspending port continues to detect incoming cable bias from its attached peer. Writing 1b to this bit clears the fault bit to 0b. This bit is cleared to 0b by system (hardware) reset and is unaffected by bus reset. 10.3 Vendor Identification Register The vendor identification page identifies the vendor/manufacturer and compliance level. The page is selected by writing 1 to the Page_Select field in base register 7. Table 10-5 shows the configuration of the vendor identification page, and Table 10-6 shows the corresponding field descriptions. Table 10-5. Page 1 (Vendor ID) Register Configuration BIT POSITION ADDRESS 0 1 2 3 4 1000 Compliance 1001 Reserved 1010 Vendor_ID[0] 1011 Vendor_ID[1] 1100 Vendor_ID[2] 1101 Product_ID[0] 1110 Product_ID[1] 1111 Product_ID[2] 5 6 7 Table 10-6. Page 1 (Vendor ID) Register Field Descriptions FIELD SIZE TYPE Compliance 8 R Compliance level. For the controller this field is 01h, indicating compliance with IEEE Std 1394a-2000. Vendor_ID 24 R Manufacturer's organizationally unique identifier (OUI). For the controller this field is 08 0028h (Texas Instruments) (the MSB is at register address 1010b). Product_ID 24 R Product identifier. For the controller this field is 42 4499h (the MSB is at register address 1101b). 200 SCPS110 DESCRIPTION September 2005 PHY Register Configuration 10.4 Vendor-Dependent Register The vendor-dependent page provides access to the special control features of the controller, as well as to configuration and status information used in manufacturing test and debug. This page is selected by writing 7 to the Page_Select field in base register 7. Table 10-7 shows the configuration of the vendor-dependent page, and Table 10-8 shows the corresponding field descriptions. Table 10-7. Page 7 (Vendor-Dependent) Register Configuration BIT POSITION ADDRESS 0 1000 NPA 1 2 3 4 Reserved 5 6 7 Link_Speed 1001 Reserved for test 1010 Reserved for test 1011 Reserved for test 1100 Reserved for test 1101 Reserved for test 1110 Reserved for test 1111 Reserved for test Table 10-8. Page 7 (Vendor-Dependent) Register Field Descriptions SIZE TYPE DESCRIPTION NPA FIELD 1 RW Null-packet actions flag. This bit instructs the PHY layer to not clear fair and priority requests when a null packet is received with arbitration acceleration enabled. If this bit is set to 1b, fair and priority requests are cleared only when a packet of more than 8 bits is received; ACK packets (exactly 8 data bits), null packets (no data bits), and malformed packets (less than 8 data bits) do not clear fair and priority requests. If this bit is cleared to 0b, fair and priority requests are cleared when any non-ACK packet is received, including null packets or malformed packets of less than 8 bits. This bit is cleared to 0b by system (hardware) reset and is unaffected by bus reset. Link_Speed 2 RW Link speed. This field indicates the top speed capability of the attached LLC. Encoding is as follows: Code Speed 00 S100 01 S200 10 S400 11 illegal This field is replicated in the sp field of the self-ID packet to indicate the speed capability of the node (PHY and LLC in combination). However, this field does not affect the PHY speed capability indicated to peer PHYs during self-ID; the PCIxx12 PHY layer identifies itself as S400 capable to its peers regardless of the value in this field. This field is set to 10b (S400) by system (hardware) reset and is unaffected by bus reset. September 2005 SCPS110 201 PHY Register Configuration 10.5 Power-Class Programming The PC0-PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field (bits 21-23) of the transmitted self-ID packet. Table 10-9 shows the descriptions of the various power classes. The default power-class value is loaded following a system (hardware) reset, but is overridden by any value subsequently loaded into the Pwr_Class field in register 4. Table 10-9. Power Class Descriptions PC0-PC2 202 DESCRIPTION 000 Node does not need power and does not repeat power. 001 Node is self-powered and provides a minimum of 15 W to the bus. 010 Node is self-powered and provides a minimum of 30 W to the bus. 011 Node is self-powered and provides a minimum of 45 W to the bus. 100 Node may be powered from the bus and is using up to 3 W. No additional power is needed to enable the link. 101 Reserved 110 Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link. 111 Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link. SCPS110 September 2005 Flash Media Controller Programming Model 11 Flash Media Controller Programming Model This section describes the internal PCI configuration registers used to program the the PCI6412, PCI6612, PCI7402, PCI7412, PCI7612, PCI8402, and PCI8412 flash media controller interface. All registers are detailed in the same format: a brief description for each register is followed by the register offset and a bit table describing the reset state for each register. A bit description table, typically included when the register contains bits of more than one type or purpose, indicates bit field names, a detailed field description, and field access tags which appear in the type column. Table 4-1 describes the field access tags. The controller is a multifunction PCI device. The flash media controller core is integrated as PCI function 2. The function 2 configuration header is compliant with the PCI Local Bus Specification as a standard header. Table 11-1 illustrates the configuration header that includes both the predefined portion of the configuration space and the user-definable registers. Table 11-1. Function 2 Configuration Register Map REGISTER NAME OFFSET Device ID Vendor ID 00h Status Command 04h Class code BIST Header type Latency timer Revision ID 08h Cache line size 0Ch Flash media base address 10h Reserved 14h-28h Subsystem ID Subsystem vendor ID 2Ch Reserved 30h Reserved PCI power-management capabilities pointer 34h Interrupt line 3Ch Reserved Maximum latency Minimum grant 38h Interrupt pin Reserved 40h Power-management capabilities Next item pointer PM data (Reserved) Power-management control and status 48h General control 4Ch PMCSR_BSE Reserved Capability ID 44h Subsystem access 50h Diagnostic 54h Reserved 58h-FCh One or more bits in this register are cleared only by the assertion of GRST. 11.1 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch. Function 2 offset: Register type: Default value: 00h Read-only 104Ch BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 September 2005 SCPS110 203 Flash Media Controller Programming Model 11.2 Device ID Register The device ID register contains a value assigned to the flash media controller by Texas Instruments. The device identification for the flash media controller is 803Bh. Function 2 offset: Register type: Default value: 02h Read-only 803Bh BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 11.3 Command Register The command register provides control over the PCIxx12 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 11-2 for a complete description of the register contents. Function 2 offset: Register type: Default value: 04h Read/Write, Read-only 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 11-2. Command Register Description BIT FIELD NAME TYPE 15-11 RSVD R 10 INT_DISABLE RW INTx disable. When set to 1b, this bit disables the function from asserting interrupts on the INTx signals. 0 = INTx assertion is enabled (default) 1 = INTx assertion is disabled 9 FBB_ENB R Fast back-to-back enable. The flash media interface does not generate fast back-to-back transactions; therefore, bit 9 returns 0b when read. 8 SERR_ENB RW SERR enable. When bit 8 is set to 1b, the flash media interface SERR driver is enabled. SERR can be asserted after detecting an address parity error on the PCI bus. 7 STEP_ENB R Address/data stepping control. The flash media interface does not support address/data stepping; therefore, bit 7 is hardwired to 0b. 6 PERR_ENB RW Parity error enable. When bit 6 is set to 1b, the flash media interface is enabled to drive PERR response to parity errors through the PERR signal. 5 VGA_ENB R VGA palette snoop enable. The flash media interface does not feature VGA palette snooping; therefore, bit 5 returns 0b when read. 4 MWI_ENB RW Memory write and invalidate enable. The flash media controller does not generate memory write invalidate transactions; therefore, bit 4 returns 0b when read. 3 SPECIAL R Special cycle enable. The flash media interface does not respond to special cycle transactions; therefore, bit 3 returns 0b when read. 2 MASTER_ENB RW Bus master enable. When bit 2 is set to 1b, the flash media interface is enabled to initiate cycles on the PCI bus. 1 MEMORY_ENB RW Memory response enable. Setting bit 1 to 1b enables the flash media interface to respond to memory cycles on the PCI bus. 0 IO_ENB R I/O space enable. The flash media interface does not implement any I/O-mapped functionality; therefore, bit 0 returns 0b when read. 204 SCPS110 DESCRIPTION Reserved. Bits 15-11 return 00000b when read. September 2005 Flash Media Controller Programming Model 11.4 Status Register The status register provides device information to the host system. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. Bits in this register may be read normally. A bit in the status register is reset when 1b is written to that bit location; a 0b written to a bit location has no effect. See Table 11-3 for a complete description of the register contents. Function 2 offset: Register type: Default value: 06h Read/Clear/Update, Read-only 0210h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 Table 11-3. Status Register Description BIT FIELD NAME TYPE DESCRIPTION 15 PAR_ERR RCU Detected parity error. Bit 15 is set to 1b when either an address parity or data parity error is detected. 14 SYS_ERR RCU Signaled system error. Bit 14 is set to 1b when SERR is enabled and the flash media controller has signaled a system error to the host. 13 MABORT RCU Received master abort. Bit 13 is set to 1b when a cycle initiated by the flash media controller on the PCI bus has been terminated by a master abort. 12 TABORT_REC RCU Received target abort. Bit 12 is set to 1b when a cycle initiated by the flash media controller on the PCI bus was terminated by a target abort. 11 TABORT_SIG RCU Signaled target abort. Bit 11 is set to 1b by the flash media controller when it terminates a transaction on the PCI bus with a target abort. 10-9 PCI_SPEED R DEVSEL timing. Bits 10 and 9 encode the timing of DEVSEL and are hardwired to 01b, indicating that the flash media controller asserts this signal at a medium speed on nonconfiguration cycle accesses. Data parity error detected. Bit 8 is set to 1b when the following conditions have been met: a. PERR was asserted by any PCI device including the flash media controller. b. The flash media controller was the bus master during the data parity error. c. Bit 6 (PERR_EN) in the command register at offset 04h in the PCI configuration space (see Section 11.3) is set to 1b. 8 DATAPAR RCU 7 FBB_CAP R Fast back-to-back capable. The flash media controller cannot accept fast back-to-back transactions; therefore, bit 7 is hardwired to 0b. 6 UDF R User-definable features (UDF) supported. The flash media controller does not support the UDF; therefore, bit 6 is hardwired to 0b. 5 66MHZ R 66-MHz capable. The flash media controller operates at a maximum PCLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0b. 4 CAPLIST R Capabilities list. Bit 4 returns 1b when read, indicating that the flash media controller supports additional PCI capabilities. Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE) in the command register (offset 04h, see Section 11.3) is a 0b and this bit is 1b, is the function's INTx signal asserted. Setting the INT_DISABLE bit to 1b has no effect on the state of this bit. This bit is set only when a valid interrupt condition exists. This bit is not set when an interrupt condition exists and signaling of that event is not enabled. 3 INT_STATUS RU 2-0 RSVD R September 2005 Reserved. Bits 2-0 return 000b when read. SCPS110 205 Flash Media Controller Programming Model 11.5 Class Code and Revision ID Register The class code and revision ID register categorizes the base class, subclass, and programming interface of the function. The base class is 01h, identifying the controller as a mass storage controller. The subclass is 80h, identifying the function as other mass storage controller, and the programming interface is 00h. Furthermore, the TI chip revision is indicated in the least significant byte (00h). See Table 11-4 for a complete description of the register contents. Function 2 offset: Register type: Default value: 08h Read-only 0180 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 11-4. Class Code and Revision ID Register Description BIT FIELD NAME TYPE DESCRIPTION 31-24 BASECLASS R Base class. This field returns 01h when read, which classifies the function as a mass storage controller. 23-16 SUBCLASS R Subclass. This field returns 80h when read, which specifically classifies the function as other mass storage controller. 15-8 PGMIF R Programming interface. This field returns 00h when read. 7-0 CHIPREV R Silicon revision. This field returns 00h when read, which indicates the silicon revision of the flash media controller. 11.6 Latency Timer and Class Cache Line Size Register The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the flash media controller. See Table 11-5 for a complete description of the register contents. Function 2 offset: Register type: Default value: 0Ch Read/Write 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 11-5. Latency Timer and Class Cache Line Size Register Description BIT FIELD NAME TYPE DESCRIPTION 15-8 LATENCY_TIMER RW PCI latency timer. The value in this register specifies the latency timer for the flash media controller, in units of PCI clock cycles. When the flash media controller is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires before the flash media transaction has terminated, then the flash media controller terminates the transaction when its GNT is deasserted. 7-0 CACHELINE_SZ RW Cache line size. This value is used by the flash media controller during memory write and invalidate, memory-read line, and memory-read multiple transactions. 206 SCPS110 September 2005 Flash Media Controller Programming Model 11.7 Header Type and BIST Register The header type and built-in self-test (BIST) register indicates the flash media controller PCI header type and no built-in self-test. See Table 11-6 for a complete description of the register contents. Function 2 offset: Register type: Default value: 0Eh Read-only 0080h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Table 11-6. Header Type and BIST Register Description BIT FIELD NAME TYPE DESCRIPTION 15-8 BIST R Built-in self-test. The flash media controller does not include a BIST; therefore, this field returns 00h when read. 7-0 HEADER_TYPE R PCI header type. The flash media controller includes the standard PCI header. Bit 7 indicates if the flash media is a multifunction device. 11.8 Flash Media Base Address Register The flash media base address register specifies the base address of the memory-mapped interface registers. Since the implementation of the flash media controller core in the controller contains 2 sockets, the size of the base address register is 4096 bytes. See Table 11-7 for a complete description of the register contents. Function 2 offset: Register type: Default value: 10h Read/Write, Read-only 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 11-7. Flash Media Base Address Register Description BIT FIELD NAME TYPE 31-13 BAR RW DESCRIPTION 12-4 RSVD R Reserved. Bits 12-4 return 0s when read to indicate that the size of the base address is 8192 bytes. Base address. This field specifies the upper bits of the 32-bit starting base address. 3 PREFETCHABLE R Prefetchable. Since this base address is not prefetchable, bit 3 returns 0b when read. 2-1 RSVD R Reserved. Bits 2-1 return 00b when read. 0 MEM_INDICATOR R Memory space indicator. Bit 0 is hardwired to 0b to indicate that the base address maps into memory space. 11.9 Subsystem Vendor Identification Register The subsystem identification register, used for system and option card identification purposes, may be required for certain operating systems. This read-only register is initialized through the EEPROM and can be written through the subsystem access register at PCI offset 50h (see Section 11.22). All bits in this register are reset by GRST only. Function 2 offset: Register type: Default value: 2Ch Read/Update 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 September 2005 SCPS110 207 Flash Media Controller Programming Model 11.10 Subsystem Identification Register The subsystem identification register, used for system and option card identification purposes, may be required for certain operating systems. This read-only register is initialized through the EEPROM and can be written through the subsystem access register at PCI offset 50h (see Section 11.22). All bits in this register are reset by GRST only. Function 2 offset: Register type: Default value: 2Eh Read/Update 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11.11 Capabilities Pointer Register The power-management capabilities pointer register provides a pointer into the PCI configuration header where the power-management register block resides. Since the PCI power-management registers begin at 44h, this read-only register is hardwired to 44h. Function 2 offset: Register type: Default value: 34h Read-only 44h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 1 0 0 0 1 0 0 11.12 Interrupt Line Register The interrupt line register is programmed by the system and indicates to the software which interrupt line the flash media interface has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not yet been assigned to the function. Function 2 offset: Register type: Default value: 3Ch Read/Write FFh BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 1 1 1 1 1 1 1 1 208 SCPS110 September 2005 Flash Media Controller Programming Model 11.13 Interrupt Pin Register This register decodes the interrupt select inputs and returns the proper interrupt value based on Table 11-8, indicating that the flash media interface uses an interrupt. If one of the USE_INTx terminals is asserted, the interrupt select bits are ignored, and this register returns the interrupt value for the highest priority USE_INTx terminal that is asserted. If bit 28, the tie-all bit (TIEALL), in the system control register (PCI offset 80h, see Section 4.29) is set to 1b, then the controller asserts the USE_INTA input to the flash media controller core. If bit 28 (TIEALL) in the system control register (PCI offset 80h, see Section 4.29) is set to 0b, then none of the USE_INTx inputs are asserted and the interrupt for the flash media function is selected by the INT_SEL bits in the flash media general control register. Function 2 offset: Register type: Default value: 3Dh Read-only 0Xh BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 X X X Table 11-8. PCI Interrupt Pin Register INT_SEL BITS USE_INTA INTPIN 00 0 01h (INTA) 01 0 02h (INTB) 10 0 03h (INTC) 11 0 04h (INTD) XX 1 01h (INTA) 11.14 Minimum Grant Register The minimum grant register contains the minimum grant value for the flash media controller core. Function 2 offset: Register type: Default value: 3Eh Read/Update 07h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 1 1 1 Table 11-9. Minimum Grant Register Description BIT 7-0 FIELD NAME MIN_GNT September 2005 TYPE DESCRIPTION RU Minimum grant. The contents of this field may be used by host BIOS to assign a latency timer register value to the flash media controller. The default for this register indicates that the flash media controller may need to sustain burst transfers for nearly 64 s and thus request a large value be programmed in bits 15-8 of the latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see Section 11.6). SCPS110 209 Flash Media Controller Programming Model 11.15 Maximum Latency Register The maximum latency register contains the maximum latency value for the flash media controller core. Function 2 offset: Register type: Default value: 3Eh Read/Update 04h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 1 0 0 Table 11-10. Maximum Latency Register Description BIT FIELD NAME TYPE DESCRIPTION 7-0 MAX_LAT RU Maximum latency. The contents of this field may be used by host BIOS to assign an arbitration priority level to the flash media controller. The default for this register indicates that the flash media controller may need to access the PCI bus as often as every 0.25 s; thus, an extremely high priority level is requested. The contents of this field may also be loaded through the serial EEPROM. 11.16 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the next capability item. See Table 11-11 for a complete description of the register contents. Function 2 offset: Register type: Default value: 44h Read-only 0001h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Table 11-11. Capability ID and Next Item Pointer Registers Description BIT FIELD NAME TYPE DESCRIPTION 15-8 NEXT_ITEM R Next item pointer. The flash media controller supports only one additional capability, PCI power management, that is communicated to the system through the extended capabilities list; therefore, this field returns 00h when read. 7-0 CAPABILITY_ID R Capability identification. This field returns 01h when read, which is the unique ID assigned by the PCI SIG for PCI power-management capability. 210 SCPS110 September 2005 Flash Media Controller Programming Model 11.17 Power-Management Capabilities Register The power-management capabilities register indicates the capabilities of the flash media controller related to PCI power management. See Table 11-12 for a complete description of the register contents. Function 2 offset: Register type: Default value: 46h Read/Update, Read-only 7E02h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 Table 11-12. Power-Management Capabilities Register Description BIT FIELD NAME TYPE DESCRIPTION 15 PME_D3COLD RU PME support from D3cold. This bit can be set to 1b or cleared to 0b via bit 4 (D3_COLD) in the general control register at offset 4Ch in the PCI configuration space (see Section 11.21). When this bit is set to 1b, it indicates that the controller is capable of generating a PME wake event from D3cold. This bit state is dependent upon the VAUX implementation and may be configured by using bit 4 (D3_COLD) in the general control register (see Section 11.21). 14-11 PME_SUPPORT R PME support. This 4-bit field indicates the power states from which the flash media interface may assert PME. This field returns a value of 1111b by default, indicating that PME may be asserted from the D3hot, D2, D1, and D0 power states. 10 D2_SUPPORT R D2 support. Bit 10 is hardwired to 1b, indicating that the flash media controller supports the D2 power state. 9 D1_SUPPORT R D1 support. Bit 9 is hardwired to 1b, indicating that the flash media controller supports the D1 power state. Auxiliary current. This 3-bit field reports the 3.3-VAUX auxiliary current requirements. When bit 15 (PME_D3COLD) is cleared, this field returns 000b; otherwise, it returns 001b. 8-6 AUX_CURRENT R 5 DSI R Device-specific initialization. This bit returns 0b when read, indicating that the flash media controller does not require special initialization beyond the standard PCI configuration header before a generic class driver is able to use it. 4 RSVD R Reserved. Bit 4 returns 0b when read. 3 PME_CLK R PME clock. This bit returns 0b when read, indicating that the PCI clock is not required for the flash media controller to generate PME. R Power-management version. If bit 7 (PCI_PM_VERSION_CTRL) in the general control register (offset 4Ch, see Section 11.21) is 0b, this field returns 010b indicating PCI Bus Power Management Interface Specification (Revision 1.1) compatibility. If the PCI_PM_VERSION_CTRL bit is 1b, this field returns 011b indicating PCI Bus Power Management Interface Specification (Revision 1.2) compatibility. 2-0 PM_VERSION September 2005 000b = Self-powered 001b = 55 mA (3.3-VAUX maximum current required) SCPS110 211 Flash Media Controller Programming Model 11.18 Power-Management Control and Status Register The power-management control and status register implements the control and status of the flash media controller. This register is not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See Table 11-13 for a complete description of the register contents. Function 2 offset: Register type: Default value: 48h Read/Clear, Read/Write, Read-only 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 11-13. Power-Management Control and Status Register Description BIT FIELD NAME TYPE 15 PME_STAT RCU DESCRIPTION 14-13 DATA_SCALE R This field returns 00b, because the data register is not implemented. 12-9 DATA_SELECT R This field returns 0h, because the data register is not implemented. 8 PME_EN RW 7-2 RSVD R PME status. This bit defaults to 0b. PME enable. Enables PME signaling. assertion is disabled. Reserved. Bits 7-2 return 00 0000b when read. Power state. This 2-bit field determines the current power state and sets the flash media controller to a new power state. This field is encoded as follows: 1-0 PWR_STATE 00 = Current power state is D0. 01 = Current power state is D1. 10 = Current power state is D2. 11 = Current power state is D3hot. RW One or more bits in this register are cleared only by the assertion of GRST. 11.19 Power-Management Bridge Support Extension Register The power-management bridge support extension register provides extended power-management features not applicable to the flash media controller; thus, it is read-only and returns 00h when read. Function 2 offset: Register type: Default value: 4Ah Read-only 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 11.20 Power-Management Data Register The power-management bridge support extension register provides extended power-management features not applicable to the flash media controller; thus, it is read-only and returns 00h when read. Function 2 offset: Register type: Default value: 4Bh Read-only 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 212 SCPS110 September 2005 Flash Media Controller Programming Model 11.21 General Control Register The general control register provides miscellaneous PCI-related configuration. See Table 11-14 for a complete description of the register contents. Function 2 offset: Register type: Default value: 4Ch Read/Write, Read-only 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 11-14. General Control Register BIT FIELD NAME TYPE DESCRIPTION 7 PCI_PM_ VERSION_CTRL RW PCI power-management version control. This bit controls the value reported in bits 2-0 (PM_VERSION) of the power-management capabilities register (offset 46h, see Section 11.17). 0 = PM_VERSION field reports 010b for PCI Bus Power Management Interface Specification (Revision 1.1) compatability. 1 = PM_VERSION field reports 011b for PCI Bus Power Management Interface Specification (Revision 1.2) compatability. 6-5 INT_SEL RW Interrupt select. These bits are program the INTPIN register and set which interrupt output is used. This field is ignored if one of the USE_INTx terminals is asserted. 00 = 01 = 10 = 11 = 4 D3_COLD RW INTA INTB INTC INTD D3cold PME support. This bit sets and clears bit 15 (PME_D3COLD) in the power-management capabilities register (offset 46h, see Section 11.17). 3 RSVD R 2 SM_DIS RW Reserved. Bit 3 returns 0b when read. SmartMedia disable. Setting this bit disables support for SmartMedia cards. The flash media controller reports a SmardMedia card as an unsupported card if this bit is set. If this bit is set, then all of the SM_SUPPORT bits in the socket enumeration register are 0b. 1 MMC_SD_DIS RW MMC/SD disable. Setting this bit disables support for MMC/SD cards. The flash media controller reports a MMC/SD card as an unsupported card if this bit is set. If this bit is set, then all of the SD_SUPPORT bits in the socket enumeration register are 0b. 0 MS_DIS RW Memory Stick disable. Setting this bit disables support for Memory Stick cards. The flash media controller reports a Memory Stick card as an unsupported card if this bit is set. If this bit is set, then all of the MS_SUPPORT bits in the socket enumeration register are 0b. One or more bits in this register are cleared only by the assertion of GRST. September 2005 SCPS110 213 Flash Media Controller Programming Model 11.22 Subsystem Access Register The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at PCI offsets 2Ch and 2Eh, respectively. See Table 11-15 for a complete description of the register contents. All bits in this register are reset by GRST only. Function 2 offset: Register type: Default value: 50h Read/Write 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 11-15. Subsystem Access Register Description BIT FIELD NAME TYPE DESCRIPTION 31-16 SubsystemID RW Subsystem device ID. The value written to this field is aliased to the subsystem ID register at PCI offset 2Eh. 15-0 SubsystemVendorID RW Subsystem vendor ID. The value written to this field is aliased to the subsystem vendor ID register at PCI offset 2Ch. 11.23 Diagnostic Register This register programs the M and N inputs to the PLL and enables the diagnostic modes. The default values for M and N in this register set the PLL output to be 80 MHz, which is divided to get the 40 MHz and 20 MHz needed by the flash media cores. See Table 11-16 for a complete description of the register contents. All bits in this register are reset by GRST only. Function 2 offset: Register type: Default value: BIT NUMBER 31 30 54h Read-only, Read/Write 0000 0105h 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 Table 11-16. Diagnostic Register Description BIT SIGNAL TYPE 31-17 TBD_CTRL R 16 DIAGNOSTIC RW 15-11 RSVD R 10-8 PLL_N RW 7-5 RSVD R 4-0 PLL_M RW 214 SCPS110 FUNCTION PLL control bits. These bits are reserved for PLL control and test bits. Diagnostic test bit. This test bit shortens the PLL clock CLK_VALID time and shortens the card detect debounce times for simulation and TDL. Reserved. Bits 15-11 return 00000b when read. PLL_N input. The default value of this field is 001b. Reserved. Bits 7-5 return 000b when read. PLL_M input. The default value of this field is 05h. September 2005 SD Host Controller Programming Model 12 SD Host Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI6412, PCI6612, PCI7402, PCI7412, PCI7612, PCI8402, and PCI8412 SD host controller interface. All registers are detailed in the same format: a brief description for each register is followed by the register offset and a bit table describing the reset state for each register. A bit description table, typically included when the register contains bits of more than one type or purpose, indicates bit field names, a detailed field description, and field access tags which appear in the type column. Table 4-1 describes the field access tags. The controller is a multifunction PCI device. The SD host controller core is integrated as PCI function 3. The function 3 configuration header is compliant with the PCI Local Bus Specification as a standard header. Table 12-1 illustrates the configuration header that includes both the predefined portion of the configuration space and the user-definable registers. Table 12-1. Function 3 Configuration Register Map REGISTER NAME OFFSET Device ID Vendor ID 00h Status Command 04h Class code BIST Header type Latency timer Revision ID 08h Cache line size 0Ch Slot 0 base address 10h Slot 1 base address 14h Slot 2 base address 18h Reserved Subsystem ID 1Ch-28h Subsystem vendor ID Reserved 30h Reserved PCI power-management capabilities pointer 34h Interrupt line 3Ch Reserved Maximum latency Minimum grant 38h Interrupt pin Reserved Slot information Reserved Next item pointer PM data (Reserved) Power-management control and status Reserved 40h 44h-7Ch Power-management capabilities PMCSR_BSE 2Ch Capability ID General control Subsystem alias 80h 84h 88h 8Ch Diagnostic 90h Reserved Slot 0 3.3-V maximum current 94h Reserved Slot 1 3.3-V maximum current 98h Reserved Slot 2 3.3-V maximum current 9Ch Reserved A0h-FCh One or more bits in this register are cleared only by the assertion of GRST. September 2005 SCPS110 215 SD Host Controller Programming Model 12.1 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch. Function 3 register offset: 00h Register type: Read-only Default value: 104Ch BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 12.2 Device ID Register The device ID register contains a value assigned to the SD host controller by Texas Instruments. The device identification for the SD host controller is 803Ch. Function 3 register offset: 02h Register type: Read-only Default value: 803Ch BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 216 SCPS110 September 2005 SD Host Controller Programming Model 12.3 Command Register The command register provides control over the SD host controller interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 12-2 for a complete description of the register contents. Function 3 register offset: 04h Register type: Read/Write, Read-only Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12-2. Command Register Description BIT FIELD NAME TYPE DESCRIPTION 15-11 RSVD R 10 INT_DISABLE RW INTx disable. When set to 1b, this bit disables the function from asserting interrupts on the INTx signals. 0 = INTx assertion is enabled (default) 1 = INTx assertion is disabled 9 FBB_ENB R Fast back-to-back enable. The SD host controller does not generate fast back-to-back transactions; therefore, bit 9 returns 0b when read. 8 SERR_ENB RW SERR enable. When bit 8 is set to 1b, the SD host controller SERR driver is enabled. SERR can be asserted after detecting an address parity error on the PCI bus. 7 STEP_ENB R Address/data stepping control. The SD host controller does not support address/data stepping; therefore, bit 7 is hardwired to 0b. 6 PERR_ENB RW Parity error enable. When bit 6 is set to 1b, the SD host controller is enabled to drive PERR response to parity errors through the PERR signal. 5 VGA_ENB R VGA palette snoop enable. The SD host controller does not feature VGA palette snooping; therefore, bit 5 returns 0b when read. 4 MWI_ENB RW Memory write and invalidate enable. The SD host controller does not generate memory write invalidate transactions; therefore, bit 4 returns 0b when read. 3 SPECIAL R Special cycle enable. The SD host controller does not respond to special cycle transactions; therefore, bit 3 returns 0b when read. 2 MASTER_ENB RW Bus master enable. When bit 2 is set to 1b, the SD host controller is enabled to initiate cycles on the PCI bus. 1 MEMORY_ENB RW Memory response enable. Setting bit 1 to 1b enables the SD host controller to respond to memory cycles on the PCI bus. 0 IO_ENB R I/O space enable. The SD host controller does not implement any I/O-mapped functionality; therefore, bit 0 returns 0b when read. September 2005 Reserved. Bits 15-11 return 00000b when read. SCPS110 217 SD Host Controller Programming Model 12.4 Status Register The status register provides device information to the host system. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. Bits in this register may be read normally. A bit in the status register is reset when 1b is written to that bit location; a 0b written to a bit location has no effect. See Table 12-3 for a complete description of the register contents. Function 3 register offset: 06h Register type: Read/Clear/Update, Read-only Default value: 0210h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 Table 12-3. Status Register Description BIT FIELD NAME TYPE DESCRIPTION 15 PAR_ERR RCU Detected parity error. Bit 15 is set to 1b when either an address parity or data parity error is detected. 14 SYS_ERR RCU Signaled system error. Bit 14 is set to 1b when SERR is enabled and the SD host controller has signaled a system error to the host. 13 MABORT RCU Received master abort. Bit 13 is set to 1b when a cycle initiated by the SD host controller on the PCI bus has been terminated by a master abort. 12 TABORT_REC RCU Received target abort. Bit 12 is set to 1b when a cycle initiated by the SD host controller on the PCI bus was terminated by a target abort. 11 TABORT_SIG RCU Signaled target abort. Bit 11 is set to 1b by the SD host controller when it terminates a transaction on the PCI bus with a target abort. 10-9 PCI_SPEED R DEVSEL timing. Bits 10 and 9 encode the timing of DEVSEL and are hardwired to 01b, indicating that the SD host controller asserts this signal at a medium speed on nonconfiguration cycle accesses. 8 DATAPAR RCU Data parity error detected. Bit 8 is set to 1b when the following conditions have been met: a. PERR was asserted by any PCI device including the SD host controller. b. The SD host controller was the bus master during the data parity error. c. Bit 6 (PERR_EN) in the command register at offset 04h in the PCI configuration space (see Section 12.3) is set to 1b. 7 FBB_CAP R Fast back-to-back capable. The SD host controller cannot accept fast back-to-back transactions; therefore, bit 7 is hardwired to 0b. 6 UDF R User-definable features (UDF) supported. The SD host controller does not support the UDF; therefore, bit 6 is hardwired to 0b. 5 66MHZ R 66-MHz capable. The SD host controller operates at a maximum PCLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0b. 4 CAPLIST R Capabilities list. Bit 4 returns 1b when read, indicating that the SD host controller supports additional PCI capabilities. 3 INT_STATUS RU Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE) in the command register (offset 04h, see Section 12.3) is a 0b and this bit is 1b, is the function's INTx signal asserted. Setting the INT_DISABLE bit to 1b has no effect on the state of this bit. This bit is set only when a valid interrupt condition exists. This bit is not set when an interrupt condition exists and signaling of that event is not enabled. 2-0 RSVD R 218 SCPS110 Reserved. Bits 2-0 return 000b when read. September 2005 SD Host Controller Programming Model 12.5 Class Code and Revision ID Register The class code and revision ID register categorizes the base class, subclass, and programming interface of the function. The base class is 08h, identifying the controller as a generic system peripheral. The subclass is 05h, identifying the function as an SD host controller. The programming interface is 01h, indicating that the function is a standard SD host with DMA capabilities. Furthermore, the TI chip revision is indicated in the least significant byte (00h). See Table 12-4 for a complete description of the register contents. Function 3 register offset: 08h Register type: Read-only Default value: 0805 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12-4. Class Code and Revision ID Register Description BIT FIELD NAME TYPE DESCRIPTION 31-24 BASECLASS R Base class. This field returns 08h when read, which broadly classifies the function as a generic system peripheral. 23-16 SUBCLASS R Subclass. This field returns 05h when read, which specifically classifies the function as an SD host controller. 15-8 PGMIF R Programming interface. If bit 0 (DMA_EN) in the general control register (offset 88h, see Section 12.22) is 0b, then this field returns 00h when read to indicate that the function is a standard SD host without DMA capabilities. If the DMA_EN bit is 1b, then this field returns 01h when read to indicate that the function is a standard SD host with DMA capabilities. 7-0 CHIPREV R Silicon revision. This field returns the silicon revision of the SD host controller. 12.6 Latency Timer and Class Cache Line Size Register The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the SD host controller. See Table 12-5 for a complete description of the register contents. Function 3 register offset: 0Ch Register type: Read/Write Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12-5. Latency Timer and Class Cache Line Size Register Description BIT FIELD NAME TYPE DESCRIPTION 15-8 LATENCY_TIMER RW PCI latency timer. The value in this register specifies the latency timer for the SD host controller, in units of PCI clock cycles. When the SD host controller is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires before the SD host transaction has terminated, then the SD host controller terminates the transaction when its GNT is deasserted. 7-0 CACHELINE_SZ RW Cache line size. This value is used by the SD host controller during memory write and invalidate, memory-read line, and memory-read multiple transactions. September 2005 SCPS110 219 SD Host Controller Programming Model 12.7 Header Type and BIST Register The header type and built-in self-test (BIST) register indicates the SD host controller PCI header type and no built-in self-test. See Table 12-6 for a complete description of the register contents. Function 3 register offset: 0Eh Register type: Read-only Default value: 0080h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Table 12-6. Header Type and BIST Register Description BIT FIELD NAME TYPE DESCRIPTION 15-8 BIST R Built-in self-test. The SD host controller does not include a BIST; therefore, this field returns 00h when read. 7-0 HEADER_TYPE R PCI header type. The SD host controller includes the standard PCI header. Bit 7 indicates if the SD host is a multifunction device. 12.8 SD Host Base Address Register The SD host base address register specifies the base address of the memory-mapped interface registers for each standard SD host socket. The size of the base address register (BAR) is 256 bytes. See Table 12-7 for a complete description of the register contents. Function 3 register offset: 10h Register type: Read/Write, Read-only Default value: 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12-7. SD Host Base Address Register Description BIT FIELD NAME TYPE DESCRIPTION 31-8 BAR RW Base address. This field specifies the upper 24 bits of the 32-bit starting base address. The size of the base address is 256 bytes. 7-4 RSVD R Reserved. Bits 7-4 return 0h when read. 3 PREFETCHABLE R Prefetchable indicator. This bit is hardwired to 0b to indicate that the memory space is not prefetchable. 2-1 TYPE R This field is hardwired to 00b to indicate that the base address is located in 32-bit address space. 0 MEM_INDICATOR R Memory space indicator. Bit 0 is hardwired to 0b to indicate that the base address maps into memory space. 220 SCPS110 September 2005 SD Host Controller Programming Model 12.9 Subsystem Vendor Identification Register The subsystem identification register, used for system and option card identification purposes, may be required for certain operating systems. This read-only register is initialized through the EEPROM and can be written through the subsystem access register at PCI offset 8Ch (see Section 12.23). All bits in this register are reset by GRST only. Function 3 register offset: 2Ch Register type: Read/Update Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12.10 Subsystem Identification Register The subsystem identification register, used for system and option card identification purposes, may be required for certain operating systems. This read-only register is initialized through the EEPROM and can be written through the subsystem access register at PCI offset 8Ch (see Section 12.23). All bits in this register are reset by GRST only. Function 3 register offset: 2Eh Register type: Read/Update Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12.11 Capabilities Pointer Register The power-management capabilities pointer register provides a pointer into the PCI configuration header where the power-management register block resides. Since the PCI power-management registers begin at 80h, this read-only register is hardwired to 80h. Function 3 register offset: 34h Register type: Read-only Default value: 80h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 1 0 0 0 0 0 0 0 12.12 Interrupt Line Register The interrupt line register is programmed by the system and indicates to the software which interrupt line the SD host controller has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not yet been assigned to the function. Function 3 register offset: 3Ch Register type: Read/Write Default value: FFh BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 1 1 1 1 1 1 1 1 September 2005 SCPS110 221 SD Host Controller Programming Model 12.13 Interrupt Pin Register This register decodes the interrupt select inputs and returns the proper interrupt value based on Table 12-8, indicating that the SD host controller uses an interrupt. If one of the USE_INTx terminals is asserted, the interrupt select bits are ignored, and this register returns the interrupt value for the highest priority USE_INTx terminal that is asserted. If bit 28, the tie-all bit (TIEALL), in the system control register (PCI offset 80h, see Section 4.29) is set to 1b, then the controller asserts the USE_INTA input to the SD host controller core. If bit 28 (TIEALL) in the system control register (PCI offset 80h, see Section 4.29) is set to 0b, then none of the USE_INTx inputs are asserted and the interrupt for the SD host controller function is selected by the INT_SEL bits in the SD host general control register. Function 3 register offset: 3Dh Register type: Read-only Default value: 0Xh BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 X X X Table 12-8. PCI Interrupt Pin Register INT_SEL BITS USE_INTA INTPIN 00 0 01h (INTA) 01 0 02h (INTB) 10 0 03h (INTC) 11 0 04h (INTD) XX 1 01h (INTA) 12.14 Minimum Grant Register The minimum grant register contains the minimum grant value for the SD host controller core. Function 3 register offset: 3Eh Register type: Read/Update Default value: 07h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 1 1 1 Table 12-9. Minimum Grant Register Description BIT FIELD NAME TYPE DESCRIPTION 7-0 MIN_GNT RU Minimum grant. The contents of this field may be used by host BIOS to assign a latency timer register value to the SD host controller. The default for this register indicates that the SD host controller may need to sustain burst transfers for nearly 64 s and thus request a large value be programmed in bits 15-8 of the latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see Section 12.6). 222 SCPS110 September 2005 SD Host Controller Programming Model 12.15 Maximum Latency Register The maximum latency register contains the maximum latency value for the SD host controller core. Function 3 register offset: 3Fh Register type: Read/Update Default value: 04h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 1 0 0 Table 12-10. Maximum Latency Register Description BIT FIELD NAME TYPE DESCRIPTION 7-0 MAX_LAT RU Maximum latency. The contents of this field may be used by host BIOS to assign an arbitration priority level to the SD host controller. The default for this register indicates that the SD host controller may need to access the PCI bus as often as every 0.25 s; thus, an extremely high priority level is requested. The contents of this field may also be loaded through the serial EEPROM. 12.16 Slot Information Register This read-only register contains information on the number of SD sockets implemented and the base address registers used. The controller only implements one SD socket. Function 3 register offset: 40h Register type: Read/Update Default value: 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 12-11. Maximum Latency Register Description BIT FIELD NAME TYPE 7 RSVD R Reserved. This bit returns 0b when read. DESCRIPTION 6-4 NUMBER_SLOTS R Number of slots. This field indicates the number of SD sockets supported by the SD host controller. Since the controller supports one SD socket, this field returns 000b when read. 3 RSVD R Reserved. This bit returns 0b when read. 2-0 FIRST_BAR R First base address register number. This field is hardwired to 000b to indicate that the first BAR used for the SD host standard registers is BAR0. 12.17 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the next capability item. See Table 12-12 for a complete description of the register contents. Function 3 register offset: 80h Register type: Read-only Default value: 0001h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Table 12-12. Capability ID and Next Item Pointer Registers Description BIT FIELD NAME TYPE DESCRIPTION 15-8 NEXT_ITEM R Next item pointer. The SD host controller supports only one additional capability, PCI power management, that is communicated to the system through the extended capabilities list; therefore, this field returns 00h when read. 7-0 CAPABILITY_ID R Capability identification. This field returns 01h when read, which is the unique ID assigned by the PCI SIG for PCI power-management capability. September 2005 SCPS110 223 SD Host Controller Programming Model 12.18 Power-Management Capabilities Register The power-management capabilities register indicates the capabilities of the SD host controller related to PCI power management. See Table 12-13 for a complete description of the register contents. Function 3 register offset: 82h Register type: Read/Update, Read-only Default value: 7E02h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 Table 12-13. Power-Management Capabilities Register Description BIT FIELD NAME TYPE DESCRIPTION 15 PME_D3COLD RU PME support from D3cold. This bit can be set to 1b or cleared to 0b via bit 4 (D3_COLD) in the general control register at offset 88h in the PCI configuration space (see Section 12.22). When this bit is set to 1b, it indicates that the SD host controller is capable of generating a PME wake event from D3cold. This bit state is dependent upon the SD host controller VAUX implementation and may be configured by using bit 4 (D3_COLD) in the general control register (see Section 12.22). 14-11 PME_SUPPORT R PME support. This 4-bit field indicates the power states from which the SD host controller may assert PME. This field returns a value of 1111b by default, indicating that PME may be asserted from the D3hot, D2, D1, and D0 power states. 10 D2_SUPPORT R D2 support. Bit 10 is hardwired to 1b, indicating that the SD host controller supports the D2 power state. 9 D1_SUPPORT R D1 support. Bit 9 is hardwired to 1b, indicating that the SD host controller supports the D1 power state. 8-6 AUX_CURRENT R Auxiliary current. This 3-bit field reports the 3.3-VAUX auxiliary current requirements. When bit 15 (PME_D3COLD) is cleared, this field returns 000b; otherwise, it returns 001b. 000b = Self-powered 001b = 55 mA (3.3-VAUX maximum current required) 5 DSI R Device-specific initialization. This bit returns 0b when read, indicating that the SD host controller does not require special initialization beyond the standard PCI configuration header before a generic class driver is able to use it. 4 RSVD R Reserved. Bit 4 returns 0b when read. 3 PME_CLK R PME clock. This bit returns 0b when read, indicating that the PCI clock is not required for the SD host controller to generate PME. 2-0 PM_VERSION R Power-management version. If bit 7 (PCI_PM_VERSION_CTRL) in the general control register (offset 88h, see Section 12.22) is 0b, this field returns 010b indicating PCI Bus Power Management Interface Specification (Revision 1.1) compatibility. If the PCI_PM_VERSION_CTRL bit is 1b, this field returns 011b indicating PCI Bus Power Management Interface Specification (Revision 1.2) compatibility. 224 SCPS110 September 2005 SD Host Controller Programming Model 12.19 Power-Management Control and Status Register The power-management control and status register implements the control and status of the SD host controller. This register is not affected by the internally-generated reset caused by the transition from the D3hot to D0 state. See Table 12-14 for a complete description of the register contents. Function 3 register offset: 84h Register type: Read/Clear, Read/Write, Read-only Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12-14. Power-Management Control and Status Register Description BIT FIELD NAME TYPE DESCRIPTION 15 PME_STAT RCU 14-13 DATA_SCALE R Data scale. This field returns 00b when read, because the SD host controller does not use the data register. 12-9 DATA_SELECT R Data select. This field returns 0h when read, because the SD host controller does not use the data register. 8 PME_EN RW 7-2 RSVD R 1-0 PWR_STATE RW PME status. This bit defaults to 0b. PME enable. Enables PME signaling. Reserved. Bits 7-2 return 000000b when read. Power state. This 2-bit field determines the current power state and sets the SD host controller to a new power state. This field is encoded as follows: 00 = Current power state is D0 01 = Current power state is D1 10 = Current power state is D2 11 = Current power state is D3hot One or more bits in this register are cleared only by the assertion of GRST. 12.20 Power-Management Bridge Support Extension Register The power-management bridge support extension register provides extended power-management features not applicable to the SD host controller; thus, it is read-only and returns 00h when read. Function 3 register offset: 86h Register type: Read-only Default value: 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 12.21 Power-Management Data Register The power-management bridge support extension register provides extended power-management features not applicable to the SD host controller; thus, it is read-only and returns 00h when read. Function 3 register offset: 87h Register type: Read-only Default value: 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 September 2005 SCPS110 225 SD Host Controller Programming Model 12.22 General Control Register The general control register provides miscellaneous PCI-related configuration. See Table 12-15 for a complete description of the register contents. Function 3 register offset: 88h Register type: Read/Write, Read-only Default value: 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 12-15. General Control Register BIT FIELD NAME TYPE DESCRIPTION 7 PCI_PM_ VERSION_CTRL RW PCI power-management version control. This bit controls the value reported in bits 2-0 (PM_VERSION) of the power-management capabilities register (offset 82h, see Section 12.18). 0 = PM_VERSION field reports 010b for PCI Bus Power Management Interface Specification (Revision 1.1) compatability. 1 = PM_VERSION field reports 011b for PCI Bus Power Management Interface Specification (Revision 1.2) compatability. 6-5 INT_SEL RW Interrupt select. These bits are program the INTPIN register and set which interrupt output is used. This field is ignored if one of the USE_INTx terminals is asserted. 00 = 01 = 10 = 11 = INTA INTB INTC INTD 4 D3_COLD RW D3cold PME support. This bit sets and clears bit 15 (PME_D3COLD) in the power-management capabilities register (offset 82h, see Section 12.18). 3 CORE_RST_CTRL RW Core reset control. This bit controls the reset for the SD host controller core. This bit does not affect the reset of the PCI portion of the SD host core. 0 = The SD host controller core is reset by either GRST or PRST (default). 1 = The SD host controller core is only reset by GRST. 2 RSVD R 1 HS_EN RW Reserved. Bit 2 returns 0b when read. High speed enable. This bit enables the high-speed SD functionality of the SD host controller core. When this bit is set, the HIGH_SPEED_SUPPORT bit in the capabilities register of each SD host socket is set. When this bit is 0, the HIGH_SPEED_SUPPORT bit of each SD host socket is 0. 0 DMA_EN RW DMA enable. This bit enables DMA functionality of the SD host controller core. When this bit is set, the PGMIF field in the class code register (offset 08h, see Section 12.5) returns 01h and the DMA_SUPPORT bit in the capabilities register of each SD host socket is set. When this bit is 0b, the PGMIF field returns 00h and the DMA_SUPPORT bit of each SD host socket is 0b. One or more bits in this register are cleared only by the assertion of GRST. 12.23 Subsystem Access Register The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at PCI offsets 2Ch and 2Eh, respectively. See Table 12-16 for a complete description of the register contents. All bits in this register are reset by GRST only. Function 3 register offset: 8Ch Register type: Read/Write Default value: 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 226 SCPS110 September 2005 SD Host Controller Programming Model Table 12-16. Subsystem Access Register Description BIT FIELD NAME TYPE DESCRIPTION 31-16 SubsystemID RW Subsystem device ID. The value written to this field is aliased to the subsystem ID register at PCI offset 2Eh. 15-0 SubsystemVendorID RW Subsystem vendor ID. The value written to this field is aliased to the subsystem vendor ID register at PCI offset 2Ch. 12.24 Diagnostic Register This register enables the diagnostic modes. See Table 12-17 for a complete description of the register contents. All bits in this register are reset by GRST only. Function 3 register offset: 90h Register type: Read-only, Read/Write Default value: 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12-17. Diagnostic Register Description BIT SIGNAL TYPE 31-17 RSVD R 16 DIAGNOSTIC RW 15-0 RSVD R FUNCTION Reserved. Bits 31-17 return 000 0000 0000 0000b when read. Diagnostic test bit. This test bit shortens the card detect debounce times for simulation and TDL. Reserved. Bits 15-0 return 0000h when read. 12.25 Slot 0 3.3-V Maximum Current Register This register is a read/write register and the contents of this register are aliased to the 3_3_MAX_CURRENT field in the slot 0 maximum current capabilities register at offset 48h in the SD host standard registers. This register is a GRST only register. Function 3 register offset: 94h Register type: Read/Write Default value: 0000h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 September 2005 SCPS110 227 Smart Card Controller Programming Model 13 Smart Card Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI6612 and PCI7612 Smart Card controller interfaces. All registers are detailed in the same format: a brief description for each register is followed by the register offset and a bit table describing the reset state for each register. A bit description table, typically included when the register contains bits of more than one type or purpose, indicates bit field names, a detailed field description, and field access tags which appear in the type column. Table 4-1 describes the field access tags. The controller is a multifunction PCI device. The Smart Card controller core is integrated as PCI function 4. The function 4 configuration header is compliant with the PCI Local Bus Specification as a standard header. Table 13-1 illustrates the configuration header that includes both the predefined portion of the configuration space and the user-definable registers. Table 13-1. Function 4 Configuration Register Map REGISTER NAME OFFSET Device ID Vendor ID 00h Status Command 04h Class code BIST Header type Latency timer Revision ID 08h Cache line size 0Ch SC global control base address 10h SC socket 0 base address 14h SC socket 1 base address 18h Reserved 1Ch-28h Subsystem ID Subsystem vendor ID Reserved 30h Reserved PCI power-management capabilities pointer 34h Interrupt line 3Ch Reserved Maximum latency Minimum grant 38h Interrupt pin Reserved 40h Power-management capabilities Next item pointer PM data (Reserved) Power-management control and status 48h General control 4Ch PMCSR_BSE Reserved Capability ID SCPS110 44h Subsystem alias 50h Class code alias 54h Smart Card configuration 1 58h Smart Card configuration 2 5Ch Reserved One or more bits in this register are cleared only by the assertion of GRST. 228 2Ch 60h-FCh September 2005 Smart Card Controller Programming Model 13.1 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch. Function 4 register offset: 00h Register type: Read-only Default value: 104Ch BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 13.2 Device ID Register The device ID register contains a value assigned to the Smart Card controller by Texas Instruments. The device identification for the Smart Card controller is 803Dh. Function 4 register offset: 02h Register type: Read-only Default value: 803Dh BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 September 2005 SCPS110 229 Smart Card Controller Programming Model 13.3 Command Register The command register provides control over the Smart Card controller interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. The SERR_EN and PERR_EN enable bits in this register are internally wired-OR between other functions, and these control bits appear separately according to their software function. See Table 13-2 for a complete description of the register contents. Function 4 register offset: 04h Register type: Read/Write, Read-only Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 13-2. Command Register Description BIT FIELD NAME TYPE DESCRIPTION 15-11 RSVD R 10 INT_DIS RW INTx disable. When set to 1b, this bit disables the function from asserting interrupts on the INTx signals. 0 = INTx assertion is enabled (default) 1 = INTx assertion is disabled 9 FBB_EN R Fast back-to-back enable. The Smart Card interface does not generate fast back-to-back transactions; therefore, bit 9 returns 0b when read. 8 SERR_EN RW System error (SERR) enable. Bit 8 controls the enable for the SERR driver on the PCI interface. SERR can be asserted after detecting an address parity error on the PCI bus. Both bits 8 and 6 (PERR_EN) must be set for this function to report address parity errors. 0 = Disable SERR output driver (default) 1 = Enable SERR output driver 230 Reserved. Bits 15-11 return 00000b when read. 7 RSVD R 6 PERR_EN RW Parity error response enable. Bit 6 controls this function response to parity errors through PERR. Data parity errors are indicated by asserting PERR, whereas address parity errors are indicated by asserting SERR. 0 = This function ignores detected parity error (default) 1 = This function responds to detected parity errors 5 VGA_EN R VGA palette snoop enable. The Smart Card interface does not feature VGA palette snooping; therefore, bit 5 returns 0b when read. 4 MWI_EN R Memory write and invalidate enable. The Smart Card controller does not generate memory write invalidate transactions; therefore, bit 4 returns 0b when read. 3 SPECIAL R Special cycle enable. The Smart Card interface does not respond to special cycle transactions; therefore, bit 3 returns 0b when read. 2 MAST_EN R Bus master enable. This function is target only. 1 MEM_EN RW 0 IO_EN R SCPS110 Reserved. Bit 7 returns 0b when read. Memory space enable. This bit controls memory access. 0 = Disables this function from responding to memory space accesses (default) 1 = Enables this function to respond to memory space accesses I/O space enable. The Smart Card interface does not implement any I/O-mapped functionality; therefore, bit 0 returns 0b when read. September 2005 Smart Card Controller Programming Model 13.4 Status Register The status register provides device information to the host system. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. Bits in this register may be read normally. A bit in the status register is reset when 1b is written to that bit location; a 0b written to a bit location has no effect. See Table 13-3 for a complete description of the register contents. Function 4 register offset: 06h Register type: Read/Clear/Update, Read-only Default value: 0210h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 Table 13-3. Status Register Description BIT FIELD NAME TYPE DESCRIPTION 15 PAR_ERR RCU Detected parity error. Bit 15 is set to 1b when either an address parity or data parity error is detected. 14 SYS_ERR RCU Signaled system error. Bit 14 is set to 1b when SERR is enabled and the Smart Card controller has signaled a system error to the host. 13 MABORT R This function does not support bus mastering. This bit is hardwired to 0b. 12 TABT_REC R This function does not support bus mastering and never receives a target abort. This bit is hardwired to 0b. 11 TABT_SIG RCU Signaled target abort. Bit 11 is set to 1b by the Smart Card controller when it terminates a transaction on the PCI bus with a target abort. 10-9 PCI_SPEED R DEVSEL timing. Bits 10 and 9 encode the timing of DEVSEL and are hardwired to 01b, indicating that the Smart Card controller asserts this signal at a medium speed on nonconfiguration cycle accesses. 8 DATAPAR R This function does not support bus mastering. This bit is hardwired to 0b. 7 FBB_CAP R Fast back-to-back capable. The Smart Card controller cannot accept fast back-to-back transactions; therefore, bit 7 is hardwired to 0b. 6 RSVD R Reserved. Bit 6 returns 0b when read. 5 66MHZ R 66-MHz capable. The Smart Card controller operates at a maximum PCLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0b. 4 CAPLIST R Capabilities list. Bit 4 returns 1b when read, indicating that the Smart Card controller supports additional PCI capabilities. The linked list of PCI power-management capabilities is implemented in this function. 3 INT_STAT RU Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE) in the command register (see Section 11.3) is 0b and this bit is 1b, is the function's INTx signal asserted. Setting the INT_DISABLE bit to 1b has no effect on the state of this bit. This bit is set only when a valid interrupt condition exists. This bit is not set when an interrupt condition exists and signaling of that event is not enabled. 2-0 RSVD R September 2005 Reserved. Bits 2-0 return 000b when read. SCPS110 231 Smart Card Controller Programming Model 13.5 Class Code and Revision ID Register The class code and revision ID register categorizes the base class, subclass, and programming interface of the function. The base class is 07h, identifying the controller as a communication device. The subclass is 80h, identifying the function as other mass storage controller, and the programming interface is 00h. Furthermore, the TI chip revision is indicated in the least significant byte (00h). See Table 13-4 for a complete description of the register contents. Function 4 register offset: 08h Register type: Read-only Default value: 0780 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 13-4. Class Code and Revision ID Register Description BIT FIELD NAME TYPE DESCRIPTION 31-24 BASECLASS R Base class. This field returns 07h when read, which classifies the function as a communication device. 23-16 SUBCLASS R Subclass. This field returns 80h when read, which specifically classifies the function as other mass storage controller. 15-8 PGMIF R Programming interface. This field returns 00h when read. 7-0 CHIPREV R Silicon revision. This field returns 00h when read, which indicates the silicon revision of the Smart Card controller. 13.6 Latency Timer and Class Cache Line Size Register The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the Smart Card controller. See Table 13-5 for a complete description of the register contents. Function 4 register offset: 0Ch Register type: Read/Write Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 13-5. Latency Timer and Class Cache Line Size Register Description BIT FIELD NAME TYPE DESCRIPTION 15-8 LATENCY_TIMER RW PCI latency timer. The value in this register specifies the latency timer for the Smart Card controller, in units of PCI clock cycles. When the Smart Card controller is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires before the Smart Card transaction has terminated, then the Smart Card controller terminates the transaction when its GNT is deasserted. 7-0 CACHELINE_SZ RW Cache line size. This value is used by the Smart Card controller during memory write and invalidate, memory-read line, and memory-read multiple transactions. 232 SCPS110 September 2005 Smart Card Controller Programming Model 13.7 Header Type and BIST Register The header type and built-in self-test (BIST) register indicates the Smart Card controller PCI header type and no built-in self-test. See Table 13-6 for a complete description of the register contents. Function 4 register offset: 0Eh Register type: Read-only Default value: 0080h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Table 13-6. Header Type and BIST Register Description BIT FIELD NAME TYPE DESCRIPTION 15-8 BIST R Built-in self-test. The Smart Card controller does not include a BIST; therefore, this field returns 00h when read. 7-0 HEADER_TYPE R PCI header type. The Smart Card controller includes the standard PCI header. Bit 7 indicates if the Smart Card is a multifunction device. 13.8 Smart Card Base Address Register 0 This register is used by this function to determine where to forward a memory transaction to the Smart Card global control register set. Bits 31-12 of this register are read/write and allow the base address to be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundary. The window size is always 4K bytes. Bits 11-0 are read-only and always return 000h. Write transactions to these bits have no effect. Bit 3 (0b) specifies that this window is nonprefetchable. Bits 2-1 (00b) specify that this memory window can allocate anywhere in the 32-bit address space. Function 4 register offset: 10h Register type: Read/Write, Read-only Default value: 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 September 2005 SCPS110 233 Smart Card Controller Programming Model 13.9 Smart Card Base Address Register 1 Each socket has its own base address register. For example, a device supports three Smart Card sockets uses three base address registers, BA1 (socket 0), BA2 (socket 1) and BA3 (socket 2). The PCIxx12 controller supports one Smart Card socket. This register is used by this function to determine where to forward a memory transaction to the Smart Card control and communication register sets. Bits 31-12 of this register are read/write and allow the base address to be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries and the window size is always 4K bytes. Bits 11-4 are read-only and always return 00h. Write transactions to these bits have no effect. Bit 3 (0b) specifies that these windows are nonprefetchable. Bits 2-1 (00b) specify that this memory window can allocate anywhere in the 32-bit address space. Function 4 register offset: 14h Register type: Read/Write, Read-only Default value: 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13.10 Subsystem Vendor Identification Register This register is read-update and can be modified through the subsystem vendor ID alias register. Default value is 104Ch. This default value complies with the WLP (Windows Logo Program) requirements without BIOS or EEPROM configuration. All bits in this register are reset by GRST only. Function 4 register offset: 2Ch Register type: Read/Update Default value: 104Ch BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 13.11 Subsystem Identification Register This register is read-update and can be modified through the subsystem ID alias register. This register has no effect to the functionality. Default value is 8035h. This default value complies with the WLP (Windows Logo Program) requirements without BIOS or EEPROM configuration. All bits in this register are reset by GRST only. Function 4 register offset: 2Eh Register type: Read/Update Default value: 8035h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 1 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 13.12 Capabilities Pointer Register The power-management capabilities pointer register provides a pointer into the PCI configuration header where the power-management register block resides. Since the PCI power-management registers begin at 44h, this read-only register is hardwired to 44h. Function 4 register offset: 34h Register type: Read-only Default value: 44h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 1 0 0 0 1 0 0 234 SCPS110 September 2005 Smart Card Controller Programming Model 13.13 Interrupt Line Register The interrupt line register is programmed by the system and indicates to the software which interrupt line the Smart Card interface has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not yet been assigned to the function. Function 4 register offset: 3Ch Register type: Read/Write Default value: FFh BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 1 1 1 1 1 1 1 1 13.14 Interrupt Pin Register This register decodes the interrupt select inputs and returns the proper interrupt value based on Table 13-7, indicating that the Smart Card interface uses an interrupt. If one of the USE_INTx terminals is asserted, the interrupt select bits are ignored, and this register returns the interrupt value for the highest priority USE_INTx terminal that is asserted. If bit 28, the tie-all bit (TIEALL), in the system control register (PCI offset 80h, see Section 4.29) is set to 1b, then the controller asserts the USE_INTA input to the Smart Card controller core. If bit 28 (TIEALL) in the system control register (PCI offset 80h, see Section 4.29) is set to 0b, then none of the USE_INTx inputs are asserted and the interrupt for the Smart Card function is selected by the INT_SEL bits in the Smart Card general control register. Function 4 register offset: 3Dh Register type: Read-only Default value: 0Xh BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 X X X Table 13-7. PCI Interrupt Pin Register INT_SEL BITS USE_INTA INTPIN 00 0 01h (INTA) 01 0 02h (INTB) 10 0 03h (INTC) 11 0 04h (INTD) XX 1 01h (INTA) 13.15 Minimum Grant Register The minimum grant register contains the minimum grant value for the Smart Card controller core. Function 4 register offset: 3Eh Register type: Read/Update Default value: 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 13-8. Minimum Grant Register Description BIT FIELD NAME TYPE DESCRIPTION 7-0 MIN_GNT RU Minimum grant. The contents of this field may be used by host BIOS to assign a latency timer register value to the Smart Card controller. The default for this register indicates that the Smart Card controller may need to sustain burst transfers for nearly 64 s and thus request a large value be programmed in bits 15-8 of the latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see Section 13.6). September 2005 SCPS110 235 Smart Card Controller Programming Model 13.16 Maximum Latency Register The maximum latency register contains the maximum latency value for the Smart Card controller core. Function 4 register offset: 3Fh Register type: Read/Update Default value: 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 13-9. Maximum Latency Register Description BIT FIELD NAME TYPE DESCRIPTION 7-0 MAX_LAT RU Maximum latency. The contents of this field may be used by host BIOS to assign an arbitration priority level to the Smart Card controller. The default for this register indicates that the Smart Card controller may need to access the PCI bus as often as every 0.25 s; thus, an extremely high priority level is requested. The contents of this field may also be loaded through the serial EEPROM. 13.17 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the next capability item. See Table 13-10 for a complete description of the register contents. Function 4 register offset: 44h Register type: Read-only Default value: 0001h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Table 13-10. Capability ID and Next Item Pointer Registers Description BIT FIELD NAME TYPE DESCRIPTION 15-8 NEXT_ITEM R Next item pointer. The Smart Card controller supports only one additional capability, PCI power management, that is communicated to the system through the extended capabilities list; therefore, this field returns 00h when read. 7-0 CAPABILITY_ID R Capability identification. This field returns 01h when read, which is the unique ID assigned by the PCI SIG for PCI power-management capability. 236 SCPS110 September 2005 Smart Card Controller Programming Model 13.18 Power-Management Capabilities Register The power-management capabilities register indicates the capabilities of the Smart Card controller related to PCI power management. See Table 13-11 for a complete description of the register contents. Function 4 register offset: 46h Register type: Read/Update, Read-only Default value: 7E02h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 Table 13-11. Power-Management Capabilities Register Description BIT FIELD NAME TYPE DESCRIPTION PME support from D3cold. This bit can be set to 1b or cleared to 0b via bit 4 (D3_COLD) in the general control register at offset 4Ch in the PCI configuration space (see Section 13.22). When this bit is set to 1b, it indicates that the controller is capable of generating a PME wake event from D3cold. This bit state is dependent upon the VAUX implementation and may be configured by using bit 4 (D3_COLD) in the general control register (see Section 13.22). 15 PME_D3COLD RU 14 PME_D3HOT R 13 PME_D2 R 12 PME_D1 R 11 PME_D0 R 10 D2_SUPPORT R D2 support. Bit 10 is hardwired to 1b, indicating that the Smart Card controller supports the D2 power state. 9 D1_SUPPORT R D1 support. Bit 9 is hardwired to 1b, indicating that the Smart Card controller supports the D1 power state. PME support. This 4-bit field indicates the power states from which the Smart Card interface may assert PME. This field returns a value of 1111b by default, indicating that PME may be asserted from the D3hot, D2, D1, and D0 power states. Auxiliary current. This 3-bit field reports the 3.3-VAUX auxiliary current requirements. When bit 15 (PME_D3COLD) is cleared, this field returns 000b; otherwise, it returns 001b. 8-6 AUX_CURRENT R 5 DSI R Device-specific initialization. This function requires device-specific initialization. 4 RSVD R Reserved. Bit 4 returns 0b when read. 3 PME_CLK R PME clock. This bit returns 0b when read, indicating that the PCI clock is not required for the Smart Card controller to generate PME. R Power-management version. If bit 7 (PCI_PM_VERSION_CTRL) in the general control register (offset 4Ch, see Section 13.22) is 0b, this field returns 010b indicating PCI Bus Power Management Interface Specification (Revision 1.1) compatibility. If the PCI_PM_VERSION_CTRL bit is 1b, this field returns 011b indicating PCI Bus Power Management Interface Specification (Revision 1.2) compatibility. 2-0 PM_VERSION September 2005 000b = Self-powered 001b = 55 mA (3.3-VAUX maximum current required) SCPS110 237 Smart Card Controller Programming Model 13.19 Power-Management Control and Status Register The power-management control and status register implements the control and status of the Smart Card controller. This register is not affected by the internally-generated reset caused by the transition from the D3hot to D0 state. See Table 13-12 for a complete description of the register contents. Function 4 register offset: 48h Register type: Read/Clear/Update, Read/Write, Read-only Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 13-12. Power-Management Control and Status Register Description BIT FIELD NAME TYPE DESCRIPTION 15 PME_STAT RCU PME status. This bit is set when the function would normally assert the PME signal independent of the state of PME_EN bit. Writing a 1b to this bit clears it and causes the function to stop asserting a PME (if enabled). Writing a 0b has no effect. This bit is initialized by GRST only when the PME_D3cold bit is 1b. 14-9 RSVD R 8 PME_EN RW 7-2 RSVD R 1-0 DSTATE RW Reserved. Bits 14-9 return 00 0000b when read. PME enable. This bit is initialized by GRST only when PME_D3cold bit is 1b. Reserved. Bits 7-2 return 00 0000b when read. Device state: This bit field controls device power-management state. Invalid state assignments are ignored. (ex. Current state 10b writing 01b. This is rejected and stays 10b. See the latest PCI Local Bus Specification.) This bit field is initialized by GRST only when PME_D3cold bit is 1b. One or more bits in this register are cleared only by the assertion of GRST. 13.20 Power-Management Bridge Support Extension Register The power-management bridge support extension register provides extended power-management features not applicable to the Smart Card controller; thus, it is read-only and returns 00h when read. Function 4 register offset: 4Ah Register type: Read-only Default value: 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 13.21 Power-Management Data Register The power-management bridge support extension register provides extended power-management features not applicable to the Smart Card controller; thus, it is read-only and returns 0 when read. Function 4 register offset: 4Bh Register type: Read-only Default value: 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 238 SCPS110 September 2005 Smart Card Controller Programming Model 13.22 General Control Register This register controls this function. Information of this register can be read from the socket configuration register in the Smart Card socket control register set. See Table 13-13 for a complete description of the register contents. Function 4 register offset: 4Ch Register type: Read/Write (EEPROM, GRST only) Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 13-13. General Control Register BIT FIELD NAME TYPE 15-8 RSVD R DESCRIPTION 7 PCI_PM_ VERSION_CTRL RW PCI power-management version control. This bit controls the value reported in bits 2-0 (PM_VERSION) of the power-management capabilities register (offset 46h, see Section 13.18). 0 = PM_VERSION field reports 010b for PCI Bus Power Management Interface Specification (Revision 1.1) compatability 1 = PM_VERSION field reports 011b for PCI Bus Power Management Interface Specification (Revision 1.2) compatability 6-5 INT_SEL RW Interrupt select. These bits are program the INTPIN register and set which interrupt output is used. This field is ignored if one of the USE_INTx terminals is asserted. Reserved. Bits 15-8 return 00h when read. 00 = 01 = 10 = 11 = 4 D3_COLD RW 3-0 RSVD R INTA (pin = 1) INTB (pin = 2) INTC (pin = 3) INTD (pin = 4) Disable function. Setting this bit to 1b hides this function. PCI configuration register of this function must be accessible at any time. Clock (PCI and 48 MHz) to the rest of the function blocks must be gated to reduce power consumption. Reserved. Bits 3-0 return 0h when read. One or more bits in this register are cleared only by the assertion of GRST. 13.23 Subsystem ID Alias Register The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at PCI offsets 2Ch and 2Eh, respectively. See Table 13-14 for a complete description of the register contents. All bits in this register are reset by GRST only. Function 4 register offset: 50h Register type: Read/Write (EEPROM, GRST only) Default value: 8035 104Ch BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 1 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 Table 13-14. Subsystem ID Alias Register Description BIT FIELD NAME TYPE 31-16 SubsystemID RW Subsystem device ID. The value written to this field is aliased to the subsystem ID register at PCI offset 2Eh. 15-0 SubsystemVendorID RW Subsystem vendor ID. The value written to this field is aliased to the subsystem vendor ID register at PCI offset 2Ch. September 2005 DESCRIPTION SCPS110 239 Smart Card Controller Programming Model 13.24 Class Code Alias Register This register is alias of the class code. Not like original register, this register is read/write and loadable from EEPROM. Function 4 register offset: 54h Register type: Read-only, Read/Write (EEPROM, GRST only) Default value: 0780 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13.25 Smart Card Configuration 1 Register BIOS or EEPROM configure system dependent Smart Card interface information through this register. Information of this register can be read from the Smart Card configuration 1 alias register in the Smart Card global control register set. The software utilizes this information and adjusts the software and firmware behavior if necessary. Corresponding bits are tied to 0b if the socket is not implemented. Class A and B support are depend on the system and integrated device. Supporting both classes requires method (pins) to control 5.0 V and 3.0 V. See Table 13-15 for a complete description of the register contents. All bits in this register are reset by GRST only. Function 4 register offset: 58h Register type: Read/Write, Read-only (EEPROM, GRST only) Default value: 0110 1101h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 240 SCPS110 September 2005 Smart Card Controller Programming Model Table 13-15. Smart Card Configuration 1 Register Description BIT FIELD NAME TYPE 31-28 SCRTCH_PAD RW 27-25 RSVD R 24 CLASS_B_SKT0 RW DESCRIPTION Scratch pad Reserved. These bits return 000b when read. 23-21 RSVD R 20 CLASS_A_SKT0 RW 19-17 RSVD R 16 EMVIF_EN_SKT0 RW Socket 0 Class B Smart Card support. When this bit is set to 1b, socket 0 supports Class B Smart Cards. Reserved. These bits return 000b when read. Socket 0 Class A Smart Card support. When this bit is set to 1b, socket 0 supports Class A Smart Cards. Reserved. These bits return 000b when read. 15-13 RSVD R 12 GPIO_EN_SKT0 RW Socket 0 EMV interface enable. When this bit is set to 1b, the internal EVM interface for socket 0 is enabled. Reserved. These bits return 000b when read. Socket 0 GPIO enable. When this bit is set to 1b, the SC_GPIOs for socket 0 are enabled. 11-9 RSVD R 8 PCMCIA_MODE_SKT0 R/W Reserved. These bits return 000b when read. 7-5 RSVD R 4 PME_SUPPORT_SKT0 RW Socket 0 PCMCIA mode. If the SC_SOCKET_SEL bit is 0, this bit must be programmed to 0. If the SC_SOCKET_SEL bit is 1, this bit must be programmed to 1. Reserved. These bits return 000b when read. 3-1 RSVD R 0 SKT0_EN RW Socket 0 PME support. When this bit is set to 1b, socket 0 card insertions cause a PME event. Reserved. These bits return 000b when read. Socket 0 enable. When this bit is set to 1b, socket 0 is enabled. 13.26 Smart Card Configuration 2 Register BIOS or EEPROM configure system dependent Smart Card interface information through this register. Information of this register can be read from the Smart Card configuration 2 alias in the Smart Card global control register set. The software utilizes this information and adjusts the software and firmware behavior, if necessary. See Table 13-16 for a complete description of the register contents. All bits in this register are reset by GRST only. Function 4 register offset: 54h Register type: Read-only, Read/Write (EEPROM, GRST only) Default value: 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 13-16. Smart Card Configuration 2 Register Description BIT SIGNAL TYPE 31-16 RSVD R Reserved. Bits 31-16 return 0000h when read. 15-8 PWRUP_DELAY_ PCMCIA R Power up delay for the PCMCIA socket. This register indicates how long the external power switch takes to apply stable power to the PCMCIA socket in ms. Software must wait before starting operation after power up. This field has no effect for the hardware. 7-0 RSVD R Reserved. Bits 7-0 return 00h when read. September 2005 FUNCTION SCPS110 241 Electrical Characteristics 14 Electrical Characteristics 14.1 Absolute Maximum Ratings Over Operating Temperature Ranges Supply voltage range, VR_PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2 V to 2.2 V AVDD_33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V VDDPLL_15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 1.836 V VDDPLL_33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V VCCCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V SC_VCC_5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Clamping voltage range, VCCP and VCCCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6 V Input voltage range, VI: PCI, CardBus, PHY, SC, miscellaneous . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Output voltage range, VO: PCI, CardBus, PHY, SC, miscellaneous . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Human Body Model (HBM) ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V Operating free-air temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 3. Applies for external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals. PCI terminals and miscellaneous terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to CardBus VCC. The limit specified applies for a dc condition. 4. Applies for external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals. PCI terminals and miscellaneous terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to CardBus VCC. The limit specified applies for a dc condition. 14.2 Recommended Operating Conditions (see Note 5) OPERATION MIN NOM MAX UNIT 1.5 V 1.35 1.5 1.65 V AVDD_33 3.3 V 3 3.3 3.6 V VCC 3.3 V 3 3.3 3.6 V VDDPLL_15 1.5 V 1.35 1.5 1.65 V VDDPLL_33 3.3 V 3 3.3 3.6 V VR_PORT (see Table 2-6 for description) 3.3 V VCCP PCI and miscellaneous I/O clamp voltage VCCCB PC Card I/O clamp voltage 5V 3.3 V SC_VCC_5V 3 3.3 3.6 4.75 5 5.25 3 3.3 3.6 5V 4.75 5 5.25 5V 4.75 5 5.25 V V V NOTE 5: Unused terminals (input or I/O) must be held high or low to prevent them from floating. 242 SCPS110 September 2005 Electrical Characteristics Recommended Operating Conditions (continued) OPERATION 3.3 V PCIk 5V 3.3 V CardBus VIH High-level input voltage PC Card 3.3 V 16-bit 5 V 16-bit Miscellaneous VI VO tt IO Input voltage Output voltage Input transition time (tr and tf) 2 0.475 VCCCB 2 2.4 0.6 SC_VCC_5V MAX VCCCB VCCCB SC_VCC_5V 0 5V 0 0.8 3.3 V CardBus 0 0.325 VCCCB 3.3 V 16-bit 0 0.8 5 V 16-bit 0 0.8 Miscellaneous 0 0.8 SC_DATA, SC_FCB, SC_RFU PCIk 0 0.5 0 PC Card 0 Miscellaneous 0 VCCP VCCCB VCC SC_DATA, SC_FCB, SC_RFU PCIk 0 SC_VCC_5V 0 PC Card 0 VCC VCC Miscellaneous 0 SC_CLK, SC_DATA, SC_FCB, SC_RFU, SC_RST 0 PCI and PC Card Miscellaneous 1 0 6 SC_DATA, SC_FCB, SC_RFU 0 1200 PC Card 0.3 VCCP -5.6 1.3 VID Differential input voltage 118 260 Cable inputs during arbitration 168 265 VIC Common-mode input voltage TPB cable inputs, source power node 0.4706 TPB cable inputs, nonsource power node 0.4706 2.515 2.015 tPU Powerup reset time GRST input Receive input skew Between TPA and TPB cable inputs V V 4 Cable inputs during data reception TPA, TPB cable inputs V VCC SC_VCC_5V TPBIAS outputs 2 S100 operation V VCCCB VCC Output current Receive input jitter UNIT VCCP VCCP 3.3 V PCIk Low-level input voltage NOM 0.5 VCCP 2 SC_DATA, SC_FCB, SC_RFU VIL MIN ns mA mV V ms 1.08 S200 operation 0.5 S400 operation 0.315 S100 operation 0.8 S200 operation 0.55 S400 operation 0.5 ns ns TA Operating ambient temperature range 0 25 70 C TJ# Virtual junction temperature 0 25 115 C Applies to external inputs and bidirectional buffers without hysteresis Miscellaneous terminals are A03, A04, A05, A06, A07, A08, A09, A13, B04, B05, B06, B07, B08, B09, B11, B16, C04, C05, C06, C07, C08, C09, E06, E07, E08, E09, E10, F01, F02, F03, F08, G02, G03, G05, H03, J05, K05, N15, P12, P17 (CCDx, CDx, CLOCK, CLK_48, CVSx, DATA, GRST, LATCH, MC_PWR_CTRL_0, MC_PWR_CTRL_1, MS_BS, MS_CD, MS_CLK, MS_DATA2, MS_DATA3, MS_SDIO, PHY_TEST_MA, RSVD/VD0, SC_CD, SCL, SC_OC, SC_PWR_CTRL, SDA, SD_CD, SD_CLK, SD_CMD, SD_DAT0, SD_DAT1, SD_DAT2, SD_DAT3, SD_WP, SM_CD, SM_CLE, SPKROUT, SUSPEND, TEST0, USB_EN, VSx, and XD_CD terminals). Applies to external output buffers For a node that does not source power, see Section 4.2.2.2 in IEEE Std 1394a-2000. # These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature. k MFUNC(0:6) share the same specifications as the PCI terminals. September 2005 SCPS110 243 Electrical Characteristics 14.3 Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted) PARAMETER TERMINALS PCI VOH High-level output voltage PC Card OPERATION 5V 3.3 V CardBus IOH = -2 mA IOH = -0.15 mA 0.9 VCC 3.3 V 16-bit IOH = -0.15 mA 2.4 5 V 16-bit IOH = -0.15 mA 2.8 IOH = -4 mA 3.3 V Low-level output voltage VOL PC Card 5V 3.3 V 16-bit IOL = 0.7 mA 5 V 16-bit IOL = 0.7 mA 3-state output high-impedance Output terminals IOZL High-impedance, low-level output current Output terminals IOZH High-impedance, high-level output current Output terminals IIL Low-level input current IIH High-level input current V VCC-0.6 0.1 VCC 0.55 0.1 VCC 0.4 0.5 3.6 V VO = VCC or GND 20 3.6 V VI = VCC VI = VCC -1 10 5.25 V VI = VCC VI = VCC 3.6 V -1 25 20 Input terminals 3.6 V VI = GND I/O terminals 3.6 V 20 PCI 3.6 V VI = GND VI = VCC Others 3.6 V 20 3.6 V VI = VCC VI = VCC 5.25 V VI = VCC 20 3.6 V VI = VCC VI = VCC 10 Input terminals I/O terminals 5.25 V V 0.55 IOL = 4 mA 5.25 V UNIT 2.4 IOL = 6 mA IOL = 0.7 mA MAX 0.9 VCC IOL = 1.5 mA 3.3 V CardBus Miscellaneous IOZ MIN IOH = -0.5 mA Miscellaneous PCI TEST CONDITIONS 3.3 V A A A A A A A 20 10 A 25 For PCI and miscellaneous terminals, VI = VCCP. For PC Card terminals, VI = VCCCB. For I/O terminals, input leakage (IIL and IIH) includes IOZ leakage of the disabled output. Miscellaneous terminals are A03, A04, A05, A06, A07, A08, A09, A13, B04, B05, B06, B07, B08, B09, B11, B16, C04, C05, C06, C07, C08, C09, E06, E07, E08, E09, E10, F01, F02, F03, F08, G02, G03, G05, H03, J05, K05, N15, P12, P17 (CCDx, CDx, CLOCK, CLK_48, CVSx, DATA, GRST, LATCH, MC_PWR_CTRL_0, MC_PWR_CTRL_1, MS_BS, MS_CD, MS_CLK, MS_DATA2, MS_DATA3, MS_SDIO, PHY_TEST_MA, RSVD/VD0, SC_CD, SCL, SC_OC, SC_PWR_CTRL, SDA, SD_CD, SD_CLK, SD_CMD, SD_DAT0, SD_DAT1, SD_DAT2, SD_DAT3, SD_WP, SM_CD, SM_CLE, SPKROUT, SUSPEND, TEST0, USB_EN, VSx, and XD_CD terminals). 14.4 Electrical Characteristics Over Recommended Ranges of Operating Conditions (unless otherwise noted) 14.4.1 Device PARAMETER VTH VO Power status threshold, CPS input TEST CONDITION 400-k resistor TPBIAS output voltage At rated IO current II Input current (PC0-PC2 inputs) Measured at cable power side of resistor. 244 SCPS110 VCC = 3.6 V MIN MAX UNIT 4.7 7.5 1.665 2.015 V V 5 A September 2005 Electrical Characteristics 14.4.2 Driver PARAMETER VOD IDIFF ISP200 ISP400 TEST CONDITION Differential output voltage 56 , See Figure 14-1 Driver difference current, TPA+, TPA-, TPB+, TPB- Drivers enabled, speed signaling off Common-mode speed signaling current, TPB+, TPB- S200 speed signaling enabled Common-mode speed signaling current, TPB+, TPB- S400 speed signaling enabled MIN MAX UNIT 172 -1.05 265 1.05 mV -4.84 -12.4 -2.53 -8.10 mA mA mA VOFF Off state differential voltage Drivers disabled, See Figure 14-1 20 mV Limits defined as algebraic sum of TPA+ and TPA- driver currents. Limits also apply to TPB+ and TPB- algebraic sum of driver currents. Limits defined as absolute limit of each of TPB+ and TPB- driver currents. TPAx+ TPBx+ 56 TPAx- TPBx- Figure 14-1. Test Load Diagram 14.4.3 Receiver PARAMETER TEST CONDITION MIN TYP 4 7 MAX UNIT k ZID Differential impedance Drivers disabled ZIC Common-mode impedance Drivers disabled VTH-R VTH-CB Receiver input threshold voltage Drivers disabled -30 Cable bias detect threshold, TPBx cable inputs Drivers disabled 0.6 1.0 V VTH+ VTH- Positive arbitration comparator threshold voltage Drivers disabled 89 168 mV Negative arbitration comparator threshold voltage Drivers disabled -168 -89 mV VTH-SP200 VTH-SP400 Speed signal threshold TPBIAS-TPA common mode voltage, drivers disabled 49 131 mV 314 396 mV 4 20 Speed signal threshold pF k 24 pF 30 mV 14.5 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature PARAMETER tc tw(H) Cycle time, PCLK tw(L) tr, tf tw tsu Pulse duration (width), GRST ALTERNATE SYMBOL TEST CONDITIONS MIN MAX UNIT 30 ns 11 ns Pulse duration (width), PCLK low tcyc thigh tlow Slew rate, PCLK v/t 1 Pulse duration (width), PCLK high Setup time, PCLK active at end of PRST September 2005 trst trst-clk 11 ns 4 V/ns 1 ms 100 ms SCPS110 245 Electrical Characteristics 14.6 Switching Characteristics for PHY Port Interface PARAMETER tr tf MAX UNIT Jitter, transmit Between TPA and TPB TEST CONDITIONS MIN TYP 0.15 ns Skew, transmit Between TPA and TPB 0.10 ns TP differential rise time, transmit 10% to 90%, at 1394 connector 0.5 1.2 ns TP differential fall time, transmit 90% to 10%, at 1394 connector 0.5 1.2 ns 14.7 Operating, Timing, and Switching Characteristics of XI PARAMETER VDD VIH High-level input voltage VIL Low-level input voltage MIN 3.0 TYP MAX 3.3 3.6 UNIT V (PLLVCC) 0.63 VCC V 0.33 VCC Input clock frequency V 24.576 MHz Input clock frequency tolerance Input slew rate Input clock duty cycle <100 PPM 0.2 4 V/ns 40% 60% 14.8 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature This data manual uses the following conventions to describe time ( t ) intervals. The format is tA, where subscript A indicates the type of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td (ten, tdis) = delay time, tsu = setup time, and th = hold time. ALTERNATE SYMBOL PARAMETER tpd Propagation delay time, See Note 6 PCLK-to-shared signal valid delay time tval PCLK-to-shared signal invalid delay time tinv ten tdis Enable time, high impedance-to-active delay time from PCLK tsu th Setup time before PCLK valid Disable time, active-to-high impedance delay time from PCLK Hold time after PCLK high TEST CONDITIONS MIN CL = 50 pF, See Note 6 MAX UNIT 11 ns 2 ton toff 2 ns tsu th 7 ns 0 ns 28 ns NOTE 6: PCI shared signals are AD31-AD0, C/BE3-C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR. 246 SCPS110 September 2005 Electrical Characteristics VCC trst1 RST CLK I/O Indeterminate Answer to Reset tio1 tATR1 T0 T1 Figure 14-2. Cold Reset Sequence VCC trst2 RST CLK I/O Indeterminate Answer to Reset tio2 T0' tATR2 T1' Figure 14-3. Warm Reset Sequence September 2005 SCPS110 247 Electrical Characteristics tdeact VCC 0.4 V RST CLK I/O Indeterminate Card Removed Here Figure 14-4. Contact Deactivation Sequence 14.9 Reset Timing tgrst VCC PCLK CLK48 GRST PRST IDSEL tclk-prst tprst-idsel 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 3V NNNNNNNNNNNNNN NNNNNNNNNNNNNN NNNNNNNNNNNNNNN NNNNNNNNNNNNNNN NNN NNN NNNNNNNNNNNNN NNNNNNNNNNNNN NNNNNNNNNNNNN NNNNNNNNNNNNN Figure 14-5. Reset Timing Diagram PARAMETER tgrst tclk-prst VCC 3.0 V to GRST PCLK and CLK48 to PRST MIN MAX UNIT 2 ms 100 s tprst-idsel PRST to IDSEL 3 s NOTES: 7. GRST may be asynchronously deasserted, that is, it does not require a valid PCLK. 8. There is no specific timing relationship of GRST to PRST. However, if GRST is deasserted after PRST then the PCLK to PRST and PRST to IDSEL apply to GRST. 248 SCPS110 September 2005 Mechanical Data 15 Mechanical Data The PCIxx12 device is available in the 216-terminal MicroStar BGA package (GHK) or the 216-terminal lead-free (Pb atomic number 82) MicroStar BGA package (ZHK). The following figure shows the mechanical dimensions for the GHK package. The GHK and ZHK packages are mechanically identical; therefore, only the GHK mechanical drawing is shown. GHK (S-PBGA-N216) PLASTIC BALL GRID ARRAY 16,10 SQ 15,90 14,40 TYP 0,80 W V U T R P N M L K J H G F E D C B A 0,80 3 1 A1 Corner 2 5 4 7 6 0,95 11 9 8 10 13 12 15 14 19 17 16 18 Bottom View 0,85 1,40 MAX Seating Plane 0,55 0,45 0,08 0,45 0,35 0,12 4145273-3/F 10/03 NOTES: B. All linear dimensions are in millimeters. C. This drawing is subject to change without notice. D. MicroStar BGA configuration. MicroStar BGA is a trademark of Texas Instruments. September 2005 SCPS110 249 PACKAGE OPTION ADDENDUM www.ti.com 22-Nov-2005 PACKAGING INFORMATION Orderable Device Status (1) PCI4512ZHK ACTIVE BGA MI CROSTA R ZHK 216 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR PCI6412ZHK ACTIVE BGA MI CROSTA R ZHK 216 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR PCI6612ZHK ACTIVE BGA MI CROSTA R ZHK 216 1 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR PCI7402ZHK ACTIVE BGA MI CROSTA R ZHK 216 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR PCI7412ZHK ACTIVE BGA MI CROSTA R ZHK 216 1 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR PCI7612ZHK ACTIVE BGA MI CROSTA R ZHK 216 1 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR PCI8402ZHK ACTIVE BGA MI CROSTA R ZHK 216 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR PCI8412ZHK ACTIVE BGA MI CROSTA R ZHK 216 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR SN2005114512ZHK ACTIVE BGA MI CROSTA R ZHK 216 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR SN2005118412ZHK ACTIVE BGA MI CROSTA R ZHK 216 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR SNA7412ZHK ACTIVE BGA MI CROSTA R ZHK 216 1 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 22-Nov-2005 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2