16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Features Async/Page/Burst CellularRAMTM Memory MT45W1MW16BDGB Features Figure 1: * Single device supports asynchronous, page, and burst operations * Random access time: 70ns * VCC, VCCQ voltages: - 1.7-1.95V VCC - 1.7-3.6V1 VCCQ * Page mode read access - Sixteen-word page size - Interpage read access: 70ns - Intrapage read access: 20ns * Burst mode write access: continuous burst * Burst mode read access: - 4, 8, or 16 words, or continuous burst - MAX clock rate: 104 MHz (tCLK = 9.62ns) - Burst initial latency: 39ns (4 clocks) @ 104 MHz - tACLK: 7ns @ 104 MHz * Low power consumption - Asynchronous read: <20mA - Intrapage read: <15mA - Intrapage read initial access, burst read: - (39ns [4 clocks] @ 104 MHz) < 35mA - Continuous burst read: <28mA - Standby: 70A - Deep power-down: <10A (TYP @ 25C) * Low-power features - Temperature-compensated refresh (TCR) - On-chip temperature sensor - Partial-array refresh (PAR) - Deep power-down (DPD) mode Options PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_1.fm - Rev. H 4/08 EN 1 2 3 4 5 6 A LB# OE# A0 A1 A2 CRE B DQ8 UB# A3 A4 CE# DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D VSSQ DQ11 A17 A7 DQ3 VCC E VCCQ DQ12 NC A16 DQ4 VSS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 NC J WAIT CLK ADV# NC NC NC Top View (Ball Down) Options (continued) Designator * Standby power - Standard * Operating temperature range - Wireless (-30C to +85C) - Industrial (-40C to +85C) Designator * Configuration - 1 Meg x 16 * Package - 54-ball VFBGA ("green") * Access time - 70ns access * Frequency - 80 MHz - 104 MHz 54-Ball VFBGA MT45W1MW16BD GB None WT1 IT2 Notes: 1. 3.6V I/O and -30C exceed the CellularRAM Workgroup 1.0 specifications. 2. Contact factory. -70 8 1 Part Number Example: MT45W1MW16BDGB-701WT 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Burst Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 WAIT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Temperature-Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Partial-Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Deep Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Access Using CRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Software Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Burst Length (BCR[2:0]) Default = Continuous Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Burst Wrap (BCR[3]) Default = Burst No Wrap (Within Burst Length) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid . . . . . . . . .25 WAIT Polarity (BCR[10]) Default = WAIT Active HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Latency Counter (BCR[13:11]) Default = Three-Clock Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Operating Mode (BCR[15]) Default = Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Deep Power-Down (RCR[4]) Default = DPD Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Temperature-Compensated Refresh (RCR[6:5]) Default = On-Chip Temperature Sensor. . . . . . . . . . . . . . . .28 Page Mode Operation (RCR[7]) Default = Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Maximum and Typical Standby Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23zTOC.fm - Rev. H 4/08 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Functional Block Diagram - 1 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Power-Up Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 WRITE Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Page Mode READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Burst Mode READ (4-word Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Burst Mode WRITE (4-word Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Wired-OR WAIT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Refresh Collision During READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Refresh Collision During WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Configuration Register WRITE in Asynchronous Mode Followed by READ ARRAY Operation . . . .19 Configuration Register WRITE in Synchronous Mode Followed by READ ARRAY Operation . . . . .20 Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 WAIT Configuration (BCR[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 WAIT Configuration (BCR[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 WAIT Configuration During Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Latency Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Refresh Configuration Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Typical Refresh Current vs. Temperature (ITCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Asynchronous READ Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Page Mode READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Single-Access Burst READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4-Word Burst READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 READ Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Continuous Burst READ Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition . .43 CE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 LB#/UB#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 WE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Burst WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Continuous Burst WRITE Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition .49 Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Asynchronous WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Asynchronous WRITE Followed by Burst READ - ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Burst READ Followed by Asynchronous WRITE (WE#-Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Burst READ Followed by Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Asynchronous WRITE Followed by Asynchronous READ - ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . .55 Asynchronous WRITE Followed by Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23zLOF.fm - Rev. H 4/08 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Bus Operations - Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Bus Operations - Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Latency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 16Mb Address Patterns for PAR (RCR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Maximum Standby Currents for Applying PAR and TCR Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Deep Power-Down Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Asynchronous READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Burst READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Asynchronous WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Burst WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23zLOT.fm - Rev. H 4/08 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory General Description General Description Micron(R) CellularRAMTM is a high-speed, CMOS PSRAM memory device developed for low-power, portable applications. The MT45W1MW16BDGB is a 16Mb DRAM core device organized as 1 Meg x 16 bits. This device includes an industry-standard burst mode Flash interface that dramatically increases read/write bandwidth compared with other low-power SRAM or Pseudo SRAM offerings. For seamless operation on a burst Flash bus, CellularRAM products incorporate a transparent self-refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. Two user-accessible control registers define device operation. The bus configuration register (BCR) defines how the CellularRAM device interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. Special attention has been focused on standby current consumption during self refresh. CellularRAM products include three system-accessible mechanisms to minimize standby current. Partial-array refresh (PAR) limits refresh to only that part of the DRAM array that contains essential data. Temperature-compensated refresh (TCR) uses an onchip sensor to adjust the refresh rate to match the device temperature. The refresh rate decreases at lower temperatures to minimize current consumption during standby. TCR can also be set by the system for maximum device temperatures of +85C, +45C, and +15C. Deep power-down (DPD) halts the REFRESH operation altogether and is used when no vital information is stored in the device. These three refresh mechanisms are accessed through the RCR. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Functional Block Diagrams Functional Block Diagrams Figure 2: Functional Block Diagram - 1 Meg x 16 A[19:0] Address Decode Logic 1,024K x 16 DRAM MEMORY ARRAY Input/ Output MUX and Buffers DQ[7:0] DQ[15:8] Refresh Configuration Register (RCR) Bus Configuration Register (BCR) CE# WE# OE# CLK ADV# CRE WAIT LB# UB# Control Logic Note: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing diagrams for detailed information. 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Ball Descriptions Ball Descriptions Table 1: VFBGA Ball Descriptions VFBGA Assignment Symbol Type Description G2, H1, D3, E4, F4, F3, G4, G3, H5, H4, H3, H2, D4, C4, C3, B4, B3, A5, A4, A3 J2 A[19:0] Input Address inputs: Inputs for addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. The address lines are also used to define the value to be loaded into the bus configuration register or the refresh configuration register. CLK Input J3 ADV# Input A6 CRE Input B5 CE# Input A2 OE# Input G5 WE# Input A1 B2 G1, F1, F2, E2, D2, C2, C1, B1, G6, F6, F5, E5, D5, C6, C5, B6 J1 LB# UB# DQ[15:0] Input Input Input/ Output Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When configured for synchronous operation, the address is latched on the first rising CLK edge when ADV# is active. CLK is static LOW or HIGH during asynchronous access READ and WRITE operations and during PAGE READ ACCESS operations. Address valid: Indicates that a valid address is present on the address inputs. Addresses can be latched on the rising edge of ADV# during asynchronous READ and WRITE operations. ADV# can be held LOW during asynchronous READ and WRITE operations. Configuration register enable: When CRE is HIGH, WRITE operations load the refresh configuration register or bus configuration register. Chip enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby or deep power-down mode. Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a configuration register or to the memory array. Lower byte enable: DQ[7:0]. Upper byte enable: DQ[15:8]. Data inputs/outputs. WAIT Output E3, H6, J4, J5, J6 D6 E1 E6 D1 NC VCC VCCQ VSS VSSQ - Supply Supply Supply Supply Note: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is gated by CE#. WAIT is used to arbitrate collisions between REFRESH and READ/WRITE operations. WAIT is asserted when a burst crosses a row boundary. WAIT is also used to mask the delay associated with opening a new internal page. WAIT is asserted and should be ignored during asynchronous and page mode operations. WAIT is High-Z when CE# is HIGH. Not internally connected. Device power supply (1.7-1.95V): Power supply for device core operation. I/O power supply (1.7-3.6V): Power supply for input/output buffers. VSS must be connected to ground. VSSQ must be connected to ground. The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. WAIT will be asserted but should be ignored during asynchronous and page mode operations. 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Bus Operations Bus Operations Table 2: Bus Operations - Asynchronous Mode Mode Power CLK1 ADV# CE# OE# WE# CRE LB#/ UB# WAIT2 DQ[15:0]3 Notes Read Write Standby No operation Configuration Register DPD Active Active Standby Idle Active L L L L L L L X X L L L H L L L X X X H H L X X L L L L L H L L X X X Low-Z Low-Z High-Z Low-Z Low-Z Data-Out Data-In High-Z X High-Z 4 4 5, 6 4, 6 Deep power-down L X H X X X X High-Z High-Z 7 Table 3: Bus Operations - Burst Mode Mode Power CLK1 ADV# CE# OE# WE# CRE LB#/ UB# WAIT2 DQ[15:0]3 Notes Async read Async write Standby No operation Initial burst read Active Active Standby Idle Active L L L L L L X X L L L H L L L X X X X H L X X H L L L L L L L X X L Low-Z Low-Z High-Z Low-Z Low-Z Data-Out Data-In High-Z X X 4 4 5, 6 4, 6 4, 8 Initial burst write Active L L H L L X Low-Z X 4, 8 Burst continue Active H L X X X L Low-Z Data-In or Data-Out 4, 8 Burst suspend Configuration register Active Active X X L L L H H X L L H X X Low-Z Low-Z High-Z High-Z 4, 8 8 Deep power-down L X H X X X X High-Z High-Z 7 DPD Notes: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 1. CLK must be LOW during async read and async write modes, and to achieve standby power during standby and DPD modes. CLK must be static (HIGH or LOW) during burst suspend. 2. The WAIT polarity is configured through the bus configuration register (BCR[10]). 3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are affected. When only UB# is in the select mode, DQ[15:8] are affected. 4. The device will consume active power in this mode whenever addresses are changed. 5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. 6. VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve standby current. 7. DPD is maintained until RCR is reconfigured. 8. Burst mode operation is initialized through the bus configuration register (BCR[15]). 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Part Numbering Information Part Numbering Information Micron CellularRAM devices are available in several different configurations and densities (see Figure 3). Figure 3: Part Number Chart MT 45 W 1M W 16 BD GB -70 8 WT ES Micron Technology Production Status Blank = Production Product Family ES = Engineering Sample 45 = PSRAM/CellularRAM Memory MS = Mechanical Sample Operating Core Voltage Operating Temperature W = 1.7-1.95V WT = -30C to +85C (see Note 1) IT = -40C to +85C (contact factory) Address Locations Standby Power Options M = Megabits Blank = Standard Operating Voltage Frequency W = 1.7-3.6V (see Note 1) 8 = 80 MHz Bus Configuration 1 = 104 MHz 16 = x16 Access/Cycle Time READ/WRITE Operation Mode 70 = 70ns BD = Asynchronous/Page/Burst Package Codes GB = VFBGA "green" (6 x 9 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm) 54-ball Notes: 1. 3.6V I/O and -30C exceed the CellularRAM Workgroup 1.0 specifications. Valid Part Number Combinations After building the part number from the part numbering chart above, visit to the Micron Part Marking Decoder Web site at www.micron.com/partsearch to verify that the part number is offered and valid. If the device required is not on this list, contact the factory. Device Marking Due to the size of the package, the Micron standard part number is not printed on the top of the device. Instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers at www.micron.com/partsearch. To view the location of the abbreviated mark on the device, refer to customer service note, CSN-11, "Product Mark/Label" at www.micron.com/csn. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Functional Description Functional Description In general, the MT45W1MW16BDGB devices are high-density alternatives to SRAM and Pseudo SRAM products, popular in low-power, portable applications. The MT45W1MW16BDGB contains a 16,777,216-bit DRAM core organized as 1,048,576 addresses by 16 bits. This device implements the same high-speed bus interface found on burst mode Flash products. The CellularRAM bus interface supports both asynchronous and burst mode transfers. Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol. Power-Up Initialization CellularRAM products include an on-chip voltage sensor used to launch the power-up initialization process. Initialization will configure the BCR and the RCR with their default settings (see Figure 17 on page 23 and Figure 22 on page 27). VCC and VCCQ must be applied simultaneously. When they reach a stable level at or above 1.7V, the device will require 150s to complete its self-initialization process. During the initialization period, CE# should remain HIGH. When initialization is complete, the device is ready for normal operation. Figure 4: Power-Up Initialization Timing Vcc = 1.7V Vcc VccQ tPU > 150s Device ready for Device Initialization normal operation Bus Operating Modes The MT45W1MW16BDGB CellularRAM products incorporate a burst mode interface found on Flash products targeting low-power, wireless applications. This bus interface supports asynchronous, page mode, and burst mode read and write transfers. The specific interface supported is defined by the value loaded into the bus configuration register. Page mode is controlled by the refresh configuration register (RCR[7]). Asynchronous Mode CellularRAM products power up in the asynchronous operating mode. This mode uses the industry-standard SRAM control bus (CE#, OE#, WE#, LB#/UB#). READ operations (Figure 5) are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified access time has elapsed. WRITE operations (Figure 6 on page 11) occur when CE#, WE#, and LB#/UB# are driven LOW. During asynchronous WRITE operations, the OE# level is a "Don't Care," and WE# will override OE#. The data to be written is latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs first). Asynchronous operations (page mode disabled) can either use the ADV input to latch the address, or ADV can be driven LOW during the entire READ/WRITE operation. During asynchronous operation, the CLK input must be held static LOW or HIGH. WAIT will be driven while the device is enabled and its state should be ignored. WE# LOW time must be limited to tCEM. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Bus Operating Modes Figure 5: READ Operation (ADV = LOW) CE# OE# WE# ADDRESS ADDRESS VALID DATA DATA VALID LB#/UB# tRC = READ Cycle Time Note: Figure 6: ADV must remain LOW for page mode operation. WRITE Operation (ADV = LOW) CE# OE# <tCEM WE# ADDRESS ADDRESS VALID DATA DATA VALID LB#/UB# tWC = WRITE Cycle Time DON'T CARE Page Mode READ Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page-mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be read quickly by simply changing the loworder address. Addresses A[3:0] are used to determine the members of the 16-address CellularRAM page. Any change in addresses A[4] or higher will initiate a new tAA access time. Figure 7 shows the timing for a page mode access. Page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. WRITE operations do not include comparable page mode functionality. During asynchronous page mode operation, the CLK input must be held static LOW or HIGH. CE# must be driven HIGH upon completion of a page mode access. WAIT will be driven while the device is enabled and its state should be ignored. Page mode is enabled by setting RCR[7] to HIGH. ADV must be driven LOW during all page mode read accesses. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Bus Operating Modes The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than tCEM. Figure 7: Page Mode READ Operation (ADV = LOW) <tCEM CE# OE# WE# ADDRESS ADDRESS[0] tAA ADDRESS ADDRESS ADDRESS [1] [2] [3] tAPA DATA D[0] tAPA D[1] tAPA D[2] D[3] LB#/UB# DON'T CARE Burst Mode Operation Burst mode operations enable high-speed synchronous READ and WRITE operations. Burst operations consist of a multi-clock sequence that must be performed in an ordered fashion. After CE# goes LOW, the address to access is latched on the next rising edge of CLK that ADV# is LOW. During this first clock rising edge, WE# indicates whether the operation is going to be a READ (WE# = HIGH, Figure 8 on page 13) or WRITE (WE# = LOW, Figure 9 on page 14). The size of a burst can be specified in the BCR as either fixed-length or continuous. Fixed-length bursts consist of four, eight, or sixteen words. Continuous bursts have the ability to start at a specified address and burst through the entire memory. The latency count stored in the BCR defines the number of clock cycles that elapse before the initial data value is transferred between the processor and CellularRAM device. The WAIT output will be asserted as soon as CE# goes LOW and will be de-asserted to indicate when data is to be transferred into (or out of ) the memory. WAIT will again be asserted if the burst crosses the boundary between 128-word rows. Once the CellularRAM device has restored the previous row's data and accessed the next row, WAIT will be de-asserted and the burst can continue (see Figure 33 on page 43). The processor can access other devices without incurring the timing penalty of the initial latency for a new burst by suspending burst mode. Bursts are suspended by stopping CLK. CLK can be stopped HIGH or LOW. If another device will use the data bus while the burst is suspended, OE# should be taken HIGH to disable the CellularRAM outputs; otherwise, OE# can remain LOW. Note that the WAIT output will continue to be active, and as a result no other devices should directly share the WAIT connection to the controller. To continue the burst sequence, OE# is taken LOW, then CLK is restarted after valid data is available on the bus. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Bus Operating Modes The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than tCEM unless row boundaries are crossed at least every tCEM. If a burst suspension will cause CE# to remain LOW for longer than tCEM, CE# should be taken HIGH and the burst restarted with a new CE# LOW/ADV# LOW cycle. Figure 8: Burst Mode READ (4-word Burst) CLK ADDRESS VALID A[19:0] ADV# Latency Code 2 (3 clocks) CE# OE# WE# WAIT DQ[15:0] D[0] D[1] D[2] D[3] LB#/UB# DON'T CARE READ Burst Identified (WE# = HIGH) Note: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN UNDEFINED Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Bus Operating Modes Figure 9: Burst Mode WRITE (4-word Burst) CLK ADDRESS VALID A[19:0] ADV# Latency Code 2 (3 clocks) CE# OE# WE# WAIT DQ[15:0] D[0] D[1] D[2] D[3] LB#/UB# DON'T CARE WRITE Burst Identified (WE# = LOW) Note: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Bus Operating Modes Mixed-Mode Operation The device can support a combination of synchronous READ and asynchronous WRITE operations when the BCR is configured for synchronous operation. The asynchronous WRITE operation requires that the clock (CLK) be held static LOW or HIGH during the entire sequence. The ADV# signal can be used to latch the target address, or it can remain LOW during the entire WRITE operation. CE# must return HIGH when transitioning between mixed-mode operations. Note that the tCKA period is the same as a READ or WRITE cycle. This time is required to ensure adequate refresh. Mixed-mode operation facilitates a seamless interface to legacy burst mode Flash memory controllers. See Figure 41 on page 51. WAIT Operation The WAIT output on a CellularRAM device is typically connected to a shared, systemlevel WAIT signal (see Figure 10). The shared WAIT signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus. Figure 10: Wired-OR WAIT Configuration CellularRAM WAIT External Pull-Up/ Pull-Down Resistor READY Processor WAIT WAIT Other Device Other Device Once a READ or WRITE operation has been initiated, WAIT goes active to indicate that the CellularRAM device requires additional time before data can be transferred. For READ operations, WAIT will remain active until valid data is output from the device. For WRITE operations, WAIT will indicate to the memory controller when data will be accepted into the CellularRAM device. When WAIT transitions to an inactive state, the data burst will progress on successive clock edges. During a Burst cycle, CE# must remain asserted until the first data is valid. Bringing CE# HIGH during this initial latency may cause data corruption. The WAIT output also performs an arbitration role when a READ or WRITE operation is launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted for additional clock cycles until the refresh has completed (see Figures 11 and 12 on page 17). When the refresh operation has completed, the READ or WRITE operation will continue normally. WAIT is also asserted when a continuous READ or WRITE burst crosses a row boundary. The WAIT assertion allows time for the new row to be accessed and permits any pending refresh operations to be performed. LB#/UB# Operation The LB# enable and UB# enable signals support byte-wide data transfers. During READ operations, the enabled byte(s) are driven onto the DQ. The DQ associated with a disabled byte are put into a High-Z state during a READ operation. During WRITE opera- PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Bus Operating Modes tions, any disabled bytes will not be transferred to the RAM array and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. When both the LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as CE# remains LOW. Figure 11: CLK A[19:0] ADV# CE# OE# WE# LB#/UB# WAIT DQ[15:0] Refresh Collision During READ Operation VIH VIL VIH VIL VALID ADDRESS VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL High-Z VOH D[0] VOL Additional WAIT states inserted to allow refresh completion. Note: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN D[1] D[2] D[3] UNDEFINED DON'T CARE Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Bus Operating Modes Figure 12: CLK A[19:0] ADV# CE# OE# WE# LB#/UB# WAIT DQ[15:0] Refresh Collision During WRITE Operation VIH VIL VIH VIL VALID ADDRESS VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL High-Z VOH D[0] VOL Additional WAIT states inserted to allow refresh completion. Note: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN D[1] D[2] D[3] DON'T CARE Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Low-Power Operation Low-Power Operation Standby Mode Operation During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation. Standby operation occurs when CE# is HIGH. The device will enter a reduced power state upon completion of a READ or WRITE operation or when the address and control inputs remain static for an extended period of time. This mode will continue until a change occurs to the address or control inputs. Temperature-Compensated Refresh Temperature-compensated refresh (TCR) allows for adequate refresh at different temperatures. This CellularRAM device includes an on-chip temperature sensor. When the sensor is enabled, it continually adjusts the refresh rate according to the operating temperature. The on-chip sensor is enabled by default. Three fixed refresh rates are also available, corresponding to temperature thresholds of +15C, +45C, and +85C. The setting selected must be for a temperature higher than the case temperature of the CellularRAM device. If the case temperature is +35C, the system can minimize self refresh current consumption by selecting the +45C setting. The +15C setting would result in inadequate refreshing and cause data corruption. Partial-Array Refresh Partial-array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map (see Table 6 on page 28). READ and WRITE operations to address ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will become corrupted. When re-enabling additional portions of the array, the new portions are available immediately upon writing to the RCR. Deep Power-Down Operation Deep power-down (DPD) operation disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled by rewriting the RCR, the CellularRAM device will require 150s to perform an initialization procedure before normal operations can resume. During this 150s period, the current consumption will be higher than the specified standby levels, but considerably lower than the active current specification. DPD cannot be enabled or disabled by writing to the RCR using the software access sequence; the RCR should be accessed using CRE instead. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Configuration Registers Two user-accessible configuration registers define the device operation. The bus configuration register (BCR) defines how the CellularRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated any time the devices are operating in a standby state. Access Using CRE The configuration registers are loaded using either a synchronous or an asynchronous WRITE operation when the configuration register enable (CRE) input is HIGH (see Figure 13 on page 19 and Figure 14 on page 20). When CRE is LOW, a READ or WRITE operation will access the memory array. The register values are placed on address pins A[19:0]. In an asynchronous WRITE, the values are latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB# are "Don't Care." Access using CRE is WRITE only. The BCR is accessed when A[19] is HIGH; the RCR is accessed when A[19] is LOW. Figure 13: Configuration Register WRITE in Asynchronous Mode Followed by READ ARRAY Operation CLK A[18:0] OPCODE ADDRESS tAVH tAVS Select Control Register A191 ADDRESS tAVS CRE tAVH tVPH ADV# tVP tCPH Initiate Control Register Access CE# tCW OE# tWP Write Address Bus Value to Control Register WE# LB#/UB# DQ[15:0] DATA VALID DON'T CARE Note: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN A[19] = LOW to load RCR; A[19] = HIGH to load BCR. 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Figure 14: Configuration Register WRITE in Synchronous Mode Followed by READ ARRAY Operation CLK Latch Control Register Value A[18:0] ADDRESS OPCODE tHD tSP Latch Control Register Address A192 ADDRESS tSP CRE tHD tSP ADV# tHD tCBPH3 tCSP CE# OE# tSP WE# tHD LB#/UB# tCEW WAIT High-Z High-Z DATA VALID DQ[15:0] DON'T CARE Notes: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 1. Non-default BCR settings for CR WRITE in synchronous mode followed by READ ARRAY operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. A[19] = LOW to load RCR; A[19] = HIGH to load BCR. 3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored--additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles. 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Software Access Software access of the configuration registers uses a sequence of asynchronous READ and asynchronous WRITE operations. The contents of the configuration registers can be read or modified using the software sequence. The configuration registers are loaded using a four-step sequence consisting of two asynchronous READ operations followed by two asynchronous WRITE operations (see Figure 15). The read sequence is virtually identical except that an asynchronous READ is performed during the fourth operation (see Figure 16). Note that a third READ cycle of the highest address will cancel the access sequence until a different address is read. The address used during all READ and WRITE operations is the highest address of the CellularRAM device being accessed (FFFFFh for 16Mb); the content at this address is not changed by using this sequence. The data value presented during the third operation (WRITE) in the sequence defines whether the BCR or the RCR is to be accessed. If the data is 0000h, the sequence will access the RCR; if the data is 0001h, the sequence will access the BCR. During the fourth operation, DQ[15:0] transfer data into or out of bits 15-0 of the configuration registers. The use of the software sequence does not affect the ability to perform the standard (CRE-controlled) method of loading the configuration registers. However, the software nature of this access mechanism eliminates the need for the control register enable (CRE) pin. If the software mechanism is used, the CRE pin can simply be tied to VSS. The port line often used for CRE control purposes is no longer required. Software access of the RCR should not be used to enter or exit DPD. Figure 15: Load Configuration Register ADDRESS READ READ WRITE WRITE ADDRESS (MAX) ADDRESS (MAX) ADDRESS (MAX) ADDRESS (MAX) CE# OE# WE# Note 0ns (Min) LB#/UB# DATA XXXXh CR VALUE IN XXXXh RCR: 0000h BCR: 0001h Note: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN DON'T CARE If the data present when WE# falls is not 0000h or 0001h, it is possible that the maximum address will be overwritten. 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Figure 16: Read Configuration Register ADDRESS READ READ WRITE READ ADDRESS (MAX) ADDRESS (MAX) ADDRESS (MAX) ADDRESS (MAX) CE# OE# WE# Note: 0ns (Min) LB#/UB# DATA XXXXh CR VALUE OUT XXXXh RCR: 0000h BCR: 0001h Note: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN DON'T CARE If the data present when WE# falls is not 0000h or 0001h, it is possible that the maximum address will be overwritten. 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Bus Configuration Register The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Figure 17 describes the control bits in the BCR. At power-up, the BCR is set to 9D4Fh. The BCR is accessed using CRE and A[19] HIGH or through the configuration register software sequence with DQ = 0001h on the third cycle. Figure 17: Bus Configuration Register Definition A15 A19 A[18:16] 18-16 19 Register Select Reserved A14 A13 A12A11 A10 15 14 Operating Mode Must be set to "0" 10 13 12 11 Latency Counter Reserved WAIT Polarity Must be set to "0" A8 A9 9 Reserved A7 7 8 WAIT Configuration (WC) Must be set to "0" BCR[13] BCR[12] BCR[11] A5 A6 Clock Configuration (CC) Output Impedance Must be set to "0" 0 0 Code 0-Reserved 0 0 1 Code 1-Reserved 0 1 0 Code 2 0 1 1 Code 3 (Default) 1 0 0 Code 4-Reserved 1 0 1 Code 5-Reserved 1 1 0 Code 6-Reserved 1 WAIT Polarity BCR[5] 0 Full Drive (default) 1 1/4 Drive BCR[6] WAIT Configuration Asserted during delay 0 Not supported 1 Asserted one data cycle before delay (default) 1 Rising edge (default) Operation Mode BCR[2] Register Select Select BCR 0 Clock Configuration 0 Asynchronous access mode (default) 1 1 Output Impedance Active HIGH (default) 1 Select RCR Burst no wrap (default) 1 Synchronous burst access mode 0 Burst wraps within the burst length 1 Active LOW 0 BCR[19] 2 Burst Wrap (Note 1) 0 0 BCR[15] 3 Burst Burst Wrap (BW)* Length (BL)* Code 7-Reserved BCR[10] BCR[8] A2 A1 A0 Must be set to "0" BCR[3] 1 Reserved A3 Latency Counter 0 1 4 5 6 Reserved A4 Note: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN BCR[1] BCR[0] Burst Length (Note 1) 0 0 1 4 words 0 1 0 8 words 0 1 1 16 words 1 1 1 Continuous burst (default) All burst WRITEs are continuous. 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Table 4: Sequence and Burst Length Burst Wrap 4-Word Burst Length 8-Word Burst Length 16-Word Burst length Continuous Burst Linear Linear Linear Linear 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 ... 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 0 1 2 0-1-2-3 1-2-3-4 2-3-4-5 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3 3-4-5-6 3-4-5-6-7-8-9-10 Starting Address BCR[3] Wrap (Decimal) 0 Yes 0 1 2 3 4 5 6 7 ... 14 15 1 No 4 4-5-6-7-8-9-10-11 5 5-6-7-8-9-10-11-12 6 6-7-8-9-10-11-1213 7-8-9-10-11-12-1314 7 ... 14 15 0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10-... 5-6-7-8-9-10-11-... 6-7-8-9-10-11-127-8-9-10-11-12-13-... ... 14-15-16-17-18-19-20... 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-18-19-2021... 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-9-10-11-12-13-14-15-162-3-4-5-6-7-8-... 17 3-4-5-6-7-8-9-10-11-12-13-14-15-16-173-4-5-6-7-8-9-... 18 4-5-6-7-8-9-10-11-12-13-14-15-16-174-5-6-7-8-9-10-... 18-19 5-6-7-8-9-10-11-12-13-...-15-16-17-185-6-7-8-9-10-11... 19-20 6-7-8-9-10-11-12-13-14-...-16-17-18-196-7-8-9-10-11-12... 20-21 7-8-9-10-11-12-13-14-...-17-18-19-207-8-9-10-11-12-13... 21-22 ... ... 14-15-16-17-18-19-...-23-24-25-26-27- 14-15-16-17-18-19-2028-29 ... 15-16-17-18-19-20-...-24-25-26-27-28- 15-16-17-18-19-20-2129-30 ... Burst Length (BCR[2:0]) Default = Continuous Burst Burst lengths define the number of words the device outputs during a burst READ operation. The device supports a burst length of 4, 8, or 16 words. The device can also be set in continuous burst mode where data is output sequentially without regard to address boundaries; the internal address wraps to 000000h if the device is read past the last address. WRITE bursts are always performed using continuous burst mode. Burst Wrap (BCR[3]) Default = Burst No Wrap (Within Burst Length) The burst wrap option determines if a 4-, 8-, or 16-word burst READ wraps within the burst length or steps through sequential addresses. If the wrap option is not enabled, the device outputs data from sequential addresses without regard to burst boundaries; the internal address wraps to 000000h if the device is read past the last address. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength The output driver strength can be altered to adjust for different data bus loading scenarios. The reduced-strength option should be more than adequate in stacked chip (Flash + CellularRAM) environments when there is a dedicated memory bus. The reduceddrive-strength option is included to minimize noise generated on the data bus during READ operations. Normal output impedance should be selected when using a discrete CellularRAM device in a more heavily loaded data bus environment. Partial drive is approximately one-quarter full drive strength. Outputs are configured at full drive strength during testing. WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus. The memory controller will use the WAIT signal to coordinate data transfer during synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after WAIT transitions to the de-asserted or asserted state, respectively (see Figures 18 and 20). When BCR[8] = 1, the WAIT signal transitions one clock period prior to the data bus going valid or invalid (see Figures 19 and 20). WAIT Polarity (BCR[10]) Default = WAIT Active HIGH The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-down resistor to maintain the de-asserted state. Figure 18: WAIT Configuration (BCR[8] = 0) CLK WAIT DQ[15:0] High-Z Data[0] Data[1] Data immediately valid (or invalid) Note: Figure 19: Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). See Figure 20 on page 26. WAIT Configuration (BCR[8] = 1) CLK WAIT D[15:0] High-Z Data[0] Data valid (or invalid) after one clock delay Note: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See Figure 20 on page 26. 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Figure 20: WAIT Configuration During Burst Operation CLK BCR[8] = 0 Data valid in current cycle. WAIT BCR[8] = 1 Data valid in next cycle. WAIT DQ[15:0] D[1] D[0] D[2] D[3] D[4] DON'T CARE Note: Non-default BCR setting for WAIT during BURST operation: WAIT active LOW. Latency Counter (BCR[13:11]) Default = Three-Clock Latency The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data value transferred. Only latency code two (three clocks) or latency code three (four clocks) is allowed (see Table 5 and Figure 21). Operating Mode (BCR[15]) Default = Asynchronous Operation The operating mode bit selects either synchronous BURST operation or the default asynchronous mode of operation. Table 5: Latency Configuration Max Input CLK Frequency (MHz) Latency Configuration Code 2 (3 clocks) 3 (4 clocks) - default Figure 21: CLK A[19:0] ADV# 104 MHz 80 MHz 66 (15ns) 104 (9.62ns) 53 (18.75ns) 80 (12.50ns) Latency Counter VIH VIL VIH VIL VALID ADDRESS VIH VIL Code 2 DQ[15:0] VOH VALID OUTPUT VOL Code 3 DQ[15:0] VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT (Default) VOH VOL DON'T CARE PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 26 UNDEFINED Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Refresh Configuration Register The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the RCR. Figure 22 describes the control bits used in the RCR. At power-up, the RCR is set to 0010h. The RCR is accessed using CRE and A[19] LOW; or through the configuration register software access sequence with DQ = 0000h on the third cycle (see "Configuration Registers" on page 19.) Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map (see Table 6 on page 28). Figure 22: Refresh Configuration Register Mapping A19 A[18:8] 19 18-8 Register Select RESERVED A6 A7 7 6 PAGE TCR A5 A4 5 4 A1 A2 3 DPD RESERVED Register Select PAR RCR[2] RCR[1] RCR[0] Refresh Coverage 0 Select RCR 0 0 0 Full array (default) 1 Select BCR 0 0 1 Bottom 1/2 array 0 RCR[7] Page Mode Enable/Disable 0 Page Mode Disabled (default) 1 Page Mode Enable RCR[6] RCR[5] Maximum Case Temp. RCR[4] 1 0 Bottom 1/4 array 0 1 1 Bottom 1/8 array 1 0 0 None of array 1 0 1 Top 1/2 array 1 1 0 Top 1/4 array 1 1 1 Top 1/8 array Deep Power-Down 1 1 +85C 0 DPD Enable 0 0 Internal sensor (default) 1 DPD Disable (default) 0 1 +45C 1 0 +15C PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN Address Bus 0 1 2 A0 Must be set to "0" All must be set to "0" RCR[19] A3 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Table 6: 16Mb Address Patterns for PAR (RCR[4] = 1) RCR[2] RCR[1] RCR[0] Active Section Address Space Size Density 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Full die One-half of die One-quarter of die One-eighth of die None of die One-half of die One-quarter of die One-eighth of die 000000h-0FFFFFh 000000h-07FFFFh 000000h-03FFFFh 000000h-01FFFFh 0 80000h-0FFFFFh C0000h-0FFFFFh E0000h-0FFFFFh 1 Meg x 16 512K x 16 256K x 16 128K x 16 0 Meg x 16 512K x 16 256K x 16 128K x 16 16Mb 8Mb 4Mb 2Mb 0Mb 8Mb 4Mb 2Mb Deep Power-Down (RCR[4]) Default = DPD Disabled The deep power-down bit enables and disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled, the CellularRAM device will require 150s to perform an initialization procedure before normal operations can resume. Deep power-down is enabled when RCR[4] = 0, and remains enabled until RCR[4] is set to "1." DPD should not be enabled or disabled with the software access sequence; instead, use CRE to access the RCR. Temperature-Compensated Refresh (RCR[6:5]) Default = On-Chip Temperature Sensor This CellularRAM device includes an on-chip temperature sensor that automatically adjusts the refresh rate according to the operating temperature. The on-chip TCR is enabled by clearing both of the TCR bits in the refresh configuration register (RCR[6:5] = 00b). Any other TCR setting enables a fixed refresh rate. When the on-chip temperature sensor is enabled, the device continually adjusts the refresh rate according to the operating temperature. The TCR bits also allow for adequate fixed-rate refresh at three different temperature thresholds (+15C, +45C, and +85C). The setting selected must be for a temperature higher than the case temperature of the CellularRAM device. If the case temperature is +35C, the system can minimize self refresh current consumption by selecting the +45C setting. The +15C setting would result in inadequate refreshing and cause data corruption. Page Mode Operation (RCR[7]) Default = Disabled The page mode operation bit determines whether page mode is enabled for asynchronous READ operations. In the power-up default state, page mode is disabled. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Electrical Characteristics Electrical Characteristics Table 7: Absolute Maximum Ratings Notes: Parameter Rating Voltage to any ball except VCC, VCCQ relative to VSS Voltage on VCC supply relative to VSS Voltage on VCCQ supply relative to VSS Storage temperature (plastic) Operating temperature (case) Wireless1 Industrial Soldering temperature and time 10 seconds (solder ball only) -0.5V to (4.0V or VCCQ + 0.3V, whichever is less) -0.2V to +2.45V -0.2V to +4.0V -55C to +150C -30C to +85C -40C to +85C +260C 1. -30C exceeds the CellularRAM Workgroup 1.0 specification of -25C. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Electrical Characteristics Table 8: Electrical Characteristics and Operating Conditions Wireless temperature1 (-30C < TC < +85C); Industrial temperature (-40C < TC < +85C) Description Conditions Supply voltage I/O supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Output leakage current IOH = -0.2mA IOL = +0.2mA VIN = 0 to VCCQ OE# = VIH or Chip disabled Operating Current Asynchronous random READ/ WRITE Asynchronous page READ VIN = VCCQ or 0V Chip enabled, IOUT = 0 Initial access, burst READ/WRITE Symbol VCC VCCQ VIH VIL VOH VOL ILI ILO 1.95 3.6 VCCQ + 0.2 0.4 0.2 VCCQ 1 1 V V V V V V A A 1 2, 3 4 5 5 mA 6 ICC1P -70 15 mA 6 ICC2 104 MHz 80 MHz 104 MHz 80 MHz 104 MHz 80 MHz Standard 35 30 28 22 33 25 70 mA 6 mA 6 mA 6 A 7 ICC3W PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 1.7 1.7 1.4 -0.2 0.8 VCCQ Notes 20 Continuous burst WRITE Notes: Units -70 ICC3R VIN = VCCQ or 0V CE# = VCCQ Max ICC1 Continuous burst READ Standby current Min ISB 1. 2. 3. 4. 5. 6. -30C and 3.6V I/O exceed the CellularRAM Workgroup 1.0 specifications. Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions. VIH (MIN) value is not aligned with CellularRAM work group 1.0 specification of VCCQ - 0.4V. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions. BCR[5] = 0b. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive output capacitance expected in the actual system. 7. ISB (MAX) values measured with PAR set to FULL ARRAY and TCR set to +85C. In order to achieve low standby current, all inputs must be driven to either VCCQ or VSS. ISB might be slightly higher for up to 500ms after power-up, after changes to the PAR array partition, or when entering standby mode. 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Electrical Characteristics Maximum and Typical Standby Currents The following table and figure refer to the maximum and typical standby currents for the MT45W1MW16BDGB device. The typical values shown in Figure 23 are measured with the default on-chip temperature sensor control enabled. The maximum values shown in Table 9 are measured with the relevant TCR bits set in the configuration register. Table 9: Maximum Standby Currents for Applying PAR and TCR Settings TCR PAR +15C (RCR[6:5] = 10b) +45C (RCR[6:5] = 01b) +85C (RCR[6:5] = 11b) Units 45 40 37 37 35 60 55 50 50 45 70 65 60 60 55 A A A A A Full array 1/2 array 1/4 array 1/8 array 0 array Notes: Figure 23: 1. For RCR[6:5] = 00b (default) refer to Figure 23, Typical Refresh Current vs. Temperature (ITCR) for typical values. 2. In order to achieve low standby current, all inputs must be driven to VCCQ or VSS. ISB might be slightly higher for up to 500ms after power-up, after changes to the PAR array portion, or when entering standby mode. 3. TCR values for 85C are 100 percent tested. TCR values for 15C and 45C are sampled only. 4. Typical ISB currents for each PAR setting with the appropriate TCR selected, or temperature sensor enabled. Typical Refresh Current vs. Temperature (ITCR) 50 45 40 35 PAR FULL PAR 1/2 PAR 1/4 PAR 0 ISB (A) 30 25 20 15 10 5 C 85 C 75 C 65 C 55 C 45 C C 35 25 C 15 C 05 C C -0 5 -1 5 C -2 5 C -3 5 -4 5 C 0 Temperature (C) Note: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN Typical ISB currents for each PAR setting with the appropriate TCR selected, or temperature sensor enabled. 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Electrical Characteristics Table 10: Deep Power-Down Specifications Description Deep power-down Table 11: Conditions Symbol Typ Units VIN = VCCQ or 0V; +25C IZZ 10 A Capacitance Description Input capacitance Input/output capacitance (DQ) Notes: Figure 24: Conditions Symbol Min Max Units Notes TC = +25C; f = 1 MHz; VIN = 0V CIN CIO 2.0 3.0 6.5 6.5 pF pF 1 1 1. These parameters are verified in device characterization and are not 100 percent tested. AC Input/Output Reference Waveform VCCQ Input 1 2 VCC/2 Test Points 3 VCCQ/2 Output VSSQ Notes: Figure 25: 1. AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns. 2. Input timing begins at VCC/2. Due to the possibility of a difference between VCC and VCCQ, the input test point may not be shown to scale. 3. Output timing ends at VCCQ/2. Output Load Circuit Test Point DUT 50 VccQ/2 30pF Notes: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0b). 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Requirements Timing Requirements Table 12: Asynchronous READ Cycle Timing Requirements 70ns Parameter 1 Symbol Address access time ADV# access time Page access time Address hold from ADV# HIGH Address setup to ADV# HIGH LB#/UB# access time LB#/UB# disable to DQ High-Z output LB#/UB# enable to Low-Z output Maximum CE# pulse width CE# LOW to WAIT valid Chip select access time CE# LOW to ADV# HIGH Chip disable to DQ and WAIT High-Z output Chip enable to Low-Z output Output enable to valid output Output hold from address change Output disable to DQ High-Z output Output enable to Low-Z output Page cycle time READ cycle time ADV# pulse width LOW ADV# pulse width HIGH Notes: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN Min t t AA AADV t APA t AVH tAVS t BA tBHZ tBLZ tCEM tCEW tCO tCVS tHZ tLZ tOE tOH tOHZ tOLZ tPC tRC tVP tVPH Max Units 70 70 20 ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns 5 10 70 8 10 1 8 7.5 70 10 8 10 20 5 8 3 20 70 10 10 Notes 4 3 2 4 3 4 3 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0b). 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 25 on page 32. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 3. High-Z to Low-Z timings are tested with the circuit shown in Figure 25 on page 32. The LowZ timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 4. Page mode enabled only. 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Requirements Table 13: Burst READ Cycle Timing Requirements 104 MHz Parameter1 Symbol Burst to READ access time CLK to output delay Burst OE# LOW to output delay CE# HIGH between subsequent burst and mixed-mode operations Maximum CE# pulse width CE# LOW to WAIT valid CLK period CE# setup time to active CLK edge Hold time from active CLK edge Chip disable to DQ and WAIT High-Z output CLK rise or fall time CLK to WAIT valid Output HOLD from CLK CLK HIGH or LOW time Output disable to DQ High-Z output Output enable to Low-Z output Setup time to active CLK edge Notes: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN Min t ABA ACLK t BOE t CBPH 5 tCEM CEW tCLK t CSP tHD Max Min 35 7 20 t t 80 MHz 1 9.62 3 2 tHZ tKHTL tKOH 8 7.5 20 20 2 3 tKP tOHZ 1 12.5 4.5 2 3 3 tSP Notes 46.5 9 20 ns ns ns ns 2 8 7.5 20 20 8 1.8 9 2 4 8 tOLZ Units 5 8 1.6 7 tKHKL Max 8 3 3 s ns ns ns ns ns ns ns ns ns ns ns ns 3 3 4 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0b). 2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. 3. Low-Z to High-Z timings are tested with the circuit shown in Figure 25 on page 32. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 4. High-Z to Low-Z timings are tested with the circuit shown in Figure 25 on page 32. The LowZ timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Requirements Table 14: Asynchronous WRITE Cycle Timing Requirements 70ns Parameter Symbol t AS AVH t AVS t AW tBW t CEW t CKA tCPH tCVS t CW tDH tDW tHZ tLZ tOW tVP tVPH tVS tWC tWHZ tWP tWPH tWR Address and ADV# LOW setup time Address hold from ADV# going HIGH Address setup to ADV# going HIGH Address valid to end of WRITE LB#/UB# select to end of WRITE CE# LOW to WAIT valid Async address-to-burst transition time CE# HIGH between subsequent asynchronous operations CE# LOW to ADV# HIGH Chip enable to end of WRITE Data hold from WRITE time Data WRITE setup time Chip disable to WAIT High-Z output Chip enable to Low-Z output End WRITE to Low-Z output ADV# pulse width ADV# pulse width HIGH ADV# setup to End of WRITE WRITE cycle time WRITE to DQ High-Z output WRITE pulse width WRITE pulse width HIGH WRITE recovery time Notes: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN t Min 0 5 10 70 70 1 70 5 10 70 0 23 Max 7.5 8 10 5 10 10 70 70 8 46 10 0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1 1 2 3 1. High-Z to Low-Z timings are tested with the circuit shown in Figure 25 on page 32. The LowZ timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 25 on page 32. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 3. WE# LOW time must be limited to tCEM (8s). 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Requirements Table 15: Burst WRITE Cycle Timing Requirements 104 MHz Parameter Symbol CE# HIGH between subsequent burst and mixed-mode operations Maximum CE# pulse width CE# LOW to WAIT valid Clock period CE# setup to CLK active edge Hold time from active CLK edge Chip disable to WAIT High-Z output CLK rise or fall time Clock to WAIT valid CLK HIGH or LOW time Setup time to active CLK edge Notes: Figure 26: t Min CBPH CEW CLK tCSP t HD tHZ t KHKL tKHTL tKP tSP t Max Min 5 tCEM t 80 MHz 1 9.62 3 2 Max 5 8 7.5 20 20 1 12.5 4.5 2 8 1.6 7 8 7.5 20 20 8 1.8 9 3 3 4 3 Units Notes ns 1 s ns ns ns ns ns ns ns ns ns 1 1. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Initialization Period Vcc (MIN) Vcc, VccQ = 1.7V Table 16: tPU Device ready for normal operation Initialization Timing Parameters -70 Parameter Symbol tPU Initialization period (required before normal operations) PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 36 Min Max Units 150 s Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Timing Diagrams Figure 27: Asynchronous READ tRC VIH A[19:0] VALID ADDRESS VIL tAA ADV# VIH VIL tHZ CE# VIH VIL LB#/UB# tCO tBA VIH tBHZ VIL tOE OE# WE# tOHZ VIH VIL VIH VIL tBLZ tOLZ tLZ VOH DQ[15:0] High-Z VOL VALID OUTPUT tCEW tHZ VOH WAIT VOL High-Z High-Z DON'T CARE PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 37 UNDEFINED Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 28: Asynchronous READ Using ADV# A[19:0] VIH VALID ADDRESS VIL tAA tAVS tVPH tAVH VIH ADV# VIL tAADV tVP tCVS tHZ VIH CE# VIL tCO tBA tBHZ VIH LB#/UB# VIL tOE tOHZ VIH OE# VIL VIH WE# tOLZ tBLZ VIL tLZ DQ[15:0] VOH High-Z VALID OUTPUT VOL tCEW WAIT tHZ VOH VOL High-Z High-Z DON'T CARE PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 38 UNDEFINED Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 29: Page Mode READ tRC A[19:4] VIH VALID ADDRESS VIL VIH A[3:0] ADV# VALID ADDRESS VIL VALID ADDRESS VALID ADDRESS tPC tAA VIH VALID ADDRESS VIL tCEM tCO VIH tHZ CE# VIL LB#/UB# tBA VIH tBHZ VIL tOHZ tOE VIH OE# VIL VIH WE# tOLZ tBLZ VIL VOH DQ[15:0] VOL tAPA tOH tLZ VALID OUTPUT High-Z tCEW VOL VALID OUTPUT VALID OUTPUT tHZ VOH WAIT VALID OUTPUT High-Z High-Z DON'T CARE PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 39 UNDEFINED Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 30: Single-Access Burst READ Operation tCLK tKP tKP tKHKL VIH CLK A[19:0] VIL VIH VIL tHD tSP VALID ADDRESS tSP tHD VIH ADV# VIL tHD tCEM CE# VIH tCSP tHZ tABA VIL tOHZ tBOE VIH OE# VIL tSP WE# tHD tOLZ VIH VIL VIH LB#/UB# VIL tCEW VOH WAIT tKHTL High-Z High-Z VOL DQ[15:0] tKOH tACLK VOH High-Z VOL VALID OUTPUT READ Burst Identified (WE# = HIGH) Notes: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN DON'T CARE UNDEFINED 1. Non-default BCR settings for single-access burst READ operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 40 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 31: 4-Word Burst READ Operation tKHKL CLK A[19:0] tKP VIL VIH tSP tHD VALID ADDRESS VIL tSP ADV# tKP tCLK VIH tHD VIH VIL tCEM CE# VIH tCBPH tHD tABA tCSP VIL tHZ tBOE OE# VIH VIL tOHZ tSP WE# LB#/UB# tOLZ tHD VIH VIL VIH VIL tKHTL tCEW WAIT VOH VOL High-Z High-Z tKOH tACLK DQ[15:0] VOH High-Z VOL VALID OUTPUT READ Burst Identified (WE# = HIGH) Note: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN VALID OUTPUT VALID OUTPUT VALID OUTPUT DON'T CARE UNDEFINED Non-default BCR settings for 4-word burst READ operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 32: READ Burst Suspend tCLK VIH CLK VIL tSP VIH A[19:0] VIL tHD VALID ADDRESS VALID ADDRESS tSP tHD VIH ADV# VIL tCBPH tCEM VIH tHZ tCSP CE# VIL tOHZ OE# tOHZ VIH VIL VIH tSP tHD WE# VIL VIH LB#/UB# VIL tBOE VOH tOLZ WAIT VOL High-Z VOH DQ[15:0] VOL High-Z tKOH tOLZ VALID OUTPUT High-Z VALID OUTPUT VALID OUTPUT VALID OUTPUT tBOE VALID OUTPUT VALID OUTPUT tACLK DON'T CARE Note: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN UNDEFINED Non-default BCR settings for READ burst suspend: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 42 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 33: CLK Continuous Burst READ Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition VIH VIL tCLK A[19:0] VIH VIL ADV# VIH VIL LB#/UB# VIH VIL CE# VIH Note 3 VIL OE# VIH VIL WE# VIH VIL tKHTL tKHTL WAIT VOH Note 2 VOL DQ[15:0] VOH VALID OUTPUT VOL VALID OUTPUT VALID OUTPUT tACLK VALID OUTPUT tKOH DON'T CARE Notes: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 1. Non-default BCR settings for continuous burst READ showing an output delay, BCR[8] = 0 for end-of-row condition: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. WAIT will be asserted a maximum of (2 x LC) cycles (BCR[8] = 0; WAIT asserted during delay). LC = latency code (BCR[13:11]). 3. CE# must not remain LOW longer than tCEM. 43 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 34: CE#-Controlled Asynchronous WRITE tWC A[19:0] VIH VALID ADDRESS VIL tAW tWR tAS VIH ADV# CE# VIL tCW VIH tCPH VIL tBW VIH LB#/UB# OE# VIL VIH VIL tWPH tWP VIH WE# VIL tDW DQ[15:0] IN VIH DQ[15:0] OUT VOH High-Z VIL VALID INPUT tWHZ tLZ WAIT tDH VOL tCEW VOH VOL tHZ High-Z High-Z DON'T CARE PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 44 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 35: LB#/UB#-Controlled Asynchronous WRITE tWC A[19:0] VIH VALID ADDRESS VIL tAW tAS ADV# tWR VIH VIL tCW CE# LB#/UB# OE# VIH VIL tBW VIH VIL VIH VIL tWP tWPH VIH WE# VIL tDW DQ[15:0] IN High-Z VIL VALID INPUT tWHZ tLZ DQ[15:0] OUT VOH VOL tCEW WAIT tDH VIH tHZ VOH VOL High-Z High-Z DON'T CARE PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 45 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 36: WE#-Controlled Asynchronous WRITE tWC VIH A[19:0] VALID ADDRESS VIL tAW tWR VIH ADV# VIL tCW VIH CE# VIL tBW VIH LB#/UB# VIL VIH OE# VIL tAS tWP tWPH VIH WE# VIL tDW DQ[15:0] IN High-Z VIL VALID INPUT VOH VOL tCEW tHZ VOH WAIT tOW tWHZ tLZ DQ[15:0] OUT tDH VIH VOL High-Z High-Z DON'T CARE PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 46 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 37: Asynchronous WRITE Using ADV# A[19:0] VIH VALID ADDRESS VIL tAVS tVS tVPH ADV# tAVH tVP tAS VIH VIL tAS tAW tCW VIH CE# VIL tBW VIH LB#/UB# OE# VIL VIH VIL tWPH tWP WE# VIH VIL tDW DQ[15:0] VIH IN VIL DQ[15:0] VOH OUT VOL High-Z VALID INPUT tWHZ tLZ tCEW WAIT tOW tHZ VOH VOL tDH High-Z High-Z DON'T CARE PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 47 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 38: Burst WRITE Operation tCLK CLK tKP tKP tKHKL VIH VIL tSP A[19:0] VIL VALID ADDRESS tSP ADV# tHD VIH tHD VIH VIL tSP tHD LB#/UB# VIH VIL tCEM CE# VIH tCSP tHD tCBPH VIL OE# VIH VIL tSP WE# tHD VIH VIL VOH WAIT VOL tCEW tKHTL tHZ High-Z High-Z tSP tHD VIH DQ[15:0] D[0] VIL WRITE Burst Identified (WE# = LOW) Note: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN D[1] D[2] D[3] DON'T CARE Non-default BCR settings for burst WRITE operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted. 48 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 39: CLK Continuous Burst WRITE Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition VIH VIL tCLK A[19:0] VIH VIL ADV# VIH VIL LB#/UB# VIH VIL CE# VIH Note 4 VIL VIH WE# VIL VIH OE# VIL tKHTL tKHTL WAIT VOH Note 3 VOL tSP tHD VIH DQ[15:0] VALID INPUT VIL VALID INPUT End of row (A[6:0] = 7Fh) Notes: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN VALID INPUT Start of row (A[6:0] = 00h) (NOTE 4) VALID INPUT DON'T CARE 1. Non-default BCR settings for continuous burst WRITE, BCR[8] = 0; WAIT active LOW; WAIT asserted during delay. Do not cross row boundaries with fixed latency. 2. CE# must not remain LOW longer than tCEM. 3. WAIT asserts for anywhere from LC to 2LC cycles. LC = latency code (BCR[13:11]). 4. Taking CE# HIGH or ADV# LOW on the start-of-row cycle will abort the burst and not write the start-of-row data. Devices from different CellularRAM vendors can assert WAIT so that the start-of-row data is input just before (as shown), or just after WAIT asserts. This difference in behavior will not be noticed by controllers that monitor WAIT, or that use WAIT to abort on the start-of-row input cycle. 49 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 40: Burst WRITE Followed by Burst READ tCLK CLK VIH VIL A[19:0] VIH VIL ADV# VIH VIL tSP tHD LB#/UB# tSP VALID ADDRESS tSP tHD tSP tHD tSP tHD VIH VIL tCSP CE# OE# tHD VIH VIL tCBPH2 tABA tCSP VIH VIL tOHZ tSP tHD VIH WE# VIL WAIT tHD VALID ADDRESS tSP tHD VOH VOL DQ[15:0] VIH IN/OUT VIL tBOE High-Z tSP tHD tACLK VOH High-Z D[0] D[1] D[2] D[3] VOL High-Z High-Z tKOH VALID OUTPUT VALID OUTPUT VALID OUTPUT DON'T CARE Notes: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN VALID OUTPUT UNDEFINED 1. Non-default BCR settings for burst WRITE followed by burst READ: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Note that the CellularRAM Workgroup 1.0 specification requires CE# to be clocked HIGH to terminate the burst. 3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. 50 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 41: Asynchronous WRITE Followed by Burst READ tCLK VIH CLK VIL A[19:0] VIH VIL VIH ADV# VIL VIH LB#/UB# VIL CE# tWC VALID ADDRESS tAVS tAVH tVP tCVS tVS tBW tHD tSP tHD tCBPH2 tCW tHD tWR tSP tABA tCSP tOHZ tAS OE# VIL DQ[15:0] VIH IN/OUT VIL tAW tSP VALID ADDRESS tVPH VIH VIL VIH VIH WE# VIL VOH WAIT VOL tCKA tWC VALID ADDRESS tAS tWC tWPH tWP tSP tHD tCEW tWHZ High-Z DATA tDH Notes: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN DATA tDW VOH VOL tBOE High-Z tKOH tACLK High-Z VALID OUTPUT VALID OUTPUT VALID OUTPUT DON'T CARE VALID OUTPUT UNDEFINED 1. Non-default BCR settings for asynchronous WRITE followed by burst READ: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Note that the CellularRAM Workgroup 1.0 specification requires CE# to be clocked HIGH to terminate the burst. 3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. 51 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 42: Asynchronous WRITE Followed by Burst READ - ADV# LOW tCLK VIH CLK VIL A[19:0] VIH VIL VIH ADV# VIL VIH LB#/UB# VIL CE# tWC VALID ADDRESS tAVS tAVH tVP tCVS tVS tBW tHD tSP tHD tCBPH2 tCW tHD tWR tSP tABA tCSP tOHZ tAS OE# VIL DQ[15:0] VIH IN/OUT VIL tAW tSP VALID ADDRESS tVPH VIH VIL VIH VIH WE# VIL VOH WAIT VOL tCKA tWC VALID ADDRESS tAS tWC tWPH tWP tSP tHD tCEW tWHZ High-Z DATA tDH Notes: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN DATA tDW VOH VOL tBOE High-Z tKOH tACLK High-Z VALID OUTPUT VALID OUTPUT VALID OUTPUT DON'T CARE VALID OUTPUT UNDEFINED 1. Non-default BCR settings for asynchronous WRITE followed by burst READ: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of these conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Note that the CellularRAM Workgroup 1.0 specification requires CE# to be clocked HIGH to terminate the burst. 3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. 52 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 43: Burst READ Followed by Asynchronous WRITE (WE#-Controlled) tCLK VIH CLK A[19:0] VIL tSP VIH tWC tHD VALID ADDRESS VALID ADDRESS VIL tSP tAW tHD tWR VIH ADV# CE# VIL tHD tCSP VIH tHZ tABA tCW tCBPH1 VIL tBOE tOHZ VIH OE# tAS VIL tSP WE# tHD tOLZ tWP tWPH VIH VIL tSP tHD tBW VIH LB#/UB# VIL tCEW tKHTL tCEW tHZ VOH WAIT High-Z High-Z VOL DQ[15:0] tKOH tACLK VOH High-Z VOL PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN tDH VALID INPUT VALID OUTPUT READ Burst Identified (WE# = HIGH) Notes: tDW DON'T CARE UNDEFINED 1. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Note that CellularRAM Workgroup specification 1.0 requires CE# to be clocked HIGH to terminate the burst. 53 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 44: Burst READ Followed by Asynchronous WRITE Using ADV# CLK A[19:0] tCLK VIH VIL VIH tSP VIL tSP VIH ADV# CE# tHD VALID ADDRESS VALID ADDRESS tVPH tHD WE# tAVH tVS tVP VIL tAW tHD tCSP VIH tAS tHZ tABA tCW tCBPH1 VIL tOHZ tBOE VIH OE# tAVS VIL tSP VIH VIL VIH tSP tHD tAS tOLZ tHD tWP tWPH tBW LB#/UB# VIL tCEW VOH WAIT VOL tKHTL tCEW High-Z tACLK DQ[15:0] VOH High-Z VOL tKOH VALID OUTPUT READ Burst Identified (WE# = HIGH) Notes: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN tHZ High-Z tDW tDH VALID INPUT DON'T CARE UNDEFINED 1. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Note that CellularRAM Workgroup specification 1.0 requires CE# to be clocked HIGH to terminate the burst. 54 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 45: A[19:0] Asynchronous WRITE Followed by Asynchronous READ - ADV# LOW VIH VIL VALID ADDRESS VALID ADDRESS tAW VALID ADDRESS tAA tWR VIH ADV# LB#/UB# VIL tBLZ tBW VIH VIL tCW CE# tBHZ tCO tCPH1 tHZ VIH VIL tLZ OE# VIL tWC tWPH tWP WE# WAIT tOHZ tOE VIH VIH VIL tHZ VOH tHZ VOL DQ[15:0] VIH IN/OUT VIL tOLZ High-Z DATA tDH Notes: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN DATA High-Z VOH VALID OUTPUT VOL tDW DON'T CARE UNDEFINED 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the appropriate internal refresh operation. Otherwise, tCPH is only required after CE#-controlled WRITEs. 55 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 46: Asynchronous WRITE Followed by Asynchronous READ A[19:0] VIH VIL ADV# LB#/UB# CE# VIH VALID ADDRESS tAVS tVPH VALID ADDRESS tAVH tAW VALID ADDRESS tAA tWR tAVS tVP tVS tVP VIL VIH VIL tCW VIH tCPH1 tCVS WE# WAIT tHZ tCO VIL tLZ tAS OE# tBHZ tAADV tBLZ tBW tCVS tAVH tOHZ VIH VIL VIH tAS tWP tWC tWPH tOLZ VIL VOH VOL DQ[15:0] VIH IN/OUT VIL Notes: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN tOE High-Z DATA tDH DATA tDW VOH VOL VALID OUTPUT High-Z DON'T CARE UNDEFINED 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the appropriate internal refresh operation. Otherwise, tCPH is only required after CE#-controlled WRITEs. 56 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Package Dimensions Package Dimensions Figure 47: 54-Ball VFBGA 0.70 0.05 SEATING PLANE A 0.10 A SOLDER BALL MATERIAL: 96.5% Sn, 3% Ag, 0.5% Cu 54X O0.37 SUBSTRATE MATERIAL: PLASTIC LAMINATE DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. PRE-REFLOW BALL DIAMETER IS 0.35 ON A 0.30 SMD BALL PAD. 3.75 0.75 TYP MOLD COMPOUND: EPOXY NOVOLAC BALL A1 ID BALL A1 ID 4.00 0.05 BALL A6 BALL A1 8.00 0.10 6.00 3.00 0.75 TYP 1.875 3.00 0.05 1.00 MAX 6.00 0.10 Notes: 1. All dimensions in millimeters; MAX/MIN or typical, as noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. The MT45W1MW16BDGB uses "green" packaging. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. CellularRAM is a trademark of Micron Technology, Inc. inside the U.S. and a trademark of Qimonda AG outside the U.S. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 57 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Revision History Revision History Rev. H, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .04/08 * Updated the MAX I/O voltage from 3.3V to 3.6V. * Updated Figure 15 on page 21 and Figure 16 on page 22 to include the 0ns MIN spec. * Changed tPU in Table 16 on page 36 from a MIN to a MAX value. * Updated Figure 42 on page 52 to include the correct drawing. Rev. G, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/07 * Table 15, "Burst WRITE Cycle Timing Requirements," on page 36: Corrected tCEM parameter label from minimum to maximum. Rev. F, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/06 * Updated Rev. letter to F Rev. F, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .06/06 * Changed the title of Figure 10 to "Wired-OR Wait Configuration" * Updated wording in the third paragraph of "WAIT Operation" on page 15 to the following: "During a Burst cycle, CE# must remain asserted until the first data is valid. Bringing CE# HIGH during this initial latency may cause data corruption." * Changed WAIT from "tCW" to "tCEW" in Figure 14 * Changed Min/Max columns from "-701" and "-708," to "104 MHz" and "80 MHz" in Table 5 * Changed "Output enable to Low-Z output" MIN value from 5 to 3 in Table 12 * Changed Min/Max columns from "-70" to "70ns" in Table 12 * Removed "CLK to DQ High-Z Output" and "CLK to Low-Z Output" rows from Table 13 * Changed "Output enable to Low-Z output" MIN value from 5 to 3 in Table 13 * Changed Min/Max columns from "-701" and "-708," to "104 MHz" and "80 MHz" in Table 13 * Changed Min/Max columns from "-70" to "70ns" in Table 14 * Changed Min/Max columns from "-701" and "-708," to "104 MHz" and "80 MHz" in Table 15 * Changed Min/Max columns from "-70" to "70ns" in Table 16 * Removed tWHZ lines and arrows in Figure 42 * Removed tWHZ lines and arrows in Figure 45 * Removed tWHZ lines and arrows in Figure 46 Rev. E, Production. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .02/06 * Changed document status to Production. Rev. D, Preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .01/06 * Changed VIH and VIL to VOH and VOL in Figure 27, 28, 29, 34, 35, 36, 37 * Updated Continuous burst READ and Standby specifications in "Features" section * Updated document designator to Preliminary * Deleted Tables 17-43. Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12/05 * Deleted "4-Word Burst READ Operation (with LB#/UB#)" timing diagram * Changed file name to new standard: p23z16_b_cr1-0 to 16mb_burst_cr1_0_p23z Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10/05 * Fixed exceptions to template (primarily minor formatting on page 1) PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 58 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Revision History * * * * Page 1, Figure 1: changed E3 ball color to white Page 1: changed multiple "-" to "-" for negative numbers (per style) Eliminated holdover references to dual parts (pgs. 10 and 30) Updated to state that "CLK must be held static LOW or HIGH" during async READ and WRITE (pgs. 7, 10, 11, 14) * Updated note 4 in Table 8 to eliminate reference to dual part (was "BCR[5:4] = 00b") Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .08/05 * Initial release with "Advance" designation. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 59 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.