1
LTC1149
LTC1149-3.3/LTC1149-5
S
FEATURE
D
U
ESCRIPTIO
■
Operation to 48V Input Voltage
■
Ultrahigh Efficiency: Up to 95%
■
Current Mode Operation for Excellent Line and
Load Transient Response
■
High Efficiency Maintained over Wide Current Range
■
Logic-Controlled Micropower Shutdown
■
Short-Circuit Protection
■
Very Low Dropout Operation: 100% Duty Cycle
■
Synchronous FET Switching for High Efficiency
■
Adaptive Nonoverlap Gate Drives
■
Available in 16-Pin Narrow SO Package
The LTC
®
1149 series is a family of synchronous step-
down switching regulator controllers featuring automatic
Burst Mode
TM
operation to maintain high efficiencies at
low output currents. These devices drive external comple-
mentary power MOSFETs at switching frequencies up
to 250kHz using a constant off-time current-mode archi-
tecture.
Special onboard regulation and level-shift circuitry allow
operation at input voltages from dropout to 48V (60V
absolute max). The constant off-time architecture main-
tains constant ripple current in the inductor, easing the
design of wide input range converters. Current mode
operation provides excellent line and load transient
response. The operating current level is user-program-
mable via an external current sense resistor.
The LTC1149 series incorporates automatic power saving
Burst Mode
operation when load currents drop below the
level required for continuous operation. Standby power is
reduced to only about 8mW at V
IN
= 12V. In shutdown,
both MOSFETs are turned off.
High Efficiency Synchronous
Step-Down Switching Regulators
Figure 1. High Efficiency Step-Down Regulator
U
A
O
PPLICATITYPICAL
0.068µF
VIN
CAP
PDRIVE
LTC1149-5
SHDN1
ITH
CT
SGND
PGATE
VCC
VCC
SHDN2 SENSE–
SENSE+
P, RGNDS
NGATE
1000pF
N-CHANNEL
IRFR024
0.047µF
1N4148
1N4148
VIN
P-CHANNEL
IRFR9024
D1
1N5819 L*
62µH RSENSE**
0.05ΩVOUT
5V/2A
COUT
220µF
CIN
100µF
100V
3.3µF
0V = NORMAL
>2V = SHUTDOWN
3300µF
CT
470pF
1k
1149 F01
*COILTRONICS CTX62-2-MP
**KRL SL-1-C1-0R050J
+
+
+
LOAD CURRENT (A)
0.02
60
EFFICIENCY (%)
70
80
100
0.2 2
1149 TA01
90
VIN = 12V
VIN = 24V
FIGURE 1 CIRCUIT
LTC1149-5 Efficiency
■
Notebook and Palmtop Computers
■
Portable Instruments
■
Battery-Operated Digital Devices
■
Industrial Power Distribution
■
Avionics Systems
■
Telecom Power Supplies
U
S
A
O
PPLICATI
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode
is a trademark of Linear Technology Corporation.
2
LTC1149
LTC1149-3.3/LTC1149-5
A
U
G
W
A
W
U
W
ARBSOLUTEXI T
I
S
WU
U
PACKAGE/ORDER I FOR ATIO
Input Supply Voltage (Pin 2)...................... –15V to 60V
V
CC
Output Current (Pin 3) .................................. 50mA
V
CC
Input Voltage (Pin 5)........................................ 16V
Continuous Output Current (Pins 4, 13) .............. 50mA
Sense Voltages (Pins 8, 9)
V
IN
≥ 12.7V .......................................... 13V to –0.3V
V
IN
< 12.7V............................. (V
CC
+ 0.3V) to –0.3V
Shutdown Voltages (Pins 10, 15) ............................. 7V
Operating Temperature Range .................... 0°C to 70°C
Extended Commercial
Temperature Range ............................... –40°C to 85°C
Junction Temperature (Note 1)............................ 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ELECTRICAL C CHARA TERISTICS
TA = 25°C, VIN = 12V, V10 = 0V (Note 2), unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
10
Feedback Voltage (LTC1149 Only) V
IN
= 9V ●1.21 1.25 1.29 V
I
10
Feedback Current (LTC1149 Only) ●0.2 1 µA
V
OUT
Regulated Output Voltage V
IN
= 9V
LTC1149-3.3 I
LOAD
= 700mA ●3.23 3.33 3.43 V
LTC1149-5 I
LOAD
= 700mA ●4.9 5.05 5.2 V
∆V
OUT
Output Voltage Line Regulation V
IN
= 9V to 48V, I
LOAD
= 50mA –40 0 40 mV
Output Voltage Load Regulation
LTC1149-3.3 5mA < I
LOAD
< 2A ●40 65 mV
LTC1149-5 5mA < I
LOAD
< 2A ●60 100 mV
Burst Mode Output Ripple I
LOAD
= 0A 50 mV
P-P
I
2
Input DC Supply Current (Note 3)
Normal Mode V
IN
= 12V 2.0 2.8 mA
V
IN
= 48V 2.2 3.0 mA
Burst Mode V
IN
= 12V 0.6 0.9 mA
V
IN
= 48V 0.8 1.1 mA
Shutdown V
IN
= 12V, V
15
= 2V 135 170 µA
V
IN
= 48V, V
15
= 2V 300 390 µA
V
CC
Internal Regulator Voltage V
IN
= 12V to 48V ●9.75 10.25 11 V
(Sets MOSFET Gate Drive Levels) I
3
= 20mA
V
2
– V
3
V
CC
Dropout Voltage V
IN
= 5V, I
3
= 10mA 200 250 mV
V
IN
– V
1
P-Gate to Source Voltage (Off) V
IN
= 12V ●–0.2 0 V
V
IN
= 48V ●–0.2 0 V
LTC1149CN
LTC1149CN-3.3
LTC1149CN-5
LTC1149CS
LTC1149CS-3.3
LTC1149CS-5
ORDER PART
NUMBER
Consult factory for Industrial and Military grade parts.
1
2
3
4
5
6
7
8
TOP VIEW
S PACKAGE
16-LEAD PLASTIC SO
N PACKAGE
16-LEAD PDIP
16
15
14
13
12
11
10
9
PGATE
VIN
VCC
PDRIVE
VCC
CT
ITH
SENSE–
CAP
SHDN2
RGND
NGATE
PGND
SGND
SENSE+
*FIXED OUTPUT VERSIONS
VFB /
SHDN1*
T
JMAX
= 125°C,
θ
JA
= 70°C/W (N)
T
JMAX
= 125°C,
θ
JA
= 110°C/ W (S)
3
LTC1149
LTC1149-3.3/LTC1149-5
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
9
– V
8
Current Sense Threshold Voltage
LTC1149 V
8
= 5V, V
10
= 1.32V (Forced) 25 mV
V
8
= V
OUT
– 100mV ●130 150 170 mV
LTC1149-3.3 V
8
= 3.5V (Forced) 25 mV
V
8
= V
OUT
– 100mV ●130 150 170 mV
LTC1149-5 V
8
= 5.3V (Forced) 25 mV
V
8
= V
OUT
– 100mV ●130 150 170 mV
V
10
Shutdown 1 Threshold
LTC1149-3.3, LTC1149-5 0.5 0.8 2 V
V
15
Shutdown 2 Threshold 0.8 1.4 2 V
I
15
Shutdown 2 Input Current V
15
= 5V 18 25 µA
I
6
C
T
Pin Discharge Current V
OUT
In Regulation, V
SENSE–
= V
OUT
50 70 90 µA
V
OUT
= 0V 2 10 µA
t
OFF
Off-Time (Note 4) C
T
= 390pF, I
LOAD
= 700mA 4 5 6 µs
t
r
, t
f
Driver Output Transition Times C
L
= 3000pF (Pins 4, 13), V
IN
= 6V 100 200 ns
ELECTRICAL C CHARA TERISTICS
TA = 25°C, VIN = 12V, V10 = 0V (Note 2), unless otherwise noted.
–40°C ≤ TA ≤ 85°C (Note 5), unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
10
Feedback Voltage LTC1149 Only 1.2 1.25 1.3 V
V
OUT
Regulated Output Voltage V
IN
= 9V
LTC1149-3.3 I
LOAD
= 700mA 3.17 3.33 3.43 V
LTC1149-5 I
LOAD
= 700mA 4.85 5.05 5.2 V
I
2
Input DC Supply Current (Note 3)
Normal Mode V
IN
= 12V 2.0 3.2 mA
V
IN
= 48V 2.2 3.5 mA
Burst Mode V
IN
= 12V 0.6 1.05 mA
V
IN
= 48V 0.8 1.30 mA
Shutdown V
IN
= 12V, V
15
= 2V 135 230 µA
V
IN
= 48V, V
15
= 2V 300 520 µA
V
CC
Internal Regulator Voltage V
IN
= 12V to 48V 9.75 10.25 11 V
(Sets MOSFET Gate Drive Levels) I
3
= 20mA
V
9
– V
8
Current Sense Threshold Voltage Low Threshold (Forced) 25 mV
High Threshold (Forced) 125 150 175 mV
V
15
Shutdown 2 Threshold 0.8 1.4 2 V
t
OFF
Off-Time (Note 4) C
T
= 390pF, I
LOAD
= 700mA, V
IN
= 10V 3.8 5 6 µs
The ● denotes specifications which apply over the full operating
temperature range.
Note 1: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formulas:
LTC1149CN, LTC1149CN-3.3, LTC1149CN-5: T
J
= T
A
+ (P
D
)(70°C/W)
LTC1149CS, LTC1149CS-3.3, LTC1149CS-5: T
J
= T
A
+ (P
D
)(110°C/W)
Note 2: Pin 10 is a shutdown pin on the LTC1149-3.3 and LTC1149-5
fixed output voltage versions and must be at ground potential for testing.
Note 3: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. The allowable operating frequency
may be limited by power dissipation at high input voltages. See Typical
Performance Characteristics and Applications Information.
Note 4: In applications where R
SENSE
is placed at ground potential, the off-
time increases approximately 40%.
Note 5: The LTC1149, LTC1149-3.3, and LTC1149-5 are not tested and
not quality assurance sampled at –40°C and 85°C. These specifications
are guaranteed by design and/or correlation.
4
LTC1149
LTC1149-3.3/LTC1149-5
CCHARA TERISTICS
UW
AT
Y
P
I
CALPER
F
O
RC
E
Load Regulation
Efficiency vs Input Voltage Line Regulation
Operating Frequency
vs (VIN – VOUT)
Gate Charge Supply Current Current Sense Threshold Voltage
DC Supply Current Supply Current in Shutdown
Off-Time vs VOUT
LOAD CURRENT (A)
0
–100
∆V
OUT
(mV)
–80
–60
–40
–20
0
20
0.5 1.0 1.5 2.0
1149 G03
2.5
FIGURE 1 CIRCUIT
V
IN
= 24V
OPERATING FREQUENCY (kHz)
50
0
GATE CHARGE CURRENT (mA)
5
10
15
20
25
30
100 150 200 250
1149 G07
Q
P
+ Q
N
= 100nC
Q
P
+ Q
N
= 50nC
OUTPUT VOLTAGE (V)
1
OFF-TIME (µs)
40
50
60
5
1149 G08
30
20
0234
10
80
70
0
LTC1149-5
LTC1149-3.3
TEMPERATURE (°C)
20
SENSE VOLTAGE (mV)
80
100
120
100
1149 G09
60
40
040 60 80
20
160
140
0
MAXIMUM
THRESHOLD
MINIMUM
THRESHOLD
(V
IN
– V
OUT
) VOLTAGE (V)
0
NORMALIZED FREQUENCY
1.0
1.5
20
1149 G06
0.5
0510 15 25
2.0
V
OUT
= 5V
T = 70°C
T = 0°C
T = 25°C
INPUT VOLTAGE (V)
0
SUPPLY CURRENT (µA)
200
300
40
1149 G05
100
010 20 30 50
400
V
SD2
= 2V
INPUT VOLTAGE (V)
0
0
SUPPLY CURRENT (mA)
0.5
1.0
1.5
2.0
2.5
3.0
10 20 30 40
1149 G04
50
ACTIVE MODE
SLEEP MODE
INPUT VOLTAGE (V)
0
–60
∆V
OUT
(mV)
–40
–20
0
20
40
60
10 20 30 40
1149 G02
50
FIGURE 1 CIRCUIT
I
LOAD
= 1A
INPUT VOLTAGE (V)
0
EFFICIENCY (%)
90
95
40
1149 G01
85
80 10 20 30 50
100 FIGURE 1 CIRCUIT
ILOAD = 1A
5
LTC1149
LTC1149-3.3/LTC1149-5
PI FU CTIO S
U
UU
PGATE (Pin 1): Level-Shifted Gate Drive Signal for Top
P-Channel MOSFET. The voltage swing at Pin 1 is from V
IN
to V
IN
– V
CC
.
V
IN
(Pin 2): Main Supply Input Pin.
V
CC
(Pin 3): Output Pin of Low Dropout 10V Regulator.
Pin
3 is not protected against DC short circuits.
PDRIVE (Pin 4): High Current Gate Drive for Top
P-Channel MOSFET. The voltage swing at Pin 4 is from V
CC
to ground.
V
CC
(Pin 5): Regulated 10V Input for Driver and Control
Supplies. Must be closely decoupled to power ground.
C
T
(Pin 6): External capacitor C
T
from Pin 6 to ground sets
the operating frequency. (The frequency is also dependent
on the ratio V
OUT
/V
IN
.)
I
TH
(Pin 7): Gain Amplifier Decoupling Point. The current
comparator threshold increases with the Pin 7 voltage.
SENSE
–
(Pin 8): Connects to internal resistive divider
which sets the output voltage in LTC1149-3.3 and
LTC1149-5 versions. Pin 8 is also the (–) input for the
current comparator.
SENSE
+
(Pin 9): The (+) Input for the Current Comparator.
A built-in offset between Pins 8 and 9 in conjunction with
R
SENSE
sets the current trip threshold.
SHDN1/V
FB
(Pin 10): In fixed output voltage versions, Pin
10 serves as a shutdown pin for the control circuitry only
(V
CC
is not affected). Taking Pin 10 of the LTC1149-3.3 or
LTC1149-5 high holds both MOSFETs off. Must be at
ground potential for normal operation.
For the LTC1149 adjustable version, Pin 10 serves as the
feedback pin from an external resistive divider used to set
the output voltage.
SGND (Pin 11): Small-Signal Ground. Must be routed
separately from other grounds to the (–) terminal of C
OUT
.
PGND (Pin 12): Driver Power Ground. Connects to source
of N-channel MOSFET and the (–) terminal of C
IN
.
NGATE (Pin 13): High Current Drive for Bottom
N-channel MOSFET. The voltage swing at Pin 13 is from
ground to V
CC
.
RGND (Pin 14): Low Dropout Regulator Ground. Con-
nects to power ground.
SHDN2 (Pin 15): Master Shutdown Pin. Taking Pin 15
high shuts down V
CC
and all control circuitry; requires a
logic signal with t
r
, t
f
< 1µs.
CAP (Pin 16): Charge Compensation Pin. A capacitor from
Pin 16 to V
CC
provides the charge required by the P-drive
level-shift capacitor during supply transitions.
The Pin 16
capacitor must be larger than the Pin 4 capacitor
.
OPERATIO
U
(Refer to Functional Diagram)
The LTC1149 series uses a current mode, constant off-
time architecture to synchronously switch an external pair
of complementary power MOSFETs. Operating frequency
is set by an external capacitor at the timing capacitor,
Pin 6.
The output voltage is sensed either by an internal voltage
divider connected to SENSE
–
, Pin 8 (LTC1149-3.3 and
LTC1149-5) or an external divider returned to V
FB
Pin 10
(LTC1149). A voltage comparator V, and a gain block G,
compare the divided output voltage with a reference
voltage of 1.25V. To optimize efficiency, the LTC1149
series automatically switches between two modes of
operation, burst and continuous. The voltage comparator
is the primary control element for Burst Mode operation,
while the gain block controls the output voltage in continu-
ous mode.
A low dropout 10V regulator provides the operating volt-
age V
CC
for the MOSFET drivers and control circuitry. The
driver outputs at Pins 4 and 13 are referenced to ground,
which fulfills the N-channel MOSFET gate drive require-
ment. The P-channel gate drive at Pin 1 must be refer-
enced to the main supply input V
IN
, which is accomplished
by level-shifting the Pin 4 signal via an internal 500k
resistor and external capacitor.
During the switch “ON” cycle in continuous mode, current
comparator C monitors the voltage between Pins 8 and 9
connected across an external shunt in series with the
inductor. When the voltage across the shunt reaches its
threshold value, the PGATE output is switched to V
IN
,
turning off the P-channel MOSFET. The timing capacitor
connected to Pin 6 is now allowed to discharge at a rate
determined by the off-time controller. The discharge
6
LTC1149
LTC1149-3.3/LTC1149-5
Pin 10 connection shown for LTC1149-3.3 and LTC1149-5; changes create LTC1149.
FU CTIO AL DIAGRA
UUW
OPERATIO
U
(Refer to Functional Diagram)
current is made proportional to the output voltage (mea-
sured by Pin 8) to model the inductor current, which
decays at a rate which is also proportional to the output
voltage. While the timing capacitor is discharging, the
NGATE output is high, turning on the N-channel MOSFET.
When the voltage on the timing capacitor has discharged
past V
TH1
, comparator T trips, setting the flip-flop. This
causes the NGATE output to go low (turning off the
N-channel MOSFET) and the PGATE output to also go low
(turning the P-channel MOSFET back on). The cycle then
repeats.
As the load current increases, the output voltage
decreases slightly. This causes the output of the gain
stage to increase the current comparator threshold, thus
tracking the load current.
The sequence of events for Burst Mode operation is very
similar to continuous operation with the cycle interrupted
by the voltage comparator. When the output voltage is at
or above the desired regulated value, the P-channel MOSFET
is held off by comparator V and the timing capacitor
continues to discharge below V
TH1
. When the timing
capacitor discharges past V
TH2
, voltage comparator S
trips, causing the internal SLEEP line to go low and the
N-channel MOSFET to turn off.
The circuit now enters sleep mode with both power
MOSFETs turned off. In sleep mode, much of the circuitry
is turned off, dropping the supply current from several
milliamperes (with the MOSFETs switching) to 600µA.
When the output capacitor has discharged by the amount
of hysteresis in comparator V, the P-channel MOSFET is
again turned on and this process repeats. To avoid the
operation of the current loop interfering with Burst Mode
operation, a built-in offset is incorporated in the gain
stage. This prevents the current comparator threshold
from increasing until the output voltage has dropped
below a minimum threshold.
To prevent both the external MOSFETs from ever being
turned on at the same time, feedback is incorporated to
sense the state of the driver output pins. Before the N-gate
output can go high, the P-drive output must also be high.
Likewise, the P-drive output is prevented from going low
when the N-gate output is high.
Using constant off-time architecture, the operating fre-
quency is a function of the input voltage. To minimize the
frequency variation as dropout is approached, the off-
time controller increases the discharge current as V
IN
drops below V
OUT
+ 1.5V. In dropout the P-channel
MOSFET is turned on continuously.
–
+
NGATE
13
PDRIVE
4
5V
CC
500k
PGATE
1
12 PGND
16
500k
CAP
3
V
CC
15
SHDN2
2
V
IN
14 RGND
–
+
–
+
9SENSE
+
V
R
S
Q
V
TH1
–
+
25mV TO 150mV
13k G
REFERENCE
1.25V
11
SGND
7
I
TH
C
V
OS
8SENSE
–
1149 FD
10
SHDN1
(V
FB
)
–
+
T
VTH2
S
SLEEP
6
C
T
OFF-TIME
CONTROL
V
IN
SENSE
–
LOW
DROPOUT
10V
REGULATOR
100k
7
LTC1149
LTC1149-3.3/LTC1149-5
TEST CIRCUIT
APPLICATIO S I FOR ATIO
WUU U
Typical Application Circuit
The basic LTC1149 series application circuit is shown in
Figure 1. External component selection is driven by the
input voltage and output load requirement, and begins
with the selection of R
SENSE
. Once R
SENSE
is known, C
T
and L can be chosen. Next, the power MOSFETs and D1
are selected. Finally, C
IN
and C
OUT
are selected and the
loop is compensated. The circuit shown in Figure 1 can be
configured for operation up to an input voltage of 48V. If
the application does not require greater than 15V opera-
tion, then the LTC1148 should be used.
R
SENSE
Selection for Output Current
R
SENSE
is chosen based on the required output current.
The LTC1149 series current comparator has a threshold
range which extends from a minimum of 25mV/R
SENSE
to
a maximum of 150mV/R
SENSE
. The current comparator
threshold sets the peak of the inductor ripple current,
yielding a maximum output current I
MAX
equal to the peak
value less half the peak-to-peak ripple current.
For proper
Burst Mode
operation, I
RIPPLE(P-P)
must be less than or
equal to the minimum current comparator threshold.
Since efficiency generally increases with ripple current,
the maximum allowable ripple current is assumed, i.e.,
I
RIPPLE(P-P)
= 25mV/R
SENSE
(see C
T
and L Selection for
Operating Frequency). Solving for R
SENSE
and allowing a
margin for variations in the LTC1149 series and external
component values yields:
R
SENSE
= 100mV
I
MAX
A graph for selecting R
SENSE
versus maximum output
current is given in Figure 2. The LTC1149 series works well
with values of R
SENSE
from 0.02Ω to 0.2Ω.
The load current below which Burst Mode
operation
commences, I
BURST
, and the peak short-circuit current,
I
SC(PK)
, both track I
MAX
. Once R
SENSE
has been chosen,
I
BURST
and I
SC(PK)
can be predicted from the following
equations:
I
BURST
≈ 15mV
R
SENSE
I
SC(PK)
= 150mV
R
SENSE
+
PGATE
V
IN
V
CC
PDRIVE
V
CC
C
T
I
TH
SENSE
–
CAP
SHDN2
RGND
NGATE
PGND
SGND
SENSE
+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC1149
0.047µF
1µF
0.068µF
V
IN
0.1µF
+
V
8
3300pF390pF
1000pF
+
V
9
– V
8
25k
75k 220µF0.05Ω
+
V
10
V
OUT
+
V
15
50µH
IRF9Z34 220µF
100V
IRFZ34
MBR380
1149 TC
V
FB
/
SHDN1
1k
+
+
+
8
LTC1149
LTC1149-3.3/LTC1149-5
APPLICATIO S I FOR ATIO
WUU U
Figure 3. Timing Capacitor Selection
L and C
T
Selection for Operating Frequency
The LTC1149 series uses a constant off-time architecture
with t
OFF
determined by an external timing capacitor C
T
.
Each time the P-channel MOSFET switch turns on, the
voltage on C
T
is reset to approximately 3.3V. During the
off-time, C
T
is discharged by a current which is propor-
tional to V
OUT
. The voltage on C
T
is analogous to the
current in inductor L, which likewise decays at a rate
proportional to V
OUT
. Thus the inductor value must track
the timing capacitor value.
The value of C
T
is calculated from the desired continuous
mode operating frequency, f:
C
T
= (7.8)(10
–5
)
f
)
)
1 – V
OUT
V
IN
A graph for selecting C
T
versus frequency including the
effects of input voltage is given in Figure 3.
As the operating frequency is increased the gate charge
losses will be higher, reducing efficiency (see Efficiency
Considerations). The complete expression for operating
frequency is given by:
f = 1
tOFF
)
)
1 – VOUT
VIN
where:
t
OFF
= (1.3)(10
4
)(C
T
)
)
)
V
REG
V
OUT
V
REG
is the desired output voltage (i.e., 5V, 3.3V), while
V
OUT
is the actual output voltage. Thus V
REG
/V
OUT
= 1
when in regulation.
Note that as V
IN
decreases, the frequency decreases.
When the input to output voltage differential drops below
1.5V, the LTC1149 series reduces t
OFF
by increasing the
discharge current in C
T
. This prevents audible operation
prior to dropout.
Once the frequency has been set by C
T
, the inductor L must
be chosen to provide no more than 25mV/R
SENSE
of peak-
to-peak inductor ripple current. This results in a minimum
required inductor value of:
L
MIN
=( 5.1)(10
5
)(R
SENSE
)(C
T
)(V
REG
)
As the inductor value is increased from the minimum
value, the ESR requirements for the output capacitor are
eased at the expense of efficiency. If too small an inductor
is used, the inductor current will decrease past zero and
change polarity. A consequence of this is that the LTC1149
series may not enter Burst Mode
operation and efficiency
will be severely degraded at low currents.
FREQUENCY (kHz)
0
0
CT CAPACITANCE (pF)
200
400
600
1400
1000
50 100
1200
800
150 200 250
VOUT = 5V
VIN = 48V
VIN = 12V
VIN = 24V
1149 F03
The LTC1149 series automatically extends t
OFF
during a
short circuit to allow sufficient time for the inductor
current to decay between switch cycles. The resulting
ripple current causes the average short-circuit current
I
SC(AVG)
to be reduced to approximately I
MAX
.
Figure 2. RSENSE vs Maximum Output Current
MAXIMUM OUTPUT CURRENT (A)
0
R
SENSE
(Ω)
0.12
0.16
0.20
4
1149 F02
0.08
0.04
01235
0.10
0.14
0.18
0.06
0.02
9
LTC1149
LTC1149-3.3/LTC1149-5
APPLICATIO S I FOR ATIO
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Inductor Core Selection
Once the minimum value for L is known, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of more expensive
ferrite, molypermalloy, or Kool Mµ
®
cores. Actual core
loss is independent of core size for a fixed inductor value,
but it is very dependent on inductance selected. As induc-
tance increases, core losses go down. Unfortunately,
increased inductance requires more turns of wire and
therefore copper losses increase.
Ferrite designs have very low core loss, so design goals
can concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design cur-
rent is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple which can cause Burst Mode
operation to be falsely
triggered in the LTC1149 series. Do not allow the core to
saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manu-
facturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire.
Because they generally lack a bobbin, mounting is more
difficult. However, new surface mount designs available
from Coiltronics do not increase the height significantly.
P-Channel MOSFET Selection
Two external power MOSFETs must be selected for use
with the LTC1149 series: a P-channel MOSFET for the
main switch, and an N-channel MOSFET for the synchro-
nous switch.
The minimum input voltage determines whether standard
threshold or logic-level threshold MOSFETs must be used.
For V
IN
> 8V, standard threshold MOSFETs (V
GS(TH)
< 4V)
may be used. If V
IN
is expected to drop below 8V, logic-
level threshold MOSFETs (V
GS(TH)
< 2.5V) are strongly
recommended. When logic-level MOSFETs are used, the
absolute maximum V
GS
rating for the MOSFETs must be
greater than the LTC1149 series internal regulator
voltage V
CC
.
Selection criteria for the P-channel MOSFET include the
on-resistance R
DS(ON)
, reverse transfer capacitance C
RSS
,
input voltage and maximum output current. When the
LTC1149 is operating in continuous mode, the duty cycle
for the P-channel MOSFET is given by:
P-Ch Duty Cycle = VOUT
VIN
The P-channel MOSFET dissipation at maximum output
current is given by:
P-Ch P
D
= V
OUT
V
IN
+ K(V
IN
)
2
(I
MAX
)(C
RSS
)(f)
(I
MAX
)
2
(1 + ∂
P
) R
DS(ON)
where ∂ is the temperature dependency of R
DS(ON)
and K
is a constant related to the gate drive current. Note the two
distinct terms in the equation. The first gives the I
2
R
losses, which are highest at low input voltages, while the
second gives the transition losses, which are highest at
high input voltages. For V
IN
< 24V, the high current
efficiency generally improves with larger MOSFETs
(although gate charge losses begin eating into the gains.
See Efficiency Considerations). For V
IN
> 24V, the transi-
tion losses rapidly increase to the point that the use of a
higher R
DS(ON)
device with lower C
RSS
actually provides
higher efficiency. This is illustrated in the Design Example
section.
The term (1 + ∂) is generally given for a MOSFET in the
form of a normalized R
DS(ON)
vs temperature curve, but
∂ = 0.007/°C can be used as an approximation for low
voltage MOSFETs. C
RSS
is usually specified in the MOSFET
electrical characteristics. The constant K is much harder to
pin down, but K = 5 can be used for the LTC1149 series to
estimate the relative contributions of the two terms in the
P-channel dissipation equation.
N-Channel MOSFET and D1 Selection
The same input voltage constraints apply to the N-channel
MOSFET as to the P-channel with regard to when logic-
level devices are required. However, the dissipation calcu-
lation is quite different. The duty cycle and dissipation for
Kool Mµ
is a registered trademark of Magnetics, Inc.
10
LTC1149
LTC1149-3.3/LTC1149-5
APPLICATIO S I FOR ATIO
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the N-channel MOSFET operating in continuous mode are
given by:
N-Ch P
D
= V
IN
–
V
OUT
V
IN
(I
MAX
)
2
(1 + ∂
N
)R
DS(ON)
N-Ch Duty Cycle = V
IN
–
V
OUT
V
IN
where ∂ is the temperature dependency of R
DS(ON)
. Note
that there is no transition loss term in the N-channel
dissipation equation because the drain-to-source voltage
is always low when the N-channel MOSFET is turning on
or off. The remaining I
2
R losses are the greatest at high
input voltage or during a short circuit, when the N-channel
duty cycle is nearly 100%. Fortunately, low R
DS(ON)
N-channel MOSFETs are readily available which reduce
losses to the point that heat sinking is not required, even
during continuous short-circuit operation.
The Schottky diode D1 shown in Figure 1 only conducts
during the dead-time between the conduction of the two
power MOSFETs. D1’s sole purpose in life is to prevent the
body diode of the N-channel MOSFET from turning on and
storing charge during the dead-time, which could cost as
much as 1% in efficiency (although there are no other
harmful effects if D1 is omitted). Therefore, D1 should be
selected for a forward voltage of less than 0.7V when
conducting I
MAX
.
Finally, both MOSFETs and D1 must be selected for
breakdown voltages higher than the maximum V
IN
.
C
IN
and C
OUT
Selection
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle V
OUT
/V
IN
. To
prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
C
IN
Required I
RMS
≈I
MAX
[V
OUT
(V
IN
–
V
OUT
)]1/2
V
IN
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
MAX
/2. This simple worst-case condition is com-
monly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturer’s
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be
paralleled to meet size or height requirements in the
design. An additional 0.1µF ceramic capacitor may also be
required on V
IN
for high frequency decoupling.
The selection of C
OUT
is driven by the required effective
series resistance (ESR). The ESR of C
OUT
must be less
than twice the value of R
SENSE
for proper operation of the
LTC1149 series:
C
OUT
Required ESR < 2R
SENSE
Optimum efficiency is obtained by making the ESR equal
to R
SENSE
. As the ESR is increased up to 2R
SENSE
, the
efficiency degrades by less than 1%. If the ESR is greater
than 2R
SENSE
, the voltage ripple on the output capacitor
will prematurely trigger Burst Mode
operation, resulting in
disruption of continuous mode and an efficiency hit which
can be several percent.
Manufacturers such as Nichicon, Chemicon and Sprague
should be considered for high performance capacitors.
The OS-CON semiconductor dielectric capacitor available
from Sanyo has the lowest ESR for its size, at a somewhat
higher price. Once the ESR requirement for C
OUT
has been
met, the RMS current rating generally far exceeds the
I
RIPPLE(P-P)
requirement.
In surface mount applications multiple capacitors may
have to be paralleled to meet the capacitance, ESR, or RMS
current handling requirements of the application. Alumi-
num electrolytic and dry tantalum capacitors are both
available in surface mount configurations. In the case of
tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. An excellent choice is
the AVX TPS series of surface mount tantalums, available
in case heights ranging from 2mm to 4mm. For example,
if 200µF/10V is called for in an application requiring 3mm
height, two AVX 100µF/10V (P/N TPSD 107K010) could be
used. Consult the manufacturer for other specific recom-
mendations.
At low supply voltages, a minimum value of C
OUT
is
suggested to prevent an abnormal low frequency operat-
ing mode (see Figure 4). When C
OUT
is too small, the
11
LTC1149
LTC1149-3.3/LTC1149-5
APPLICATIO S I FOR ATIO
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Figure 5. High Efficiency Step-Down Regulator with VOUT > VCC
regulator loop adapts to the current change and returns
V
OUT
to its steady state value. During this recovery time
V
OUT
can be monitored for overshoot or ringing which
would indicate a stability problem. The Pin 7 external
components shown in the Figure 1 circuit will prove
adequate compensation for most applications.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(C
LOAD
).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
LTC1149 Adjustable Applications
When an output voltage other than 3.3V or 5V is required,
the LTC1149 adjustable version is used with an external
resistive divider from V
OUT
to V
FB
Pin 10. The regulated
voltage is determined:
VOUT = 1.25
)
)
1 + R2
R1
In applications where V
OUT
is greater than the LTC1149
internally regulated V
CC
voltage, R
SENSE
must be moved to
output ripple at low frequencies will be large enough to trip
the voltage comparator. This causes the Burst Mode
operation to be activated when the LTC1149 series would
normally be in continuous operation. The effect is most
pronounced with low values of R
SENSE
and can be
improved by operating at higher frequencies with lower
values of L. The output remains in regulation at all times.
Checking Transient Response
Switching regulators take several cycles to respond to a
step in DC (resistive) load current. When a load step
occurs, V
OUT
shifts by an amount equal to (∆I
LOAD
)(ESR),
where ESR is the effective series resistance of C
OUT
.
∆I
LOAD
also begins to charge or discharge C
OUT
until the
0.068µF
V
IN
CAP
PDRIVE
LTC1149
I
TH
C
T
PGATE
V
CC
V
CC
SHDN2
SENSE
–
SENSE
+
100pF
IRFZ34
0.047µF
1N4148
1N4148
V
IN
IRF9Z34
1N5819
R
SENSE
0.05Ω
150µF
50V
1µF
0V = NORMAL
>2V = SHUTDOWN
3300pF
C
T
200pF
1k
1149 F05
GNDS
NGATE
V
FB
1000pF
100µH
R2
215k
1%
R1
25k
1%
150µF
16V
OS-CON
LOAD
V
OUT
OUTPUT
GROUND
CONNECTION
V
OUT
= 1.25
()
1 + R2
R1
VALUES SHOWN FOR V
OUT
= 12V
+
+
+
(V
IN
– V
OUT
) VOLTAGE (V)
0
C
OUT
(µF)
600
800
1000
4
1149 F04
400
200
01235
L = 50µH
R
SENSE
= 0.02Ω
L = 25µH
R
SENSE
= 0.02Ω
L = 50µH
R
SENSE
= 0.05Ω
Figure 4. Minimum Suggested COUT
12
LTC1149
LTC1149-3.3/LTC1149-5
APPLICATIO S I FOR ATIO
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the ground side of the output to prevent the absolute
maximum voltage ratings of the sense pins from being
exceeded. This is shown in Figure 5. When the current
sense comparator is operating at 0V common mode, the
off-time increases approximately 40%, requiring the use
of a smaller timing capacitor C
T
.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100 – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-
age of input power. (For high efficiency circuits only small
errors are incurred by expressing losses as a percentage
of output power.)
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1149 series circuits: 1) LTC1149 DC supply
current, 2) MOSFET gate charge current, 3) I
2
R losses and
4) P-channel transition losses.
1. The DC supply current is the current which flows into
V
IN
Pin 2 less the gate charge current. For V
IN
= 12V the
LTC1149 DC supply current is 0.6mA for no load, and
increases proportionally with load up to 2mA after the
LTC1149 series has entered continuous mode.
Because the DC supply current is drawn from V
IN
, the
resulting loss increases with input voltage. For
V
IN
= 24V, the DC bias losses are generally less than 3%
for load currents over 300mA. However, at very low
load currents the DC bias current accounts for nearly all
of the loss.
2. MOSFET gate charge current results from switching the
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from V
IN
to ground. The
resulting dQ/dt is a current out of V
IN
which is typically
much larger than the DC supply current. In continuous
mode, I
GATECHG
= f (Q
N
+ Q
P
). The typical gate charge
for a 0.1Ω N-channel power MOSFET is 25nC, and for
a P-channel about twice that value. This results in
I
GATECHG
= 7.5mA in 100kHz continuous operation, for
a 5% to 10% typical mid-current loss with V
IN
= 24V.
Note that the gate charge loss increases directly with
both input voltage and operating frequency. This is the
principal reason why the highest efficiency circuits
operate at moderate frequencies. Furthermore, it
argues against using larger MOSFETs than necessary
to control I
2
R losses, since overkill can cost efficiency
as well as money!
3. I
2
R losses are easily predicted from the DC resistances
of the MOSFET, inductor and current shunt. In continu-
ous mode all of the output current flows through L and
R
SENSE
, but is “chopped” between the P-channel and
N-channel MOSFETs. If the two MOSFETs have
approximately the same R
DS(ON)
, then the resistance of
one MOSFET can simply be summed with the resis-
tances of L and R
SENSE
to obtain I
2
R losses. For
example, if each R
DS(ON)
= 0.1Ω, R
L
= 0.15Ω and
R
SENSE
= 0.05Ω, then the total resistance is 0.3Ω. This
results in losses ranging from 3% to 12% as the output
current increases from 0.5A to 2A. I
2
R losses cause the
efficiency to roll-off at high output currents.
4. Transition losses apply only to the P-channel MOSFET,
and only when operating at high input voltages (typi-
cally 24V or greater). Transition losses can be esti-
mated from:
Transition Loss ≈ 5(V
IN
)
2
(I
MAX
)(C
RSS
)(f)
For example, if V
IN
= 48V, I
MAX
= 2A, C
RSS
= 300pF (a very
large MOSFET) and f = 100kHz, the transition loss is 0.7W.
A loss of this magnitude would not only kill efficiency but
would probably require additional heat sinking for the
MOSFET! See Design Example for further guidelines on
how to select the P-channel MOSFET.
Other losses including C
IN
and C
OUT
ESR dissipative
losses, Schottky conduction losses during dead-time, and
inductor core losses, generally account for less than 2%
total additional loss.
13
LTC1149
LTC1149-3.3/LTC1149-5
LTC1149 Package Dissipation
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC1149 series
to be exceeded. The LTC1149 supply current is dominated
by the gate charge supply current, which is given as a
function of operating frequency in the Typical Perfor-
mance Characteristics. The LTC1149 series junction tem-
perature can be estimated by using the equations given in
Note 1 of the Electrical Characteristics. For example, the
LT1149CS is limited to less than 11mA from a 48V supply:
T
J
= 70°C + (11mA)(48V)(110°C/W)
= 128°C exceeds absolute maximum
To prevent the maximum junction temperature from being
exceeded, the Pin 2 supply current must be checked in
continuous mode when operating at the maximum V
IN
.
Design Example
As a design example, assume V
IN
= 24V, V
OUT
= 5V,
I
MAX
= 2.5A and f = 100kHz. R
SENSE
, C
T
and L can
immediately be calculated:
R
SENSE
=
)
)
100mV
2.5 = 0.039Ω
C
T
= (7.8)(10
–5
)
100kHz 1 – 5V
24V = 620pF
L
MIN
= (5.1)(10
5
)(0.039Ω)(620pF)(5V) = 62µH
Selection of the P-channel MOSFET involves doing calcu-
lations for different sized MOSFETs to determine the
relative loss contributions. Taking an International Recti-
fier IRF9Z34 for example, R
DS(ON)
= 0.14Ω Max,
Q
P
= 35nC and C
RSS
= 200pF (V
DS
= V
IN
/2). These values
can be used to estimate the I
2
R losses, transition losses
and gate charge supply current losses:
Est. I
2
R Loss (T
J
= 100°C) =
(5V/24V)(2.5)
2
(1 + 0.5)0.14Ω = 270mW
Est. Transition Loss =
5(24V)
2
(2.5A)(200pF)(100kHz) = 145mW
Est. Gate Charge Loss =
(100kHz)(35nC)(24V) = 85mW
APPLICATIO S I FOR ATIO
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The same calculations were repeated for a smaller device,
the Motorola MTD2955 (R
DS(ON)
= 0.3Ω) and a larger one,
the Harris RFP30P05 (R
DS(ON)
= 0.065Ω). The results are
summarized in the table.
CONDITIONS
V
IN
= 24V, V
OUT
= 5V
F = 100kHz, I
OUT
= 2.5A MTD2955 IRF9Z34 RFP30P05
Est. I
2
R Loss (100°C) 550mW 270mW 120mW
Est. Transition Loss 110mW 145mW 290mW
Est. Gate Charge Loss 60mW 85mW 240mW
Est. Total Loss 720mW 500mW 650mW
P-CHANNEL MOSFET
For this set of conditions, the midsized P-channel MOSFET
actually produces the lowest total losses at I
MAX
. The
resulting efficiency differences will be even more pro-
nounced at lower output currents. Note that only the I
2
R
and transition losses are dissipated in the MOSFET; the
gate charge supply current loss is dissipated by the
LTC1149 series.
Selection of the N-channel MOSFET is somewhat easier; it
need only be sized for the anticipated I
2
R losses at 100%
duty cycle (worst-case assumption for short circuit.) The
Siliconix Si9410, for example, has R
DS(ON)
= 0.03Ω Max
and Q
N
= 30nC. This will produce an I
2
R loss of 250mW at
100°C and a gate charge supply current loss of 75mW. As
with the P-channel device, the use of a larger MOSFET may
actually result in lower midcurrent efficiency.
C
IN
will require an RMS current rating of at least 1.25A at
temperature, and C
OUT
will require an ESR of 0.04Ω for
optimum efficiency. The output capacitor ESR require-
ment can be fulfilled by a single OS-CON or by two or more
surface mount tantalums in parallel.
Auxiliary Windings – Suppressing Burst Mode
Operation
The LTC1149 synchronous switch removes the normal
limitation that power must be drawn from the inductor
primary winding in order to extract power from auxiliary
windings. With synchronous switching, auxiliary outputs
may be loaded without regard to the primary output load,
providing that the loop remains in continuous mode
operation.
Burst Mode operation can be suppressed at low output
currents with a simple external network which cancels the
14
LTC1149
LTC1149-3.3/LTC1149-5
circuitry. Turning on the N-channel MOSFET when this
fault is detected will then force the system fuse to blow.
The N-channel MOSFET needs to be sized so it will safely
handle this overcurrent condition. The typical delay from
pulling the C
T
Pin 6 high to when the NGATE Pin 13 goes
high is 250ns.
Under shutdown conditions, the N-channel
is held off and pulling Pin 6 high will not cause the output
to be crowbarred.
A small N-channel FET can be used as an interface between
the overvoltage detect circuitry and the LTC1149 as shown
in Figure 7.
APPLICATIO S I FOR ATIO
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Figure 7. Output Crowbar Interface
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1149 series. These items are also illustrated graphi-
cally in the layout diagram of Figure 8. Check the following
in your layout:
1. Are the signal and power grounds segregated? The
LTC1149 signal ground Pin 11 must connect separately
to the (–) plate of C
OUT
. The other ground Pins 12 and
14 should return to the source of the N-channel MOSFET,
anode of the Schottky diode and (–) plate of C
IN
, which
should have as short lead lengths as possible.
2. Does the LTC1149 SENSE
–
Pin 8 connect to a point
close to R
SENSE
and the (+) plate of C
OUT
? In adjustable
applications, the resistive divider R1, R2 must be
connected between the (+) plate of C
OUT
and signal
ground.
3. Are the SENSE
–
and SENSE
+
leads routed together with
minimum PC trace spacing? The differential decou-
pling capacitor between Pins 8 and 9 should be as close
as possible to the LTC1149. Up to 100Ω may be placed
Figure 6. Suppressing Burst Mode Operation
25mV minimum current comparator threshold. This tech-
nique is also useful for eliminating audible noise from
certain types of inductors in high current (I
OUT
> 5A)
applications when they are lightly loaded.
An external offset is put in series with the SENSE
–
pin to
subtract from the built-in 25mV offset. An example of this
technique is shown in Figure 6. Two 100Ω resistors are
inserted in series with the leads from the sense resistor.
With the addition of R3, a current is generated through R1
causing an offset of:
VOFFSET = VOUT
)
)
R1
R1 + R3
If V
OFFSET
> 25mV, the minimum threshold will be cancelled
and Burst Mode
operation is prevented from occurring.
Since V
OFFSET
is constant, the maximum load current is
also decreased by the same offset. Thus, to get back to the
same I
MAX
, the value of the sense resistor must be lower:
R
SENSE
≈75mV
I
MAX
To prevent noise spikes from erroneously tripping the
current comparator, a 1000pF capacitor is needed across
Pins 8 and 9.
Output Crowbar
An added feature to using an N-channel MOSFET as the
synchronous switch is the ability to crowbar the output
with the same MOSFET. Pulling the timing capacitor Pin 6
above 1.5V when the output voltage is greater than the
desired regulated value, will turn on the N-channel MOSFET.
A fault condition which causes the output voltage to go
above a maximum value can be detected by external
LTC1149
SENSE
+
SENSE
–
9
81000pF R1
100Ω
R2
100Ω
LR
SENSE
C
OUT
R3
1149 F06
+
LTC1149
5
6
VN2222LLCROWBAR
ACTIVE WHEN CROWBAR = V
IN
OFF WHEN CROWBAR = GROUND
1149 F07
V
CC
C
T
15
LTC1149
LTC1149-3.3/LTC1149-5
APPLICATIO S I FOR ATIO
WUU U
Figure 8. LTC1149 Series Layout Diagram (see Layout Checklist)
in series with each sense lead to help decouple Pins 8
and 9. However, when these resistors are used, the
capacitor should be no larger than 1000pF.
4. Does the (+) plate of C
IN
connect to the source of the
P-channel MOSFET as closely as possible? An addi-
tional 0.1µF ceramic capacitor between V
IN
and power
ground may be required in some applications.
5. Is the V
CC
decoupling capacitor connected closely
between Pin 5 of the LTC1149 and power ground? This
capacitor carries the MOSFET driver peak currents.
6. Is the SHDN1 Pin 10 (fixed output versions only)
actively pulled to ground during normal operation? The
SHDN1 pin is high impedance and must not be allowed
to float. In adjustable versions, Pin 10 is the feedback
pin and is very sensitive to pickup from the switch node.
Care must be taken to isolate V
FB
from possible capaci-
tive coupling of the inductor switch signal.
Troubleshooting Hints
Since efficiency is critical to LTC1149 series applications,
it is very important to verify that the circuit is functioning
correctly in both continuous and Burst Mode operation.
The waveform to monitor is the voltage on the timing
capacitor Pin 6.
In continuous mode (I
LOAD
> I
BURST
) the voltage on Pin 6
should be a sawtooth with a 0.9V
P-P
swing. This voltage
should never dip below 2V as shown in Figure 9a.
When load currents are low (I
LOAD
< I
BURST
) Burst Mode
operation should occur with the C
T
pin waveform periodi-
cally falling to ground as shown in Figure 9b.
If Pin 6 is observed falling to ground at high output
currents, it indicates poor decoupling or improper ground-
ing. Refer to the Board Layout Checklist.
Figure 9. CT Pin 6 Waveforms
3.3V
0V
(a) CONTINUOUS MODE OPERATION
3.3V
0V
(b) Burst Mode OPERATION 1149 F09
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PGATE
V
IN
V
CC
PDRIVE
V
CC
C
T
I
TH
SENSE
–
CAP
SD2
RGND
NGATE
PGND
SGND
C
OUT
D1
P-CHANNEL
1k
3300pFC
T
R1
R2 R
SENSE
N-CHANNEL
C
IN
L
+
–
–
+
V
OUT
V
IN
OUTPUT DIVIDER REQUIRED WITH
ADJUSTABLE VERSION ONLY
BOLD LINES INDICATE HIGH CURRENT PATHS
1149 F08
1000pF
V
FB/
SHDN1
SENSE
+
100pF
+
1µF
0.068µF
1N4148 1N4148
SHUTDOWN
0.047µF
+
+
16
LTC1149
LTC1149-3.3/LTC1149-5
TYPICAL APPLICATIO S
U
Figure 10. High Efficiency 8V to 20V Input 3.3V/1A Output Regulator
PGATE
V
IN
V
CC
P-DRIVE
V
CC
C
T
I
TH
SENSE
–
CAP
SHDN2
R-GND
NGATE
PGND
SGND
SHDN1
SENSE
+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC1149-3.3
0.068µF
0.047µF
1N4148 1N4148
3300pF
1k
390pF1µF
1000pF
IRFR024 1N5818
100µF
35V
V
IN
8V TO 20V
L*
68µH R
SENSE
**
0.1Ω
220µF
6.3V
AVX
1149 F10
V
OUT
3.3V/1A
*COILTRONICS CTX02-11932
**DALE WSC-1/2-0.1
IRFR9024
0V = NORMAL
>2V = SHUTDOWN
+
+
+
Figure 11. High Efficiency 8V to 20V Input 3.3V/3A Output Regulator
PGATE
VIN
VCC
PDRIVE
VCC
CT
ITH
SENSE–
CAP
SHDN2
RGND
NGATE
PGND
SGND
SHDN1
SENSE+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC1149-3.3
0.068µF
0.047µF
1N4148 1N4148
3300pF
1k
470pF3.3µF
1000pF
IRFZ34 1N5818
220µF
35V
VIN
8V TO 20V
L*
33µH RSENSE**
0.033Ω
220µF
6.3V × 2
AVX
1149 F11
VOUT
3.3V/3A
*COILTRONICS CTX33-4-KM
**KRL SL-1-C1-0R033J
IRF9Z34
SHUTDOWN
100Ω
100Ω
+
+
+
17
LTC1149
LTC1149-3.3/LTC1149-5
Figure 12. Ultra Wide Input Range (5.5V to 25V) High Efficiency 5V Regulator
TYPICAL APPLICATIO S
U
PGATE
VIN
VCC
PDRIVE
VCC
CT
ITH
SENSE–
CAP
SHDN2
RGND
NGATE
PGND
S-GND
SHDN1
SENSE+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC1149-5
0.068µF
0.047µF
1N4148 1N4148
3300pF
1k
220pF1µF
1000pF
Si9410DY 1N5818
220µF
35V
VIN
5.5V TO 25V
L*
33µH RSENSE**
0.05Ω
220µF
10V × 2
AVX
1149 F12
VOUT
5V/2A
*COILTRONICS CTX33-4 Kool Mµ
**KRL SL-1-C1-0R050J
Si9435DY
SHUTDOWN
+
+
+
Figure 13. 250kHz High Efficiency 12V Input 5V/2A Output Regulator
PGATE
V
IN
V
CC
PDRIVE
V
CC
C
T
I
TH
SENSE
–
CAP
SHDN2
RGND
NGATE
PGND
SGND
SHDN1
SENSE
+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC1149-5
0.068µF
0.047µF
1N4148 1N4148
3300pF
1k
180pF1µF
1000pF
Si9410DY 1N5818
100µF
25V
V
IN
8V TO 16V
L*
22µH R
SENSE
**
0.05Ω
220µF
10V
AVX
1149 F13
V
OUT
5V/2A
*DALE LPE-6562-220MB
**KRL SL-1-C1-0R050J
Si9430DY
SHUTDOWN
+
+
+
18
LTC1149
LTC1149-3.3/LTC1149-5
TYPICAL APPLICATIO S
U
Figure 14. High Efficiency 48V Input 5V/2.5A Output Regulator
PGATE
V
IN
V
CC
PDRIVE
V
CC
C
T
I
TH
SENSE
–
CAP
SHDN2
RGND
NGATE
PGND
SGND
SHDN1
SENSE
+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC1149-5
0.068µF
0.047µF
1N4148 1N4148
3300pF
1k
620pF3.3µF
1000pF
IRFZ34 MBR380
100µF
100V
L*
68µH R
SENSE
**
0.04Ω
220µF
10V
OS-CON
1149 F14
V
OUT
5V/2.5A
*HURRICANE LAB HL-KI168M
**IRC LR2512-01-R040-G
MTD2955
SHUTDOWN
V
IN
48V
0.1µF
100Ω
100Ω
+
+
+
Figure 15. Logic Selectable 5V/2A or 3.3V/2A High Efficiency Regulator
PGATE
V
IN
V
CC
PDRIVE
V
CC
C
T
I
TH
SENSE
–
CAP
SHDN2
RGND
NGATE
PGND
SGND
V
FB
SENSE
+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC1149
0.068µF
0.047µF
1N4148 1N4148
3300pF
1k
390pF1µF
1000pF
RFD14N05SM 1N5818
100µF
35V
V
IN
8V TO 20V
L*
50µH R
SENSE
**
0.05Ω
220µF
10V × 2
AVX
1149 F15
V
OUT
3.3V/2A
OR 5V/2A
*COILTRONICS CTX50-2-MP
**IRC LR2010-01-R050-G
RFD15P05SM
SHUTDOWN
100pF R1A
33k
1%
R2
56k
1%
VN2222LL 0V: V
OUT
= 3.3V
5V: V
OUT
= 5V
R1B
43k
1%
+
+
+
19
LTC1149
LTC1149-3.3/LTC1149-5
TYPICAL APPLICATIO S
U
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
N16 1197
0.255 ± 0.015*
(6.477 ± 0.381)
0.770*
(19.558)
MAX
16
12345678
910
11
12
13
14
15
0.020
(0.508)
MIN
0.125
(3.175)
MIN
0.130 ± 0.005
(3.302 ± 0.127)
0.065
(1.651)
TYP
0.045 – 0.065
(1.143 – 1.651)
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.009 – 0.015
(0.229 – 0.381)
0.300 – 0.325
(7.620 – 8.255)
0.325 +0.035
–0.015
+0.889
–0.381
8.255
()
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
N Package
16-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTIO
U
Figure 16. 25W High Efficiency Regulator Using N-Channel MOSFET Switches
0.1µF
PGATE
V
IN
V
CC
PDRIVE
V
CC
C
T
I
TH
SENSE
–
CAP
SHDM2
RGND
NGATE
PGND
SGND
SHDN1
SENSE
+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC1149-5
1N4148
3300pF
1k
820pF3.3µF
1000pF
IRFZ44 MBR380
1000µF
63V
L*
50µH R
SENSE
**
0.02Ω
220µF
10V × 2
OS-CON
1149 F16
V
OUT
5V/5A
*COILTRONICS CTX50-5-52
**DALE LVR-3-0.02
V
IN
12V TO 36V
100Ω
100Ω
0V = NORMAL
>2V = SHUTDOWN
VN2222LL
10k
470Ω
2N2222
220Ω
2N3906
0.1µF
MTP30N06EL
MUR110
SEE APPLICATIONS INFORMATION TO SUPPRESS
Burst Mode
TM
OPERATION AT LOW CURRENTS
+
+
+
20
LTC1149
LTC1149-3.3/LTC1149-5
LINEAR TECHNOLOGY CORPORATION 1993
1149fa LT/TP 0898 REV A 2K • PRINTED IN USA
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTIO
U
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.016 – 0.050
0.406 – 1.270
0.010 – 0.020
(0.254 – 0.508)× 45°
0° – 8° TYP
0.008 – 0.010
(0.203 – 0.254)
S16 0695
12345678
0.150 – 0.157**
(3.810 – 3.988)
16 15 14 13
0.386 – 0.394*
(9.804 – 10.008)
0.228 – 0.244
(5.791 – 6.197)
12 11 10 9
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
TYP
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH 
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD 
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
TYPICAL APPLICATION
U
Figure 17. High Efficiency 24V Input 12V/3A Output Regulator
PART NUMBER DESCRIPTION COMMENTS
LTC1148HV High Efficiency, Synchronous Step-Down Switching Regulator 4V < V
IN
< 20V
LTC1159 High Efficiency, Synchronous Step-Down Switching Regulator 4V < V
IN
< 40V, I
SHUTDOWN
= 20µA
LTC1435A High Efficiency, Low Noise, Synchronous Switching Regulator 3.5V < V
IN
< 36V, N-Channel Driver
LTC1438 Dual, Low Noise, Synchronous Switching Regulator 3.5V < V
IN
< 36V, N-Channel Driver
RELATED PARTS
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear-tech.com
PGATE
V
IN
V
CC
PDRIVE
V
CC
C
T
I
TH
SENSE
–
CAP
SHDN2
RGND
NGATE
PGND
SGND
V
FB
SENSE
+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC1149
0.068µF
0.047µF
1N4148 1N4148
3300pF
1k
300pF3.3µF
1000pF
MTP36N06E MBR160
220µF
50V
V
IN
20V TO 30V
L*
100µH
150µF
16V × 2
OS-CON
1149 F17
V
OUT
12V/3A
*HURRICANE LAB HL-EK210M
**KRL SL-1-C1-0R033J
MTP23P06
SHUTDOWN
100Ω
100Ω
R1
20k
1%
R2
172k
1%
R
SENSE
**
0.033Ω
OUTPUT
GROUND
CONNECTION
100pF
+
+
+