March 2003
Production
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P1817A/B
3/10/03, v. 0.5 Alliance Semiconductor P. 1 of 6
Low-Power Mobile VGA EMI Reduction IC
Features
• FCC approved method of EMI attenuation
• Generates a low EMI spread spectrum and a non-
spread reference signal of th e input clock frequency
• Optimized for frequency range from
• P1817A: 20 to 32 MHz operation
• P1817B: 10 to 20 MHz operation
• Internal loop filter minimizes external components
and board space
• Two selectable spread ranges
• Low inherent cycle-to-cycle jitter
• 3.3 V or 5 V operating voltage
• CMOS/TTL compatible inputs and outputs
•Ultra low power CMOS design:
3.17mA @3.3V, 10 MHz 6.20mA @5.0V, 10 MHz
4.28mA @3.3V, 14 MHz 7.50mA @5.0V, 14 MHz
5.50mA @3.3V, 20 MHz 9.50mA @5.0V, 20 MHz
• Supports notebook VGA and other LCD timing con-
troller applications
• SSON pin for Spread Spectrum On/Off and Standby
Mode controls
• Available in 8-pin SOIC and TSSOP
Block Diagram
Frequency
divider
Feedback
divider
Modulation
Phase
detector Loop
filter VCO Output
divider
Crystal
oscillator
ModOUT
SR0 SSON VDD
VSS
PLL
XIN
XOUT
Ref
Product Description
The P1817 is a versatile spread spectrum frequency
modulator designed specifically for a wide range of clock
frequencies. It reduces electromagnetic interference (EMI)
at the clock source allowing system-wide reduction of EMI
of downstream clock and data depend ent signals. It allows
significant system cost savings by reducing the number of
circuit board layers and shielding traditionally required to
pass EMI regulations.
The P1817 modulates the output of a sin gle PLL in order to
spread the band wid th of a synthesized clock, thereby
decreasing the peak amplitudes of its harmonics. This
results in significantly lower system EMI compared to the
typical narrow band signal produced by oscillators and
most clock generators. Lowering EMI by increasing a
signal’s bandwidth is called spread spectrum clock
generation.
The P1817 uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented by using a proprietary all-digital method.
Applications
The P1817 is targeted toward the notebook VGA chip
and other displays using an LVDS interface, PC
peripheral devices, and embedded systems.
Pin Diagram
CLKIN/XIN
VSS
SR0
SSON/SBM
XOUT
VDD
REF
ModOUT
1
2
3
4
8
7
6
5
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3/10/03, v. 0.5 Alliance Semiconductor P. 2 of 6
Standby Mode Selection
Spread Range Selection, VDD = 5 V
Spread Range Selection, VDD = 3.3 V
Pin Description
CLKIN SSON/SBM Spread
Spectrum ModOUT PLL Mode
Disabled 0 N/A Disabled Disabled Standby
Disabled 1 N /A Disabled Free running Free running
Enabled 0 Off Reference Disabled Buffer out
Enabled 1 On Normal Normal Normal
CLKIN frequency SR0 Spreading range Modulation rate
10 MHz 1 ±1.5%
(CLKIN/10) * 20.83 kHz
0 ±1.9%
14.318 MHz 1 ±1.36%
0 ±1.64%
15 MHz 1 ±1.3%
0 ±1.5%
20 MHz 1 ±0.95%
0 ±1.125%
CLKIN frequency SR0 Spreading range Modulation rate
10 MHz 1 ±1.5%
(CLKIN/10) * 20.83 kHz
0 ±1.65%
14.318 MHz 1 ±1.4%
0 ±1.7%
15 MHz 1 ±1.37%
0 ±1.63%
20 MHz 1 ±1.1%
0 ±1.28%
Pin # Name Type Description
1 CLKIN/XIN I Connect to externally generated clock signal. To put the part into standby mode,
disable the input clock signal to this pin and pull SSON/SBM (pin 4) low. (See
Standby Mode Selection.)
2 VSS P Ground connection. Connect to system ground.
3SR0I
Digital logic input used to select Spreading Range. (See Spread Spectrum
Selection.) This pin has an internal pull-up resistor.
4 SSON/SBM I Spread Spectrum On/Of f and Sta ndby Mode control. (See Stan dby Mode Selection.)
This pin has an intern al pu ll-u p resis tor.
5 ModOUT O Spread Spectrum clock output or Reference output. (See Standby Mode Selection.)
6 REF O Reference output.
7 VDD P Connect to +3.3 V or 5.0 V.
8 XOUT I Connect to crystal. No connect if externally generated clock signal is used.
P1817A/B
3/10/03, v. 0.5 Alliance Semiconductor P. 3 of 6
Schematic for Notebook VGA Application
CLKIN/XIN
VSS
SR0
SSON/SBM
XOUT
VDD
REF
ModOUT
1
2
3
4
8
7
6
5
P1817A/B
VDD
0.1 uF
Pull pin 4 low to turn Spread Spectrum
off and enable Standby Mode.1
10 to 20 MHz and 20 to 32 MHz
EMI reduced clock output.
1 To set the P1817 to standby mode, disable the input clock (pin 1 CLKIN), and pull pin 4 SSON/SBM low.
Ferrite
bead
VDD
0 Ω
0 ΩVDD
0 Ω
0 Ω
Use either pull-up or pull-down
resistors with 0 Ω.
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3/10/03, v. 0.5 Alliance Semiconductor P. 4 of 6
Absolute Maximum Ratings
DC Electrical Characteristics
AC Electrical Characteristics
Symbol Parameter Rating Units
VDD, VIN Voltage on any pin with respect to GND -0.5 to +7.0 V
TSTG Storage temperature -65 to +125 ° C
TAOperating temperature 0 to +70 ° C
Symbol Parameter Min Typ Max Units
VIL Input low voltage GND - 0.3 – 0.8 V
VIH Input high voltage 2.0 – VDD + 0.3 V
IIL Input low current
(pull-up resistor on inputs SR0 and SSON/SBM) ––-35µA
IIH Input high curren t – – 35 µA
IXOL XOUT output low current at 0.4 V, VDD = 3.3V – 3 – mA
at 0.4 V, VDD = 5.0 V – 20 – mA
IXOH XOUT output high current at 2.5 V, VDD = 3.3 V – 3 – mA
at 4.5 V, VDD = 5.0 V – 20 – mA
VOL Output low voltage VDD = 3.3 V, IOL = 20 mA – – 0.4 V
VDD = 5.0 V, IOL = 20 mA–––V
VOH Output high voltage VDD = 3.3 V, IOL = 20 mA 2.5 – – V
VDD = 5.0 V, IOL = 20 mA 4.5 – – V
IDD Static supply current standby mode – 0.6 – mA
ICC Dynamic supply current Normal mode:
3.3 V and 10 pF loading fIN-min fIN-typ fIN-max
3.2–7.0mA
5.0 V and 10 pF loading 6.2 – 13.6 mA
VDD Operating vo lt ag e 2.7 3.3 5.5 V
tON Power-up time (first locked cycle after power up) – 0.18 – mS
ZOUT Clock output imped an ce – 50 – Ω
Symbol Parameter Min Typ Max Units
fIN Input frequency (See device type P1817A or P1817B.) 10 – 32 MHz
fOUT Output frequency (See device type P1817A or P1817B.) 10 – 32 MHz
tLH1
1 tLH and tHL are measured into a capacitive load of 15 pF.
Output rise time Measured at 0.8 V to 2.0 V 0.7 0.9 1.1 ns
Measured at 1.2 V to 3.75 V – 0.75 – ns
tHL1Output fall time Measured at 2.0 V to 0.8 V 0.6 0.8 1.0 ns
Measured at 1.2 V to 3.75 V – 0.75 – ns
tJC Jitter (cycle to cycle) – – 360 ps
tDOutput duty cycle 45 50 55 %
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Mechanical Package Outline (8-Pin SOIC)
Mechanical Package Outline (8-Pin TSSOP)
INCHES MILLIMETERS
SYMBOL MIN NOR MAX MIN NOR MAX
A0.057 0.064 0.071 1.45 1.63 1.80
A1 0.004 0.007 0.010 0.10 0.18 0.25
A2 0.053 0.061 0.069 1.35 1.55 1.75
B0.012 0.016 0.020 0.31 0.41 0.51
C0.004 0.006 0.001 0.10 0.15 0.25
D0.186 0.194 0.202 4.72 4.92 5.12
E0.148 0.156 0.164 3.75 3.95 4.15
e0.050 BSC 1.27 BSC
H0.224 0.236 0.248 5.70 6.00 6.30
L0.012 0.020 0.028 0.30 0.50 0.70
a0° 5° 8° 0° 5° 8°
Note: Controlling dimensions are millimeters.
SOIC - 0.074 grams unit weight
D
A1
eB
A
A2
P1817A/B
LOT NUMBER
YYWW
H
a
C
L
E
INCHES MILLIMETERS
SYMBOL MIN NOR MAX MIN NOR MAX
A– – 0.047 – – 1.10
A1 0.002 – 0.006 0.05 – 0.15
A2 0.031 0.039 0.041 0.80 1.00 1.05
B0.007 – 0.012 0.19 – 0.30
C0.004 – 0.008 0.09 – 0.20
D0.114 0.118 0.122 2.90 3.00 3.10
E0.169 0.173 0.177 4.30 4.40 4.50
e0.026 BSC 0.65 BSC
H0.244 0.252 0.260 6.20 6.40 6.60
L0.018 0.024 0.030 0.45 0.60 0.75
a0° – 8° 0° – 8°
Note: Controlling dimensions are millimeters.
TSSOP - 0.034 grams unit weight
D
A1
eB
A
A2
H
a
C
L
E
P
1817A/B
Lot #
YYWW
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the
trademarks of their respective c ompanies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this
document. The data contain ed here in r epresent s Al liance ’s best data and/or estimates at the time of issuance. Alliance rese rves the right to change or correct this data at any time, without notice. If the product described herein is
under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to
operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express
or implied warranties related to the sale and/or use of Alliance products including liability or warranties relate d to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as
express agreed to in Alliance’s Te rms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made e xclusively according to Alliance’s Terms and Conditions of Sale. The pur chase of
products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products
for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user , and the inclusion of Alliance products in such life-supporting systems
implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
P1817A/B
3/10/03, v. 0.5 Alliance Semiconductor P. 6 of 6
Ordering Information
Examples
Licensed under U.S. Patent Nos. 5,488,627 and 5,631,920.
Preliminary datasheet. Specifications subject to change without notice.
Order Number Marking
Input
frequency
(MHz) Package type Pb free Quantity/
reel Temperature
P1817A-08ST P181 7A 20 – 32 8-pin SOIC, tube No 0° C to 70° C
P1817AF-08ST P1817AF 20 – 32 8-pin SOIC, tube Yes 0° C to 70° C
I1817A-08SR P1817A 20 – 32 8-pin SOIC, tape & reel No 2,500 -20° C to 85° C
I1817BF-08TR P1817BF 10 – 20 8-pin TSSOP, tape & reel Yes 2,500 -20° C to 85° C
X 1817X 08 XX
Package: ST = SOIC in Tube
Device pin count
Device Number
Flow: P = Commercial temperature range (0°C to 70°C)
SR = SOIC in Tape and Reel
TT = TSSOP in Tube
TR = TSSOP in Tape and Reel
I = Industrial temperature range (-25°C to 85°C)
X -
F = Pb free