HDSP2003LP - OSRAM OPTO SEMICONDUCTORS

Red HDSP2000LP

Yellow HDSP2001LP

High Efficiency Red HDSP2002LP

Green HDSP2003LP

Lead (Pb) Free Product - RoHS Compliant

0.150" 4-Character 5 x 7 Dot Matrix

Serial Input Alphanumeric Display

2009-03-31 1

DESCRIPTION

The HDSP200XLP are fo ur digit 5 x 7 dot matrix serial input alpha-

numeric displays. The displays are available in red, yellow, high

efficiency red, or bright green. The package is a standard

twelve-pin DIP with a flat plastic lens. The display can be stacked

horizontally or vertically to form messages of any length.

The HDSP200XLP has two fourteen-bit CMOS shift registers with

built-in row dr ivers. These shif t reg is t ers drive twenty-eight rows

and enable the design of customized fonts. Cascading multiple

displays is possible because of the Data In and Data Out pins.

Data In and Out are easily input with the clock signal and dis-

played in paral le l o n the row drivers. Dat a Ou t re pr es en ts th e ou t-

put of the 7th bit of digit number four shift register The shift

display cluster are tied to a single pin (see Block Diagram). High

true data in the shift register enables the output current mirror

driver stage a ss oc iat e d wi t h ea c h row of LEDs in the 5 x 7 di o de

array.

The TTL compatible VB input may either be tied to VCC for maxi-

mum display intensity or pulse width modulated to achieve inten-

sity control and reduce power consumption.

In the normal mode of opera tion , inp ut d ata for digit four, column

one is loaded into th e seven on-boar d sh ift r egi ster loca tion s on e

through seve n. Colum n o ne data for digits 3, 2, and 1 is shif ted into

the display shift register loc ation s. Then column one inp ut i s

enabled for an appropriate period of time, T. A similar p rocess is

repeated for columns 2, 3, 4, and 5. If the deco de t i me and loa d

data time into the shift register is t, then with fiv e colu mns , each col -

umn of the display is operating at a duty factor of:

T+t, allotted to each display column, is generally chosen to pro-

vide the maximum duty factor consistent with the minimum refresh

rate necessary to achieve a flicker free display. For most strobed

display systems, each column of the display should be refreshed

(turned on) at a minimum rate of 1 00 ti mes pe r se co nd .

With columns to be addressed, this refresh rate then gives a v alue f or

the time T+t of: 1⁄ [5 x (100)] =2.0 msec. If the de vice is operated at

5.0 MHz clock r ate maximum, it is possible to maintain t<T. For short

display strings, the duty f actor will then approach 20%.

DF T

5T t+

()

-------------------=

FEATURES

• Four 0.150" Dot Matrix Characters

• Four Colors: Red, Yellow, High Efficiency

Red, Green

• Wide Viewing Angle: X Ax is +50°, Y Axis +75°

• Built-in CMOS Shift Registers with Constant

Current LED Row Drivers

• Custom Fonts from Shift Registers

• Easily Cascaded f or Multiple Displays

• TTL Compatible

•End Stackable

• Extended Operating Temperature Range:

–40°C to + 85°C

• Categorize d for Luminous Intensity

• All Displays Color Matched

• Compact Plastic Package

• 100% Burned-in and Tested

2009-03-31 2

HDSP2000LP, HDSP2001LP, HDSP2002LP, HDSP2003LP

Package Outlines Dimensions in mm (inch)

Ordering Information

Type Color of Emission Character Height

[inch] ([mm]) Ordering Code

HDSP2000LP red

0.150 (3.7)

Q68000A8131

HDSP2001LP yellow Q68000A8304

HDSP2002LP high efficiency red Q68000A8132

HDSP2003LP green Q68000A8133

IDOD5206

123456

12 7891011

2.11 (0.083) 4.44 (0.175)±0.13 (0.005)

17.75 (0.699) max.

3.71 (0.146)

8.89 (0.350)

HDPS200XLP Z

OSRAM YYWW V

Indicator

Pin 1

EIA Date Code

Luminous Intensity Code

or Color Code for Yellow

2.54 (0.100)±0.13 (0.005)

10 pl., non cum.

0.51 (0.020)±0.08 (0.003)

5.08 (0.200)

3.81 (0.150)

0.3 (0.012)±0.05 (0.002)

7.24 (0.285)±0.25 (0.010)

Column 33

No Connection

Column 5

Column 4

Column 2

Column 1

FunctionPin

Tolerance: ±0.38 (0.015)

Part No.

4.32 (0.170)

12 pl.

Ground

Data In

Data Out

Clock

Pin Function

HDSP2000LP, HDSP2001LP, HDSP2002LP, HDSP2003LP

2009-03-31 3

Maximum Allowable Power Dissipation vs.

Temperature Timing Characteristics

Peak Column Current vs. Column Voltage

Maximum Ratings

Parameter Symbol Value Unit

Operating temperature range Top – 40 … + 85 °C

Storage temperature range Tstg – 40 … + 100 °C

DC Supply Voltage VCC -0.5 to + 7.0 V

Inputs, Data Out and VB-0.5 to VCC +0.5 V

Column Input Voltage VCOL -0.5 to + 6.0 V

Solder temperature 063“ (1.59 mm)

below seating plane, t < 5.0 s TS260 °C

Allowable Power Dissipation at TA=25°C1) 0.86 W

1) Maximum allowable dissipation is derived from VCC=5.25 V, VB=2.4 V, VCOL=3.5 V, 20 LEDs on per character, 20% DF.

AC Electrical Characteristics

(VCC=4.75 to 5.25 V, TA=–40°C to 85°C)

Symbol Description Min. Max.1) Units Fig.

TSETUP Setup Time 50 —ns 1

THOLD Hold Time 25 —ns 1

TWL Clock Width Low 75 —ns 1

TWH Clock Width High 75 —ns 1

F(CLK) Clock

Frequency 05.0 MHz 1

TTHL, TTLH Clock Transition Time —200 ns 1

TPHL, TPLH Propagation Delay

Clock to Data Out —125 ns 1

1)VB Pulse Width Modulation Frequency—50 kHz (max).

IDDG5323

-60

˚C

-40 -20 0 20 40 60 80 120

jmax

= 100 ˚C

0.2

0.4

0.6

0.8

1.0

= 0 ˚C/W

10 ˚C/W

thJA

20 ˚C/W

40 ˚C/W

TWL

l/fCLOCK

TPLH, TPHL

TTHL

CLOCK

DATA IN

DATA OUT

THOLD

TSETUP

TWH

TON

TOFF

2.4 V

0.4 V

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

DISPLAY ON (illuminated)

OFF (not illuminated)

90%

10%

IDDG5324

COL

123456V

100

200

300

400

500

600

HDSP2000

HDSP2001/2/3

= 5.25 V

= 25 ˚C,

All SR Stages = Logical 1

2009-03-31 4

HDSP2000LP, HDSP2001LP, HDSP2002LP, HDSP2003LP

Recommended Operating Conditions

Parameter Symbol Min. Typ. Max. Units

Supply Voltage VCC 4.75 5.0 5.25 V

Data Out Current, Low State IOL — — 1.6 mA

Data Out Current, High State IOH –0.5 — — mA

Column Input Voltage, Column On HDSP2000LP1) VCOL 2.4 —3.5 V

Column Input Voltage, Column On, HDSP2001LP/2002LP/2003LP1) VCOL 2.75 —3.5 V

Setup Time TSETUP 70 — — ns

Hold Time THOLD 30 — — ns

Width of Clock TW(CLK) 75 — — ns

Clock Frequency TCLK — — 5.0 MHz

Clock Transition Time TTHL — — 200 ns

1) See Figure „Peak column current versus column voltage“ on page 3

Electrical characteristics (–40°C to +85°C, unless otherwis e specified)

Description Symbol Min. Typ.1) Max. Units Test Conditions

Supply Current (quiescent) VCC — 1 5 mA VB=0.4 V VCC=5.25 V

VCLK=VDATA=2.4 V

All SR Stages=Logical 1

— 1 5 mA VB=2.4 V

Supply Current (operating) VCC —1.5 10.0 mA FCLK=5.0 MHz

Column Current at any Column Input2) iCOL (All) — — 10 µA VB=0.4 V VCC=5.25 V

VCOL=3.5 V

All SR Stages=Logical 1

ICOL —335 410 mA VB=2.4 V

VB, Clock or Data Input , Threshold Low

VB, Clock or Data Input, Threshold High VIL

VIH

2.0 —0.8 V

VVCC= 4.75 V–5.25 V

Data Out Voltage VOH 2.4 — — V IOH=–0.5 mA VCC=4.75 V

ICOL=0 mA

VOL — — 0.4 VIOL=1.6 mA

Input Current Logical 0, VB only IIL –30 –110 –300 µA VCC=4.75 V–5.25 V, VIL=0.8 V

Input Current Logical 0 Data, Clock IIL —–1 –10 µA

Power Dissipation per Package2) PD—0.4 — W VCC=5.0, VCOL=3.5 V, 17.5% DF

15 LEDs on per character, VB=2.4 V

Thermal Resistance IC

Junction-to-Ambient RqJ-A —85 — °C/W/

Device

1) All typical values specified at VCC=5.0 V and TA=25°C unless otherwise noted.

2) See Figure „Peak column current versus column voltage“ on page 3

HDSP2000LP, HDSP2001LP, HDSP2002LP, HDSP2003LP

2009-03-31 5

Optical Characteristics

Notes:

1) The displa ys are categ orized for luminous intensity with the intensity category designated by a letter code on the bo ttom of the package.

2) Dominant wavelength (ldom) is derived from the CIE chromaticity diagram and represents the single wavelength which defines the color

of the device.

3) The luminous sterance of the LED may be calculated using the following relationships:

LV (cd/m2)=IV (Candela)/A (Meter)2

LV (Footlamberts)=p IV (Candela)/A (Foot)2

HDSP2000LP, A=5 58 x 10-8 m2=6 x 10-7 ft.2

HDSP2001/2/3LP, A=7.8 x 10-8m2=8.4 x 10-7ft.2

4) All typical values specified at VCC=5.0 V and TA=25°C unless otherwise noted.

Red HDSP2000LP

Description Symbol Min. Typ.4) Units Test Conditions

Peak Lumin ou s Intensity per LED1) 3)

(Character Average) IVpeak 105 200 µcd VCC=5.0 V, VCOL=3.5 V,

TJ=25°C , VB=2.4 V

Peak Wavelength λVpeak —655 nm —

Dominant Wavelength 2) λdom —639 nm —

Yellow HDSP2001LP

Description Symbol Min. Typ.4) Units Test Conditions

Peak Lumin ou s Intensity per LED1) 3)

(Character Average) IVpeak 400 1140 µcd VCC=5.0 V, VCOL=3.5 V,

TJ=25°C , VB=2.4 V

Peak Wavelength λVpeak —583 nm —

Dominant Wavelength 2) λdom —585 nm —

High Efficiency Red HDSP2002LP

Description Symbol Min. Typ.4) Units Test Conditions

Peak Lumin ou s Intensity per LED1) 3)

(Character Average) IVpeak 400 1430 µcd VCC=5.0 V, VCOL=3.5 V,

TJ=25°C , VB=2.4 V

Peak Wavelength λVpeak —635 nm —

Dominant Wavelength 2) λdom —626 nm —

Green HDSP2003LP

Description Symbol Min. Typ.4) Units Test Conditions

Peak Lumin ou s Intensity per LED1) 3)

(Character Average) IVpeak 650 1550 µcd VCC=5.0 V, VCOL=3.5 V,

TJ=25°C , VB=2.4 V

Peak Wavelength λVpeak —565 nm —

Dominant Wavelength 2) λdom —569 nm —

2009-03-31 6

HDSP2000LP, HDSP2001LP, HDSP2002LP, HDSP2003LP

Block Diagram

General Quality Assurance Levels

Generic data available.

Contrast Enhancement Filters

Display Color Ambient Lighting

Dim Moderate Bright

Red

HDSP2000LP Panelgraphic Dark Red 63

Panelgraphic Ruby Red 60

Chequers Red 118

Plexiglass 2423

Polaroid HNCP37

3M Light Control Film

Panelgraphic Gray 10

Chequers Gray 105

—

Yellow

HDSP2001LP Panelgraphic Yellow 27 Polaroid HNCP 10-Glass*

Marks Polarized MPC 30-25C**

HER

HDSP2002LP Panelgraphic Ruby Red 60

Chequers Red 112 Polaroid HNCP 10-Glass*

Marks Polarized MPC 20-15C**

Green

HDSP20013P Panelgraphic Green 48

Chequers Green 107 Polaroid HNCP 10-Glass*

Marks Polarized MPC 50-12C**

Note:

1. Optically coated circular polarized filters, such as Polaroid HNCP10.

*Polaroid Corp. **Marks Polarized Corp.

1 Upland Rd., Bldg. #2 25-B Jefryn Blvd. W

Norwood, MA 02062 Deer Park, NY 11729

800/225-2770 516/242-1300

FAX 516/242-1347

Marks Polarized Corp. manufactures

to MIL-1- 45208 inspection system.

IDBD5062

LED

Matrix

LED

Matrix

LED

Matrix

Rows 1-7 Rows 1-7 Rows 1-7

Constant Current Sinking LED Drivers

28-bit SIPO Shift Register

Rows 8-14 Rows 15-21 Rows 22-28 Serial

Data

Output

1234567

Serial

Input

Data

Control,

Blanking

Clock

Rows

12345

Column Drive Inputs

Columns

HDSP2000LP, HDSP2001LP, HDSP2002LP, HDSP2003LP

2009-03-31 7

Thermal Considerations

The small alphanumeric displays are hybrid LED and CMOS

assemblies that are designed for reliable operation in commercial,

industrial, and military environments. Optimum reliability and

optical performance will result when the junction temperature of the

LEDs and CMOS ICs are kept as low as possible.

Thermal Modeling

HSDP200XLP consist of two driver ICs and four 5 x 7 LED

matrixes. A thermal model of the display is shown in Figure

„Thermal Model“. It illustrates that the junction temperature of the

semiconductor = junction self heating + the case temperature rise

+ the ambient temperature.

Equation 1 shows this relationship.

Thermal Model

See Equation 1 below.

The junction rise within the LED is the product of the thermal

impedance of an individual LED (37°C/W, DF=20%, F=200 Hz),

times the forward voltage, VF(LED), and forward current IF(LED), of

13 – 14.5 mA. This rise averages TJ(LED)=1°C. The Table below

shows the VF(LED) for the respective displays.

The junction rise within the LED driver IC is the combination of the

power dissipated by the IC quiescen t cur rent and the 28 ro w driver

current sinks. The IC junction rise is given in Equation 2.

A thermal resistance of 28°C/W results in a typical junction rise of

6°C.

See Equation 2 below.

For ease of calculations the maximum allowable electrical operat-

ing condition is dependent upon the aggregate thermal resistance

of the LED matrixe s and the tw o driv e r ICs. All of the thermal man-

agement calculations are based upon the parallel combination of

these two networks which is 15°C/W. Maximum allowable power

dissipation is given in Equation 3.

Equation 3.

For further reference see Figures „Maximum Allowable Power Dis-

sipation vs. Temperature“ (page 3) and Figures from page 8 on.

Key to equation symbols

DF Duty factor

ICC Quiescent IC current

ICOL Column current

n Number of LEDs on in a 5 x 7 array

PCASE Package power dissipation excluding LED

under consideration

PCOL Power dissipation of a column

PDISPLAY Power dissipation of the display

PLED Power dissipation of a LED

RqCA Thermal resistance case to ambient

RqJC Thermal resistance junction to case

TAAmbient temperature

TJ(IC) Junction temperature of an IC

TJ(LED) Junction temperature of a LED

TJ(MAX) Maximum junction temperature

VCC IC voltage

VCOL Column voltage

VF(LED) Forward voltage of LED

ZqJC Thermal impedance junction to case

Equation 1.

Equation 2.

Model Number VF

Min. Typ. Max.

HDSP2000LP 1.6 1.7 2.0

HSDP2001/2/3LP 1.9 2.2 3.0

IDDG5321

LED Power

LED

IC Power

θ2

LED Power

θ1

LED

LED Power

LED

IC Power

LED Power

1θ

LED

PDISPLAY

TJMAX()

–

RθJC RθCA

----------------------------------------=

PDISPLAY 5VCOL ICOL n35⁄()DF VCC ICC

TJ LED()

PLED ZθJC PCASE RθJC RθCA

+()TA

++=

TJ LED()ICOL 28⁄()VF LED()

ZθJC

[]n35⁄()ICOL DF 5VCOL

()VCC ICC

+[]RθJC RθCA

+[]TA

+⋅+=

TJIC() PCOL RθJC RθCA

+()TA

TJIC() 5V

COL VFLED()

–()ICOL 2⁄()n35⁄()DF⋅⋅ VCC ICC

⋅+[]RθJC RθCA

+[]⋅TA

HDSP2000LP, HDSP2001LP, HDSP2002LP, HDSP2003LP

2009-03-31 8

Optical Considerations

The light output of the LEDs is in v ersely r elated to the LED diode’s

junction temperature as shown in Figure „Normalized Luminous

Intensity vs. J unction Temperature“. F or optimum light output, k eep

the thermal resistance of the socket or PC board as low as possi-

ble.

Normalized Luminous Intensity vs.

Junction Temperature

When mounted in a 10°C/W so c ket and operate d at Absolute Max-

imum Electrical conditions, the HDSP200XLP will show an LED

junction rise of 17°C. lf TA=40°C, then the LED’s TJ will be 57°C.

Under these conditions the following figure shows that the I V will

be 75% of its 25°C value.

Maximum LED Junction Temperature vs.

Socket Thermal Resistance

Maximum Package Power Dissipation

Package Power Dissipation

IDDG5326

-60

Normalized

Luminous Intensity

-40 -20 0 20 40 60 80 100 ˚C 140

-1

= 25 ˚C

Normalized to:

IDDG5327

Socket Thermal

n = 20 LEDs, DF = 20%

COL

= 3.5 V, COL

= 410 mA

= 5.25 V,

= 10 mA

˚C

510 15 20 25 30 35 ˚C/W 50

Resistance

= 0.87 W

IDDG5328

= 25 ˚C

LEDs on per Character

510 15 20 25 30 35 40

DF = 20%,

COL

= 3.5 V,

COL

= 410 mA

= 5.25 V,

= 10 mA

0.5

1.0

1.5

IDDG5329

= 25 ˚C

LEDs on per Character

510 15 20 25 30 35 40

DF = 20%,

COL

= 3.5 V,

COL

= 410 mA

= 5.25 V,

= 10 mA

0.5

1.0

1.5

HDSP2000LP, HDSP2001LP, HDSP2002LP, HDSP2003LP

2009-03-31 9

Maximum Character Power Dissipation

Character Power Dissipation

Soldering Considerations

The HDSP200xLP can be hand soldered using a grounded iron

set to 260°C.

The display is compatible with leadfree and tin/lead solder. Wave

soldering is also possible f ollowing these conditions . Preheat does

not exceed 93°C on the solder side of the PC board or a package

surface temperature of 85°C. Water soluble organic acid flux (ex-

cept carboxylic acid) or resin-based RMA flux without alcohol can

be used.

W ave temperature of 245°C +/-5°C with a dwell between 1.5 sec. to

3 sec. Exposure to the wave should not exceed temperatures

above 260°C for five seconds at 0.063 inches below the seating

plane. The packages should not be immersed in the wave.

IDDG5330

= 25 ˚C

LEDs on per Character

510 15 20 25 30 35 40

DF = 20%,

COL

= 3.5 V,

COL

= 410 mA

= 5.25 V,

= 10 mA

0.5

1.0

1.5

IDDG5331

LEDs on per Character

5 10152025303540

Duty Factor = 5%

COL

= 3.5 V,

COL

= 335 mA

= 5 V,

= 5 mA

0.5

1.0

1.5

2.0

10%

17%

20%

2009-03-31 10

HDSP2000LP, HDSP2001LP, HDSP2002LP, HDSP2003LP

Cleaning the Displays

IMPORTANT— Do not use cleaning agents containing alcohol of any type with this display. The least of fensiv e

cleaning solution is hot D.l. water (60 °C) for less than 15 minutes. Addition of mild sa ponifiers is acceptable. Do not u se

commercial dishwasher detergents.

For post solder cleaning use water or non-alcohol mixtures formulated for vapor cleaning processing or non-alcohol

mixtures formulated for room temperature cleaning. Nonalcohol vapor cleaning processing for up to two minutes in

vapors at boiling is permissible. For suggested solvents refer to Appnote 19 at www.osram-os.com

Published by

OSRAM Opto Semiconductors GmbH

Leibnizstrasse 4, D-93055 Regensburg

www.osram-os.com

Attention please!

The information describes the type of component and shall not be considered as assured characteristics.

Terms of delivery and rights to change design reserved. Due to technical requirements components may contain

dangerous substances. For information on the types in question please contact our Sales Organization.

If printed or downloaded, please find the latest version in the Interne t.

Packing

Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office.

By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing

material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs

incurred.

Components used in life-support devices or systems must be expressly authorized for such purpose! Critical

components1) may only be used in life-support devices or systems2) with the express written approval of OSRAM OS.

1) A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure

of that life-support device or system, or to affect its safety or the effectiveness of that device or system.

2) Life support devices or systems are intended (a) to be implanted in th e human body, or (b) to support and/or maintain and susta in human

life. If they fail, it is reasonable to assume that the health and the life of the user may be endangered.

Revision History: 2009-03-31

Previous Version: 2008-09-03

Page Subjects (major changes since last revision) Date of change

all Lead free device 2006-01-23

update of outline drawing 2008-09-03

2ordering code corrected 2009-03-31