Semiconductor Components Industries, LLC, 2005
January, 2005 − Rev. 5 1Publication Order Number:
MC74LCX541/D
MC74LCX541
Low−Voltage CMOS Octal
Buffer Flow Through Pinout
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
The MC74LCX541 is a high performance, non−inverting octal
buffer operating from a 2.3 to 3.6 V supply. This device is similar in
function to the MC74LCX244, while providing flow through
architecture. High impedance TTL compatible inputs significantly
reduce current loading to input drivers while TTL compatible outputs
offer improved switching noise performance. A VI specification of
5.5 V allows MC74LCX541 inputs to be safely driven from 5 V
devices. The MC74LCX541 is suitable for memory address driving
and all TTL level bus oriented transceiver applications.
Current drive capability is 24 mA at the outputs. The Output Enable
(OE1. OE2) inputs, when HIGH, disables the output by placing them
in a HIGH Z condition.
Features
•Designed for 2.3 to 3.6 V VCC Operation
•5 V Tolerant − Interface Capability With 5 V TTL Logic
•Supports Live Insertion and Withdrawal
•IOFF Specification Guarantees High Impedance When VCC = 0 V
•LVTTL Compatible
•LVCMOS Compatible
•24 mA Balanced Output Sink and Source Capability
•Near Zero Static Supply Current in All Three Logic States (10 A)
Substantially Reduces System Power Requirements
•Latchup Performance Exceeds 500 mA
•ESD Performance: Human Body Model >2000 V
Machine Model >200 V
•Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
20
1
1
20
MARKING
DIAGRAMS
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
SOIC−20
DW SUFFIX
CASE 751D
LCX541
AWLYYWW
LCX
541
ALYW
TSSOP−20
DT SUFFIX
CASE 948E
SOEIAJ−20
M SUFFIX
CASE 967
74LCX541
AWLYWW
1
1
1
20
1
20
20
20
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
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MC74LCX541
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2
Figure 1. Pinout: 20−Lead (Top View)
1920 18 17 16 15 14
21 34567
VCC
13
8
12
9
11
10
OE2 O0 O1 O2 O3 O4 O5 O6 O7
OE1 D0 D1 D2 D3 D4 D5 D6 D7 GND
Figure 2. LOGIC DIAGRAM
OE1 1
D0 2O0
18
D1 3O1
17
D2 4O2
16
D3 5O3
15
D4 6O4
14
D5 7O5
13
D6 8O6
12
D7 9O7
11
OE2 19
PIN NAMES
Function
Output Enable Inputs
Data Inputs
3−State Outputs
Pins
OEn
Dn
On
TRUTH TABLE
INPUTS OUTPUTS
OE1 OE2 Dn On
L L L L
L L H H
X H X Z
H X X Z
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance
State; X = High or Low Voltage Level and Transitions are Acceptable, for
ICC reasons, DO NOT FLOAT Inputs
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MAXIMUM RATINGS
Symbol Parameter Value Condition Unit
VCC DC Supply Voltage −0.5 to +7.0 V
VIDC Input Voltage −0.5 ≤ VI ≤ +7.0 V
VODC Output Voltage −0.5 ≤ VO ≤ +7.0 Output in 3−State V
−0.5 ≤ VO ≤ VCC + 0.5 Note 1 V
IIK DC Input Diode Current −50 VI < GND mA
IOK DC Output Diode Current −50 VO < GND mA
+50 VO > VCC mA
IODC Output Source/Sink Current ±50 mA
ICC DC Supply Current Per Supply Pin ±100 mA
IGND DC Ground Current Per Ground Pin ±100 mA
TSTG Storage Temperature Range −65 to +150 °C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Output in HIGH or LOW State. IO absolute maximum rating must be observed.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage Operating
Data Retention Only 2.0
1.5 3.3
3.3 3.6
3.6 V
VIInput Voltage 0 5.5 V
VOOutput Voltage (HIGH or LOW State)
(3−State) 0
0VCC
5.5 V
IOH HIGH Level Output Current, VCC = 3.0 V − 3.6 V −24 mA
IOL LOW Level Output Current, VCC = 3.0 V − 3.6 V 24 mA
IOH HIGH Level Output Current, VCC = 2.7 V − 3.0 V −12 mA
IOL LOW Level Output Current, VCC = 2.7 V − 3.0 V 12 mA
TAOperating Free−Air Temperature −40 +85 °C
t/VInput Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V 0 10 ns/V
ORDERING INFORMATION
Device Package Shipping†
MC74LCX541DW SOIC−20 38 Units / Rail
MC74LCX541DWG SOIC−20
(Pb−Free) 38 Units / Rail
MC74LCX541DWR2 SOIC−20 1000 Tape & Reel
MC74LCX541DR2G SOIC−20
(Pb−Free) 1000 Tape & Reel
MC74LCX541DT TSSOP−20* 75 Units / Rail
MC74LCX541DTR2 TSSOP−20* 2000 Tape & Reel
MC74LCX541MEL SOEIAJ−20 2000 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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4
DC ELECTRICAL CHARACTERISTICS
TA = −40°C to +85°C
Symbol Characteristic Condition Min Max Unit
VIH HIGH Level Input Voltage (Note 2) 2.7 V ≤ VCC ≤ 3.6 V 2.0 V
VIL LOW Level Input Voltage (Note 2) 2.7 V ≤ VCC ≤ 3.6 V 0.8 V
VOH HIGH Level Output Voltage 2.7 V ≤ VCC ≤ 3.6 V; IOH = −100 A VCC − 0.2 V
VCC = 2.7 V; IOH = −12 mA 2.2
VCC = 3.0 V; IOH = −18 mA 2.4
VCC = 3.0 V; IOH = −24 mA 2.2
VOL LOW Level Output Voltage 2.7 V ≤ VCC ≤ 3.6 V; IOL = 100 A 0.2 V
VCC = 2.7 V; IOL= 12 mA 0.4
VCC = 3.0 V; IOL = 16 mA 0.4
VCC = 3.0 V; IOL = 24 mA 0.55
IIInput Leakage Current 2.7 V ≤ VCC ≤ 3.6 V; 0 V ≤ VI ≤ 5.5 V ±5.0 A
IOZ 3−State Output Current 2.7 ≤ VCC ≤ 3.6 V; 0 V ≤ VO ≤ 5.5 V;
VI = VIH or V IL ±5.0 A
IOFF Power−Off Leakage Current VCC = 0 V; VI or VO = 5.5 V 10 A
ICC Quiescent Supply Current 2.7 ≤ VCC ≤ 3.6 V; VI = GND or VCC 10 A
CC
y
2.7 ≤ VCC ≤ 3.6 V; 3.6 ≤ VI or VO ≤ 5.5 V ±10 A
ICC Increase in ICC per Input 2.7 ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V 500 A
2. These values of VI are used to test DC electrical characteristics only.
AC ELECTRICAL CHARACTERISTICS (tR = tF = 2.5 ns; CL = 50 pF; RL = 500 )
Limits
TA = −40°C to +85°C
VCC = 3.0 V to 3.6 V VCC = 2.7 V
Symbol Parameter Waveform Min Max Max Unit
tPLH
tPHL
Propagation Delay
Input to Output 1 1.5
1.5 6.5
6.5 7.5
7.5 ns
tPZH
tPZL
Output Enable Time to
High and Low Level 2 1.5
1.5 8.5
8.5 9.5
9.5 ns
tPHZ
tPLZ
Output Disable Time From
High and Low Level 2 1.5
1.5 7.5
7.5 8.5
8.5 ns
tOSHL
tOSLH
Output−to−Output Skew (Note 3) 1.0
1.0 ns
3. Skew is defined as the absolute value of the dif ference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
DYNAMIC SWITCHING CHARACTERISTICS
TA = +25°C
Symbol Characteristic Condition Min Typ Max Unit
VOLP Dynamic LOW Peak Voltage (Note 4) VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V 0.8 V
VOLV Dynamic LOW Valley Voltage (Note 4) VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V 0.8 V
4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol Parameter Condition Typical Unit
CIN Input Capacitance VCC = 3.3 V, VI = 0 V or VCC 7 pF
COUT Output Capacitance VCC = 3.3 V, VI = 0 V or VCC 8 pF
CPD Power Dissipation Capacitance 10 MHz, VCC = 3.3 V, VI = 0 V or VCC 25 pF
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WAVEFORM 1 − PROPAGATION DELAYS
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
2.7 V
0 V
VOH
VOL
Dn
On
tPHL
tPLH
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
2.7 V
0 V
≈ 0 V
OEn
On
tPZH
≈ 3.0 V
tPHZ
tPZL tPLZ
On
1.5 V
1.5 V
1.5 V1.5 V
1.5 V 1.5 V
Figure 3. AC Waveforms
1.5 V
VCC
VOH − 0.3 V
VOL + 0.3 V
GND
OPEN
PULSE
GENERATOR
RT
DUT
VCC
RL
R1
CL
6 V
GND
TEST SWITCH
tPLH, tPHL Open
tPZL, tPLZ 6 V
Open Collector/Drain tPLH and tPHL 6 V
tPZH, tPHZ GND
CL = 50 pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 500 or equivalent
RT = ZOUT of pulse generator (typically 50 )
Figure 4. Test Circuit
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PACKAGE DIMENSIONS
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
20
1
11
10
B20X
H10X
C
L
18X A1
A
SEATING
PLANE
hX 45
E
D
M
0.25 M
B
M
0.25 S
AS
B
T
eT
B
A
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D12.65 12.95
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
0 7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE B
DIM
A
MIN MAX MIN MAX
INCHES
6.60 0.260
MILLIMETERS
B4.30 4.50 0.169 0.177
C1.20 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.27 0.37 0.011 0.015
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN
FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
110
1120
PIN 1
IDENT
A
B
−T−
0.100 (0.004)
C
DGH
SECTION N−N
K
K1
JJ1
N
N
M
F
−W−
SEATING
PLANE
−V−
−U−
S
U
M
0.10 (0.004) V S
T
20X REFK
L
L/2
2X
S
U0.15 (0.006) T
DETAIL E
0.25 (0.010)
DETAIL E 6.40 0.252
−−− −−−
S
U0.15 (0.006) T
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7
PACKAGE DIMENSIONS
SOEIAJ−20
M SUFFIX
CASE 967−01
ISSUE O
DIM MIN MAX MIN MAX
INCHES
−−− 2.05 −−− 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.18 0.27 0.007 0.011
12.35 12.80 0.486 0.504
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
−−− 0.81 −−− 0.032
A1
HE
Q1
LE
10 0
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
HE
A1
LEQ1
c
A
ZD
E
20
110
11
b
M
0.13 (0.005)
e
0.10 (0.004)
VIEW P
DETAIL P
M
L
A
b
c
D
E
e
L
M
Z
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to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74LCX541/D
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