MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
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1
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Low Supply Voltage Range, 2.7 V to 3.6 V
Ultralow Power Consumption:
− Active Mode: 400 µA at 1 MHz, 3.0 V
− Standby Mode: 1.6 µA
− Off Mode (RAM Retention): 0.1 µA
Five Power-Saving Modes
Wake-Up From Standby Mode in Less
Than 6 µs
Frequency-Locked Loop, FLL+
16-Bit RISC Architecture,
125-ns Instruction Cycle Time
Embedded Signal Processing for
Single-Phase Energy Metering With
Integrated Analog Front-End and
Temperature Sensor (ESP430CE1)
16-Bit Timer_A With Three
Capture/Compare Registers
Integrated LCD Driver for 128 Segments
Serial Communication Interface (USART),
Asynchronous UART or Synchronous SPI
Selectable by Software
Brownout Detector
Supply Voltage Supervisor/Monitor With
Programmable Level Detection
Serial Onboard Programming,
No External Programming Voltage Needed,
Programmable Code Protection by Security
Fuse
Bootstrap Loader in Flash Devices
Family Members Include:
− MSP430FE423:
8KB + 256B Flash Memory,
256B RAM
− MSP430FE425:
16KB + 256B Flash Memory,
512B RAM
− MSP430FE427:
32KB + 256B Flash Memory,
1KB RAM
Available in 64-Pin Quad Flat Pack (QFP)
For Complete Module Descriptions, Refer
to the MSP430x4xx Family User’s Guide,
Literature Number SLAU056
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6µs.
The MSP430FE42x series are microcontroller configurations with three independent 16-bit sigma-delta
analog-to-digital (A/D) converters and an embedded signal processor core used to measure and calculate
single-phase energy in both 2-wire and 3-wire configurations. Also included are a built-in 16-bit timer, 128 LCD
segment drive capability, and 14 I/O pins.
Typical applications include 2-wire and 3-wire single-phase metering including tamper-resistant meter
implementations.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Copyright 2008 Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
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AVAILABLE OPTIONS
PACKAGED DEVICES
TAPLASTIC 64-PIN QFP
(PM)
−40°C to 85°C
MSP430FE423IPM
MSP430FE425IPM
MSP430FE427IPM
pin designation
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P1.5/TACLK/ACLK/S28
P2.3/SVSIN
P2.4/UTXD0
P2.5/URXD0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1/S31
P1.3/SVSOUT/S3
0
P1.4/S29
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1.6/SIMO0/S27
P1.7/SOMI0/S26
P2.0/TA2/S25
P2.1/UCLK0/S24
R33
R23
R13
R03
COM3
COM2
COM1
COM0
S23
S21
S22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I1+
I1−
I2+
I2−
V1+
V1−
XIN
XOUT
P2.2/STE0
S0
S1
S2
S4
S3
MSP430FE42x
VREF
AVCC
DVCC
AVSS
DVSS
†Open connection recommended for all unused analog inputs.
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
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functional block diagram
DVCC DVSS AVCC AVSS
RST/NMI
P1
Flash
32KB
16KB
8KB
RAM
1KB
512B
256B
Watchdog
WDT+
15/16-Bit
Timer_A3
3 CC Reg
Port 1
8 I/O
Interrupt
Capability
POR/
SVS/
Brownout
Basic
Timer 1
1 Interrupt
Vector
LCD
128
Segments
1,2,3,4 MUX
fLCD
8
USART0
UART or
SPI
Function
ESP430CE1
Embedded
Signal
Processing,
Analog
Front-End
Oscillators
FLL+
MCLK
8 MHz
CPU
incl. 16
Registers
XOUT
JTAG
Interface
XIN
SMCLK
ACLK
MDB
MAB
Emulation
P2
Port 2
6 I/O
Interrupt
Capability
6
Module
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
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Terminal Functions
TERMINAL
PN I/O DESCRIPTION
NAME NO.
I/O
DESCRIPTION
DVCC 1Digital supply voltage, positive terminal.
I1+ 2 I Current 1 positive analog input. − Internal connection to SD16 Channel 0 A0+. (see Note 1)
I1− 3 I Current 1 negative analog input. − Internal connection to SD16 Channel 0 A0−. (see Note 1)
I2+ 4 I Current 2 positive analog input. − Internal connection to SD16 Channel 1 A0+. (see Note 1)
I2− 5 I Current 2 negative analog input. − Internal connection to SD16 Channel 1 A0−. (see Note 1)
V1+ 6 I Voltage 1 positive analog input. − Internal connection to SD16 Channel 2 A0+. (see Note 1)
V1− 7 I Voltage 1 negative analog input. − Internal connection to SD16 Channel 2 A0−. (see Note 1)
XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9 O Output terminal of crystal oscillator XT1
VREF 10 I/O Input for an external reference voltage / internal reference voltage output (can be used as mid-voltage)
P2.2/STE0 11 I/O General-purpose digital I/O / slave transmit enable—USART0/SPI mode
S0 12 O LCD segment output 0
S1 13 O LCD segment output 1
S2 14 O LCD segment output 2
S3 15 O LCD segment output 3
S4 16 O LCD segment output 4
S5 17 O LCD segment output 5
S6 18 O LCD segment output 6
S7 19 O LCD segment output 7
S8 20 O LCD segment output 8
S9 21 O LCD segment output 9
S10 22 O LCD segment output 10
S11 23 O LCD segment output 11
S12 24 O LCD segment output 12
S13 25 O LCD segment output 13
S14 26 O LCD segment output 14
S15 27 O LCD segment output 15
S16 28 O LCD segment output 16
S17 29 O LCD segment output 17
S18 30 O LCD segment output 18
S19 31 O LCD segment output 19
S20 32 O LCD segment output 20
S21 33 O LCD segment output 21
S22 34 O LCD segment output 22
S23 35 O LCD segment output 23
COM0 36 O Common output, COM0−3 are used for LCD backplanes.
COM1 37 O Common output, COM0−3 are used for LCD backplanes.
COM2 38 O Common output, COM0−3 are used for LCD backplanes.
COM3 39 O Common output, COM0−3 are used for LCD backplanes.
R03 40 I Input port of fourth positive (lowest) analog LCD level (V5)
NOTE 1: Open connection recommended for all unused analog inputs.
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
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Terminal Functions (Continued)
TERMINAL
PN I/O DESCRIPTION
NAME NO.
R13 41 I Input port of third most positive analog LCD level (V4 or V3)
R23 42 I Input port of second most positive analog LCD level (V2)
R33 43 O Output port of most positive analog LCD level (V1)
P2.1/UCLK0/S24 44 I/O General-purpose digital I/O / external clock input-USART0/UART or SPI mode, clock output—USART0/SPI
mode / LCD segment output 24 (See Note 1)
P2.0/TA2/S25 45 I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, Compare: Out2 output / LCD segment output
25 (See Note 1)
P1.7/SOMI0/S26 46 I/O General-purpose digital I/O / slave out/master in of USART0/SPI mode / LCD segment output 26
(See Note 1)
P1.6/SIMO0/S27 47 I/O General-purpose digital I/O / slave in/master out of USART0/SPI mode / LCD segment output 27
(See Note 1)
P1.5/TACLK/
ACLK/S28 48 I/O General-purpose digital I/O / Timer_A and SD16 clock signal TACLK input / ACLK output (divided by 1,
2, 4, or 8) / LCD segment output 28 (See Note 1)
P1.4/S29 49 I/O General-purpose digital I/O / LCD segment output 29 (See Note 1)
P1.3/SVSOUT/
S30 50 I/O General-purpose digital I/O / SVS: output of SVS comparator / LCD segment output 30 (See Note 1)
P1.2/TA1/S31 51 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A, CCI1B input, Compare: Out1 output / LCD segment
output 31 (See Note 1)
P1.1/TA0/MCLK 52 I/O General-purpose digital I/O / Timer_A, Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0 53 I/O General-purpose digital I/O / Timer_A, Capture: CCI0A input, Compare: Out0 output / BSL transmit
TDO/TDI 54 I/O Test data output port. TDO/TDI data output or programming data input terminal.
TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI.
TMS 56 I Test mode select. TMS is used as an input port for device programming and test.
TCK 57 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 58 I Reset input or nonmaskable interrupt input port
P2.5/URXD0 59 I/O General-purpose digital I/O / receive data in—USART0/UART mode
P2.4/UTXD0 60 I/O General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/SVSIN 61 I/O General-purpose digital I/O / Analog input to brownout, supply voltage supervisor
AVSS 62 Analog supply voltage, negative terminal. Supplies SD16, SVS, brownout, oscillator, and LCD resistive
divider circuitry.
DVSS 63 Digital supply voltage, negative terminal.
AVCC 64 Analog supply voltage, positive terminal. Supplies SD16, SVS, brownout, oscillator, and LCD resistive
divider circuitry; must not power up prior to DVCC.
NOTE 1: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.
General-Purpose Register
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R12
R13
General-Purpose Register
General-Purpose Register
R6
R7
General-Purpose Register
General-Purpose Register
R8
R9
General-Purpose Register
General-Purpose Register
R10
R11
General-Purpose Register
General-Purpose Register
R14
R15
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
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short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator, respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
Table 1. Instruction Word Formats
Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 −−−> R5
Single operands, destination only e.g. CALL R8 PC −−>(TOS), R8−−> PC
Relative jump, un/conditional e.g. JNE Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register MOV Rs,Rd MOV R10,R11 R10 −−> R11
Indexed MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)−−> M(6+R6)
Symbolic (PC relative) MOV EDE,TONI M(EDE) −−> M(TONI)
Absolute MOV &MEM,&TCDAT M(MEM) −−> M(TCDAT)
Indirect MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) −−> M(Tab+R6)
Indirect
autoincrement MOV @Rn+,Rm MOV @R10+,R11 M(R10) −−> R11
R10 + 2−−> R10
Immediate MOV #X,TONI MOV #45,TONI #45 −−> M(TONI)
NOTE: S = source D = destination
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
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operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
Active mode (AM)
− All clocks are active
Low-power mode 0 (LPM0)
− CPU is disabled
ACLK and SMCLK remain active, MCLK is available to modules
FLL+ loop control remains active
Low-power mode 1 (LPM1)
− CPU is disabled
ACLK and SMCLK remain active, MCLK is available to modules
FLL+ loop control is disabled
Low-power mode 2 (LPM2)
− CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
Low-power mode 3 (LPM3)
− CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
Low-power mode 4 (LPM4)
− CPU is disabled
ACLK is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
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interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-up
External Reset
Watchdog
Flash memory
PC Out-of-Range (see Note 4)
WDTIFG
KEYV
(see Note 1)
Reset 0FFFEh 15, highest
NMI
Oscillator Fault
Flash memory access violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh 14
ESP430
MBCTL_OUTxIFG,
MBCTL_INxIFG
(see Notes 1 and 2)
Maskable 0FFFAh 13
SD16
SD16CCTLx SD16OVIFG,
SD16CCTLx SD16IFG
(see Notes 1 and 2)
Maskable 0FFF8h 12
0FFF6h 11
Watchdog Timer WDTIFG Maskable 0FFF4h 10
USART0 Receive URXIFG0 Maskable 0FFF2h 9
USART0 Transmit UTXIFG0 Maskable 0FFF0h 8
0FFEEh 7
Timer_A3 TACCR0 CCIFG (see Note 2) Maskable 0FFECh 6
Timer_A3
TACCR1 and TACCR2
CCIFGs, and TACTL TAIFG
(see Notes 1 and 2)
Maskable 0FFEAh 5
I/O port P1 (eight flags) P1IFG.0 to P1IFG.7
(see Notes 1 and 2) Maskable 0FFE8h 4
0FFE6h 3
0FFE4h 2
I/O port P2 (eight flags) P2IFG.0 to P2IFG.7
(see Notes 1 and 2) Maskable 0FFE2h 1
Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.
4. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh) or from
within unused address ranges (from 0600h to 0BFFh).
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
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special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1 and 2
7654 0
UTXIE0 OFIE WDTIE
32 1
rw–0 rw–0 rw–0
Address
0h URXIE0 ACCVIE NMIIE
rw–0 rw–0 rw–0
WDTIE: Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
OFIE: Oscillator-fault interrupt enable
NMIIE: Nonmaskable interrupt enable
ACCVIE: Flash access violation interrupt enable
URXIE0: USART0: UART and SPI receive interrupt enable
UTXIE0: USART0: UART and SPI transmit interrupt enable
7654 0321
Address
1h BTIE
rw-0
BTIE: Basic Timer1 interrupt enable
interrupt flag register 1 and 2
7654 0
UTXIFG0 OFIFG WDTIFG
32 1
rw–0 rw–1 rw–(0)
Address
02h URXIFG0 NMIIFG
rw–1 rw–0
WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC
power up or a reset condition at the RST/NMI pin in reset mode.
OFIFG: Flag set on oscillator fault
NMIIFG: Set via RST/NMI pin
URXIFG0: USART0: UART and SPI receive flag
UTXIFG0: USART0: UART and SPI transmit flag
7654 0321
Address
3h BTIFG
rw-0
BTIFG: Basic Timer1 interrupt flag
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
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module enable registers 1 and 2
7654 0
UTXE0
32 1
rw–0 rw–0
Address
04h URXE0
USPIE0
URXE0: USART0: UART mode receive enable
UTXE0: USART0: UART mode transmit enable
USPIE0: USART0: SPI mode transmit and receive enable
7654 0321
Address
05h
Legend: rw−0,1: Bit Can Be Read and Written. It Is Reset or Set by PUC.
rw−(0,1): Bit Can Be Read and Written. It Is Reset or Set by POR.
SFR Bit Not Present in Device.
memory organization
MSP430FE423 MSP430FE425 MSP430FE427
Memory
Interrupt vector
Code memory
Size
Flash
Flash
8KB
0FFFFh − 0FFE0h
0FFFFh − 0E000h
16KB
0FFFFh − 0FFE0h
0FFFFh − 0C000h
32KB
0FFFFh − 0FFE0h
0FFFFh − 08000h
Information memory Size 256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Boot memory Size 1kB
0FFFh − 0C00h
1kB
0FFFh − 0C00h
1kB
0FFFh − 0C00h
RAM Size 256 Byte
02FFh − 0200h
512 Byte
03FFh − 0200h
1KB
05FFh − 0200h
Peripherals 16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
BSL Function PM Package Pins
Data Transmit 53 - P1.0
Data Receive 52 - P1.1
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
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flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
Flash memory has n segments of main memory and two segments of information memory (A and B) of
128 bytes each. Each segment in main memory is 512 bytes in size.
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A and B can be erased individually, or as a group with segments 0 to n.
Segments A and B are also called information memory.
New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
Segment 0
With Interrupt Vectors
Segment 1
Segment 2
Segment n−1
Segment n
32KB
Segment A
Segment B
Main Memory
Information Memory
0FFFFh
0FA00h
0FE00h
0FDFFh
0FC00h
0FBFFh
0F9FFh
08400h
083FFh
08200h
081FFh
01000h
010FFh
08000h
01080h
0107Fh
16KB
0FFFFh
0FA00h
0FE00h
0FDFFh
0FC00h
0FBFFh
0F9FFh
0C400h
0C3FFh
0C200h
0C1FFh
01000h
010FFh
0C000h
01080h
0107Fh
8KB
0FFFFh
0FA00h
0FE00h
0FDFFh
0FC00h
0FBFFh
0F9FFh
0E400h
0E3FFh
0E200h
0E1FFh
01000h
010FFh
0E000h
01080h
0107Fh
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide, literature
number SLAU056.
oscillator and system clock
The clock system in the MSP430FE42x family of devices is supported by the FLL+ module that includes support
for a 32768 Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency
crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and
low-power consumption. The FLL+ features a digital frequency locked loop (FLL) hardware which in conjunction
with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.
The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The FLL+ module
provides the following clock signals:
Auxiliary clock (ACLK), sourced from a 32768 Hz watch crystal or a high frequency crystal.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must ensure the default FLL+ settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are two 8-bit I/O ports implemented—ports P1 and P2 (only six P2 I/O signals are available on external
pins):
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of port P1 and six bits of P2.
Read/write access to port-control registers is supported by all instructions.
NOTE:
Six bits of port P2 (P2.0 to P2.5) are available on external pins, but all control and data bits for port
P2 are implemented.
Basic Timer1
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and
clock for the LCD module.
LCD drive
The LCD driver generates the segment and common signals required to drive an LCD display. The LCD
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
WDT+ watchdog timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_A3 SIGNAL CONNECTIONS
INPUT PIN
NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE
BLOCK
MODULE OUTPUT
SIGNAL OUTPUT PIN NUMBER
48 - P1.5 TACLK TACLK
ACLK ACLK
Timer
NA
SMCLK SMCLK Timer NA
48 - P1.5 TACLK INCLK
53 - P1.0 TA0 CCI0A 53 - P1.0
52 - P1.1 TA0 CCI0B
CCR0
TA0
DVSS GND CCR0 TA0
DVCC VCC
51 - P1.2 TA1 CCI1A 51 - P1.2
51 - P1.2 TA1 CCI1B
CCR1
TA1
DVSS GND CCR1 TA1
DVCC VCC
45 - P2.0 TA2 CCI2A 45 - P2.0
ACLK (internal) CCI2B
CCR2
TA2
DVSS GND CCR2 TA2
DVCC VCC
USART0
The MSP430FE42x devices have one hardware universal synchronous/asynchronous receive transmit
(USART0) peripheral module that is used for serial data communication. The USART supports synchronous
SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive
channels.
ESP430CE1
The ESP430CE1 module integrates a hardware multiplier, three independent 16-bit Sigma-Delta A/D
converters (SD16) and an embedded signal processor (ESP430). The ESP430CE1 module measures 2 or
3-wire, single-phase energy and automatically calculates parameters which are made available to the MSP430
CPU. The module can be calibrated and initialized to accurately calculate energy, power factor, etc., for a wide
range of metering sensor configurations.
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog Watchdog Timer control WDTCTL 0120h
Timer_A3 Timer_A interrupt vector TAIV 012Eh
_
Timer_A control TACTL 0160h
Capture/compare control 0 TACCTL0 0162h
Capture/compare control 1 TACCTL1 0164h
Capture/compare control 2 TACCTL2 0166h
Reserved 0168h
Reserved 016Ah
Reserved 016Ch
Reserved 016Eh
Timer_A register TAR 0170h
Capture/compare register 0 TACCR0 0172h
Capture/compare register 1 TACCR1 0174h
Capture/compare register 2 TACCR2 0176h
Reserved 0178h
Reserved 017Ah
Reserved 017Ch
Reserved 017Eh
Hardware Multiplier Sum extend SUMEXT 013Eh
p
(see Note 1) Result high word RESHI 013Ch
Result low word RESLO 013Ah
Second operand OP2 0138h
Multiply signed + accumulate/operand1 MACS 0136h
Multiply + accumulate/operand1 MAC 0134h
Multiply signed/operand1 MPYS 0132h
Multiply unsigned/operand1 MPY 0130h
Flash Flash control 3 FCTL3 012Ch
Flash control 2 FCTL2 012Ah
Flash control 1 FCTL1 0128h
SD16 (see Note 1) General Control SD16CTL 0100h
()
(see also: Peripherals
with Byte Access)
Channel 0 Control SD16CCTL0 0102h
with Byte Access) Channel 1 Control SD16CCTL1 0104h
Channel 2 Control SD16CCTL2 0106h
Reserved 0108h
Reserved 010Ah
Reserved 010Ch
Reserved 010Eh
Interrupt vector word register SD16IV 0110h
Channel 0 conversion memory SD16MEM0 0112h
NOTE 1: Module is contained within ESP430CE1. Registers not accessible when ESP430 is active. ESP430 must be disabled or suspended
to allow CPU access to these modules.
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PERIPHERALS WITH WORD ACCESS
SD16 Channel 1 conversion memory SD16MEM1 0114h
(continued, see Note 1) Channel 2 conversion memory SD16MEM2 0116h
Reserved 0118h
Reserved 011Ah
Reserved 011Ch
Reserved 011Eh
ESP430 (ESP430CE1) ESP430 Control ESPCTL 0150h
()
Mailbox Control MBCTL 0152h
Mailbox In 0 MBIN0 0154h
Mailbox In 1 MBIN1 0156h
Mailbox Out 0 MBOUT0 0158h
Mailbox Out 1 MBOUT1 015Ah
ESP430 Return Value 0 RET0 01C0h
: : :
ESP430 Return Value 31 RET31 01FEh
PERIPHERALS WITH BYTE ACCESS
SD16 (see Note 1) Channel 0 Input Control SD16INCTL0 0B0h
()
(see also: Peripherals
with Word Access)
Channel 1 Input Control SD16INCTL1 0B1h
with Word Access) Channel 2 Input Control SD16INCTL2 0B2h
Reserved 0B3h
Reserved 0B4h
Reserved 0B5h
Reserved 0B6h
Reserved 0B7h
Channel 0 preload SD16PRE0 0B8h
Channel 1 preload SD16PRE1 0B9h
Channel 2 preload SD16PRE2 0BAh
Reserved 0BBh
Reserved 0BCh
Reserved 0BDh
Reserved 0BEh
Reserved 0BFh
LCD LCD memory 20 LCDM20 0A4h
: : :
LCD memory 16 LCDM16 0A0h
LCD memory 15 LCDM15 09Fh
: : :
LCD memory 1 LCDM1 091h
LCD control and mode LCDCTL 090h
NOTE 1: Module is contained within ESP430CE1. Registers not accessible when ESP430 is active. ESP430 must be disabled or suspended
to allow CPU access to these modules.
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
USART0 Transmit buffer U0TXBUF 077h
Receive buffer U0RXBUF 076h
Baud rate U0BR1 075h
Baud rate U0BR0 074h
Modulation control U0MCTL 073h
Receive control U0RCTL 072h
Transmit control U0TCTL 071h
USART control U0CTL 070h
Brownout, SVS SVS control register SVSCTL 056h
FLL+ Clock FLL+ Control1 FLL_CTL1 054h
FLL+ Control0 FLL_CTL0 053h
System clock frequency control SCFQCTL 052h
System clock frequency integrator SCFI1 051h
System clock frequency integrator SCFI0 050h
Basic Timer1 BT counter2 BTCNT2 047h
BT counter1 BTCNT1 046h
BT control BTCTL 040h
Port P2 Port P2 selection P2SEL 02Eh
Port P2 interrupt enable P2IE 02Dh
Port P2 interrupt-edge select P2IES 02Ch
Port P2 interrupt flag P2IFG 02Bh
Port P2 direction P2DIR 02Ah
Port P2 output P2OUT 029h
Port P2 input P2IN 028h
Port P1 Port P1 selection P1SEL 026h
Port P1 interrupt enable P1IE 025h
Port P1 interrupt-edge select P1IES 024h
Port P1 interrupt flag P1IFG 023h
Port P1 direction P1DIR 022h
Port P1 output P1OUT 021h
Port P1 input P1IN 020h
Special Functions SFR module enable 2 ME2 005h
p
SFR module enable 1 ME1 004h
SFR interrupt flag 2 IFG2 003h
SFR interrupt flag 1 IFG1 002h
SFR interrupt enable2 IE2 001h
SFR interrupt enable1 IE1 000h
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings†
Voltage applied at VCC to VSS −0.3 V to + 4.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to any pin (see Note 1) −0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diode current at any device terminal ±2 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature (unprogrammed device) −55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature (programmed device) −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TDI/TCLK pin when blowing the JTAG fuse.
recommended operating conditions (see Note 1)
PARAMETER MIN NOM MAX UNITS
Supply voltage during program execution; ESP430 and SD16 disabled,
VCC (AVCC = DVCC = VCC) (see Note 1) MSP430FE42x 1.8 3.6 V
Supply voltage during program execution; SVS enabled, PORON = 1,
ESP430 and SD16 disabled, VCC (AVCC = DVCC = VCC)
(see Note 1 and Note 2)
MSP430FE42x 2.0 3.6 V
Supply voltage during program execution; ESP430 or SD16 enabled or
during programming of flash memory, VCC (AVCC = DVCC = VCC)
(see Note 1)
MSP430FE42x 2.7 3.6 V
Supply voltage (see Note 1), VSS (AVSS = DVSS = VSS) 0 0 V
Operating free-air temperature range, TAMSP430FE42x −40 85 °C
LF selected, XTS_FLL=0 Watch crystal 32768 Hz
LFXT1 crystal frequency, f
(
LFXT1
)
(see Note 3) XT1 selected, XTS_FLL=1 Ceramic resonator 450 8000 kHz
LFXT1
crystal
frequency,
f(LFXT1)
(see
Note
3)
XT1 selected, XTS_FLL=1 Crystal 1000 8000 kHz
Processor frequency (signal MCLK) f (see Note 4)
VCC = 2.7 V DC 8.4
MHz
Processor frequency (signal MCLK), f(System) (see Note 4) VCC = 3.6 V DC 8.4 MHz
NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can
be tolerated during power up and operation.
2. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing supply voltage.
POR is going inactive when the supply voltage is raised above minimum supply voltage plus the hysteresis of the SVS circuitry.
3. The LFXT1 oscillator in LF-mode requires a watch crystal.
4. For frequencies above 8 MHz, MCLK is sourced by the built-in oscillator (DCO and FLL+).
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AVCC + DVCC excluding external current (see Note 1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
I(AM)
Active mode,
f(MCLK) = f(SMCLK) = f(DCO) = 1 MHz,
f(ACLK) = 32,768 Hz, XTS_FLL = 0
(program executes in flash)
TA = −40°C to 85°C VCC = 3 V 400 500 µA
I(LPM0)
Low-power mode, (LPM0/LPM1)
f(MCLK) = f(SMCLK) = f(DCO) = 1 MHz,
f(ACLK) = 32,768 Hz, XTS_FLL = 0
FN_8=FN_4=FN_3=FN_2=0 (see Note 2)
TA = −40°C to 85°C VCC = 3 V 130 150 µA
I(LPM2) Low-power mode, (LPM2) (see Note 2) TA = −40°C to 85°C VCC = 3 V 10 22 µA
TA = −40°C 1.5 2.0
Low power mode (LPM3) (see Note 2)
TA = 25°C
V3V
1.6 2.1
A
I(LPM3) Low-power mode, (LPM3) (see Note 2) TA = 60°CVCC = 3 V 1.7 2.2 µA
TA = 85°C 2.0 2.6
TA = −40°C 0.1 0.5
I
LPM4
Low-power mode, (LPM4) (see Note 2) TA = 25°CVCC = 3 V 0.1 0.5 µA
Low power
mode,
(LPM4)
(see
Note
2)
TA = 85°C
VCC
3
V
0.8 2.5
µA
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
The current consumption in LPM2, LPM3, and LPM4 are measured with active Basic Timer1 and LCD (ACLK selected).
The current consumption of the ESP430CE1 and the SVS module are specified in their respective sections.
LPMx currents measured with WDT+ disabled.
The currents are characterized with a KDS Daishinku DT−38 (6 pF) crystal.
2. Current for brownout included.
current consumption of active mode versus system frequency
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
current consumption of active mode versus supply voltage
I(AM) = I(AM) [3 V] + 170 µA/V × (VCC – 3 V)
f (MHz)
1.8 V 3.6 V
2.7 V 3 V
4.15 MHz
8.4 MHz
VCC − Supply Voltage − V
fSystem − Maximum Processor Frequency − MHz
Supply Voltage Range with
ESP430 or SD16 Enabled and During
Programming of the Flash Memory
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Supply Voltage Range
During Program
Execution
6 MHz
Figure 1. Frequency vs Supply Voltage
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Schmitt-trigger inputs − Ports P1 and P2; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIT+ Positive-going input threshold voltage VCC = 3 V 1.5 1.98 V
VIT− Negative-going input threshold voltage VCC = 3 V 0.9 1.3 V
Vhys Input voltage hysteresis (VIT+ − VIT−) VCC = 3 V 0.45 1 V
inputs Px.x, TAx
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
t
External interrupt timing
Port P1, P2: P1.x to P2.x, External tri
gg
er si
g
nal 3 V 1.5 cycle
t(int) External interrupt timing
Port
P1
,
P2:
P1
.
x
to
P2
.
x
,
External
trigger
signal
for the interrupt flag, (see Note 1) 3 V 50 ns
t(cap) Timer_A, capture timing TAx 3 V 50 ns
f(TAext)
Timer_A clock frequency
externally applied to pin TACLK, INCLK t(H) = t(L) 3 V 10 MHz
f(TAint) Timer_A clock frequency SMCLK or ACLK signal selected 3 V 10 MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with
trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in
MCLK cycles.
leakage current (see Note 1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
Ilkg(P1.x) Leaka
g
ePort P1 Port 1: V(P1.x) (see Note 2)
V=3V
±50
nA
Ilkg(P2.x)
Leakage
current Port P2 Port 2: V(P2.x) (see Note 2) VCC = 3 V ±50 nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as an input.
outputs − Ports P1 and P2
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
High level output voltage
IOH(max) = −1.5 mA, VCC = 3 V, See Note 1 VCC−0.25 VCC
V
VOH High-level output voltage IOH(max) = −6 mA, VCC = 3 V, See Note 2 VCC−0.6 VCC
V
V
Low level output voltage
IOL(max) = 1.5 mA, VCC = 3 V, See Note 1 VSS VSS+0.25
V
VOL Low-level output voltage IOL(max) = 6 mA, VCC = 3 V, See Note 2 VSS VSS+0.6 V
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the
maximum specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the
maximum specified voltage drop.
output frequency
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fPx.y (1 ≤ x ≤ 2, 0 ≤ y ≤ 7) CL = 20 pF,
IL = ± 1.5mA VCC = 3 V DC 12 MHz
fACLK,
fMCLK,
fSMCLK
P1.1/TA0/MCLK
P1.5/TACLK/ACLK/S28 CL = 20 pF VCC = 3 V 12 MHz
P1.5/TACLK/ACLK/
fACLK = fLFXT1 = fXT1 40% 60%
P1
.
5/TACLK/ACLK/
S28, CL = 20 pF fACLK = fLFXT1 = fLF 30% 70%
tXdc
Duty cycle of output frequency
S28,
CL
20
pF
VCC = 3 V fACLK = fLFXT1 50%
t
Xdc
Duty
cycle
of
output
frequency
P1.1/TA0/MCLK,
CL = 20 pF,
VCC = 3 V
fMCLK = fDCOCLK
50%−
15 ns 50% 50%+
15 ns
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1 and P2 (continued)
Figure 2
VOL − Low-Level Output Voltage − V
0
5
10
15
20
25
30
0.0 0.5 1.0 1.5 2.0 2.5
VCC = 2.2 V
P2.1
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OL
I− Typical Low-level Output Current − mA
Figure 3
VOL − Low-Level Output Voltage − V
0
10
20
30
40
50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = 3 V
P2.1
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OL
I− Typical Low-level Output Current − mA
Figure 4
VOH − High-Level Output Voltage − V
−30
−25
−20
−15
−10
−5
0
0.0 0.5 1.0 1.5 2.0 2.5
VCC = 2.2 V
P2.1
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OL
I− Typical High-level Output Current − mA
Figure 5
VOH − High-Level Output Voltage − V
−50
−40
−30
−20
−10
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = 3 V
P2.1
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OL
I− Typical High-level Output Current − mA
NOTE: One output loaded at a time
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f = 1 MHz 6
td
(
LPM3
)
Delay time f = 2 MHz VCC = 3 V 6µs
td(LPM3)
Delay
time
f = 3 MHz
VCC
3
V
6
µs
RAM (see Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRAMh CPU halted (see Note 1) 1.6 V
NOTE 1: This parameter defines the minimum supply voltage when the data in the program memory RAM remain unchanged. No program
execution should take place during this supply voltage condition.
LCD
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(33) Voltage at R33 2.5 VCC +0.2
V(23)
Analog voltage
Voltage at R23
V3V
(V33−V03) × 2/3 + V03
V
V(13)
Analog voltage Voltage at R13 VCC = 3 V (V(33)−V(03)) × 1/3 + V(03)
V
V(33) − V(03) Voltage at R33/R03 2.5 VCC +0.2
I(R03) R03 = VSS No load at all ±20
I(R13) Input leakage R13 = VCC/3 segment and
common lines
±20 nA
I(R23)
pg
R23 = 2 × VCC/3
common
li
nes,
VCC = 3 V ±20
V(Sxx0) V(03) V(03) − 0.1
V(Sxx1) Se
g
ment line
I 3 A
V3V
V(13) V(13) − 0.1
V
V(Sxx2)
Segment
line
voltage I(Sxx) = −3 µA, VCC = 3 V V(23) V(23) − 0.1 V
V(Sxx3) V(33) V(33) + 0.1
USART0 (see Note 1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
t(τ)USART0: deglitch time VCC = 3 V, SYNC = 0, UART mode 150 280 500 ns
NOTE 1: The signal applied to the USART0 receive signal/terminal (URXD0) should meet the timing requirements of t(τ) to ensure that the URXS
flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating conditions to
set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the
URXD0 line.
POR brownout, reset (see Notes 1 and 2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(BOR) 2000 µs
VCC(start) dVCC/dt ≤ 3 V/s (see Figure 6) 0.7 × V(B_IT−) V
V(B_IT−)
Brownout
dVCC/dt ≤ 3 V/s (see Figure 6, Figure 7, Figure 8) 1.71 V
Vhys(B_IT−)
B
rownout dVCC/dt ≤ 3 V/s (see Figure 6) 70 130 180 mV
t(reset)
Pulse length needed at RST/NMI pin to accepted reset internally,
VCC = 3 V 2µs
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT−)
+ Vhys(B_IT−) is ≤ 1.8 V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT−) + Vhys(B_IT−).
The default FLL+ settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired
operating frequency. See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout/SVS circuit.
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
0
1
V
VCC(start)
Vhys(B_IT−)
VCC
td(BOR)
(B_IT−)
Figure 6. POR/Brownout Reset (BOR) vs Supply Voltage
VCC (drop) − V
0
0.5
1
1.5
2
0.001 1 1000
V = 3 V
Typical Conditions
1 ns 1 ns
tpw − Pulse Width − µst
pw − Pulse Width − µs
cc
VCC
3 V
VCC(drop)
tpw
Figure 7. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
3 V
VCC(drop)
tpw
0
0.5
1
1.5
2
tpw − Pulse Width − µs
0.001 1 1000 tftr
tpw − Pulse Width − µs
tf = tr
V = 3 V
Typical Conditions
cc
VCC (drop) − V
Figure 8. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SVS (supply voltage supervisor/monitor) (see Note 1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
t
dVCC/dt > 30 V/ms (see Figure 9) 5 150
µs
t(SVSR)4 dVCC/dt ≤ 30 V/ms 2000 µs
td(SVSon) SVSon, switch from VLD=0 to VLD ≠ 0, VCC = 3 V 20 150 µs
tsettle VLD ≠ 0‡12 µs
V(SVSstart) VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 9) 1.55 1.7 V
VLD = 1 70 120 155 mV
Vh
y
s
(
SVS_IT−
)
VCC/dt ≤ 3 V/s (see Figure 9) VLD = 2 .. 14 V(SVS_IT−)
x 0.004
V(SVS_IT−)
x 0.008
Vhys(SVS
_
IT
−
)
VCC/dt ≤ 3 V/s (see Figure 9), external voltage applied
on P2.3 VLD = 15 4.4 10.4 mV
VLD = 1 1.8 1.9 2.05
VLD = 2 1.94 2.1 2.25
VLD = 3 2.05 2.2 2.37
VLD = 4 2.14 2.3 2.48
VLD = 5 2.24 2.4 2.6
VLD = 6 2.33 2.5 2.71
VCC/dt ≤3 V/s (see Figure 9)
VLD = 7 2.46 2.65 2.86
V(SVS IT )
VCC/dt ≤ 3 V/s (see Figure 9) VLD = 8 2.58 2.8 3
V
V
(SVS_IT−) VLD = 9 2.69 2.9 3.13
V
VLD = 10 2.83 3.05 3.29
VLD = 11 2.94 3.2 3.42
VLD = 12 3.11 3.35 3.61†
VLD = 13 3.24 3.5 3.76†
VLD = 14 3.43 3.7†3.99†
VCC/dt ≤ 3 V/s (see Figure 9), external voltage applied
on P2.3 VLD = 15 1.1 1.2 1.3
ICC(SVS)
(see Note 1) VLD ≠ 0, VCC = 2.2 V/3 V 10 15 µA
†The recommended operating voltage range is limited to 3.6 V.
‡tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 1: The current consumption of the SVS module is not included in the ICC current consumption data.
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
VCC(start)
VCC
V(B_IT−)
Brownout
Region
V(SVSstart)
V
Software Sets VLD>0:
SVS is Active
Undefined
0
1
Brownout
0
1
0
1
Set POR
Brownout
Region
SVS Circuit is Active From VLD > to VCC < V(B_IT−)
SVS out
Vhys(SVS_IT−)
Vhys(B_IT−)
td(BOR)
td(SVSon)
td(SVSR)
td(BOR)
(SVS_IT−)
Figure 9. SVS Reset (SVSR) vs Supply Voltage
VCC(drop)
0
0.5
1
1.5
2
1 ns 1 ns
tpw − Pulse Width − µs
1 10 1000
tftr
t − Pulse Width − µs
100
tf = tr
Rectangular Drop
VCC(drop) − V
Triangular Drop
3 V
VCC tpw
3 V
VCC tpw
VCC(drop)
Figure 10. VCC(drop) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
DCO
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
f(DCOCLK)
N(DCO)=01Eh, FN_8=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0,
fCrystal = 32.768 kHz 3 V 1 MHz
f(DCO=2) FN_8=FN_4=FN_3=FN_2=0 ; DCOPLUS = 1 3 V 0.3 0.7 1.3 MHz
f(DCO=27) FN_8=FN_4=FN_3=FN_2=0; DCOPLUS = 1 3 V 2.7 6.1 11.3 MHz
f(DCO=2) FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1 3 V 0.8 1.5 2.5 MHz
f(DCO=27) FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1 3 V 6.5 12.1 20 MHz
f(DCO=2) FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1 3 V 1.3 2.2 3.5 MHz
f(DCO=27) FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1 3 V 10.3 17.9 28.5 MHz
f(DCO=2) FN_8=0, FN_4= 1, FN_3= FN_2=x; DCOPLUS = 1 3 V 2.1 3.4 5.2 MHz
f(DCO=27) FN_8=0, FN_4=1, FN_3= FN_2=x; DCOPLUS = 1 3 V 16 26.6 41 MHz
f(DCO=2) FN_8=1, FN_4=FN_3=FN_2=x; DCOPLUS = 1 3 V 4.2 6.3 9.2 MHz
f(DCO=27) FN_8=1,FN_4=FN_3=FN_2=x; DCOPLUS = 1 3 V 30 46 70 MHz
S
Step size between adjacent DCO taps: 1 < TAP ≤ 20 1.06 1.11
Sn
Step
size
between
adjacent
DCO
taps:
Sn = fDCO(Tap n+1) / fDCO(Tap n), (see Figure 12 for taps 21 to 27) TAP = 27 1.07 1.17
Dt
Temperature drift, N(DCO) = 01Eh, FN_8=FN_4=FN_3=FN_2=0
D = 2; DCOPLUS = 0 3 V –0.2 –0.3 –0.4 %/C
DV
Drift with VCC variation, N(DCO) = 01Eh, FN_8=FN_4=FN_3=FN_2=0
D = 2; DCOPLUS = 0 0 5 15 %/V
TA − °CVCC − V
f(DCO)
f(DCO205C)
f(DCO)
f(DCO3V)
1.8 3.02.4 3.6
1.0
20 6040 85
1.0
0−20−400
Figure 11. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
12720
1.11
1.17
DCO Tap
Sn - Stepsize Ratio between DCO Taps
Min
Max
1.07
1.06
Figure 12. DCO Tap Step Size
DCO Frequency
Adjusted by Bits
29 to 25 in SCFI1 {N{DCO}}
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=x
FN_4=x
FN_8=1
Legend
Tolerance at Tap 27
Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range
f(DCO)
Figure 13. Five Overlapping DCO Ranges Controlled by FN_x Bits
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
OSCCAPx = 0h 3 V 0
C
Inte
g
rated input capacitance OSCCAPx = 1h 3 V 10
pF
CXIN
Integrated
input
capacitance
(see Note 4) OSCCAPx = 2h 3 V 14 pF
OSCCAPx = 3h 3 V 18
OSCCAPx = 0h 3 V 0
C
Inte
g
rated output capacitance OSCCAPx = 1h 3 V 10
pF
CXOUT
Integrated
output
capacitance
(see Note 4) OSCCAPx = 2h 3 V 14 pF
OSCCAPx = 3h 3 V 18
VIL
Input levels at XIN
see Note 3
2 2 V/3 V
VSS 0.2×VCC
V
VIH
Input levels at XIN see Note 3 2.2 V/3 V 0.8×VCC VCC
V
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2pF. The effective load capacitor for the crystal is
(CXIN x CXOUT) / (CXIN + CXOUT). It is independent of XTS_FLL .
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines must be
observed:
•Keep as short a trace as possible between the ’FE42x and the crystal.
•Design a good ground plane around oscillator pins.
•Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
•Avoid running PCB traces underneath or adjacent to XIN an XOUT pins.
•Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
•If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
•Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation.
This signal is no longer required for the serial programming adapter.
3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.
4. External capacitance is recommended for precision real-time clock applications; OSCCAPx = 0h.
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
ESP430CE1, SD16 and ESP430 power supply and recommended operating conditions
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
AVCC
Analog supply
voltage
AVCC = DVCC
AVSS = DVSS = 0V 2.7 3.6 V
SD16LP = 0, GAIN(V): 1, GAIN(I1): 1, I2: off 3 V 2.0 2.6
SD16LP
0,
fMCLK = 4MHz,
f f /4
GAIN(V): 1, GAIN(I1): 32, I2: off 3 V 2.4 3.3
Total Digital &
Analog supply
fSD16 = fMCLK/4,
SD16REFON
=
1,
GAIN(V): 1, GAIN(I1): 1, GAIN(I2): 1 3 V 2.7 3.6
I
Analog supply
current when
SD16REFON
=
1
,
SD16VMIDON = 0 GAIN(V): 1, GAIN(I1): 32, GAIN(I2): 32 3 V 3.4 4.9
mA
IESP430CE1
current
when
ESP430 and SD16
i
SD16LP = 1, GAIN(V): 1, GAIN(I1): 1, I2: off 3 V 1.5 2.1 mA
active
(IAVCC +I
DVCC)
SD16LP
1,
fMCLK = 2MHz,
f f /4
GAIN(V): 1, GAIN(I1): 32, I2: off 3 V 1.6 2.1
(I
AVCC +
I
DVCC
)
fSD16 = fMCLK/4,
SD16REFON
=
1,
GAIN(V): 1, GAIN(I1): 1, GAIN(I2): 1 3 V 2.1 2.8
SD16REFON
=
1
,
SD16VMIDON = 0 GAIN(V): 1, GAIN(I1): 32, GAIN(I2): 32 3 V 2.2 3.0
Analog supply
SD16LP
=
0,
GAIN: 1, 2 3 V 650 950
Analog supply
current: 1 active
SD16LP
=
0
,
fSD16 = 1 MHz, GAIN: 4, 8, 16 3 V 730 1100
ISD16
current:
1
active
SD16 channel
fSD16
1
MHz,
SD16OSR = 256 GAIN: 32 3 V 1050 1550
µA
I
SD16 including internal
reference SD16LP = 1,
f0 5 MHz
GAIN: 1 3 V 620 930
µ
A
reference
(ESP430 disabled) fSD16 = 0.5 MHz,
SD16OSR = 256 GAIN: 32 3 V 700 1060
fMAINS
Mains frequency
range 33 80 Hz
f
Analog front-end
input clock
SD16LP = 0 (Low power mode disabled) 3 V 1
MHz
fSD16 input clock
frequency SD16LP = 1 (Low power mode enabled) 3 V 0.5 MHz
ESP430CE1, SD16 input range (see Note 1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
SD16GAINx = 1, SD16REFON = 1 ±500
Differential input SD16GAINx = 2, SD16REFON = 1 ±250
V
Differential
input
voltage range for
specified
SD16GAINx = 4, SD16REFON = 1 ±125
mV
VID specified
performance
SD16GAINx = 8, SD16REFON = 1 ±62 mV
performance
(see Note 2) SD16GAINx = 16, SD16REFON = 1 ±31
(see
Note
2)
SD16GAINx = 32, SD16REFON = 1 ±15
Z
Input impedance
(one input pin
fSD16 = 1MHz, SD16GAINx = 1 3 V 200
kΩ
ZI(one input pin
to AVSS)fSD16 = 1MHz, SD16GAINx = 32 3 V 75 kΩ
Z
Differential
Input impedance
fSD16 = 1MHz, SD16GAINx = 1 3 V 300 400
kΩ
ZID Input impedance
(IN+ to IN−) fSD16 = 1MHz, SD16GAINx = 32 3 V 100 150 kΩ
VI
Absolute input
voltage range
AVSS-
1.0V AVCC V
VIC
Common-mode
input voltage range
AVSS-
1.0V AVCC V
NOTES: 1. All parameters pertain to each SD16 channel.
2. The analog input range depends on the reference voltage applied to VREF
. If VREF is sourced externally, the full-scale range
is defined by VFSR+ = +(VREF/2)/GAIN and VFSR− = −(VREF/2)/GAIN. The analog input range should not exceed 80% of
VFSR+ or VFSR−.
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
ESP430CE1, SD16 performance (fSD16 = 1MHz, SD16OSRx = 256, SD16REFON = 1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
SD16GAINx = 1,Signal Amplitude = 500mV 3 V 83.5 85
SD16GAINx = 2,Signal Amplitude = 250mV 3 V 81.5 84
SINAD
Si
g
nal-to-noise + SD16GAINx = 4,Signal Amplitude = 125mV fIN = 50 Hz, 3 V 76 79.5
SINAD
Signal to noise
+
distortion ratio SD16GAINx = 8,Signal Amplitude = 62mV
fIN
=
50
Hz
,
100 Hz 3 V 73 76.5 dB
SD16GAINx = 16,Signal Amplitude = 31mV 3 V 69 73
SD16GAINx = 32,Signal Amplitude = 15mV 3 V 62 69
SD16GAINx = 1 3 V 0.97 1.00 1.02
SD16GAINx = 2 3 V 1.90 1.96 2.02
G
SD16GAINx = 4 3 V 3.76 3.86 3.96
GNominal gain SD16GAINx = 8 3 V 7.36 7.62 7.84
SD16GAINx = 16 3 V 14.56 15.04 15.52
SD16GAINx = 32 3 V 27.20 28.35 29.76
E
Offset error
SD16GAINx = 1 3 V ±0.2
EOS Offset error SD16GAINx = 32 3 V ±1.5 %FSR
dE /dT
Offset error
temperature
SD16GAINx = 1 3 V ±4±20
m
dEOS/dT temperature
coefficient SD16GAINx = 32 3 V ±20 ±100
FSR/C
CMRR
Common-mode
SD16GAINx = 1, Common-mode input signal:
VID = 500 mV, fIN = 50 Hz, 100 Hz 3 V >90
CMRR
Common mode
rejection ratio SD16GAINx = 32, Common-mode input signal:
VID = 16 mV, fIN = 50 Hz, 100 Hz 3 V >75
dB
AC PSRR AC power supply
rejection ratio SD16GAINx = 1, VCC = 3 V ± 100 mV, fVCC = 50 Hz 3 V >80 dB
XTCrosstalk 3 V <−100 dB
ESP430CE1, SD16 temperature sensor
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
TCSensor
Sensor temperature
coefficient 1.18 1.32 1.46 mV/K
VOffset,sensor
Sensor offset
voltage −100 100 mV
Stt
Temperature sensor voltage at TA = 85°C3 V 435 475 515
VSensor
Sensor output
voltage (see Note 2)
Temperature sensor voltage at TA = 25°C3 V 355 395 435 mV
VSensor
vo
lt
age
(
see
N
o
t
e
2)
Temperature sensor voltage at TA = 0°C3 V 320 360 400
mV
NOTES: 1. The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor ( 273 + T [°C] ) + VOffset,sensor [mV]
2. Results based on characterization and/or production test, no TCSensor or VOffset,sensor.
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
ESP430CE1, SD16 built-in voltage reference
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VREF
Internal reference
voltage SD16REFON = 1, SD16VMIDON = 0 3 V 1.14 1.20 1.26 V
IREF
Reference supply
current SD16REFON = 1, SD16VMIDON = 0 3 V 175 260 µA
TC Temperature
coefficient SD16REFON = 1, SD16VMIDON = 0 (see Note 1) 3 V 20 50 ppm/K
CREF
VREF load
capacitance SD16REFON = 1, SD16VMIDON = 0 (see Note 2) 100 nF
ILOAD
VREF(I) maximum
load current SD16REFON = 0, SD16VMIDON = 0 3 V ±200 nA
tON Turn-on time SD16REFON = 0 → 1, SD16VMIDON = 0, CREF = 100 nF 3 V 5 ms
DC PSR
DC power supply
rejection,
∆VREF/∆VCC
SD16REFON = 1, SD16VMIDON = 0, VCC = 2.5 V to 3.6 V 200 µV/V
NOTES: 1. Calculated using the box method: (MAX(−40...85°C) − MIN(−40...85°C)) / MIN(−40...85°C) / (85 − (−40°C))
2. There is no capacitance required on VREF
. However, a capacitance of at least 100nF is recommended to reduce any reference
voltage noise.
ESP430CE1, SD16 reference output buffer
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VREF,BUF
Reference buffer
output voltage SD16REFON = 1, SD16VMIDON = 1 3 V 1.2 V
IREF,BUF
Reference supply +
reference output
buffer quiescent
current
SD16REFON = 1, SD16VMIDON = 1 3 V 385 600 µA
CREF(O)
Required load
capacitance on
VREF
SD16REFON = 1, SD16VMIDON = 1 470 nF
ILOAD,Max
Maximum load
current on VREF SD16REFON = 1, SD16VMIDON = 1 3 V ±1 mA
Maximum voltage
variation vs load
current
|ILOAD| = 0 to 1mA 3 V −15 +15 mV
tON Turn-on time SD16REFON = 0 → 1, SD16VMIDON = 1, CREF = 470 nF 3 V 100 µs
ESP430CE1, SD16 external reference input
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VREF(I) Input voltage range SD16REFON = 0 3 V 1.0 1.25 1.5 V
IREF(I) Input current SD16REFON = 0 3 V 50 nA
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
ESP430CE1, active energy measurement test conditions and accuracy, TA = 25°C (See Note 1)
fACLK = 32,768 Hz (watch crystal)
fMCLK = 4.194MHz (FLL+)
fSD16 = fMCLK/4 = 1.049MHz
Single point calibration at I = 10 A, PF = 0.5 lagging
Measurements according to IEC1036
Input conditions (unless otherwise noted):
IB = 6 A, IMAX = n * IB = 60 A, n = 10, VN = 230 V, fMAINS = 50 Hz
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
I = 0.05*IB, V = VN, PF = 1.0 3 V ±0.17
I = 0.1*IB to IMAX, V = VN, PF = 1.0
V1 SD16GAINx
=
1
3 V ±0.18
I = 0.1*IB, V = VN, PF = 0.5 lagging
V1
SD16GAINx
=
1
I1 SD16GAINx = 1 3 V ±0.19
Maximum error I = 0.2*IB to IMAX, V = VN, PF = 0.5 lagging
I1
SD16GAINx
=
1
3 V ±0.27 %
Maximum
error
I = 0.1*IB, V = VN, PF = 0.8 leading See Figure 14: 3 V ±0.15
%
I = 0.2*IB to IMAX, V = VN, PF = 0.8 leading
g
R1 = 0Ω, RB = 12.4Ω3 V ±0.24
I = 0.2*IB to IMAX, V = VN, PF = 0.25 lagging 3 V ±0.38
Input conditions (unless otherwise noted):
IB = 10 A, IMAX = n * IB = 60 A, n = 6, VN = 230 V, fMAINS = 50 Hz
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
I = 0.05*IB, V = VN, PF = 1.0 3 V ±0.11
I = 0.1*IB to IMAX, V = VN, PF = 1.0
V1 SD16GAINx
=
1
3 V ±0.18
I = 0.1*IB, V = VN, PF = 0.5 lagging
V1
SD16GAINx
=
1
I1 SD16GAINx = 32 3 V ±0.45
Maximum error I = 0.2*IB to IMAX, V = VN, PF = 0.5 lagging
I1
SD16GAINx
=
32
3 V ±0.33 %
Maximum
error
I = 0.1*IB, V = VN, PF = 0.8 leading See Figure 15: 3 V ±0.10
%
I = 0.2*IB to IMAX, V = VN, PF = 0.8 leading
g
Rshunt = 0.2mΩ3 V ±0.18
I = 0.2*IB to IMAX, V = VN, PF = 0.25 lagging 3 V ±0.51
NOTES: 1. Measurements performed using complete hardware solution. Error shown contain temperature dependencies of all components
including the MSP430FE42x, crystal, and discrete components.
2. I1 SD16GAIN x = 1,4: CT part number = T60404−E4624−X101 ( Vacuumschmelze)
I1 SD16GAINx = 8: shunt part number = A−H2−R005−F1−K2−0.1 (Isabellenhütte Heusler GmbH KG)
I1 SD16GAINx = 32: shunt part number = BVO−M−R0002−5.0 (Isabellenhütte Heusler GmbH KG)
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
1k
1uH
1.5k
990k
CT
I
33nF
1k
1uH
1k
1k1uH
33nF
33nF
33nF
I1+
I1−
V1
+
V1
−
RB
R1
Figure 14. Energy measurement test circuitry (SD16GAINx = 1, 4)
1k
1uH
1.5k
990k
I
33nF
1k
1uH
1k
1k1uH
33nF
33nF
33nF
Rshunt
I1+
I1−
V1+
V1−
Figure 15. Energy measurement test circuitry (SD16GAINx = 8, 32)
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ESP430CE1, I1 SD16GAINx = 1 typical characteristics (see Note 1)
Figure 16
Line Current − A
−1.00
−0.75
−0.50
−0.25
0.00
0.25
0.50
0.75
1.00
0.01 0.10 1.00 10.00 100.00
MEASUREMENT ERROR AS % OF READING
(TA = 25°C)
Error − %
PF = 1 PF = 0.5 lag
PF = 0.8 lead
fMAINS = 50 Hz
VLINE = 230 V
0.03 60
Figure 17
Line Current − A
−1.00
−0.75
−0.50
−0.25
0.00
0.25
0.50
0.75
1.00
0.01 0.10 1.00 10.00 100.00
MEASUREMENT ERROR AS % OF READING
(TA = −40°C)
Error − %
PF = 0.5 lag
PF = 0.8 lead
0.03 60
PF = 1
fMAINS = 50 Hz
VLINE = 230 V
Figure 18
Line Current − A
−1.00
−0.75
−0.50
−0.25
0.00
0.25
0.50
0.75
1.00
0.01 0.10 1.00 10.00 100.00
MEASUREMENT ERROR AS % OF READING
(TA = 85°C)
Error − %
PF = 0.5 lag
PF = 0.8 lead
0.03 60
PF = 1
fMAINS = 50 Hz
VLINE = 230 V
NOTES: 1. Results corrected for typical phase error of CT used. (−40°C to 25°C: −0.7°; 25°C to 85°C: +0.5°)
See Figure 14 for test circuitry: CT part number = T60404−E4624−X101 ( Vacuumschmelze), R1 = 0Ω, RB = 12.4Ω
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ESP430CE1, I1 SD16GAINx = 4 typical characteristics (see Note 1)
Figure 19
Line Current − A
−1.00
−0.75
−0.50
−0.25
0.00
0.25
0.50
0.75
1.00
0.01 0.10 1.00 10.00 100.00
MEASUREMENT ERROR AS % OF READING
(TA = 25°C)
Error − %
PF = 1
PF = 0.8 lead
0.03 60
PF = 0.5 lag
fMAINS = 50 Hz
VLINE = 230 V
Figure 20
Line Current − A
−1.00
−0.75
−0.50
−0.25
0.00
0.25
0.50
0.75
1.00
0.01 0.10 1.00 10.00 100.00
MEASUREMENT ERROR AS % OF READING
(TA = −40°C)
Error − %
PF = 1
PF = 0.5 lag
PF = 0.8 lead
0.03 60
fMAINS = 50 Hz
VLINE = 230 V
Figure 21
Line Current − A
−1.00
−0.75
−0.50
−0.25
0.00
0.25
0.50
0.75
1.00
0.01 0.10 1.00 10.00 100.00
MEASUREMENT ERROR AS % OF READING
(TA = 85°C)
Error − %
PF = 0.5 lag
PF = 0.8 lead
0.03 60
PF = 1
fMAINS = 50 Hz
VLINE = 230 V
NOTES: 1. Results corrected for typical phase error of CT used. (−40°C to 25°C: −0.7°; 25°C to 85°C: +0.5°)
See Figure 14 for test circuitry: CT part number = T60404−E4624−X101 ( Vacuumschmelze), R1 = 9.36Ω, RB = 3.16Ω
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ESP430CE1, I1 SD16GAINx = 8 typical characteristics (see Note 1)
Figure 22
Line Current − A
−1.00
−0.75
−0.50
−0.25
0.00
0.25
0.50
0.75
1.00
0.01 0.10 1.00 10.00 100.00
MEASUREMENT ERROR AS % OF READING
(TA = 25°C)
Error − %
PF = 0.8 lead
0.03 60
PF = 1
PF = 0.5 lag
fMAINS = 50 Hz
VLINE = 230 V
Figure 23
Line Current − A
−1.00
−0.75
−0.50
−0.25
0.00
0.25
0.50
0.75
1.00
0.01 0.10 1.00 10.00 100.00
MEASUREMENT ERROR AS % OF READING
(TA = −40°C)
Error − %
PF = 1
PF = 0.5 lag
PF = 0.8 lead
0.03 60
fMAINS = 50 Hz
VLINE = 230 V
Figure 24
Line Current − A
−1.00
−0.75
−0.50
−0.25
0.00
0.25
0.50
0.75
1.00
0.01 0.10 1.00 10.00 100.00
MEASUREMENT ERROR AS % OF READING
(TA = 85°C)
Error − %
PF = 0.5 lag
PF = 0.8 lead
0.03 60
PF = 1
fMAINS = 50 Hz
VLINE = 230 V
NOTES: 1. See Figure 15 for test circuitry: shunt part number = A−H2−R005−F1−K2−0.1 (Isabellenhütte Heusler GmbH KG)
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ESP430CE1, I1 SD16GAINx = 32 typical characteristics (see Note 1)
Figure 25
Line Current − A
−1.00
−0.75
−0.50
−0.25
0.00
0.25
0.50
0.75
1.00
0.01 0.10 1.00 10.00 100.00
MEASUREMENT ERROR AS % OF READING
(TA = 25°C)
Error − %
PF = 0.8 lead
0.05 60
PF = 1
PF = 0.5 lag
fMAINS = 50 Hz
VLINE = 230 V
Figure 26
Line Current − A
−1.00
−0.75
−0.50
−0.25
0.00
0.25
0.50
0.75
1.00
0.01 0.10 1.00 10.00 100.00
MEASUREMENT ERROR AS % OF READING
(TA = −40°C)
Error − %
PF = 0.5 lag
PF = 0.8 lead
0.05 60
PF = 1
fMAINS = 50 Hz
VLINE = 230 V
Figure 27
Line Current − A
−1.00
−0.75
−0.50
−0.25
0.00
0.25
0.50
0.75
1.00
0.01 0.10 1.00 10.00 100.00
MEASUREMENT ERROR AS % OF READING
(TA = 85°C)
Error − %
PF = 1
PF = 0.5 lag
PF = 0.8 lead
0.05 60
fMAINS = 50 Hz
VLINE = 230 V
NOTES: 1. See Figure 15 for test circuitry: shunt part number = BVO−M−R0002−5.0 (Isabellenhütte Heusler GmbH KG)
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Flash Memory
PARAMETER TEST
CONDITIONS VCC MIN NOM MAX UNIT
VCC(PGM/
ERASE) Program and Erase supply voltage 2.7 3.6 V
fFTG Flash Timing Generator frequency 257 476 kHz
IPGM Supply current from DVCC during program 2.7 V/ 3.6 V 3 5 mA
IERASE Supply current from DVCC during erase 2.7 V/ 3.6 V 3 7 mA
tCPT Cumulative program time see Note 1 2.7 V/ 3.6 V 10 ms
tCMErase Cumulative mass erase time see Note 2 2.7 V/ 3.6 V 200 ms
Program/Erase endurance 104105cycles
tRetention Data retention duration TJ = 25°C 100 years
tWord Word or byte program time 35
tBlock, 0Block program time for 1st byte or word 30
tBlock, 1-63 Block program time for each additional byte or word
see Note 3
21
t
tBlock, End Block program end-sequence wait time see Note 3 6tFTG
tMass Erase Mass erase time 5297
tSeg Erase Segment erase time 4819
NOTES: 1. The cumulative programming time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all
programming methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To
achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
JTAG Interface
PARAMETER TEST
CONDITIONS VCC MIN NOM MAX UNIT
f
TCK input frequency
see Note 1
2.2 V 0 5 MHz
fTCK TCK input frequency see Note 1 3 V 0 10 MHz
RInternal Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2 2.2 V/ 3 V 25 60 90 kΩ
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG Fuse (see Note 1)
PARAMETER TEST
CONDITIONS VCC MIN NOM MAX UNIT
VCC(FB) Supply voltage during fuse-blow condition TA = 25°C 2.5 V
VFB Voltage level on TDI/TCLK for fuse-blow 6 7 V
IFB Supply current into TDI/TCLK during fuse-blow 100 mA
tFB Time to blow fuse 1 ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic
Port P1, P1.0 to P1.1, input/output with Schmitt-trigger
P1OUT.x
Module X OUT
P1DIR.x
Direction Control
From Module
P1SEL.x
D
EN
Interrupt
Edge
Select
P1IES.x P1SEL.x
P1IE.x
P1IFG.x
P1IRQ.x EN
Set
Q
0
1
1
0
Pad Logic
0: Input
1: Output
Bus
keeper
CAPD.x
PnSEL.x PnDIR.x
Direction
From Module
PnOUT.x Module X
OUT PnIN.x PnIE.x PnIFG.x PnIES.x
Module X IN
P1SEL.1 P1DIR.1 P1OUT.1 P1IN.1 P1IE.1 P1IFG.1 P1IES.1
P1SEL.0 P1DIR.0 P1OUT.0 P1IN.0 P1IE.0 P1IFG.0 P1IES.0
P1DIR.1
P1DIR.0
MCLK
Module X IN
P1IN.x
P1.0/TA0
P1.1/TA0/MCLK
Control
NOTE: 0 ≤ x ≤ 1.
Port Function is Active if CAPD.x = 0
†Timer_A3
Out0 Sig.†CCI0A†
CCI0B†
CAPD.x
DVSS
DVSS
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
Port P1, P1.2 to P1.7, input/output with Schmitt-trigger
DVSS
P1OUT.x
Module X OUT
P1DIR.x
Direction Control
From Module
P1SEL.x
D
EN
Interrupt
Edge
Select
P1IES.x P1SEL.x
P1IE.x
P1IFG.x
P1IRQ.x EN
Set
Q
0
1
1
0
Pad Logic
0: Input
1: Output
Bus
keeper
DVSS
PnSEL.x PnDIR.x
Direction
From Module
PnOUT.x Module X
OUT PnIN.x PnIE.x PnIFG.x PnIES.x
Module X IN
P1SEL.7 P1DIR.7 P1OUT.7 P1IN.7 P1IE.7 P1IFG.7 P1IES.7
P1SEL.2 P1DIR.2 P1OUT.2 P1IN.2 P1IE.2 P1IFG.2 P1IES.2
P1SEL.3 P1DIR.3 P1OUT.3 P1IN.3 P1IE.3 P1IFG.3 P1IES.3
P1SEL.4 P1DIR.4 P1OUT.4 P1IN.4 P1IE.4 P1IFG.4 P1IES.4
P1SEL.5 P1DIR.5 P1OUT.5 P1IN.5 P1IE.5 P1IFG.5 P1IES.5
P1SEL.6 P1DIR.6 P1OUT.6 P1IN.6 P1IE.6 P1IFG.6 P1IES.6
SVSOUT
DCM_SOMI
P1DIR.2
P1DIR.3
P1DIR.4
P1DIR.5
DCM_SIMO
ACLK
Module X IN
P1IN.x P1.5/TACLK/ACLK/S28
P1.2/TA1/S31
P1.4/S29
P1.3/SVSOUT/S30
Control
NOTE: 2 ≤ x ≤ 7.
Port Function is Active if Port/LCD = 0
†Timer_A3
‡USART0
SIMO0(o)‡
Out1 Sig.†CCI1A†
unused
unused
TACLK†
P1.7/SOMI0/S26
P1.6/SIMO0/S27
Segment xx
Port/LCD
Port/LCD Segment
S26
S31
S30
S29
S28
S27
SOMI0(o)‡
SIMO0(i)‡
SOMI0(i)‡
0: LCDM
< 0E0h
1: LCDM
≥ 0E0h
0: LCDM
< 0C0h
1: LCDM
≥ 0C0h
SYNC
MM
STC
STE
SYNC
MM
STC
STE
DCM_SOMI
DCM_SIMO
Direction Control for SOMI0
Direction Control for SIMO0
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.0 to P2.1, input/output with Schmitt-trigger
P2OUT.x
Module X OUT
P2DIR.x
Direction Control
From Module
P2SEL.x
D
EN
Interrupt
Edge
Select
P2IES.x P2SEL.x
P2IE.x
P2IFG.x
P2IRQ.x EN
Set
Q
0
1
1
0
PnSel.x PnDIR.x Dir. Control
from module PnOUT.x Module X
OUT PnIN.x PnIE.x PnIFG.x PnIES.xModule X IN
0: Port active
1: Segment xx function active
P2Sel.0 P2DIR.0
P2Sel.1 P2DIR.1
P2DIR.0
DCM_UCLK
P2OUT.0
P2OUT.1
P2IN.0
P2IN.1 UCLK0(i)
Out2sig.
UCLK0(o)
P2IE.0
P2IE.1
P2IFG.0
P2IFG.1
P2IES.0
P2IES.1
Module X IN
P2IN.x
Pad Logic
0: Input
1: Output
Bus
Keeper
CCI2A
Port/LCD
Port/LCD
Segment xx
P2.0/TA2/S25
P2.1/UCLK0/S24
†
† Timer_A3
‡ USART0
‡
†
‡
Segment
S25
S24
0: LCDM
< 0E0h
1: LCDM
≥ 0E0h
NOTE: 0 ≤ x ≤ 1.
Port Function is Active if Port/LCD = 0
SYNC
MM
STC
STE
DCM_UCLK
Direction Control for UCLK0
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.2 to P2.5, input/output with Schmitt-trigger
DVSS
P2OUT.x
Module X OUT
P2DIR.x
Direction Control
From Module
P2SEL.x
D
EN
Interrupt
Edge
Select
P2IES.x P2SEL.x
P2IE.x
P2IFG.x
P2IRQ.x EN
Set
Q
0
1
1
0
Pad Logic
0: Input
1: Output
Bus
keeper
CAPD.x
PnSEL.x PnDIR.x
Direction
From Module
PnOUT.x Module X
OUT PnIN.x PnIE.x PnIFG.x PnIES.x
Module X IN
P2SEL.2 P2DIR.2 P2OUT.2 P2IN.2 P2IE.2 P2IFG.2 P2IES.2
P2SEL.3 P2DIR.3 P2OUT.3 P2IN.3 P2IE.3 P2IFG.3 P2IES.3
P2SEL.4 P2DIR.4 P2OUT.4 P2IN.4 P2IE.4 P2IFG.4 P2IES.4
P2SEL.5 P2DIR.5 P2OUT.5 P2IN.5 P2IE.5 P2IFG.5 P2IES.5
DVSS
DVSS
P2DIR.3
DVCC
DVSS DVSS
Module X IN
P2IN.x P2.5/URXD0
P2.2/STE0
P2.4/UTXD0
P2.3/SVSIN
Control
NOTE: 2 ≤ x ≤ 5
Port function is active if CAPD.x = 0
†USART0
UTXD0†
STE0†
unused
unused
URXD0†
DVSS
DVSS
CAPD.x
To BrownOut/SVS for P2.3/SVSIN
DVSS
SVSCTL VLD
DVSS
DVSS
= 1111b
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
Port P2, unbonded GPIOs P2.6 and P2.7
EN
D
0
1
0
1
Interrupt
Edge
Select
EN
Set
Q
P2IE.x
P2IFG.x
P2IRQ.x
Interrupt
Flag P2IES.x
P2SEL.x
Module X IN
P2IN.x
P2OUT.x
Module X OUT
Direction Control
From Module
P2DIR.x
P2SEL.x
Bus Keeper
0
1
0: Input
1: Output
Node Is Reset With PUC
PUC
NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins
P2Sel.x P2DIR.x
DIRECTION
CONTROL
FROM MODULE
P2OUT.x MODULE X OUT P2IN.x MODULE X IN P2IE.x P2IFG.x P2IES.x
P2Sel.6 P2DIR.6 P2DIR.6 P2OUT.6 DVSS P2IN.6 unused P2IE.6 P2IFG.6 P2IES.6
P2Sel.7 P2DIR.7 P2DIR.7 P2OUT.7 DVSS P2IN.7 unused P2IE.7 P2IFG.7 P2IES.7
NOTE: Unbonded GPIOs 6 and 7 of port P2 can be used as interrupt flags. Only software can affect the interrupt flags. They work as software
interrupts.
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
TDI
TDO
TMS
TDI/TCLK
TDO/TDI
Controlled
by JTAG
TCK
TMS
TCK
DVCC
Controlled by JTAG
Test
JTAG
and
Emulation
Module
DVCC
DVCC
Burn and Test
Fuse
G
D
S
U
G
D
S
U
TCK
Tau ~ 50 ns
Brownout
Controlled by JTAG
RST/NMI
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF , of 1.8 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be
taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 28). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
The JTAG pins are terminated internally, and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
ITF
ITDI/TCLK
Figure 28. Fuse Check Mode Current, MSP430FE42x
MSP430FE42x
MIXED SIGNAL MICROCONTROLLER
SLAS396C − JULY 2003 − REVISED OCTOBER 2008
45
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Data Sheet Revision History
Literature
Number Summary
SLAS396 Preliminary Product Preview data sheet release
SLAS396A Production Data data sheet release
SLAS396B
Updated functional block diagram (page 3)
Clarified test conditions in recommended operating conditions table (page 17)
Changed “Supply voltage during program execution; SVS enabled, PORON = 1, ESP430 and SD16 disabled” MIN value
from 2.2 V to 2.0 V (page 17)
Clarified test conditions for I(LPM0) in supply current into AVCC + DVCC table (page 18)
Clarified test conditions in USART0 table (page 21)
Changed PSRR to AC PSRR in EP430CP1, SD16 performance table (page 29)
Added DC PSR in EP430CP1, SD16 built-in voltage reference table (page 30)
Added tON parameter to ESP430CE1, SD16 built-in voltage reference table (page 30)
Corrected PF = 0 to PF = 1 in Figure 16 through Figure 27 (page 33 through page 36)
Changed tCPT maximum value from 4 ms to 10 ms in Flash memory table (page 37)
SLAS396C Modified labels on Figure 16 through Figure 27 (page 33 through page 36)
NOTE: Page and figure numbers refer to the respective document revision and may differ in other revisions.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
MSP430FE423IPM ACTIVE LQFP PM 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430FE423IPMR ACTIVE LQFP PM 64 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430FE425IPM ACTIVE LQFP PM 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430FE425IPMR ACTIVE LQFP PM 64 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430FE427IPM ACTIVE LQFP PM 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430FE427IPMR ACTIVE LQFP PM 64 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Oct-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
MSP430FE423IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
MSP430FE425IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
MSP430FE427IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
MSP430FE427IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MSP430FE423IPMR LQFP PM 64 1000 336.6 336.6 41.3
MSP430FE425IPMR LQFP PM 64 1000 336.6 336.6 41.3
MSP430FE427IPMR LQFP PM 64 1000 336.6 336.6 41.3
MSP430FE427IPMR LQFP PM 64 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PM (S-PQFP-G64) PLASTIC QUAD FLATPACK
4040152/C 11/96
32
17 0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
Gage Plane
0,27
33
16
48
1
0,17
49
64
SQ
SQ
10,20
11,80
12,20
9,80
7,50 TYP
1,60 MAX
1,45
1,35
0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
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