AM186CH50KCWC - Advanced Micro Devices

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon

Am186ER/Am188ER

AMD continues 16-bit innovation

386-Class Performance, Enhanced System

Integration, and Built-in SRAM

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon Am186ER and Am188ER

.%\WHV5$0

$P(0

&RUH

$P(0

&RUH

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon Am186 System Evolution

80C186 Based

3.37 MIP System Am186EM Based

5.35 MIP System Am186ER Based

6.6 MIP System

CPU

Basic

System

Logic

RAM

FLASH

CPU

Basic

System

Logic

RAM

FLASH

Internal

External

CPU

RAM

FLASH

Advanced

System

Logic

Basic

System

Logic

Advanced

System

Logic

Advanced

System

Logic

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon Typical 80C186 Design

Flash/

Oscillator

CLK

+5V

Buffered clocks

Chip selects for peripheral s with 256 registers

Byte Write Enables

-BHE

Address

Mux’ed A/D EPROM

Interrupt input

÷ 2 Input

Frequency

Application

I/O

Specific

80C186

Address/Data

ALE

Int 0

Control/Status

-PCS1

-PCS2

-PCS3

-PCS4

-PCS5

-WR

expansion

SRAM

-WE Serial

Port

Parallel

I/O

Address

Latch

32 PIOs Latch

qPotential system cost savings

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon

Typical 80C186EM Design

(Glueless System Bus)

Am186EM

Address/Data

Int 0

Control/Status

-PCS1

-PCS2

-PCS3

Int 4

Address

ALE

CLKOUTA

1X or ÷ 2 Input Frequency Crystal

CLKOUTB

nterrupt input

expansion

Buffered clocks

Chip selects for peripherals with 256 registers

TXD

RXD

Serial Port

PIO(0:31)

Paralllel I/O*

Flash/

EPROM

SRAM Application

Specific

I/O

*16 bit reset configuration latch and up to

32 general purpose programmable I/Os

qNew or Enhanced Features

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon

Typical Am186ER Design

(Glueless System Bus & Inte grated RAM)

*16 bit reset configuration latch and up to 32

general purpose programmable I/Os

Am186ER

Address/Data

Int 0

Control/Status

-PCS1

-PCS2

-PCS3

Int 4

Address

ALE

CLKOUTA

1X, 4x, or ÷ 2 Input

Frequency Crystal

CLKOUTB

Interrupt input

expansion

Buffered clocks

Chip selects for peripherals with 256 registers

TXD

RXD

Serial Port

PIO(0:31)

Paralllel I/O*

Flash/

EPROM

Application

Specific

I/O

32Kbytes

RAM

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon Am186/188ER vs. 80C186/188

• Software compatible wi th 80C186/188

• 25 to 50MHz

– Higher perform ance o ptions

• Glueless connection to memory

– Lower system cost

• Demultiplexed address bus

– Zero wait state u sing commodity memories

• Use Am188ER to replace low f requency 80C186

– 25 MHz Am188ER eq uals12 MHz 80C186 performance

– Save on routing a nd space while using cheaper x8

components

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon Am186/188EM vs. Am186/188ER

• No wait state inte rnal RAM

– 16Kx16 for Am 18 6ER, and 32Kx8 for Am188ER

– Visible f or debugging

•Low Power

– 3.3v Vcc with 5V tolerant IO

– TTL compatible

– Integration of RAM re duces system power

• Multiple clocking modes

– ½x, 1x, and 4x system frequency vs. input frequency

– Use a 12.5 MHz crystal for 50MHz system

• Same 100 pin TQFP and PQFP package/pinout

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon Am186ER Block Diagram

Chip

Selects

Chip

Selects

Timer

Unit

(3)

Timer

Unit

(3)

Interrupt

Control

Unit

Interrupt

Control

Unit

DMA

Control

(2)

DMA

Control

(2)

GPIO

(32)

GPIO

(32)

Synch

Serial

I/F

Synch

Serial

I/F

High Perf.

186 (5 0

MHZ)

High Perf.

186 (5 0

MHZ)

Watchdog

Timer

Watchdog

Timer

PLL

/2, 1x, 4x

PLL

/2, 1x, 4x UART

w/DMA

UART

w/DMA

Glueless

Connection

to RAM/ROM

Glueless

Connection

to RAM/ROM

32K Byt es

RAM

32K Byt es

RAM

CPU voltage : 3.3v w/5v tolerant I/Os

Packages: 100 PQFP and TQFP

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon

Am186ER and Am188ER Features

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon

Am186/188ER

New Features w/ Revision B

• Increased Performance - 50 MHZ - 6.6 MIPs

• DMA to/from asynchronous serial port

• Hardware Watc hdog Timer

– Generates NMI or reset

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon

Am186/188ER Rev B

Enhanced Features Con’t

• Am186/188ER 40MHz max at Industrial Temp

now available in both PQFP and TQFP

– PQFP 25, 33 & 40MHz at Industrial Temp available

– TQFP 25, 3 3 & 40MHz at I ndustrial Temp available

• If you are currently using an EM/EMLV or

ES/ESLV and need to upgrade to a higher

frequency industrial grade device (3.3V),

consider the ER

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon Am186ER/188ER Feature Set

– 32K Bytes of integrated RAM

– Asynchronous and synchro nous serial ports

– Glueless interface to ROM, SRAM, PSRAM and FLASH

– 32 programmable I/Os

– Interrupt controller with 13 interrupt sources

– 3 tim ers (with pulse width m odulat ion)

– 2 DMA channels and 13 chip selects

– Integrate d PLL

• two clockouts

• system frequency is /2, 1x, and 4x the input frequency

– Am188ER gives 60% of the perform ance o f Am18 6ER

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon On-Board RAM

• 16Kx16 for Am186ER and 32Kx8 for

Am188ER

• Same performance as no-wait state external

RAM

• Locatable on any 32 Kbytes Boundary

• Show reads on the address bus for easier

debugging

– Externally disp lays data from internal RAM re ads

– Show reads enabled in hardware or softwa re

• Internal memory disable

– Disable with hardware or software

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon Diagram of the Show Reads

CLKOUTA

t1t2t3t4

AD15–AD0

AddressA19–A0

ALE

DataAddress

911

25 27

LCS, UCS

MCS3–MCS0,

PCS6–PCS5,

PCS3–PCS0

Internal RAM Show Read Cycle Waveform

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon 5V Tolerant I/Os

• Vcc on the Am186ER and Am188ER is 3.3V

– Inputs are 5V tolerant

• up to 2.6V over Vcc on inputs

– Outp uts drive TTL Logic

• logic one to 2.4V

• Allows mixed voltage system

– Supports legacy 5V com ponents

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon Clock and Power Management Unit

• Up to 50 MHz speeds

• Clock options

– /2 for system s running lower than 20MHz

– 1x for systems running between 16 and 40MHz

– 4x for systems running between 16 and 50MHz

• 2 CLKOUT pins - program options:

– Normal ope ratin g frequency

– Power save frequency

– Can be disabled

• Power save mode

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon PRL Register

• Used for code to identify product and revision

– Indicate s the current release level of th e processor

– Specifies either the 8 bit or 16 bit controller

• Revision B

– Am186ER = 28h

– Am188ER = 29h

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon

ER and EM Family: Common Features

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon Demultiplexed Bus

• Am186ER demultiplexed addr ess & data bus

yields:

– Higher perform ance

• Address available time increased

• No ALE required

• Data setup time decreased

– Lower system cost

• Eliminates glue logic needed to latch memory address

• Using commodity memory reduces cost

– Multiplexed bus st ill sup ported for periph erals

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon Demultiplexed Bus Interface

CLKOUT

80C186

Multip lexed Address/Data Bus

Am186ER

Multip lexed Address/Data Bus

Am186ER

Non-Multiplexed Address Bu s

t4 t1 t2 t3 t4 t1

Address

Data

Dat

taccess Am186E M

tDVCL

tlatch

tCLAV

Addres

taccessAm186/Am186EM

tCLAV

Address

tCLAV

taccess 186

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon Asynchronous Serial Port

• Asynchronous protocol

– Full duplex, 7 o r 8 bit

– Odd/even/no parity, 1 or 2 stop bits

• Interrupts

– Tx, Rx, Break

– Framing, parity, & overrun errors

• Baud rate generator

– div = (CLK Freq) / (32 * Baud rate) - 1

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon Synchronous Serial Interface

• High speed serial transfers

– Up to 25 Mbits/s at 50MHz

– Half-duplex bi-directional

– ASIC or Ma ch ™ control

– Master with up to 2 slaves directly supported with

enables

• more than 2 slaves supported with PIOs

– Operates in polled mode only

– SCLK at 1/2, 1 / 4, 1/8 and 1/16 CPU clock

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon 32 Programmable I/O Pins

• Up to 32 PIO pins are available for I/O if their

alternate functions are unused

– Input

– Input with weak internal pull-up/pull-down

• polarity depends on original pin

–Output

– Open -drain output

• Multiplexed with other signals

– Default de pends on pin

• Read or written through the peripheral control block

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon

The reset configuration register function is to store

data from the AD bus at reset. The illustration below

demonstrates this.

16-Bit Reset

Configuration Register

Vcc

AD0

AD15

Vss

Vcc

Vss

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon

80C186, EM, and ER Family: Common

Features

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon Three 16-bit Timers

• Sam e as the 80C186

• Watchdog timer functionality added to timer 1

• Supports pulse width modulation

• Can re-trigger on external events

• Continuous or one-shot count

• Can generate interrupt on terminal count

• Chainable interrupts

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon Three 16-bit Timers(cont.)

Am186EM Features

§Inside the line indicates I/Os internal to the timers

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon Chip Selects

• 6 chip-selects (PCS) with a range of 256 bytes

for use with peripheral devices

– Mapped to memory or I/O space

• 4 chip-selects (MCS) with a range of 2K to

128Kbytes

• 2 chip select outputs (UCS and LCS) for use

in the top and bottom of memory map

– Good for system code and external RAM

– UCS is initial chip select after reset

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon Two DMA Channels

• Same as 80C186

• DMA options

– Mem-mem, mem-I/O, I/O-I/O

– byte or word

– 2 Bus cycles per transfer (read followed by a write)

– Interrupt after last transfer

– DMA channel priority

– DMA pointer increment/decrement/static

– Synchronization - source /destination/none

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon DRAM Refresh Control

• Simplifies DRAM control logic

• Options

– Refresh request rate

– Enable/Disable refresh

– PSRAM refre sh han dled with separate pin

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon PIC - Peripheral Interrupt Controller

• Total of 13 interrupts

– 7 internal interrupts

• 3 timer interrupts

• 2 DMA interrupts

• asynchronous serial port interrupt

• watchdog timer interrupt

– 6 external in terrupts

• 5 maskable interrupt pins

• 1 nonmaskable interrupt pin

• Edge or level sensitive

• Masked or slave mode options

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon Hardware Watchdog Timer

• Recover from software hangs

• Generates NMI or system reset

• 1.34 ns timeout at 50 MHz

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon PCB - Peripheral Control Block

• 128 - contiguous 16-bit register

• Provides access to all internal peripherals

• Mapped anywhere in memory or I/O space

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon

ONCE Mode

“On Circuit Emul ation”

• Can be used for boar d testing

• Useful in debugging

• Tri-states all pins

• Activated by tying UCS & LCS low at reset

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon

Options and Timeline for the

Am186ER and Am188ER Revision B

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon Schedule Am186/188 (Rev B)

• Announcement: March 31, 1998

• Data Sheet (printed) : March 31, 1998

• User’s manual (printed): March 31, 1998

• General Samples Avai lable: May 1998

• Demo Boards Avai lable: May 1998

• Production Starts: 3Q98

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon Am186/Am188ER Notes

• The existing Am186/188ER is in full production.

• Rev B yields higher performance and more features.

• Design-ins should occur with Rev B silicon.

• Rev B is backward compatible with Rev A with only 1

exception.

– In external clocking configuration for an oscillator, X2 pin

should f loat instead of being gro unde d as in Rev A. For a

crystal configuration, no changes are required.

– This change was required to imp ro ve the oscillator.

AMD Embedded Processor Division, Am186ER Technical Overview

Systems in Silicon

Options

-50 V C \W

LEAD FORMING

\W = Trimmed and Formed

TEMPERATURE RANGE

C = Commercial(Tc = 0 to 100 C)

Tc = Case temperature

PACKAGE TYPE

V=100-pin thin quad flat pack (TQFP)

K=100-pin plastic quad flat pack(PQFP)

SPEED OPTION

-25=25MHz

-33=33MHz

-40=40MHz

-50=50MHz

DEVICE NUMBER/DESCRIPTION

Am186ER = High-Pe rfor mance, 10C186 -

Compatible 16-Bit Embedded

Microcontroller with 16Kx16 Inte rnal

RAM

Am188ER = High-Pe rfor mance, 80C188 -

Compatible 16-Bit Embedded

Microcontro ller with 32Kx8 Internal

RAM

Am186ER