PDM31516 PDM31516 32K x 16 CMOS 3.3V Static RAM Description Features n n n n n n n n n 1 The PDM31516 is a high-performance CMOS static RAM organized as 32,768 x 16 bits. The PDM31516 features low power dissipation using chip enable (CE) and has an output enable input (OE) for fast memory access. Byte access is supported by upper and lower byte controls. High-speed access times - Com'l: 10, 12, 15 and 20 ns - Ind: 12, 15 and 20 ns Low power operation (typical) - PDM31516SA Active: 200 mW Standby: 10 mW High-density 32K x 16 architecture 3.3V (0.3V) power supply Fully static operation TTL-compatible inputs and outputs Output buffer controls: OE Data byte controls: LB, UB Packages: Plastic SOJ (400 mil) - SO Plastic TSOP (II) - T The PDM31516 operates from a single 3.3V power supply and all inputs and outputs are fully TTLcompatible. The PDM31516 is available in a 44-pin 400-mil plastic SOJ and a 44-pin plastic TSOP (II) package for high-density surface assembly and is suitable for use in high-speed applications requiring high-speed storage. 2 3 4 5 6 7 A7-A0 Row Decoder Row Address Buffer Functional Block Diagram Memory Cell Array 256 x 128 x 32 16K x 32 8 Vcc Vss 9 Data Input/ Output Buffer I/O15-I/O0 Sense Amp 10 Column Decoder WE OE UB LB CE Control Logic Clock Generator 11 Column Address Buffer 12 A14-A8 Rev. 3.1 - 4/27/98 1 PDM31516 Pin Configuration SOJ TSOP (II) NC 1 44 A4 NC 1 44 A4 A3 2 43 A5 A3 2 43 A5 A2 3 42 A6 A2 3 42 A6 A1 4 41 OE A1 4 41 OE A0 5 40 UB A0 5 40 UB CE 6 39 LB CE 6 39 LB I/O0 7 38 I/O15 I/O0 7 38 I/O15 I/O1 8 37 I/O14 I/O1 8 37 I/O14 I/O2 9 36 I/O13 I/O2 9 36 I/O13 I/O3 10 35 I/O12 I/O3 10 35 I/O12 Vcc 11 34 Vss Vcc 11 34 Vss Vss 12 33 Vcc Vss 12 33 Vcc I/O4 32 I/O11 I/O4 I/O11 31 I/O10 I/O5 13 14 32 I/O5 13 14 31 I/O10 I/O6 15 30 I/O9 I/O6 15 30 I/O9 I/O7 16 29 I/O8 I/O7 16 29 I/O8 WE 28 NC WE NC 27 A7 A14 17 18 28 A14 17 18 27 A7 A13 19 26 A8 A13 19 26 A8 A12 20 21 22 25 A9 A12 25 A9 24 A10 A11 24 A10 23 NC NC 20 21 22 23 NC A11 NC Pin Description Name Description A14-A0 Address Inputs I/O15-I/O0 Data Inputs CE Chip Enable Input WE Write Enable Input OE Output Enable Input LB, UB Data Byte Control Inputs NC No Connect Vss Ground VCC Power (+3.3V) Capacitance (TA = +25C, f = 1.0 MHz) Symbol Parameter Conditions Max. Unit CIN Input Capacitance VIN = VSS 6 pF CI/O Output Capacitance VI/O = VSS 8 pF NOTE: 1. This parameter is determined by device characterization, but is not production tested. 2 Rev. 3.1 - 4/27/98 PDM31516 Operating Mode Mode CE OE WE LB UB I/O7-I/O0 I/O15-I/O8 Power Read L L H L L Output Output ICC H L High Impedance Output ICC L H Output High Impedance ICC L L Input Input ICC H L High Impedance Input ICC L H Input High Impedance ICC Write L Output Disable Standby X L L H H X x High Impedance High Impedance ICC L X X H H High Impedance High Impedance ICC H X X X X High Impedance High Impedance ISB 1 2 3 4 NOTE: 1. H = VIH, L = VIL, X = DON'T CARE Absolute Maximum Ratings (1) Symbol Rating Com'l. Ind. Unit VTERM Terminal Voltage with Respect to VSS -0.5 to +4.6 -0.5 to +4.6 V TBIAS Temperature Under Bias -55 to +125 -65 to +135 C TSTG Storage Temperature -55 to +125 -65 to +150 C PT Power Dissipation 1.5 1.5 W IOUT DC Output Current 50 50 mA 125 145 C Tj Maximum Junction Temperature (2) 5 6 7 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Appropriate thermal calculations should be performed in all cases and specifically for those where the chosen package has a large thermal resistance (e.g., TSOP). The calculation should be of the form: Tj = Ta + P * ja where Ta is the ambient temperature, P is average operating power and ja the thermal resistance of the package. For this product, use the following ja values: 8 9 SOJ: 59o C/W TSOP: 87o C/W 10 Recommended DC Operating Conditions Symbol Description VCC VSS Industrial Commercial Rev. 3.1 -4/27/98 Min. Typ. Max. Unit Supply Voltage 3.0 3.3 3.6 V Supply Voltage 0 0 0 V Ambient Temperature -40 25 85 C Ambient Temperature 0 25 70 C 11 12 3 PDM31516 DC Electrical Characteristics (VCC = 3.3V 0.3V) Symbol Parameter Test Conditions Min. Max. Unit ILI Input Leakage Current VCC = Max., VIN = Vss to VCC Com'l/ Ind. -5 5 A ILO Output Leakage Current VCC= Max., CE = VIH, VOUT = Vss to VCC Com'l/ Ind. -5 5 A VIL Input Low Voltage -0.3(1) 0.8 V VIH Input High Voltage 2.2 Vcc + 0.3 V VOL Output Low Voltage IOL = 8 mA, VCC = Min. -- 0.4 V VOH Output High Voltage IOH = -4 mA, VCC = Min. 2.4 -- V NOTE: 1. VIL(min) = -3.0V for pulse width less than 20 ns. Power Supply Characteristics -10 Symbol Parameter ICC Operating Current CE = VIL -12 Com'l Com'l 130 120 -15 Ind. 130 -20 Com'l Ind. Com'l Ind. 110 120 100 110 Unit mA f = fMAX = 1/tRC VCC = Max. IOUT = 0 mA ISB Standby Current CE = VIH 15 15 15 15 15 15 15 mA 2 2 5 2 5 2 5 mA f = fMAX = 1/tRC VCC = Max. ISB1 Full Standby Current CE VHC f=0 VCC = Max., VIN VCC - 0.2V or 0.2V NOTE: All values are maximum guaranteed values. VLC 0.2V, VHC VCC - 0.2V AC Test Conditions Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Output load 4 VSS to 3.0V 2.5 NS 1.5V 1.5V See Figures 1 and 2 Rev. 3.1 - 4/27/98 PDM31516 +3.3V +3.3V 1 317 317 DOUT DOUT 351 351 30 pF 5 pF 2 Figure 2. Output Load Equivalent (for tLZCE, tHZCE, tLZWE, tHZWE) Figure 1. Output Load 3 4 Read Timing Diagram (1) 5 tRC ADDRESSES tAA 6 tOH tACE CE tAOE 7 tHZCE(6) OE tBA tHZOE(6) 8 UB, LB tLZBE(6) tHZBE(6) tLZOE(6) 9 tLZCE(6) DOUT Output Data Valid 10 11 12 Rev. 3.1 -4/27/98 5 PDM31516 AC Electrical Characteristics Description -10 READ Cycle -12 -15 -20 Symbol Min Max Min Max Min Max Min Max Unit READ cycle time tRC 10 -- 12 -- 15 -- 20 -- ns Address access time tAA -- 10 -- 12 -- 15 -- 20 ns Chip enable access time tACE -- 10 -- 12 -- 15 -- 20 ns Byte access time tBA -- 6 -- 7 -- 8 -- 9 ns Output hold from address change tOH 3 -- 3 -- 3 -- 3 -- ns Byte disable to output in low-Z tLZBE 0 -- 0 -- 0 -- 0 -- ns Byte enable to output in high-Z tHZBE -- 7 -- 8 -- 9 -- 9 ns Chip enable to output in low-Z(1) tLZCE 3 -- 3 -- 3 -- 3 -- ns tHZCE -- 6 -- 7 -- 8 -- 9 ns tAOE -- 6 -- 7 -- 8 -- 9 ns tLZOE 0 -- 0 -- 0 -- 0 -- ns tHZOE -- 6 -- 7 -- 8 -- 9 ns Chip disable to output high-Z(1, 2) Output enable access time Output enable to output in low-Z Output disable to output in high-Z(2) NOTES: 1. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE. 2. tHZCE, tHZOE, and tHZWE are specified with CL = 5 pF as in Figure 2. Transition is measured 200 mV from steady state voltage. Write Cycle 1 Timing Diagram (5) (WE Controlled) tWC ADDRESSES tAW tAS tWP tAH WE tCW CE tBW UB, LB tHZWE(6) DOUT (3) tLZWE(6) High Impedance tDS DIN 6 (4) tDH Data Stable Rev. 3.1 - 4/27/98 PDM31516 Write Cycle 2 Timing Diagram(5) (CE Controlled) 1 tWC ADDRESSES tAW tAS tWP tAH 2 WE tCW 3 CE tBW UB, LB tLZBE(6) 4 tHZWE(6) tLZCE(6) High Impedance DOUT tDS DIN 5 tDH Data Stable 6 Write Cycle 3 Timing Diagram(5) (UB, LB Controlled) tWC 7 ADDRESSES tAW tAS tWP tAH 8 WE tCW CE 9 tBW UB, LB tLZCE(6) 10 tHZWE(6) tLZBE(6) High Impedance DOUT tDS DIN tDH 11 Data Stable 12 Rev. 3.1 -4/27/98 7 PDM31516 AC Electrical Characteristics Description -10 WRITE Cycle Sym -12 -15 -20 Min. Max. Min. Max. Min. Max. Min. Max. Unit WRITE cycle time tWC 10 -- 12 -- 15 -- 20 -- ns Chip enable to end of write tCW 9 -- 10 -- 11 -- 12 -- ns Address valid to end of write tAW 9 -- 10 -- 11 -- 12 -- ns Byte pulse width tBW 9 -- 10 -- 12 -- 13 -- ns Address setup time tAS 0 -- 0 -- 0 -- 0 -- ns Address hold from end of write tAH 0 -- 0 -- 0 -- 0 -- ns Write pulse width tWP 7 -- 8 -- 9 -- 10 -- ns Data setup time tDS 6 -- 7 -- 8 -- 9 -- ns Data hold time tDH 0 -- 0 -- 0 -- 0 -- ns Byte disable to output in low Z(4, 5) tLZBE 1 -- 1 -- 1 -- 1 -- ns Byte enable to output in high Z(4, 5) tHZBE -- 7 -- 7 -- 8 -- 9 ns Z(4, 5) tLZOE 0 -- 0 -- 0 -- 0 -- ns Output enable to output in high Z(4, 5) tHZOE -- 7 -- 7 -- 8 -- 9 ns Output disable to output in low Z(4, 5) tLZWE 1 -- 1 -- 1 -- 1 -- ns Write enable to output in high Z(4, 5) tHZWE -- 7 -- 7 -- 8 -- 9 ns Write disable to output in low NOTES: 1. The operating temperature (TA) is guaranteed with transverse air flow exceeding 400 linear feet per minute. 2. WE is HIGH for read cycles. 3. If the CE LOW transition occurs coincident with or after the WE LOW transition, outputs remain in a high impedance state. 4. If the CE HIGH transition occurs coincident with or after the WE HIGH transition, outputs remain in a high impedance state. 5. If OE is HIGH during a write cycle, the outputs are in a high-impedance state during this period. 6. The following parameters are measured using the load shown in Figures 1 and 2. (A) tCOE, tOEE, tBE, tOEW .....Output Enable Time (B) tCOD, tODO, tBD, tODW ....Output Disable Time Ordering Information XXXXX X Device Type Power XX X Speed Package Type X X Process Temp. Range Preferred Shipping Container Blank Tubes TR Tape & Reel TY Tray Blank Commercial (0 to +70C) I Industrial (-40C to +85C) A Automotive ( -40C to +105C) SO T 44-pin 400-mil Plastic SOJ 44-pin Plastic TSOP (II) 10 12 15 20 Commercial Only SA Standard Power PDM31516 - (32Kx16) Static RAM Faster Memories for a Faster World TM 8 Rev. 3.1 - 4/27/98