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PDM31516
Description
The PDM31516 is a high-performance CMOS static
RAM organized as 32,768 x 16 bits. The PDM31516
features low power dissipation using chip enable
(CE) and has an output enable input (OE) for fast
memory access. Byte access is supported by upper
and lower byte controls.
The PDM31516 operates from a single 3.3V power
supply and all inputs and outputs are fully TTL-
compatible.
The PDM31516 is available in a 44-pin 400-mil plas-
tic SOJ and a 44-pin plastic TSOP (II) package for
high-density surface assembly and is suitable for use
in high-speed applications requiring high-speed
storage.
PDM31516
32K x 16 CMOS
3.3V Static RAM
A7-A0 Memory
Cell
Array
256 x 128 x 32
Row Address
Buffer
Control
Logic
Sense Amp
Column
Decoder
Column
Address
Buffer
Row Decoder
Clock
Generator
A14-A8
CE
LB
UB
OE
WE
Data
Input/
Output
Buffer
Vcc
Vss
I/O15-I/O0
Features
n
High-speed access times
- Com’l: 10, 12, 15 and 20 ns
- Ind: 12, 15 and 20 ns
n
Low power operation (typical)
- PDM31516SA
Active: 200 mW
Standby: 10 mW
n
High-density 32K x 16 architecture
n
3.3V (
±
0.3V) power supply
n
Fully static operation
n
TTL-compatible inputs and outputs
n
Output buffer controls: OE
n
Data byte controls: LB, UB
n
Packages:
Plastic SOJ (400 mil) - SO
Plastic TSOP (II) - T
Functional Block Diagram
16K x 32
PDM31516
2 Rev. 3.1 - 4/27/98
Pin Configuration SOJ
Capacitance
(T
A
= +25
°
C, f = 1.0 MHz)
NOTE: 1. This parameter is determined by device characterization, but is not production tested.
Symbol Parameter Conditions Max. Unit
C
IN
Input Capacitance V
IN
= V
SS
6pF
C
I/O
Output Capacitance V
I/O
= V
SS
8pF
1
2
3
4
5
6
7
8
9
10
11
12
15
16 29
30
31
32
NC
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
Vcc
Vss
I/O4
I/O5
I/O6
I/O7
WE
A14
A13
A12
A11
NC
A4
A5
A6
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
Vss
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A7
A8
A9
A10
NC
13
14
33
34
35
36
37
38
39
40
41
42
43
44
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20
21
22
17
18
23
24
25
26
27
28
Pin Description
Name Description
A14-A0 Address Inputs
I/O15-I/O0 Data Inputs
CE Chip Enable Input
WE Write Enable Input
OE Output Enable Input
LB, UB Data Byte Control Inputs
NC No Connect
V
ss
Ground
V
CC
Power (+3.3V)
1
2
3
4
5
6
7
8
9
10
11
12
15
16 29
30
31
32
NC
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
Vcc
Vss
I/O4
I/O5
I/O6
I/O7
WE
A14
A13
A12
A11
NC
A4
A5
A6
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
Vss
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A7
A8
A9
A10
NC
13
14
33
34
35
36
37
38
39
40
41
42
43
44
19
20
21
22
17
18
23
24
25
26
27
28
TSOP (II)
PDM31516
Rev. 3.1 -4/27/98 3
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Operating Mode
NOTE: 1. H = V
IH
, L = V
IL
, X = DON’T CARE
Mode CE OE WE LB UB I/O7-I/O0 I/O15-I/O8 Power
Read L L H L L Output Output I
CC
H L High Impedance Output I
CC
L H Output High Impedance I
CC
Write L X L L L Input Input I
CC
H L High Impedance Input I
CC
L H Input High Impedance I
CC
Output Disable L H H X x High Impedance High Impedance I
CC
L X X H H High Impedance High Impedance I
CC
Standby H XXXXHigh Impedance High Impedance I
SB
Absolute Maximum Ratings
(1)
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all cases and specifically f or
those where the chosen package has a large thermal resistance (e.g., TSOP). The
calculation should be of the form: T
j
= T
a
+ P *
θ
ja
where T
a
is the ambient tempera-
ture, P is a v er age operating po w er and
θ
ja
the thermal resistance of the package. For
this product, use the following
θ
ja
values:
SOJ: 59
o
C/W
TSOP: 87
o
C/W
Recommended DC Operating Conditions
Symbol Rating Com’l. Ind. Unit
V
TERM
Terminal Voltage with Respect to V
SS
–0.5 to +4.6 –0.5 to +4.6 V
T
BIAS
Temperature Under Bias –55 to +125 –65 to +135
°
C
T
STG
Storage Temperature –55 to +125 –65 to +150
°
C
P
T
Power Dissipation 1.5 1.5 W
I
OUT
DC Output Current 50 50 mA
T
j
Maximum Junction Temperature
(2)
125 145
°
C
Symbol Description Min. Typ. Max. Unit
V
CC
Supply V oltage 3.0 3.3 3.6 V
V
SS
Supply V oltage 0 0 0 V
Industrial Ambient Temperature –40 25 85
°
C
Commercial Ambient Temperature 0 25 70
°
C
PDM31516
4 Rev. 3.1 - 4/27/98
Power Supply Characteristics
NOTE: All values are maximum guaranteed values.
V
LC
≤
0.2V, V
HC
≥
V
CC
– 0.2V
-10 -12 -15 -20
Symbol Parameter Com’l Com’l Ind. Com’l Ind. Com’l Ind. Unit
I
CC
Operating Current
CE = V
IL
130 120 130 110 120 100 110 mA
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
OUT
= 0 mA
I
SB
Standby Current
CE = V
IH
15 15 15 15 15 15 15 mA
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
SB1
Full Standby Current
CE
≥
V
HC
2 2 5 2525mA
f = 0
V
CC
= Max.,
V
IN
≥
V
CC
– 0.2V or
≤
0.2V
AC Test Conditions
Input pulse levels VSS to 3.0V
Input rise and fall times 2.5 NS
Input timing reference levels 1.5V
Output reference levels 1.5V
Output load See Figures 1 and 2
DC Electrical Characteristics
(V
CC
= 3.3V
±
0.3V)
NOTE: 1.V
IL
(min) = –3.0V for pulse width less than 20 ns.
Symbol Parameter Test Conditions Min. Max. Unit
I
LI
Input Leakage Current V
CC
= Max., V
IN
= Vss to V
CC
Com’l/
Ind. –5 5
µ
A
I
LO
Output Leakage Current V
CC
= Max.,
CE = V
IH
, V
OUT
= Vss to V
CC
Com’l/
Ind. –5 5
µ
A
V
IL
Input Low Voltage –0.3
(1)
0.8 V
V
IH
Input High Voltage 2.2 Vcc +
0.3 V
V
OL
Output Low Voltage I
OL
= 8 mA, V
CC
= Min. — 0.4 V
V
OH
Output High Voltage I
OH
= –4 mA, V
CC
= Min. 2.4 — V
PDM31516
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Read Timing Diagram (1)
tAA
tRC
UB, LB
OE
CE
ADDRESSES
tOH
tAOE
tBA
DOUT Output Data Valid
tLZBE(6)
tLZOE(6)
tLZCE(6)
tACE
tHZCE(6)
tHZOE(6)
tHZBE(6)
+3.3V
317Ω
351Ω
D
OUT
30 pF
Figure 1. Output Load Figure 2. Output Load Equivalent
(for tLZCE, tHZCE, tLZWE, tHZWE)
+3.3V
317Ω
351Ω
DOUT
5 pF
PDM31516
6 Rev. 3.1 - 4/27/98
AC Electrical Characteristics
NOTES: 1.At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE.
2. tHZCE, tHZOE, and tHZWE are specified with CL = 5 pF as in Figure 2. Transition is measured ± 200 mV from
steady state voltage.
Write Cycle 1 Timing Diagram (5) (WE Controlled)
Description –10 –12 –15 –20
READ Cycle Symbol Min Max Min Max Min Max Min Max Unit
READ cycle time tRC 10—12—15—20—ns
Address access time tAA —10—12—15—20ns
Chip enable access time tACE —10—12—15—20ns
Byte access time tBA —6—7—8—9ns
Output hold from address change tOH 3—3—3—3—ns
Byte disable to output in low-Z tLZBE 0—0—0—0—ns
Byte enable to output in high-Z tHZBE —7—8—9—9ns
Chip enable to output in low-Z(1) tLZCE 3—3—3—3—ns
Chip disable to output high-Z(1, 2) tHZCE —6—7—8—9ns
Output enable access time tAOE —6—7—8—9ns
Output enable to output in low-Z tLZOE 0—0—0—0—ns
Output disable to output in high-Z(2) tHZOE —6—7—8—9ns
t
AW
tAS
t
WC
UB, LB
CE
WE
ADDRESSES
t
WP
t
LZWE(6)
t
CW
t
BW
High Impedance
t
HZWE(6)
t
AH
t
DH
t
DS
Data Stable
(3) (4)
D
OUT
D
IN
PDM31516
Rev. 3.1 -4/27/98 7
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Write Cycle 2 Timing Diagram(5) (CE Controlled)
t
AW
tAS
t
WC
UB, LB
CE
WE
ADDRESSES
t
WP
t
CW
High Impedance
t
DH
t
DS
Data Stable
D
OUT
D
IN
t
AH
t
BW
t
LZBE(6)
t
LZCE(6)
t
HZWE(6)
Write Cycle 3 Timing Diagram(5) (UB, LB Controlled)
tAW
tAS
tWC
UB, LB
CE
WE
ADDRESSES
tWP
tCW
High Impedance
tDH
tDS
Data Stable
DOUT
DIN
tAH
tBW
tLZBE(6)
tLZCE(6) tHZWE(6)
PDM31516
8 Rev. 3.1 - 4/27/98
AC Electrical Characteristics
NOTES: 1. The operating temperature (TA) is guaranteed with transverse air flow exceeding 400 linear feet per minute.
2. WE is HIGH for read cycles.
3. If the CE LOW transition occurs coincident with or after the WE LOW transition, outputs remain in a high impedance
state.
4. If the CE HIGH transition occurs coincident with or after the WE HIGH transition, outputs remain in a high impedance
state.
5. If OE is HIGH during a write cycle, the outputs are in a high-impedance state during this period.
6. The following parameters are measured using the load shown in Figures 1 and 2.
(A) tCOE, tOEE, tBE, tOEW .....Output Enable Time
(B) tCOD, tODO, tBD, tODW ....Output Disable Time
Ordering Information
Description -10 -12 -15 -20
WRITE Cycle Sym Min. Max. Min. Max. Min. Max. Min. Max. Unit
WRITE cycle time tWC 10—12—15—20—ns
Chip enable to end of write tCW 9 —10—11—12—ns
Address valid to end of write tAW 9 —10—11—12—ns
Byte pulse width tBW 9 —10—12—13—ns
Address setup time tAS 0—0—0—0—ns
Address hold from end of write tAH 0—0—0—0—ns
Write pulse width tWP 7—8—9—10—ns
Data setup time tDS 6—7—8—9—ns
Data hold time tDH 0—0—0—0—ns
Byte disable to output in low Z(4, 5) tLZBE 1—1—1—1—ns
Byte enable to output in high Z(4, 5) tHZBE —7—7—8—9ns
Output disable to output in low Z(4, 5) tLZOE 0—0—0—0—ns
Output enable to output in high Z(4, 5) tHZOE —7—7—8—9ns
Write disable to output in low Z(4, 5) tLZWE 1—1—1—1—ns
Write enable to output in high Z(4, 5) tHZWE —7—7—8—9ns
Device Type Power Speed Package
Type
Process
Temp. Range Preferred
Shipping
Container
Commercial (0° to +70°C)
Industrial (–40°C to +85°C)
10 Commercial Only
12
15
20
SA Standard Power
Blank
I
A Automotive (
–40°C to +105°C)
Blank Tubes
TR Tape & Reel
TY Tray
PDM31516 - (32Kx16) Static RAM
XXXXX X XX X X X
SO 44-pin 400-mil Plastic SOJ
T 44-pin Plastic TSOP (II)
Faster Memories for a Faster World ™
