Semiconductor Corporation CS5509 Single Supply, 16-Bit A/D Converter Features Delta-Sigma A/D Converter - 16-bit No Missing Codes - Linearity Error: +0.0015%FS @ Differential Input - Pin Selectable Unipolar/Bipolar Ranges - Common Mode Rejection 105 dB @ de 120 dB @ 50, 60 Hz @ Either 5V or 3.3V Digital Interface @ On-chip Self-Calibration Circuitry @ Output Update Rates up to 200/second General Description The CS5509 is a single supply, 16-bit, serial-output CMOS A/D converter. The CS5509 uses charge-bal- anced (delta-sigma) techniques to provide a low cost, high resolution measurement at output word rates up to 200 samples per second. The on-chip digital fitter offers superior line rejection at 50Hz and 60Hz when the device is operated from a 32.768 kHz clock (output word rate = 20 Hz.). The CS5509 has on-chip self-calibration circuitry which can be initiated at any time or temperature to ensure minimum offset and full-scale errors. Low power, high resolution and small package size make the CS5509 an ideal solution for loop-powered transmitters, panel meters, weigh scales and battery powered instruments. ORDERING INFORMATION: CS5509-AP -40C to +85C 16-pin PDIP @ Ultra Low Power: 1.7 mW CS5509-AS -40C to +85C 16-pin SOIC VREF+ VREF- VA+ GND VD+ 9 10 1 12 cs Serial SCLK 7 Interface AIN+ Differential Logic SDATA 4th order Digital DRDY delta-sigma Filter 8 modulator - AIN- o-2 + | - [ CAL : | Calibration pC BP/UP Calibration SRAM | osc fe tas CONV XIN XOUT Crystal Semiconductor Corporation / . ; MAR '95 P.O. Box 17847, Austin, TX 78760 Copyright Crystal Semiconductor Ty Poration 1998 DS125F 1 (512) 445 7222 FAX: (512) 445 7581 (All Rights Reserved) 2-489 MB 2546324 0007857 2ctbotherwise specified.) (Notes 1, 2) CS5509 ANALOG CHARACTERISTICS (ta = 25C; VA+ = 5V + 10%; VD+ = 3.3V + 5%; VREF+ = 2.5V, VREF- = OV; fe_k = 330KHz; Bipolar Mode; Reource = 502 with a 10nF to GND at AIN; AIN- = 2.5V; unless Parameter* Min Typ Max Units Accuracy Linearity Error foik = 32.768 kHz - 0.0015 0.003 +%FS feik = 165 kHz - 0.0015 0.003 +%FS foLk = 247.5 kHz - 0.0015 0.003 +%FS fork = 330 kHz - 0.005 0.0125 +%FS Differential Nonlinearity - +0.25 +0.5 LSB Full Scale Error (Note 3) - +0.25 +2 LSB Full Scale Drift (Note 4) - 40.5 - LSB Unipolar Offset (Note 3) - +0.5 +2 LSB Unipolar Offset Drift (Note 4) - +0.5 - LSB Bipolar Offset (Note 3) - +0.25 +1 LSB Bipolar Offset Drift (Note 4) - 40.25 - LSB Noise (Referred to Output) - 0.16 - LSBrms Analog Input Analog Input Range: Unipolar - 0 to +2.5 - Volts Bipolar (Note 5, 6) - +2.5 - Volts Common Mode Rejection: de - 105 - dB foLk = 32.768kHz 50,60 Hz (Note 2) 120 - - dB Input Capacitance - 15 - pF DC Bias Current (Note 1) - 5 - nA Power Supplies DC Power Supply Currents: ITotal - 360 450 pA lAnalog - 300 - HA IDigital - 60 : nA Power Dissipation (Note 7) - 1.7 2.25 mw Power Supply Rejection - 80 - dB Notes: 1. Both source resistance and shunt capacitance are critical in determining the CS5509s source impedance requirements. Refer to the text section Analog Input Impedance Considerations. . Specifications guaranteed by design, characterization and/or test. . Applies after calibration at the temperature of interest. . Total drift over the specified temperature range since calibration at power-up at 25C. . The input is differential. Therefore, GND < Signal + Common Mode Voltage < VA+. . The CS5509 can accept input voltages up to the VA+ analog supply. In unipolar mode the CS5509 Oa & wh will output all 1's if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will output all 0s if the input becomes more negative than 0 Volts. in bipolar mode the CS5509 will output all 1s if the de input magnitude ((AIN+)-(AIN-}) exceeds ((VREF+)-(VREF-)) and will output all 0's if the input becomes more negative in magnitude than -((VREF+)-(VREF-)). . All outputs unloaded. All inputs CMOS levels. * Refer to the Specification Definitions immediately following the Pin Description Section. Specifications are subject to change without notice. 2-490 DS125F1 Mi 2S54b3e4 0007858 leoCS5509 DYNAMIC CHARACTERISTICS Parameter Symbol Ratio Units Modulator Sampling Frequency fs fon/2 Hz Output Update Rate (CONV = 1) fout felk/1622 Hz Filter Corner Frequency f-aaB folk/1928 Hz Settling Time to 1/2 LSB (FS Step) ts 1/fout s 5V DIGITAL CHARACTERISTICS (ta = 25C; VAs, VD+ = 5V + 10%; GND = 0.) (Notes 2, 8) Parameter Symbol Min Typ Max Units High-Level Input Voltage: XIN ViH 3.6 - - V All Pins Except XIN VIH 2.0 - - Vv Low-Level Input Voltage: XIN ViL - - 1.5 Vv All Pins Except XIN VIL : : 0.8 Vv High-Level Output Voltage (Note 9)| Vou | (VD+)-1.0 - Vv Low-Level Output Voltage lout = 1.6mA} Voi - - 0.4 Vv Input Leakage Current lin - H1 +10 A 3-State Leakage Current loz - : +10 LA Digital Output Pin Capacitance Cout : 9 : pF Notes: 8. All measurements are performed under static conditions. 9. Iout = -100 WA. This guarantees the ability to drive one TTL load. (VOH = 2.4V @ lout = -40 A). 3.3V DIGITAL CHARACTERISTICS (ta = 25C; VA+ = 5V + 10%; VD+ = 3.3V + 5%; GND = 0.) (Notes 2, 8) Parameter Symbol Min Typ Max Units High-Level Input Voltage: XIN} VI 0.7VD+ - - Vv All Pins Except XIN} VIH 0.6VD+ : - Vv Low-Level Input Voltage: XIN} Vit - - 0.3VD+ Vv All Pins Except XIN| VIL : - 0.16VD+ Vv High-Level Output Voltage lout = -400nA| VoH | (VD+)-0.3 - - Vv Low-Level Output Voltage lout = 400A] VoL : - 0.3 Vv Input Leakage Current lin : +1 +10 nA 3-State Leakage Current loz : +10 nA Digital Output Pin Capacitance Cout : 9 - pF DS125F1 9-491 Mm 2546324 9007859 Ob5 aLogic 0 = OV, Logic 1 = VD+; CL = 50 pF.) (Note 2) CS5509 | 5V SWITCHING CHARACTERISTICS (tq = 25C; VA+, VD+ = 5V + 10%; Input Levels: Parameter Symbol Min Typ Max Units Master Clock Frequency Internal Oscillator: XIN 30.0 32.768 53.0 kHz External Clock: felk 30 : 330 kHz Master Clock Duty Cycle 40 - 60 % Rise Times: Any Digital Input (Note 10)! tise - - 1.0 us Any Digital Output : 50 : ns Fall Times: Any Digital Input (Note 10)} trail - : 1.0 us Any Digital Output : 20 - ns Start-Up Power-On Reset Period (Note 11)| _ tres : 10 - ms Oscillator Start-up Time | XTAL=32.768 kHz (Note 12)| _tosu - 500 - ms Wake-up Period (Note 13)} _ twup - 1800/folk - s Calibration CONV Pulse Width (CAL=1) (Note 14)}| _ tcow 100 - - ns CONV and CAL High to Start of Calibration tscl - - 2/fotk+200 ns Start of Calibration to End of Calibration teal : 3246/falk : s Conversion CONV Pulse Width tepw 100 : - ns CONV High to Start of Conversion tson - - 2ffcotk+200 ns Set Up Time BP/UP stable prior to DRDY falling| __tbus 82/felk - - s Hold Time BP/UP stable after DRDY falls} tbun 0 : - ns Start of Conversion to End of Conversion (Note 15)! _ teon - 1624 /felk - s Notes: 10. Specified using 10% and 90% points on waveform of interest. 11. An internal power-on-reset is activated whenever power is applied to the device. 12. Oscillator start-up time varies with the crystal parameters. This specification does not apply when using an external clock source. 13. The wake-up period begins once the oscillator starts; or when using an external fo|k, after the power-on reset time elapses. 14, Calibration can also be initiated by pulsing CAL high while CONV=1. 15, Conversion time will be 1622/fc|k if CONV remains high continuously. 2-492 Me 2546324 0007660 880 DS125F12p 6 Mt ae ae ae wna ae nn CS5509 3.3V SWITCHING CHARACTERISTICS (ta = 25C; VA+ = 5V + 10%; VD+ = 3.3V + 5%; Input Levels: Logic 0 = OV, Logic 1 = VD+; Cr. = 50 pF.) (Note 2) Parameter Symbol Min Typ Max Units Master Clock Frequency Internal Oscillator: XIN 30.0 32.768 53.0 kHz External Clock: folk 30 - 330 kHz Master Clock Duty Cycle 40 - 60 % Rise Times: Any Digital Input (Note 10)) _ trise - - 1.0 us Any Digital Output - 50 - ns Fall Times: Any Digital Input (Note 10); tral - - 1.0 Ls Any Digital Output : 20 - ns Start-Up Power-On Reset Period (Note 11)| tres : 10 : ms Oscillator Start-up Time XTAL=32.768 kHz (Note 12)| _ tosu : 500 - ms Wake-up Period (Note 13)} _ twup - 1800/felk - s Calibration CONV Pulse Width (CAL=1) (Note 14)} teow 100 : - ns CONV and CAL High to Start of Calibration tscl : - 2/fclk+200 ns Start of Calibration to End of Calibration tcal : 3246 /fok - s Conversion CONV Pulse Width tepw 100 - - ns CONV High to Start of Conversion tsen - : 2ffetk+200 ns Set Up Time BP/UP stable prior to DRDY falling| tous 82 /folk - - s Hold Time BP/UP stable after DRDY falls|__ tbun 0 - : ns Start of Conversion to End of Conversion (Note 15)} _tcon : 1624 /folk - s DS125F1 2-493 WE 25463924 OOO7Sb1L 717ref Fifi ff f ii : maser CS5509 eS XIN XIN/2 CAL I CONV 4 STATE Calibration Figure 1. Calibration Timing (Not to Scale) % XN VIVID SIV VE NN Z XIN/2 Z CONV. Z fo _ Z DRDY BP/UP toon Z tous touh STATE Conversion 7% Z Figure 2. Conversion Timing (Not to Scale) 2-494 DS125F1 Me 2546324 0007862 653 @ eceee e rere eee eee a CS5509 5V SWITCHING CHARACTERISTICS (Ta = 25C; VA+, VD+ = 5V + 10%; Input Levels: Logic 0 = OV, Logic 1 = VD+; CL = 50 pF.) (Note 2) Parameter Symbol Min Typ Max Units Serial Clock fsclk 0 - 2.5 MHz Serial Clock Pulse Width High} tph 200 - - ns Pulse Width Low; _ tol 200 - - ns Access Time: CS Low to data valid (Note 16)| __ tesa : 60 200 ns Maximum Delay Time: SCLK falling to new SDATA bit} tad - 150 310 ns (Note 17) Output Float Delay CS High to output Hi-Z (Note 18) tat - 60 150 ns SCLK falling to Hi-Z} _tta2 : 160 300 ns Notes: 16. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for 2 clock cycles. The propagation delay time may be as great as 2 fo, cycles plus 200 ns. To guarantee proper clocking of SDATA when using asynchronous CS, SCLK(i) should not be taken high sooner than 2 fel + 200 ns after CS goes low. 17. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the serial port shifting mechanism before falling edges can be recognized. 18. If CS is returned high before all data bits are output, the SDATA output will complete the current data bit and then go to high impedance. 3.3V SWITCHING CHARACTERISTICS (ta = 25C; VA+ = 5V + 10%, VD+ = 3.3V + 5%: Input Levels : Logic 0 = OV, Logic 1 = VD+; CL = 50pF.) (Note 2) Parameter Symbol Min Typ Max Units Serial Clock fsclk 0 : 1.25 MHz Serial Clock Pulse Width High| tph 200 - - ns Pulse Width Low, __ tpl 200 : - ns Access Time: CS Low to data valid (Note 16)| __tosd : 100 200 ns Maximum Delay Time: SCLK falling to new SDATA bit] __ tad - 400 600 ns (Note 17) Output Float Delay CS High to output Hi-Z (Note 18)} tra1 - 70 150 ns SCLK falling to Hi-Z| _tta2 - 320 500 ns DS125F1 2-495 =a ES4b324 0007443 S4Tnp nn 0 0 ae a es a binawawnns/ CS5509 Oe DRDY \ os tesd * ie Hw ie that SDATA(o) Hi-Z -{_ MSB MSB-1 \ MSB-2_ } tga le SCLK(i) / | \ | \ DRDY \ Z | Z cs 4 tesd - g SDATA(o) Hi-Z{_MSB__| MSB-1 7) LsB+2 { LSB+H1 { LSB } 4 tdd i fe j tpn ie tha SCLK(i) / [ Z\ tol Figure 3. Timing Relationships (Not to Scale) 2-496 DS125F1 OO?P8b4 42, me7 ann 0 2 ee ee eee a maaan as CS5509 RECOMMENDED OPERATING CONDITIONS (dann = ov) (Note 19) Parameter Symbol Min Typ Max Units DC Power Supplies: Positive Digital VD+ 3.15 5.0 5.5 Vv Positive Analog VA+ 4.5 5.0 5.5 Vv L2 Analog Reference Voltage (Note 20) |(VREF+)-(VREF-) 1.0 2.6 3.6 Vv Analog Input Voltage: (Note 6) Unipolar VAIN 0 - |(VREF+)-(VREF-)} V Bipolar VAIN -((VREF+)-(VREF-))} - |(VREF+)-(VREF-)| V Notes: 19. All voltages with respect to ground. 20. The CS5509 can be operated with a reference voltage as low as 100 mV; but with a corresponding reduction in noise-free resolution. The common mode voltage of the voltage reference may be any value as long as +VREF and -VREF remain inside the supply values of VA+ and GND. ABSOLUTE MAXIMUM RATINGS* Parameter Symbol Min Typ Max Units DC Power Supplies: Ground (Note 21)| GND -0.3 - (VD+)-0.3 Vv Positive Digital (Note 22)} VD+ -0.3 - 6.0 Vv Positive Analog VA+ -0.3 - 6.0 Vv Input Current, Any Pin Except Supplies (Notes 23 & 24) lin - - +10 mA Output Current lout - : +25 mA Power Dissipation (Total) (Note 25) : : 500 mw Analog Input Voltage AiN and VREF pins VINA -0.3 : (VA+)+0.3 Vv Digital Input Voltage VIND -0.3 - (VD+)+0.3 Vv Ambient Operating Temperature TA -40 - 85 C Storage Temperature Tstg -65 - 150 C Notes: 21. No pin should go more positive than (VA+)+0.3V. 22. VD+ must always be less than (VA+)+0.3V, and can never exceed +6.0 V. 23. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pin. 24. Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a power supply pin is + 50 mA. 25. Total power dissipation, including all input currents and output currents. * WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. DS125F1 2-497 MM 7S54b3e4 OO0O78bES 3heCS5509 GENERAL DESCRIPTION The CS5509 is a low power, 16-bit, monolithic CMOS A/D converter designed specifically for measurement of de signals. The CS5509 in- cludes a delta-sigma charge-balance converter, a voltage reference, a calibration microcontroller with SRAM, a digital filter and a serial interface. The CS5509 is optimized to operate from a 32.768 kHz crystal but can be driven by an ex- ternal clock whose frequency is between 30 kHz and 330 kHz. When the digital filter is operated with a 32.768 kHz clock, the filter has zeros pre- cisely at 50 and 60 Hz line frequencies and multiples thereof. The CS5509 uses a "start convert" command to start a convolution cycle on the digital filter. Once the filter cycle is completed, the output port is updated. When operated with a 32.768 kHz clock the ADC converts and updates its output port at 20 samples/sec. The output port operates in a synchronous externally-clocked in- terface format. THEORY OF OPERATION Basic Converter Operation The CS5509 A/D converter has three operating states. These are stand-by, calibration, and con- version. When power is first applied, an internal power-on reset delay of about 10 ms resets all of the logic in the device. The oscillator must then begin oscillating before the device can be con- sidered functional. After the power-on reset is applied, the device enters the wake-up period for 1800 clock cycles after clock is present. This al- lows the delta-sigma modulator and other circuitry (which are operating with very low cur- rents) to reach a stable bias condition prior to entering into either the calibration or conversion states. During the 1800 cycle wake-up period, the device can accept an input command. Execu- tion of this command will not occur until the complete wake-up period elapses. If no com- mand is given, the device enters the standby state. Calibration After the initial application of power, the CS5509 must enter the calibration state prior to performing accurate conversions. During calibra- tion, the chip executes a two-step process. The device first performs an offset calibration and then follows this with a gain calibration. The two calibration steps determine the zero refer- ence point and the full scale reference point of the converters transfer function. From these points it calibrates the zero point and a gain slope to be used to properly scale the output digital codes when doing conversions. The calibration state is entered whenever the CAL and CONV pins are high at the same time. The state of the CAL and CONV pins at power- on are recognized as commands, but will not be executed until the end of the 1800 clock cycle wake-up period. If CAL and CONV become active (high) during the 1800 clock cycle wake-up time, the converter will wait until the wake-up period elapses before executing the calibration. If the wake-up time has elapsed, the converter will be in the standby mode waiting for instruction and will enter the calibration cycle immediately if CAL and CONV become active. The calibration lasts for 3246 clock cycles. Calibration coefficients are then retained in the SRAM (static RAM) for use dur- ing conversion. The state of BP/UP is ignored during calibration but should remain stable throughout the calibra- tion period to minimize noise. When conversions are performed in unipolar mode or in bipolar mode, the converter uses the same calibration factors to compute the digital 2-498 DS125F1 Me 2546324 O0078bb OTT aCS5509 output code. The only difference is that in bipo- Jar mode the on-chip microcontroller offsets the computed output word by a code value of 8000H. This means that the bipolar measure- ment range is not calibrated from full scale positive to full scale negative. Instead it is cali- brated from the bipolar zero scale point to full scale positive. The slope factor is then extended below bipolar zero to accommodate the negative input signals. The converter can be used to con- vert both unipolar and bipolar signals by changing the BP/UP pin. Recalibration is not re- quired when switching between unipolar and bipolar modes. At the end of the calibration cycle, the on-chip microcontroller checks the logic state of the CONV signal. If the CONV input is low the de- vice will enter the standby mode where it waits for further instruction. If the CONV signal is high at the end of the calibration cycle, the con- verter will enter the conversion state and perform a conversion on the input channel. The CAL signal can be returned low any time after calibration is initiated. CONV can also be re- turned low, but it should never be taken low and then taken back high until the calibration period has ended and the converter is in the standby state. If CONV is taken low and then high again with CAL high while the converter is calibrating, the device will interrupt the current calibration cycle and start a new one. If CAL is taken low and CONV is taken low and then high during calibration, the calibration cycle will continue as the conversion command is disregarded. The state of BP/UP is not important during calibra- tions. If an "end of calibration signal is desired, pulse the CAL signal high while leaving the CONV signal high continuously. Once the calibration is completed, a conversion will be performed. At the end of the conversion, DRDY will fall to in- dicate the first valid conversion after the calibration has been completed. Conversion The conversion state can be entered at the end of the calibration cycle, or whenever the converter is idle in the standby mode. If CONV is taken high to initiate a calibration cycle ( CAL also high), and remains high until the calibration cy- cle is completed (CAL is taken low after CONV transitions high), the converter will begin a con- version upon completion of the calibration period. The BP/UP pin is not a latched input. The BP/UP pin controls how the output word from the digital filter is processed. In bipolar mode the output word computed by the digital filter is offset by 8000H (see Understanding Converter Calibration). BP/UP can be changed after a con- version is started as long as it is stable for 82 clock cycles of the conversion period prior to DRDY falling. If one wishes to intermix meas- urement of bipolar and unipolar signals on various input signals, it is best to switch the BP/UP pin immediately after DRDY falls and leave BP/UP stable until DRDY falls again. The digital filter in the CS5509 has a Finite Im- pulse Response and is designed to settle to full accuracy in one conversion time. if CONV is left high, the CS5509 will perform continuous conversions. The conversion time will be 1622 clock cycles. If conversion is initi- ated from the standby state, there may be up to two XIN clock cycles of uncertainty as to when conversion actually begins. This is because the internal logic operates at one half the external clock rate and the exact phase of the internal clock may be 180 out of phase relative to the XIN clock. When a new conversion is initiated from the standby state, it will take up to two XIN clock cycles to begin. Actual conversion will use 1624 clock cycles before DRDY goes low to indicate that the serial port has been up- dated. See the Serial Interface Logic section of DS125F1 2-499 we 254b3e4 O0076b? 135 =(ee the data sheet for information on reading data from the serial port. In the event the A/D conversion command (CONV going positive) is issued during the con- version state, the current conversion will be terminated and a new conversion will be initi- ated. Voltage Reference The CS5509 uses a differential voltage reference input. The positive input is VREF+ and the negative input is WREF-. The voltage between VREF+ and VREF- can range from 1 volt mini- mum to 3.6 volts maximum. The gain slope will track changes in the reference without recalibra- tion, accommodating ratiometric applications. Analog Input Range The analog input range is set by the magnitude of the voltage between the VREF+ and VREF- pins. In unipolar mode the input range will equal the magnitude of the voltage reference. In bipolar mode the input voltage range will equate to plus and minus the magnitude of the voltage reference. While the voltage reference can be as great as 3.6 volts, its common mode voltage can be any value as long as the reference inputs VREF+ and VREF- stay within the supply volt- ages VA+ and GND. The differential input voltage can also have any common mode value as long as the maximum signal magnitude stays within the supply voltages. The A/D converter is intended to measure de or low frequency inputs. It is designed to yield ac- curate conversions even with noise exceeding the input voltage range as long as the spectral com- ponents of this noise will be filtered out by the digital filter. For example, with a 3.0 volt refer- ence in unipolar mode, the converter will accurately convert an input de signal up to 3.0 volts with up to 15% overrange for 60 Hz noise. A 3.0 volt de signal could have a 60 Hz CS5509 Unipolar Input Output Bipolar Input Voltage Codes Voltage >(VREF - 1.5 LSB) FFFF | >(VREF - 1.5 LSB) FFEF VREF - 1.5 LSB FFFE | VREF-1.5LSB 8000 VREF/2 - 0.5 LSB 7FFF -0.5 LSB 0001 +0.5 LSB 0000 | -VREF +0.5 LSB <(+0.5 LSB) 0000 |<(-VREF +0.5 LSB) Note: Table excludes common mode voltage on the signal and reference inputs. Table 1. Output Coding component which is 0.5 volts above the maxi- mum input of 3.0 (3.5 volts peak; 3.0 volts dc plus 0.5 volts peak noise) and still accurately convert the input signal (XIN = 32.768 kHz). This assumes that the signal plus noise ampli- tude stays within the supply voltages. The CS5509 converters output data in binary format when converting unipolar signals and in offset binary format when converting bipolar sig- nals. Table 1 outlines the output coding for both unipolar and bipolar measurement modes. Converter Performance The CS5509 A/D converter has excellent linear- ity performance. Calibration minimizes the errors in offset and gain. The CS5509 device has no missing code performance to 16-bits. Figure 4 illustrates the DNL of the CS5509, The converter achieves Common Mode Rejection (CMR) at de of 105 dB typical, and CMR at 50 and 60 Hz of 120 dB typical. The CS5509 can experience some drift as tem- perature changes. The CS5509_ uses chopper-stabilized techniques to minimize drift. Measurement errors due to offset or gain drift can be eliminated at any time by recalibrating the converter. 2-500 DS125F1 ME 2546324 0007468 O71ee CS5509 +1 TIT TIT Ty TT Ty TETTTyT TT DNL (LSB) TH T es 42 -- ea ] bo 32,768 65,535 Codes Figure 4. CS5509 Differential Nonlinearity plot. Analog Input Impedance Considerations The analog input of the CS5509 can be modeled as illustrated in Figure 5. Capacitors (15 pF each) are used to dynamically sample each of the inputs (AIN+ and AIN-). Every half XIN cycle the switch alternately connects the capacitor to the output of the buffer and then directly to the AIN pin. Whenever the sample capacitor is switched from the output of the buffer to the AIN pin, a small packet of charge (a dynamic demand of current) is required from the input source to settle the voltage of the sample capaci- tor to its final value. The voltage on the output of the buffer may differ up to 100 mV from the actual input voltage due to the offset voltage of the buffer. Timing allows one half of a XIN clock cycle for the voltage on the sample capaci- tor to settle to its final value. AIN+ 15 pF Vos $ 100 mena internal +t Bias / AIN- =, fohage a 145 pF a aie Figure 5. Analog Input Model An equation for the maximum acceptable source resistance is derived. -1 Rsmax = Ve 2XIN (15pF + Cpx7) In| *- (ISpF + CEXT) In vy. , LSpFd0Omy) (1S5pF + CexT This equation assumes that the offset voltage of the buffer is 100 mV, which is the worst case. The value of Ve is the maximum error voltage which is acceptable. CRxT is the combination of any external or stray capacitance. For a maximum error voltage (Ve) of 10 LV in the CS5509 (1/4LSB at 16-bits), the above equa- tion indicates that when operating from a 32.768 kHz XIN, source resistances up to 110 kQ are acceptable in the absence of external capacitance (CEXT = 0). The VREF+ and VREF- inputs have nearly the same structure as the AIN+ and AIN- inputs. Therefore, the discussion on analog input imped- ance applies to the voltage reference inputs as well. DS125F1 2-501 M@ 2546324 0007669 TOS a0 1 1 0 Net eo XV 82,768KHZ - - \ot ot | 1X22 880.00kHz Attenuation (dB) oO o -100 -120 -160 T T T T q T T T 7 t T T T x1 0 40 80 120 160 200 240 X2 0 402.83 805.66 1208.5 1611.3 2014.2 2416.9 Frequency (Hz) Figure 6. Filter Magnitude Plot to 260 Hz 0 20+ - +0: . Frequency : 1 ~ 407 " 2 a 3 ZT et... 4 ae 3 6 3 eee -80 7 x 8 -100 7 8 10 | 7 W205 00 ot -140 t t t 1 t t t t t oO 5 10 15 20 25 30 35 40 45 50 Frequency (Hz) Figure 7. Filter Magnitude Plot to 50 Hz Digital Filter Characteristics The digital filter in the CS5509 is the combina- tion of a comb filter and a low pass filter. The comb filter has zeros in its transfer function which are optimally placed to reject line interfer- ence frequencies (50 and 60 Hz and their multiples) when the CS5509 is clocked at 32.768 kHz. Figures 6, 7 and 8 illustrate the magnitude and phase characteristics of the filter. CS5509 Frequency | Notch |j/Frequency | Minimum (Hz) Depth (Hz) Attenuation (dB) (dB) 50 125.6 504+1% 55.5 60 126.7 604+1% 58.4 100 145.7 10041% 62.2 120 136.0 12041% 68.4 150 118.4 15041% 74.9 180 132.9 18041% 87.9 200 102.5 200+1% 94.0 240 108.4 24041% 104.4 Table 2. Filter Notch Attenuation (XIN = 32.768 kHz) 190 135 te INR ee 90 7 45 4 45+ - Phase (Degrees) Oo -90 4 -135 + -180 oe ee ee ee he ee XIN = 32.768 kHz ge woe ee eee 0 T T T T t T F T 15 20 25 30 36 40 45 50 Frequency (Hz) Figure 8. Filter Phase Plot to 50 Hz Figure 6 illustrates the filter attenuation from dc to 260 Hz. At exactly 50, 60, 100, and 120 Hz the filter provides over 120 dB of rejection. Ta- ble 2 in dicates the filter attenuation for each of the potential line interference frequencies when the converter is operating with a 32.768 kHz clock. The converter yields excellent attenuation of these damenta interference frequencies even if the fun- I line frequency should vary + 1% from 2-502 MB 2546324 0007870 727 DS125F1CS5509 a a a a enna its specified frequency. The -3dB corner fre- quency of the filter when operating from a 32.768 kHz clock is 17 Hz. Figure 8 illustrates that the phase characteristics of the filter are pre- cisely linear phase. If the CS5509 is operated at a clock rate other than 32.768 kHz, the filter characteristics, in- cluding the comb filter zeros, will scale with the operating clock frequency. Therefore, optimum rejection of line frequency interference will oc- cur with the CS5509 running at 32.768 kHz. Anti-Alias Considerations for Spectral Measurement Applications Input frequencies greater than one half the out- put word rate (CONV = 1) may be aliased by the converter. To prevent this, input signals should be limited in frequency to no greater than one half the output word rate of the converter (when CONV =1). Frequencies close to the modulator sample rate (XIN/2) and multiples thereof may also be aliased. If the signal source includes spectral components above one half the output word rate (when CONV = 1) these components should be removed by means of low-pass filter- ing prior to the A/D input to prevent aliasing. Spectral components greater than one half the output word rate on the VREF inputs (VREF+ and VREF-) may also be aliased. Filtering of the reference voltage to remove these spectral com- ponents from the reference voltage is desirable. Crystal Oscillator The CS5509 is designed to be operated using a 32.768 kHz tuning fork" type crystal. One end of the crystal should be connected to the XIN input. The other end should be attached to XOUT. Short lead lengths should be used to minimize stray capacitance. Over the industrial temperature range (-40 to +85 C) the on-chip gate oscillator will oscillate with other crystals in the range of 30 kHz to 53 kHz. The chip will operate with external clock frequencies from 30 kHz to 330 kHz over the in- dustrial temperature range. The 32.768 kHz crystal is normally specified as a time-keeping crystal with tight specifications for both initial frequency and for drift over temperature. To maintain excellent frequency stability, these crys- tals are specified only over limited operating temperature ranges (i.e. -10 C to +60 C) by the manufacturers. Applications of these crystals with the CS5509 does not require tight initial tolerance or low tempco drift. Therefore, a lower cost crystal with looser initial tolerance and tem- peo will generally be adequate for use with the CS5509. Also check with the manufacturer about wide temperature range application of their standard crystals. Generally, even those crystals specified for limited temperature range will oper- ate over much larger ranges if frequency stability over temperature is not a requirement. The fre- quency stability can be as bad as +3000 ppm over the operating temperature range and still be typically better than the line frequency (50 Hz or 60 Hz) stability over cycle-to-cycle during the course of a day. Serial Interface Logic The digital filter in the CS5509 takes 1624 clock cycles to compute an output word once a con- version begins. At the end of the conversion cycle, the filter will attempt to update the serial port. Two clock cycles prior to the update DRDY will go high. When DRDY goes high Just prior to a port update it checks to see if the port is either empty or unselected (CS = 1). If the port is empty or unselected, the digital filter will update the port with a new output word. When new data is put into the port DRDY will go low. DS125F1 2-503 2546324 0007471 bbbCS5509 Reading Serial Data SDATA is the output pin for the serial data. When CS goes low after new data becomes available (DRDY goes low), the SDATA pin comes out of Hi-Z with the MSB data bit pre- sent, SCLK is the input pin for the serial clock. If the MSB data bit is on the SDATA pin, the first rising edge of SCLK enables the shifting mechanism. This allows the falling edges of SCLK to shift subsequent data bits out of the port. Note that if the MSB data bit is output and the SCLK signal is high, the first falling edge of SCLK will be ignored because the shifting mechanism has not become activated. After the first rising edge of SCLK, each subsequent fall- ing edge will shift out the serial data. Once the LSB is present, the falling edge of SCLK will cause the SDATA output to go to Hi-Z and DRDY to return high. The serial port register will be updated with a new data word upon the completion of another conversion if the serial port has been emptied, or if the CS is inactive (high). CS can be operated asynchronously to the DRDY signal. The DRDY signal need not be monitored as long as the CS signal is taken low for at least two XIN clock cycles plus 200 ns prior to SCLK being toggled. This ensures that CS has gained control over the serial port. Power Supplies and Grounding The analog and digital supply pins to the CS5509 are brought out on separate pins to minimize noise coupling between the analog and digital sections of the chip. In the digital section of the chip the supply current flows into the VD+ pin and out of the GND pin. As a CMOS device, the CS5509 requires that the supply volt- age on the VA+ pin always be more positive than the voltage on any other pin of the device. If this requirement is not met, the device can latch-up or be damaged. In all circumstances the VA+ voltage must remain more positive than the VD+ or GND pins; VD+ must remain more positive than the GND pin. Figure 9a illustrates the System Connection Dia- gram for the CS5509. Note that all supply pins are bypassed with 0.1 uF capacitors and that the VD+ digital supply is derived from the VA+ sup- ply. Figure 9b illustrates the CS5509 operating from a +5V analog supply and +3.3V digital supply. When using separate supplies for VA+ and VD+, VA+ must be established first. WD+ should never become more positive than VA+ under any operating condition. Remember to investigate transient power-up conditions, when one power supply may have a faster rise time. SHER se ee) Maal Sa es Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Os Call Applications Engineering. Caii:(512)445-7222 2-504 DS125F1 ME 2546324 0007872 ST2 mmTF EE a a CS5509 100 AWW +5V 0.1] uF 0.1] pF Analog __ 11 13 _ Supply v VA+ VD+ v Optional 4 14 Clock Lp XIN SCLK Serial Source =. Data 32.768 kHz4, XOUT SDATA| 1 + interface CS5509 7 Analog AIN+ Signal , 8 AIN- ==| 1 cS CONV +2 + 25) VREF+ eat 3 Logie Voltage BP/UP Reference_ 10.) VREF- DRpy | GND ji2 \7 Figure 9a. System Connection Diagram Using a Single Supply DS125F1 2-505 me cS4b3aek poo7a7a 434 =ap a 0 0 ee ae ae a mina nna CS5509 Note: VD+ must never be more positive than VA+ 0 +3.3V to +5V +5V 0.1] uF 0.1} WF Digital Analog _ 1 13 __ Supply Supply v VA+ VD+ v7 Optional 4 14 Clock | TT XIN SCLK Serial Source Ss, Data 32.768 kHz J XOUT spata 1 Interface C$5509 7 Analog oP AINE Signal , 8! AIN- | 1 cs CONV 2 3 : CAL ome Voltage ~ VREF+ BP/UP Reference | 10 VREF- DRDY 16 GND jie V7 Figure 9b. System Connection Diagram Using Split Supplies 2-506 DS125F1 Mm 2546324 0007874 375 mm1 mE 2 0 ae eee eee a misao fsa CS5509 Le PIN DESCRIPTIONS* CHIP SELECT DATA READY CONVERT SERIAL DATA OUTPUT CALIBRATE SERIAL CLOCK INPUT CRYSTAL IN POSITIVE DIGITAL POWER CRYSTAL OUT GROUND BIPOLAR/UNIPOLAR DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT POSITIVE ANALOG POWER VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT *Pinout applies to both PDIP and SOIC Clock Generator XIN; XOUT - Crystal In; Crystal Out, Pins 4, 5. A gate inside the chip is connected to these pins and can be used with a crystal to provide the master clock for the device. Alternatively, an external (CMOS compatible) clock can be supplied into the XIN pin to provide the master clock for the device. Loss of clock will put the device into a lower powered state (approximately 70% power reduction). Serial Output I/O CS - Chip Select, Pin 1. This input allows an external device to access the serial port. DRDY - Data Ready, Pin 16. Data Ready goes low at the end of a digital filter convolution cycle to indicate that a new output word has been placed into the serial port. DRDY will return high after all data bits are shifted out of the serial port or two master clock cycles before new data becomes available if the CS pin is inactive (high). SDATA - Serial Data Output, Pin 15. SDATA is the output pin of the serial output port. Data from this pin will be output at a rate determined by SCLK. Data is output MSB first and advances to the next data bit on the falling edges of SCLK. SDATA will be in a high impedance state when not transmitting data. SCLK - Serial Clock Input, Pin 14. A clock signal on this pin determines the output rate of the data from the SDATA pin. This pin must not be allowed to float. DS125F1 2-507 wa 2546324 0007875 col meaD nn 0 a ae aes a finan! CS5509 a Control Input Pins CAL - Calibrate, Pin 3. When taken high the same time that the CONV pin is taken high the converter will perform a self-calibration which includes calibration of the offset and gain scale factors in the converter. CONV - Convert, Pin 2. The CONV pin initiates a calibration cycle if it is taken from low to high while the CAL pin is high, or it initiates a conversion if it is taken from low to high with the CAL pin low. If CONV is held high (CAL low) the converter will do continuous conversions. BP/UP - Bipolar/Unipolar, Pin 6. The BP/UP pin selects the conversion mode of the converter. When high the converter will convert bipolar input signals; when low it will convert unipolar input signals. Measurement and Reference Inputs AIN+, AIN- - Differential Analog Inputs, Pins 7, 8. Analog differential inputs to the delta-sigma modulator. VREF+, VREF- - Differential Voltage Reference Inputs, Pins 9, 10. A differential voltage reference on these pins operates as the voltage reference for the converter. The voltage between these pins can be any voltage between 1.0 and 3.6 volts. Power Supply Connections VA+ - Positive Analog Power, Pin 11. Positive analog supply voltage. Nominally +5 volts. VD+ - Positive Digital Power, Pin 13. Positive digital supply voltage. Nominally +5 volts or +3.3 volts. GND - Ground, Pin 12. Ground. 2-508 DS125F1 Wm 2546324 O00787b 145 Me Meena eeae a 2 0a ae ees nwa nen CS5509 SPECIFICATION DEFINITIONS Linearity Error The deviation of a code from a straight line which connects the two endpoints of the A/D Converter transfer function. One endpoint is located 1/2 LSB below the first code transition and the other endpoint is located 1/2 LSB beyond the code transition to all ones. Units in percent of full-scale. Differential Nonlinearity The deviation of a codes width from the ideal width. Units in LSBs. Full Scale Error The deviation of the last code transition from the ideal [{(VREF+) - (VREF-)} - 4 LSB]. Units are in LSBs. Unipolar Offset The deviation of the first code transition from the ideal (4 LSB above the voltage on the AIN- pin.) when in unipolar mode (BP/UP low). Units are in LSBs. Bipolar Offset The deviation of the mid-scale transition (011...111 to 100...000) from the ideal (4 LSB below the voltage on the AIN- pin.) when in bipolar mode (BP/UP high). Units are in LSBs DS125F1 = me 2546324 ooo7a7? O84 MeCS5509 ree APPENDIX The following companies provide 32.768 kHz crystals in many package varieties and temperature ranges. Fox Electronics 5570 Enterprise Parkway Fort Meyers, FL 33905 (813) 693-0099 Micro Crystal Division / SMH 702 West Algonquin Road Arlington Heights, IL 60005 (708) 806-1485 SaRonix 4010 Transport Street Palo Alto, California 94303 (415) 856-6900 Statek 512 North Main Orange, California 92668 (714) 639-7810 TQD Lid. North Street Crewkerne Somerset TA18 7AK England 01460 77155 Mr. Pierre Hersberger Microcrystal/DIV. ETA S.A. Schild-Rust-Strasse 17 Grenchen CH-2540 Switzerland 065 53 05 57 Taiwan Xtal Corp. 5E. No. 16, Sec 2, Chung Yang S. RD. Reitou, Taipei, Taiwan R. O. C. Tel: 02-894-1202 Fax: 02-895-6207 Interquip Limited 24/F Million Fortune Industrial Centre 34-36 Chai Wan Kok Street, Tsuen Wan N T Tel: 4135515 Fax: 4137053 S& T Enterprises, Ltd. Rm 404 Blk B Sea View Estate North Point, Hong Kong Tel: 5784921 Fax: 8073126 Mr. Darren Mcleod Hy-Q International Pty. Ltd. 12 Rosella Road, FRANKSON, 3199 Victoria, Australia Tel: 61-3-783 9611 Fax: 61-3-783 9703 2-510 DS125F1 mm 2546324 0007678 TL0