Revision 1.1
Jan. 2004
1
R0201-BS62LV4006
Very Low Power/Voltage CMOS SRAM
512K X 8 bit
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade: 29mA (@55ns) operating current
I -grade: 30mA (@55ns) operating current
C-grade: 24mA (@70ns) operating current
I -grade: 25mA (@70ns) operating current
0.45uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 68mA (@55ns) operating current
I -grade: 70mA (@55ns) operating current
C-grade: 58mA (@70ns) operating current
I -grade: 60mA (@70ns) operating current
2.0uA (Typ.) CMOS standby current
• High speed access time :
-55 55ns
-70 70ns
• Automatic power down when chip is deselected
• Fully static operation
The BS62LV4006 is a high performance, very low power CMOS
Static Random Access Memory organized as 524,288 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.45uA at 3.0V/25oCand maximum access time of 55ns at 3.0V/85oC.
Easy memory expansion is provided by an active LOW chip enable
(CE) , and active LOW output enable (OE) and three-state output
drivers.
The BS62LV4006 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV4006 is available in the JEDEC standard 32L SOP, TSOP
, PDIP, TSOP II and STSOP package.
DESCRIPTION
FEATURES
BLOCK DIAGRAM
PRODUCT FAMILY
PIN CONFIGURATIONS
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Address
Input
Buffer
Row
Decoder
Memory Array
2048 X 2048
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
Address Input Buffer
Data
Buffer
Input
Control
GND
Vdd
OE
WE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
8
8
8
8
16
256
2048
2048
22
A11 A9 A8 A3 A2 A1 A0 A10
BS62LV4006
BSI
POWER DISSIPATION
SPEED
( ns ) STANDBY
( I CCSB1 , Max )
Operating
( I CC , Max ) PKG
TYPE
BS62LV4006TC TSOP-32
BS62LV4006STC STSOP-32
BS62LV4006SC SOP -32
BS62LV4006EC TSOP2-32
BS62LV4006PC
+0 O C to +70 O C 2.4V ~ 5.5V 55 / 70 5uA 30uA 24mA 58mA
PDIP -32
BS62LV4006TI TSOP-32
BS62LV4006STI STSOP-32
BS62LV4006SI SOP -32
BS62LV4006EI TSOP2-32
BS62LV4006PI
-40 O C to +85 O C 2.4V ~ 5.5V 55 / 70 10uA 60uA 25mA 60mA
PDIP -32
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
A11
A9
A8
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
A6
A5
A4
•
BS62LV4006TC
BS62LV4006STC
BS62LV4006TI
BS62LV4006STI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
•
BS62LV4006SC
BS62LV4006SI
BS62LV4006EC
BS62LV4006EI
BS62LV4006PC
BS62LV4006PI
PRODUCT
FAMILY OPERATING
TEMPERATURE Vcc
RANGE 55ns :3.0~5.5V Vcc = 3.0V Vcc = 3.0V Vcc =5.0V
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• Three state outputs and TTL compatible
70ns :2.7~5.5V Vcc =5.0V 70ns 70ns
Revision 1.1
Jan. 2004
2
R0201-BS62LV4006
Name Function
A0-A18 Address Input These 19 address inputs select one of the 524,288 x 8-bit words in the RAM
CE Chip Enable Input CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
DQ0-DQ7 Data Input/Output
Ports
These 8 bi-directional ports are used to read data from or write data into the RAM.
Vcc Power Supply
GND Ground
TRUTH TABLE
PIN DESCRIPTIONS
BSI
MODE WE CE OE I/O OPERATION Vcc CURRENT
Not selected X H X High Z ICCSB, ICCSB1
Output Disabled H L H High Z ICC
Read H L L DOUT ICC
Write L L X DIN ICC
SYMBOL PARAMETER CONDITIONS MAX. UNIT
CIN Input
Capacitance
VIN=0V 6 pF
CDQ Input/Output
Capacitance
VI/O=0V 8 pF
ABSOLUTE MAXIMUM RATINGS(1) OPERATING RANGE
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not 100% tested.
SYMBOL PARAMETER RATING UNITS
V
TERM Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5 V
T
BIAS Temperature Under Bias -40 to +85 O C
T
STG Storage Temperature -60 to +150 O C
P
T Power Dissipation 1.0 W
I
OUT DC Output Current 20 mA
BS62LV4006
RANGE AMBIENT
TEMPERATURE Vcc
Commercial 0 O C to +70 O C 2.4V ~ 5.5V
Industrial -40 O C to +85 O C 2.4V ~ 5.5V
Revision 1.1
Jan. 2004
3
R0201-BS62LV4006
1. Typical characteristics are at TA= 25oC. 2. Fmax = 1/tRC .
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4. IccSB1_MAX. is 5uA/30uA at Vcc=3.0V/5.0V and TA=70oC. 5. Icc_MAX. is 30mA(@3.0V)/70mA(@5.0V) under 55ns operation.
DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC )
1. Vcc = 1.5V, TA= + 25OC
2. tRC = Read Cycle Time
3. IccDR_MAX. is 0.8uA at TA=70OC.
DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
BSI
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
CE
Data Retention Mode
Vcc
tCDR
Vcc
tR
VIHVIH
Vcc VDR 1.5V
≥
CE Vcc - 0.2V
≥
BS62LV4006
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS
VDR Vcc for Data Retention CE ≧ Vcc - 0.2V
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V 1.5 -- -- V
ICCDR Data Retention Current CE ≧ Vcc - 0.2V
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V -- 0.3 1.3 uA
tCDR Chip Deselect to Data
Retention Time 0 -- -- ns
tR Operation Recovery Time
See Retention Waveform
TRC
(2) -- -- ns
PARAMETER
NAME PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS
VIL Guaranteed Input Low
Voltage(3) -0.5 -- 0.8 V
VIH Guaranteed Input High
Voltage(3) 2.2 -- Vcc+0.3 V
IIL Input Leakage Current Vcc = Max, VIN = 0V to Vcc -- -- 1 uA
ILO Output Leakage Current Vcc = Max, CE = VIH, or OE = VIH,
VI/O = 0V to Vcc -- -- 1 uA
VOL Output Low Voltage -- -- V
VOH Output High Voltage Vcc = Min, IOH = -1.0mA -- -- V
ICC Operating Power Supply
Current
CE = VIL, IDQ = 0mA,
F=Fmax(2) -- -- 25 mA
ICCSB Standby Current-TTL CE = VIH, IDQ = 0mA -- --
1.0
mA
ICCSB1 CE ≧Vcc-0.2V,
VIN ≧Vcc - 0.2V or VIN ≦0.2V -- 0.45
60
uA
Vcc = 3.0 V
Vcc = 3.0 V
Vcc = 5.0 V
Vcc = 5.0 V
Vcc = 5.0 V
Vcc = 3.0 V
Vcc = 3.0 V
Standby Current-CMOS
Vcc = 5.0 V
Vcc = 5.0 V
Vcc = 3.0 V
10
60
Vcc = 5.0 V
Vcc = 5.0 V
Vcc = 3.0 V
Vcc = 3.0 V
0.8
2.0
2.4
0.4
0.5
2.0
2.4
0.4
Vcc = Max, IOL = 2.0mA
(5)
(4)
70ns
70ns
Revision 1.1
Jan. 2004
4
R0201-BS62LV4006
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
BSI BS62LV4006
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output
Timing Reference Level
0.5Vcc
Output Load
CL = 30pF+1TTL
CL = 100pF+1TTL
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME DESCRIPTION UNIT
tAVAX tRC Read Cycle Time 55 -- -- 70 -- -- ns
tAVQV tAA Address Access Time -- -- 55 -- -- 70 ns
tELQV tACS Chip Select Access Time -- -- 55 -- -- 70 ns
tGLQV tOE Output Enable to Output Valid -- -- 30 -- -- 35 ns
tELQX tCLZ Chip Select to Output Low Z 10 -- -- 10 -- -- ns
tGLQX tOLZ Output Enable to Output in Low Z 10 -- -- 10 -- -- ns
tEHQZ tCHZ Chip Deselect to Output in High Z -- -- 30 -- -- 35 ns
tGHQZ tOHZ Output Disable to Output in High Z -- -- 25 -- -- 30 ns
tAXOX tOH Data Hold from Address Change 10 -- -- 10 -- -- ns
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t RC
t OH
t AA
DOUT
ADDRESS
t OH
CYCLE TIME : 55ns
MIN. TYP. MAX.
(Vcc = 3.0~5.5V)
MIN. TYP. MAX.
(Vcc = 2.7~5.5V)
CYCLE TIME : 70ns
Revision 1.1
Jan. 2004
5
R0201-BS62LV4006
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL .
5. The parameter is guaranteed but not 100% tested.
BSI BS62LV4006
READ CYCLE3 (1,4)
READ CYCLE2 (1,3,4)
tCLZ
t CHZ
(5)
D OUT
CE
(5)
tACS
t OH
t RC
tOE
D OUT
CE
OE
ADDRESS
tCLZ
(5)
t ACS
t CHZ
(1,5)
t OHZ (5)
tOLZ
tAA
Revision 1.1
Jan. 2004
6
JEDEC
PARAMETER
NAME
DESCRIPTION UNIT
tAVAX tWC Write Cycle Time 55 -- -- 70 -- -- ns
tE1LWH tCW Chip Select to End of Write 55 -- -- 70 -- -- ns
tAVWLtAS Address Set up Time 0 -- -- 0 -- -- ns
tAVWH tAW Address Valid to End of Write 55 -- -- 70 -- -- ns
tWLWH tWP Write Pulse Width 30 -- -- 35 -- -- ns
tWHAX tWR Write Recovery Time (CE , WE) 0 -- -- 0 -- -- ns
tWLOZ tWHZ Write to Output in High Z -- -- 25 -- -- 30 ns
tDVWH tDW Data to Write Time Overlap 25 -- -- 30 -- -- ns
tWHDX tDH Data Hold from Write Time 0 -- -- 0 -- -- ns
tGHOZ tOHZ Output Disable to Output in High Z -- -- 25 -- -- 30 ns
tWHQX tOW End ot Write to Output Active 5 -- -- 5 -- -- ns
R0201-BS62LV4006
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
WRITE CYCLE
BSI BS62LV4006
PARAMETER
NAME
CYCLE TIME : 55ns
MIN. TYP. MAX.
(Vcc = 3.0~5.5V)
MIN. TYP. MAX.
(Vcc = 2.7~5.5V)
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t WR
(3)
t CW
(11)
(2)
t WP
t AW
t OHZ
(4,10)
t AS
t DH
t DW
DIN
D OUT
WE
CE
OE
ADDRESS
(5)
t WC
CYCLE TIME : 70ns
Revision 1.1
Jan. 2004
7
R0201-BS62LV4006
BSI BS62LV4006
WRITE CYCLE2 (1,6)
t WC
tCW
(11)
(2)
t WP
t AW
t WHZ
(4,10)
t AS
t DH
t DW
DIN
D OUT
WE
CE
ADDRESS
(5)
t OW (7) (8)
(8,9)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
Revision 1.1
Jan. 2004
8
BSI BS62LV4006
R0201-BS62LV4006
ORDERING INFORMATION
PACKAGE DIMENSIONS
BASE METAL
WITH PLATING
cc1
SECTION A-A
b1
b
SOP -32
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
BS62LV4006 X X ZY Y
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
PACKAGE
S: SOP
E: TSOP 2
ST: Small TSOP
T: TSOP
P: PDIP
Revision 1.1
Jan. 2004
9
BSI BS62LV4006
R0201-BS62LV4006
TSOP - 32
TSOP2 - 32
Revision 1.1
Jan. 2004
10
BSI BS62LV4006
R0201-BS62LV4006
PACKAGE DIMENSIONS (continued)
PDIP - 32
STSOP - 32
