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S6E2DH Series
32-bit ARM® Cortex®-M4F
FM4 Microcontroller
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 002-05038 Rev.*C Revised June 28, 2017
Devices in the S6E2DH Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series
is based on the ARM Cortex-M4F Processor with on-chip Flash memory and SRAM. The series has peripheral functions such as
graphics engine, display controller, motor control timers, ADCs, and Communication Interfaces (USB, CAN, UART, CSIO, I2C, LIN).
The products that are described in this data sheet are TYPE4-M4 category products. See the FM4 Family Peripheral Manual Main
Part (002-04856).
Features
32-bit ARM Cortex-M4F Core
Processor version: r0p1
Up to 160 MHz frequency operation
Built-in FPU
Supports DSP instructions
Memory Protection Unit (MPU): improves the reliability of an
embedded system
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 128 peripheral interrupts
and 16 priority levels
24-bit system timer (Sys Tick): System timer for OS task
management
On-Chip Memories
Flash memory
This series has on-chip flash memory with these features:
384 Kbytes
Built-in Flash Accelerator System with 16 Kbytes trace
buffer memory
Security function for code protection
Notes:
• The read access to flash memory can be achieved
without wait-cycle up to operation frequency of 72 MHz.
• Even at the operation frequency more than 72 MHz, an
equivalent access to flash memory can be obtained by
Flash Accelerator System.
SRAM
This is composed of two independent SRAMs (SRAM0 and
SRAM2). SRAM0 is connected to I-code bus and D-code bus
of Cortex-M4F core. SRAM2 is connected to the system bus of
Cortex-M4F core.
SRAM0: 32 Kbytes
SRAM2: 4 Kbytes
VRAM
This series is equipped with a SRAM for GDC.
Max 512 Kbytes
VFLASH
S6E2DH5GJA is equipped with a Flash for GDC.
2 Mbytes
External Bus Interface
Supports SRAM, NOR, NAND Flash and SDRAM devices
Up to two chip selects CS0 and CS8 (CS8 is only for
SDRAM)
8-/16-bit data width
Up to 25-bit address bit
Maximum area size : Up to 256 Mbytes
Supports address/data multiplexing
Supports external RDY function
Supports the scramble function
Possible to set the validity/invalidity of the scramble
function for the external areas 0x6000_0000 to
0x7FFF_FFFF in 4 Mbytes units.
Possible to set two kinds of the scramble key.
Note: It is necessary to prepare the dedicated software
library to use the scramble function.
USB Interface (One channel)
A USB interface is composed of device and host.
USB device
USB2.0 Full-Speed supported
Max 6 EndPoint supported
• EndPoint 0 is for control transfer
• EndPoint 1, 2 can be selected for bulk-transfer,
interrupt-transfer or isochronous-transfer
• EndPoint 3 to 5 can select bulk-transfer or
interrupt-transfer
EndPoint 1 to 5 comprise the double buffer
The size of each endpoint is as follows.
• Endpoint 0, 2 to 5: 64 bytes
• EndPoint 1: 256 bytes
USB host
USB2.0 Full-Speed / Low-Speed supported
Bulk-transfer, interrupt-transfer and isochronous-transfer
support
USB device connected/disconnected automatically detect
In/out token handshake packet automatically accepted
Max 256-byte packet-length supported
Wake-up function supported
Document Number: 002-05038 Rev.*C Page 2 of 183
S6E2DH Series
CAN-FD Interface (One channel)
Compatible with CAN Specification 2.0A/B
Maximum transfer rate: 5 Mbps
Message buffer for receiver: Up to 192 messages
Message buffer for transmitter: Up to 32 messages
CAN with flexible data rate (non-ISO CAN FD)
Notes:
CAN FD cannot communicate between non-ISO CAN FD
and ISO CAN FD, because non-ISO CAN FD and ISO
CAN FD are different frame format.
About the problem of "non-ISO CAN FD", see the White
Paper from CiA(CAN in Automation).
http://www.can-newsletter.org/engineering/standardization/
141222_can-fd-and-crc-issued_white-paper_bosch
Multi-function Serial Interface (Max eight channels)
64 bytes with FIFO (the FIFO step numbers vary depending
on the settings of the communication mode or bit length.)
Operation mode is selectable from the following for each
channel.
UART
CSIO
LIN
I2C
UART
Full-duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Various error detect functions available (parity errors,
framing errors, and overrun errors)
CSIO
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detect function available
Serial chip select function (ch.6 and ch.7 only)
Supports High-speed SPI (ch.6 only)
Data length 5 to 16-bit
LIN
LIN protocol Rev.2.1 supported
Full-duplex double buffer
Master/Slave mode supported
LIN break field generation (can change to 13 to 16-bit
length)
LIN break delimiter generation (can change to 1 to 4-bit
length)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
I2C
Standard mode (Max 100 kbps) / Fast mode (Max 400
kbps) supported
Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.4=ch.A)
supported
DMA Controller (Eight channels)
The DMA controller has an independent bus for the CPU, so
the CPU and the DMA controller can process simultaneously.
8 independently configured and operated channels
Transfer can be started by software or requested from the
built-in peripherals
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Transfer data type: bytes/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
DSTC (Descriptor System Data Transfer Controller)
(128 channels)
The DSTC can transfer data at high-speed without going via
the CPU. The DSTC adopts the descriptor system and,
following the specified contents of the descriptor that has
already been constructed on the memory, can directly access
the memory/peripheral device and performs the data transfer
operation.
It supports the software activation, the hardware activation,
and the chain activation functions.
A/D Converter (Max 24 channels)
12-bit A/D Converter
Successive Approximation type
Built-in 2 units
Conversion time: 1.0 μs @ 3.3 V
Priority conversion available (priority at two levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for priority conversion: four steps)
Base Timer (Max eight channels)
Operation mode is selectable from the followings for each
channel.
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when
they are not used for external bus or peripherals. Moreover, the
port relocate function is built in. It can set to which I/O port the
peripheral function can be allocated.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in port relocate function
Up to 98 general-purpose I/O ports @ 120-pin package
Some I/O pins are 5V tolerant.
See "4. Pin Descriptions" and "5. I/O Circuit Type" for the
corresponding pins.
Document Number: 002-05038 Rev.*C Page 3 of 183
S6E2DH Series
Multi-Function Timer (One unit)
The multi-function timer is composed of the following blocks.
Minimum resolution : 6.25 ns
16-bit free-run timer × 3ch.
Input capture × 4ch.
Output compare × 6ch.
A/D activation compare × 6ch.
Waveform generator × 3ch.
16-bit PPG timer × 3ch.
The following functions can be used to achieve motor control.
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D converter activate function
DTIF (motor emergency stop) interrupt function
Real-Time Clock (RTC)
The real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
Interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
Quadrature Position/Revolution Counter (QPRC)
(One channel)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use up/down counter.
The detection edge of the three external event input pins AIN,
BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Dual Timer (32-/16-bit Down Counter)
The dual timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
Free-running
Periodic (=Reload)
One-shot
Watch Counter
The watch counter is used for wake up from the low-power
consumption mode. It is possible to select the main clock, sub
clock, built-in High-speed CR clock or built-in Low-speed CR
clock as the clock source.
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
External Interrupt Controller Unit
External interrupt input pin: Max 16 pins
Include one non-maskable interrupt (NMI)
Watchdog Timer (Two channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a hardware
watchdog and a software watchdog.
The hardware watchdog timer is clocked by low-speed internal
CR oscillator. Therefore, the hardware watchdog is active in
any power saving mode except RTC mode and stop mode.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps verify data transmission or storage
integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
PRGCRC (Programmable Cyclic Redundancy
Check) Accelerator
The CRC accelerator helps verify data transmission or storage
integrity.
CCITT CRC16, IEEE-802.3 CRC32 and a generating
polynominal are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Generating polynominal
SD Card Interface
It is possible to use the SD card that conforms to the following
standards.
Part 1 Physical Layer Specification version 3.01
Part E1 SDIO Specification version 3.00
Part A2 SD Host Controller Standard Specification version
3.00
1-bit or 4-bit data bus
Document Number: 002-05038 Rev.*C Page 4 of 183
S6E2DH Series
I2S Interface (TX x two channels, RX x two channels)
Support three transfer protocols
I2S
Left Justified
DSP mode
Master/Slave Mode selectable
RX only, TX only or TX and RX simultaneous operation
selectable
Word length is programmable from 7 bits to 32 bits
RX/TX FIFO integrated (RX: 66 words x 32 bits, TX: 66
words x 32 bits)
DMA, interrupts, or polling based data transfer supported
GDC Unit
Controller for external graphics display
Accelerator for 2D block image transfer (blit) operations
Embedded SRAM video memory
High-Speed Quad SPI (Serial Peripheral Interface for
external memory extensions)
SDRAM interface for external memory extensions
HBI (Hyper Bus Interface) interface for external memory
extensions
Maximum core system clock frequency : 160 MHz
Clock and Reset
Clocks
Five clock sources (two external oscillators, two internal CR
oscillator, and Main PLL) that are dynamically selectable.
Main clock: 4 MHz to 20 MHz
Sub Clock : 32.768 kHz
High-speed internal CR Clock: 4 MHz
Low-speed internal CR Clock: 100 kHz
Main PLL Clock
Resets
Reset requests from INITX pin
Power on reset
Software reset
Watchdog timers reset
Low voltage detector reset
Clock supervisor reset
Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to
supervise abnormality of the external clocks.
External OSC clock failure (clock stop) is detected, reset is
asserted.
External OSC frequency anomaly is detected, interrupt or
reset is asserted.
Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage has been set,
Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-Power Consumption Mode
Six low-power consumption modes are supported.
Sleep
Timer
RTC
Stop
Deep standby RTC (selectable from with/without RAM
retention)
Deep standby Stop (selectable from with/without RAM
retention)
Peripheral Clock Gating
The system can reduce the current consumption of the total
system with gating the operation clocks of peripheral functions
not used.
VBAT
The consumption power during the RTC operation can be
reduced by supplying the power supply independent from the
RTC (calendar circuit)/32 kHz oscillation circuit. The following
circuits can also be used.
RTC
32 kHz oscillation circuit
Power-on circuit
Back up register : 32 bytes
Port circuit
Debug
Serial Wire Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM) provide comprehensive
debug and trace facilities.
Unique ID
Unique value of the device (41-bit) is set.
Power Supply
Two Power Supplies
Power supply:
VCC= 2.7 V to 3.6 V (when USB or GDC unit is not used)
= 3.0 V to 3.6 V (when USB or GDC unit is used)
Power supply for VBAT:
VBAT = 1.65 V to 3.6 V
Document Number: 002-05038 Rev.*C Page 5 of 183
S6E2DH Series
Table of Contents
Features ................................................................................................................................................................................... 1
1. Product Lineup .................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment ................................................................................................................................................................. 9
4. Pin Descriptions .............................................................................................................................................................. 13
5. I/O Circuit Type ............................................................................................................................................................... 47
6. Handling Precautions ..................................................................................................................................................... 54
6.1 Precautions for Product Design ................................................................................................................................... 54
6.2 Precautions for Package Mounting .............................................................................................................................. 55
6.3 Precautions for Use Environment ................................................................................................................................ 57
7. Handling Devices ............................................................................................................................................................ 58
8. Block Diagram ................................................................................................................................................................. 61
9. Memory Size .................................................................................................................................................................... 62
10. Memory Map .................................................................................................................................................................... 62
11. Pin Status in Each CPU State ........................................................................................................................................ 64
12. Electrical Characteristics ............................................................................................................................................... 72
12.1 Absolute Maximum Ratings ......................................................................................................................................... 72
12.2 Recommended Operating Conditions ......................................................................................................................... 73
12.3 DC Characteristics ...................................................................................................................................................... 77
12.3.1 Current Rating .............................................................................................................................................................. 77
12.3.2 Pin Characteristics ....................................................................................................................................................... 87
12.4 AC Characteristics ....................................................................................................................................................... 88
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 88
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 89
12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 89
12.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL) ...................................... 90
12.4.5 Operating Conditions of USB/I2S/GDC PLL (In the Case of Using Main Clock for Input Clock of PLL) ....................... 90
12.4.6 Operating Conditions of Main PLL (In the Case of Using Built-in High-Speed CR Clock for Input Clock of Main PLL) 91
12.4.7 Reset Input Characteristics .......................................................................................................................................... 91
12.4.8 Power-on Reset Timing ................................................................................................................................................ 92
12.4.9 GPIO Output Characteristics ........................................................................................................................................ 92
12.4.10 External Bus Timing ................................................................................................................................................. 93
12.4.11 Base Timer Input Timing ......................................................................................................................................... 104
12.4.12 CSIO Timing ........................................................................................................................................................... 105
12.4.13 External Input Timing .............................................................................................................................................. 138
12.4.14 Quadrature Position/Revolution Counter Timing .................................................................................................... 139
12.4.15 I2C Timing ............................................................................................................................................................... 142
12.4.16 SD Card Interface Timing ....................................................................................................................................... 144
12.4.17 ETM Timing ............................................................................................................................................................ 146
12.4.18 JTAG Timing ........................................................................................................................................................... 147
12.4.19 I2S Timing ............................................................................................................................................................... 148
12.4.20 GDC:Panel Output Timing ...................................................................................................................................... 153
12.4.21 GDC: SDRAM-IF Timing ......................................................................................................................................... 154
12.4.22 GDC: High-Speed Quad SPI Timing ...................................................................................................................... 156
12.4.23 GDC: HyperBus I/F Timing ..................................................................................................................................... 158
12.5 12-bit A/D Converter .................................................................................................................................................. 160
Document Number: 002-05038 Rev.*C Page 6 of 183
S6E2DH Series
12.6 USB Characteristics .................................................................................................................................................. 164
12.7 Low-Voltage Detection Characteristics ...................................................................................................................... 168
12.7.1 Low-Voltage Detection Reset ..................................................................................................................................... 168
12.7.2 Interrupt of Low-Voltage Detection ............................................................................................................................. 168
12.8 MainFlash Memory Write/Erase Characteristics ........................................................................................................ 169
12.9 VFLASH Memory Write/Erase Characteristics .......................................................................................................... 169
12.10 Standby Recovery Time ............................................................................................................................................ 170
12.10.1 Recovery Cause: Interrupt/WKUP .......................................................................................................................... 170
12.10.2 Recovery Cause: Reset .......................................................................................................................................... 172
13. Ordering Information .................................................................................................................................................... 174
14. Package Dimensions .................................................................................................................................................... 175
15. Errata .............................................................................................................................................................................. 179
15.1 Part Numbers Affected .............................................................................................................................................. 179
15.2 Qualification Status ................................................................................................................................................... 179
15.3 Errata Summary ........................................................................................................................................................ 179
16. Major Changes .............................................................................................................................................................. 180
Document History ............................................................................................................................................................... 181
Sales, Solutions, and Legal Information ........................................................................................................................... 183
Document Number: 002-05038 Rev.*C Page 7 of 183
S6E2DH Series
1. Product Lineup
Memory Size
Product Name
S6E2DH5G0A
S6E2DH5J0A
S6E2DH5GJA
On-chip Flash memory
384 Kbytes
On-chip SRAM
SRAM
36 Kbytes
SRAM0
32 Kbytes
SRAM2
4 Kbytes
VRAM for GDC
512 Kbytes
VFLASH for GDC
-
2 Mbytes
Function
Product Name
S6E2DH5G0A
S6E2DH5J0A
S6E2DH5GJA
Pin count
120/161
176
120
CPU
Cortex-M4F, MPU, NVIC 128ch.
Freq.
160 MHz
Power supply voltage range
2.7 V to 3.6 V
USB2.0 (Device/Host)
1ch.
CAN-FD (non-ISO CAN FD)
1ch.
DMAC
8ch.
DSTC
128ch.
GDC
unit
Graphics・Display controller
1 unit
High-Speed Quad SPI
1ch.
(VFLASH only)
Hyper Bus Interface
1 unit
-
SDRAM-IF
-
1ch.
-
External Bus Interface
Addr:25-bit (Max), Data: 8-/16-bit, CS:2 (Max)
SRAM, NOR Flash, NAND Flash, SDRAM
Multi-function Serial Interface (UART/CSIO/LIN/I2C)
8ch. (Max)
Base Timer (PWC/Reload timer/PWM/PPG)
8ch. (Max)
MF Timer
A/D activation compare
6ch.
1 unit
Input capture
4ch.
Free-run timer
3ch.
Output compare
6ch.
Waveform generator
3ch.
PPG
3ch.
SD Card Interface
1 unit
I2S
2 units
QPRC
1ch.
Dual Timer
1 unit
Real-Time Clock
1 unit
Watch Counter
1 unit
CRC Accelerator
Yes(Fixed, Programmable)
Watchdog Timer
1ch. (SW) + 1ch. (HW)
External Interrupts
16 pins (Max)+ NMI × 1
I/O ports
98 pins (Max)
154 pins (Max)
90 pins (Max)
12-bit A/D converter
24ch. (2 units)
CSV (Clock Super Visor)
Yes
LVD (Low-Voltage Detector)
2ch.
Built-in CR
High-speed
4 MHz
Low-speed
100 kHz
Debug Function
SWJ-DP/ETM
Unique ID
Yes
Document Number: 002-05038 Rev.*C Page 8 of 183
S6E2DH Series
Notes:
− All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
− See 12.4.3 Built-in CR Oscillation Characteristics for the accuracy of the built-in CR.
2. Packages
Product Name
Package
S6E2DH5G0A
S6E2DH5J0A
S6E2DH5GJA
LQFP: LQM120 (0.5 mm pitch)
-
LQFP: LQP176 (0.5 mm pitch)
-
-
FBGA: FDJ161 (0.5 mm pitch)
-
-
Ex-LQFP(TEQFP): LEM120 (0.5 mm pitch)
: Supported
Note:
− See 14. Package Dimensions for detailed information on each package.
Document Number: 002-05038 Rev.*C Page 9 of 183
S6E2DH Series
3. Pin Assignment
LQM120 / LEM120
(TOP VIEW)
Note:
− The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
VSS
P81/UDP0
P80/UDM0
VCC
P60/SIN4_0/INT15_1/WKUP3/MALE_0
P61/UHCONX0/SOT4_0/TX2_0/RTCCO_0/SUBOUT_0/MDQM0_0
P62/SCK4_0/RX2_0/INT14_1/MDQM1_0
P63/ADTG_3/RTS4_0/PNL_PD0
P64/CTS4_0/PNL_PD1
P65/PNL_PD2
P66/SIN3_1/INT13_1/PNL_PD3
P67/SOT3_1/PNL_PD4/MSDCKE_0
P68/SCK3_1/PNL_PD5/MSDCLK_0
VSS
P0E/WKUP2/PNL_PD6/MCSX8_0
P0D/PNL_PD7/MSDWEX_0
P0C/SCK5_1/PNL_PD8/MAD11_0
P0B/SOT5_1/TIOB7_1/PNL_PD9/MAD12_0
P0A/SIN5_1/TIOA7_1/INT12_1/PNL_PD10/MAD13_0
P09/SCK2_1/PNL_PD11/MAD14_0
P08/SOT2_1/PNL_PD12/MAD15_0
P07/SIN2_1/INT11_1/PNL_PD13/MAD16_0
P06/TX2_2/PNL_PD14/MAD17_0
P05/RX2_2/INT10_1/PNL_PD15/MAD18_0
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MAD24_0
P01/TCK/SWCLK
P00/TRSTX
VCC
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
VCC 1 90 VSS
P3B/TIOA0_1/INT04_1/AIN0_1/I2SMCLK0_0/RTO00_0/MAD10_0 2 89 P97/AN23/PNL_PD16/MCASX_0
P3C/SCS70_0/TIOA1_1/INT05_1/BIN0_1/I2SDO0_0/RTO01_0/MAD09_0 3 88 P96/AN22/PNL_TSIG5/PNL_PD17/MRASX_0
P3D/SIN7_0/TIOA2_1/INT06_1/ZIN0_1/I2SWS0_0/RTO02_0/MAD08_0 4 87 P95/AN21/SCK1_1/PNL_TSIG6/PNL_PD18/MAD19_0
P3E/SOT7_0/TIOA3_1/INT07_1/I2SDI0_0/RTO03_0/MAD07_0 5 86 P94/AN20/SOT1_1/TRACED3/PNL_TSIG7/PNL_PD19/MAD20_0
P3F/SCK7_0/TIOA4_1/I2SCK0_0/RTO04_0/MAD06_0 6 85 P93/AN19/SIN1_1/TRACED2/INT09_1/PNL_TSIG8/PNL_PD20/MNREX_0/MAD21_0
P7C/TIOA5_1/RTO05_0/MWEX_0 7 84 P92/AN18/SCK0_1/TRACED1/PNL_TSIG9/PNL_PD21/MNWEX_0/MAD22_0
P7B/ADTG_2/MOEX_0/GE_HBCSX1 8 83 P91/AN17/SOT0_1/TRACED0/PNL_TSIG10/PNL_PD22/MNCLE_0/MAD23_0
P33/SIN6_0/INT00_1/S_DATA1_0 9 82 P90/AN16/SIN0_1/TRACECLK/INT08_1/PNL_TSIG11/PNL_PD23/MNALE_0/MCLKOUT_0
P34/SOT6_0/FRCK0_0/S_DATA0_0 10 81 P1F/AN15/SCK6_1/TIOB7_0/MADATA15_0
P35/SCK6_0/IC03_0/S_CLK_0 11 80 P1E/AN14/SOT6_1/TIOA7_0/RTO05_1/MADATA14_0
P36/SCS60_0/INT01_1/IC02_0/S_CMD_0 12 79 P1D/AN13/SIN6_1/TIOB6_0/INT15_0/RTO04_1/MADATA13_0
VCC 13 78 P1C/AN12/SCS60_1/TIOA6_0/INT14_0/RTO03_1/MADATA12_0
VSS 14 77 P1B/AN11/SCK5_0/TIOB5_0/ZIN0_2/RTO02_1/MADATA11_0
P37/RX2_1/INT02_1/GE_HBRESETX/IC01_0/S_DATA3_0 15 76 P1A/AN10/SOT5_0/TIOA5_0/BIN0_2/RTO01_1/MADATA10_0
P38/TX2_1/INT03_1/GE_HBINTX/IC00_0/S_DATA2_0 16 75 P19/AN09/SIN5_0/TIOB4_0/INT13_0/AIN0_2/RTO00_1/MADATA09_0
P39/ADTG_0/GE_HBRSTOX/DTTI0X_0/S_WP_0 17 74 P18/AN08/SCK3_0/TIOA4_0/IC03_1/MADATA08_0
P3A/GE_HBWPX/S_CD_0 18 73 P17/AN07/SOT3_0/TIOB3_0/IC02_1/MADATA07_0
P7A/GE_HBRWDS 19 72 P16/AN06/SIN3_0/TIOA3_0/INT12_0/IC01_1/MADATA06_0
P70/GE_SPCK/GE_HBCK 20 71 P15/AN05/SCK2_0/TIOB2_0/INT11_0/IC00_1/MADATA05_0
P71/GE_SPDQ0/GE_HBCSX0 21 70 P14/AN04/SOT2_0/TIOA2_0/DTTI0X_1/MADATA04_0
P72/INT00_0/GE_SPDQ3/GE_HBDQ0 22 69 P13/AN03/SIN2_0/TIOB1_0/INT10_0/FRCK0_1/MADATA03_0
P73/INT01_0/GE_SPCSX0/GE_HBDQ1 23 68 P12/AN02/SCK1_0/TIOA1_0/ZIN0_0/MADATA02_0
P74/INT02_0/GE_SPDQ1/GE_HBDQ2 24 67 P11/AN01/SOT1_0/TIOB0_0/BIN0_0/MADATA01_0
P75/INT03_0/GE_SPDQ2/GE_HBDQ3 25 66 P10/AN00/SIN1_0/TIOA0_0/INT09_0/AIN0_0/MADATA00_0
P76/INT04_0/GE_HBDQ4 26 65 AVRH
P77/INT05_0/GE_HBDQ5 27 64 AVRL
P78/INT06_0/GE_HBDQ6 28 63 AVSS
P79/INT07_0/GE_HBDQ7 29 62 AVCC
VCC 30 61 VCC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
VSS
P20/NMIX/WKUP0
P21/I2SMCLK1_0/MAD05_0
P22/SIN0_0/INT08_0/I2SDO1_0/CROUT_0/MAD04_0
P23/SOT0_0/TIOA6_1/I2SWS1_0/MAD03_0
P24/SCK0_0/TIOB6_1/I2SDI1_0/MAD02_0
P25/I2SCK1_0/MAD01_0
C
VSS
VCC
P26/RTCCO_1/SUBOUT_1/MAD00_0
P27/ADTG_1/CROUT_1/MRDY_0
P50/WKUP1/MCSX0_0
P51/TIOB0_1/PNL_TSIG4/PNL_PWE
P52/TIOB1_1/PNL_DCLK
P53/TIOB2_1/PNL_TSIG2/PNL_DEN
P54/TIOB3_1/PNL_TSIG3/PNL_LE
P55/TIOB4_1/PNL_TSIG0/PNL_LH_SYNC
P56/TIOB5_1/PNL_TSIG1/PNL_FV_SYNC
INITX
P46/X0A
P47/X1A
VBATVCC
P48/VREGCTL
P49/VWAKEUP
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
120pin Package
Document Number: 002-05038 Rev.*C Page 10 of 183
S6E2DH Series
LQM120 (S6E2DH5GJA)
(TOP VIEW)
*1: The DNU0 / 1 (23 pin / 24 pin), please pull up and short-circuit on the board.
For more information, please refer to the 7.Handling Devices.
(N.C.): Do not connect anything.
Note:
− The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
VSS
P81/UDP0
P80/UDM0
VCC
P60/SIN4_0/INT15_1/WKUP3/MALE_0
P61/UHCONX0/SOT4_0/TX2_0/RTCCO_0/SUBOUT_0/MDQM0_0
P62/SCK4_0/RX2_0/INT14_1/MDQM1_0
P63/ADTG_3/RTS4_0/PNL_PD0
P64/CTS4_0/PNL_PD1
P65/PNL_PD2
P66/SIN3_1/INT13_1/PNL_PD3
P67/SOT3_1/PNL_PD4/MSDCKE_0
P68/SCK3_1/PNL_PD5/MSDCLK_0
VSS
P0E/WKUP2/PNL_PD6/MCSX8_0
P0D/PNL_PD7/MSDWEX_0
P0C/SCK5_1/PNL_PD8/MAD11_0
P0B/SOT5_1/TIOB7_1/PNL_PD9/MAD12_0
P0A/SIN5_1/TIOA7_1/INT12_1/PNL_PD10/MAD13_0
P09/SCK2_1/PNL_PD11/MAD14_0
P08/SOT2_1/PNL_PD12/MAD15_0
P07/SIN2_1/INT11_1/PNL_PD13/MAD16_0
P06/TX2_2/PNL_PD14/MAD17_0
P05/RX2_2/INT10_1/PNL_PD15/MAD18_0
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MAD24_0
P01/TCK/SWCLK
P00/TRSTX
VCC
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
VCC 1 90 VSS
P3B/TIOA0_1/INT04_1/AIN0_1/I2SMCLK0_0/RTO00_0/MAD10_0 2 89 P97/AN23/PNL_PD16/MCASX_0
P3C/SCS70_0/TIOA1_1/INT05_1/BIN0_1/I2SDO0_0/RTO01_0/MAD09_0 3 88 P96/AN22/PNL_TSIG5/PNL_PD17/MRASX_0
P3D/SIN7_0/TIOA2_1/INT06_1/ZIN0_1/I2SWS0_0/RTO02_0/MAD08_0 4 87 P95/AN21/SCK1_1/PNL_TSIG6/PNL_PD18/MAD19_0
P3E/SOT7_0/TIOA3_1/INT07_1/I2SDI0_0/RTO03_0/MAD07_0 5 86 P94/AN20/SOT1_1/TRACED3/PNL_TSIG7/PNL_PD19/MAD20_0
P3F/SCK7_0/TIOA4_1/I2SCK0_0/RTO04_0/MAD06_0 6 85 P93/AN19/SIN1_1/TRACED2/INT09_1/PNL_TSIG8/PNL_PD20/MNREX_0/MAD21_0
P7C/TIOA5_1/RTO05_0/MWEX_0 7 84 P92/AN18/SCK0_1/TRACED1/PNL_TSIG9/PNL_PD21/MNWEX_0/MAD22_0
P7B/ADTG_2/MOEX_0 8 83 P91/AN17/SOT0_1/TRACED0/PNL_TSIG10/PNL_PD22/MNCLE_0/MAD23_0
P33/SIN6_0/INT00_1/S_DATA1_0 9 82 P90/AN16/SIN0_1/TRACECLK/INT08_1/PNL_TSIG11/PNL_PD23/MNALE_0/MCLKOUT_0
P34/SOT6_0/FRCK0_0/S_DATA0_0 10 81 P1F/AN15/SCK6_1/TIOB7_0/MADATA15_0
P35/SCK6_0/IC03_0/S_CLK_0 11 80 P1E/AN14/SOT6_1/TIOA7_0/RTO05_1/MADATA14_0
P36/SCS60_0/INT01_1/IC02_0/S_CMD_0 12 79 P1D/AN13/SIN6_1/TIOB6_0/INT15_0/RTO04_1/MADATA13_0
VCC 13 78 P1C/AN12/SCS60_1/TIOA6_0/INT14_0/RTO03_1/MADATA12_0
VSS 14 77 P1B/AN11/SCK5_0/TIOB5_0/ZIN0_2/RTO02_1/MADATA11_0
P37/RX2_1/INT02_1/IC01_0/S_DATA3_0 15 76 P1A/AN10/SOT5_0/TIOA5_0/BIN0_2/RTO01_1/MADATA10_0
P38/TX2_1/INT03_1/IC00_0/S_DATA2_0 16 75 P19/AN09/SIN5_0/TIOB4_0/INT13_0/AIN0_2/RTO00_1/MADATA09_0
P39/ADTG_0/DTTI0X_0/S_WP_0 17 74 P18/AN08/SCK3_0/TIOA4_0/IC03_1/MADATA08_0
P3A/S_CD_0 18 73 P17/AN07/SOT3_0/TIOB3_0/IC02_1/MADATA07_0
(N.C.) 19 72 P16/AN06/SIN3_0/TIOA3_0/INT12_0/IC01_1/MADATA06_0
(N.C.) 20 71 P15/AN05/SCK2_0/TIOB2_0/INT11_0/IC00_1/MADATA05_0
(N.C.) 21 70 P14/AN04/SOT2_0/TIOA2_0/DTTI0X_1/MADATA04_0
VCC 22 69 P13/AN03/SIN2_0/TIOB1_0/INT10_0/FRCK0_1/MADATA03_0
(DNU0)*1 23 68 P12/AN02/SCK1_0/TIOA1_0/ZIN0_0/MADATA02_0
(DNU1)*1 24 67 P11/AN01/SOT1_0/TIOB0_0/BIN0_0/MADATA01_0
(N.C.) 25 66 P10/AN00/SIN1_0/TIOA0_0/INT09_0/AIN0_0/MADATA00_0
(N.C.) 26 65 AVRH
P77/INT05_0 27 64 AVRL
P78/INT06_0 28 63 AVSS
P79/INT07_0 29 62 AVCC
VCC 30 61 VCC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
VSS
P20/NMIX/WKUP0
P21/I2SMCLK1_0/MAD05_0
P22/SIN0_0/INT08_0/I2SDO1_0/CROUT_0/MAD04_0
P23/SOT0_0/TIOA6_1/I2SWS1_0/MAD03_0
P24/SCK0_0/TIOB6_1/I2SDI1_0/MAD02_0
P25/I2SCK1_0/MAD01_0
C
VSS
VCC
P26/RTCCO_1/SUBOUT_1/MAD00_0
P27/ADTG_1/CROUT_1/MRDY_0
P50/WKUP1/MCSX0_0
P51/TIOB0_1/PNL_TSIG4/PNL_PWE
P52/TIOB1_1/PNL_DCLK
P53/TIOB2_1/PNL_TSIG2/PNL_DEN
P54/TIOB3_1/PNL_TSIG3/PNL_LE
P55/TIOB4_1/PNL_TSIG0/PNL_LH_SYNC
P56/TIOB5_1/PNL_TSIG1/PNL_FV_SYNC
INITX
P46/X0A
P47/X1A
VBATVCC
P48/VREGCTL
P49/VWAKEUP
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
120pin Package
Document Number: 002-05038 Rev.*C Page 11 of 183
S6E2DH Series
LQP176
(TOP VIEW)
Note:
− The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
VSS
P81/UDP0
P80/UDM0
VCC
P60/SIN4_0/INT15_1/WKUP3/MALE_0
P61/UHCONX0/SOT4_0/TX2_0/RTCCO_0/SUBOUT_0/MDQM0_0
P62/SCK4_0/RX2_0/INT14_1/MDQM1_0
PDD/GE_SDCSX
PDC/GE_SDCASX
PDB/GE_SDRASX
PDA/GE_SDWEX
P63/ADTG_3/RTS4_0/PNL_PD0
P64/CTS4_0/PNL_PD1
P65/PNL_PD2
P66/SIN3_1/INT13_1/PNL_PD3
P67/SOT3_1/PNL_PD4/MSDCKE_0
P68/SCK3_1/PNL_PD5/MSDCLK_0
VSS
P0E/WKUP2/PNL_PD6/MCSX8_0
P0D/PNL_PD7/MSDWEX_0
P0C/SCK5_1/PNL_PD8/MAD11_0
P0B/SOT5_1/TIOB7_1/PNL_PD9/MAD12_0
P0A/SIN5_1/TIOA7_1/INT12_1/PNL_PD10/MAD13_0
P09/SCK2_1/PNL_PD11/MAD14_0
P08/SOT2_1/PNL_PD12/MAD15_0
P07/SIN2_1/INT11_1/PNL_PD13/MAD16_0
P06/TX2_2/PNL_PD14/MAD17_0
P05/RX2_2/INT10_1/PNL_PD15/MAD18_0
PD9/GE_SDDQM0
PD8/GE_SDDQM1
PD7/GE_SDDQM2
PD6/GE_SDDQM3
PD5/GE_SDA0
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MAD24_0
P01/TCK/SWCLK
P00/TRSTX
PD4/GE_SDA1
PD3/GE_SDA2
PD2/GE_SDA3
PD1/GE_SDA4
PD0/GE_SDA5
VCC
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
VCC 1 132 VSS
PA0/GE_SDCKE 2 131 P97/AN23/PNL_PD16/MCASX_0
PA1/GE_SDCLK 3 130 P96/AN22/PNL_TSIG5/PNL_PD17/MRASX_0
PA2/GE_SDDQ31 4 129 PCD/GE_SDA6
PA3/GE_SDDQ30 5 128 PCC/GE_SDA7
P3B/TIOA0_1/INT04_1/AIN0_1/I2SMCLK0_0/RTO00_0/MAD10_0 6 127 PCB/GE_SDA8
P3C/SCS70_0/TIOA1_1/INT05_1/BIN0_1/I2SDO0_0/RTO01_0/MAD09_0 7 126 PCA/GE_SDA9
P3D/SIN7_0/TIOA2_1/INT06_1/ZIN0_1/I2SWS0_0/RTO02_0/MAD08_0 8 125 P95/AN21/SCK1_1/PNL_TSIG6/PNL_PD18/MAD19_0
P3E/SOT7_0/TIOA3_1/INT07_1/I2SDI0_0/RTO03_0/MAD07_0 9 124 P94/AN20/SOT1_1/TRACED3/PNL_TSIG7/PNL_PD19/MAD20_0
P3F/SCK7_0/TIOA4_1/I2SCK0_0/RTO04_0/MAD06_0 10 123 P93/AN19/SIN1_1/TRACED2/INT09_1/PNL_TSIG8/PNL_PD20/MNREX_0/MAD21_0
P7C/TIOA5_1/RTO05_0/MWEX_0 11 122 P92/AN18/SCK0_1/TRACED1/PNL_TSIG9/PNL_PD21/MNWEX_0/MAD22_0
P7B/ADTG_2/MOEX_0/GE_HBCSX1 12 121 P91/AN17/SOT0_1/TRACED0/PNL_TSIG10/PNL_PD22/MNCLE_0/MAD23_0
PA8/GE_SDDQ29 13 120 P90/AN16/SIN0_1/TRACECLK/INT08_1/PNL_TSIG11/PNL_PD23/MNALE_0/MCLKOUT_0
PA9/GE_SDDQ28 14 119 P1F/AN15/SCK6_1/TIOB7_0/MADATA15_0
PAA/GE_SDDQ27 15 118 P1E/AN14/SOT6_1/TIOA7_0/RTO05_1/MADATA14_0
PAB/GE_SDDQ26 16 117 P1D/AN13/SIN6_1/TIOB6_0/INT15_0/RTO04_1/MADATA13_0
PAC/GE_SDDQ25 17 116 P1C/AN12/SCS60_1/TIOA6_0/INT14_0/RTO03_1/MADATA12_0
PAD/GE_SDDQ24 18 115 PC9/GE_SDA10
P33/SIN6_0/INT00_1/S_DATA1_0 19 114 PC8/GE_SDA11
P34/SOT6_0/FRCK0_0/S_DATA0_0 20 113 PC7/GE_SDBA0
P35/SCK6_0/IC03_0/S_CLK_0 21 112 PC6/GE_SDBA1
P36/SCS60_0/INT01_1/IC02_0/S_CMD_0 22 111 P1B/AN11/SCK5_0/TIOB5_0/ZIN0_2/RTO02_1/MADATA11_0
VCC 23 110 P1A/AN10/SOT5_0/TIOA5_0/BIN0_2/RTO01_1/MADATA10_0
VSS 24 109 P19/AN09/SIN5_0/TIOB4_0/INT13_0/AIN0_2/RTO00_1/MADATA09_0
P37/RX2_1/INT02_1/GE_HBRESETX/IC01_0/S_DATA3_0 25 108 P18/AN08/SCK3_0/TIOA4_0/IC03_1/MADATA08_0
P38/TX2_1/INT03_1/GE_HBINTX/IC00_0/S_DATA2_0 26 107 P17/AN07/SOT3_0/TIOB3_0/IC02_1/MADATA07_0
P39/ADTG_0/GE_HBRSTOX/DTTI0X_0/S_WP_0 27 106 P16/AN06/SIN3_0/TIOA3_0/INT12_0/IC01_1/MADATA06_0
P3A/GE_HBWPX/S_CD_0 28 105 P15/AN05/SCK2_0/TIOB2_0/INT11_0/IC00_1/MADATA05_0
PA4/GE_SDDQ23 29 104 P14/AN04/SOT2_0/TIOA2_0/DTTI0X_1/MADATA04_0
PA5/GE_SDDQ22 30 103 P13/AN03/SIN2_0/TIOB1_0/INT10_0/FRCK0_1/MADATA03_0
PA6/GE_SDDQ21 31 102 P12/AN02/SCK1_0/TIOA1_0/ZIN0_0/MADATA02_0
PA7/GE_SDDQ20 32 101 P11/AN01/SOT1_0/TIOB0_0/BIN0_0/MADATA01_0
P7A/GE_HBRWDS 33 100 P10/AN00/SIN1_0/TIOA0_0/INT09_0/AIN0_0/MADATA00_0
P70/GE_SPCK/GE_HBCK 34 99 PC5/GE_SDDQ0
P71/GE_SPDQ0/GE_HBCSX0 35 98 PC4/GE_SDDQ1
P72/INT00_0/GE_SPDQ3/GE_HBDQ0 36 97 PC3/GE_SDDQ2
P73/INT01_0/GE_SPCSX0/GE_HBDQ1 37 96 PC2/GE_SDDQ3
P74/INT02_0/GE_SPDQ1/GE_HBDQ2 38 95 PC1/GE_SDDQ4
P75/INT03_0/GE_SPDQ2/GE_HBDQ3 39 94 PC0/GE_SDDQ5
P76/INT04_0/GE_HBDQ4 40 93 AVRH
P77/INT05_0/GE_HBDQ5 41 92 AVRL
P78/INT06_0/GE_HBDQ6 42 91 AVSS
P79/INT07_0/GE_HBDQ7 43 90 AVCC
VCC 44 89 VCC
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VSS
P20/NMIX/WKUP0
PB0/GE_SDDQ19
PB1/GE_SDDQ18
PB2/GE_SDDQ17
PB3/GE_SDDQ16
P21/I2SMCLK1_0/MAD05_0
P22/SIN0_0/INT08_0/I2SDO1_0/CROUT_0/MAD04_0
P23/SOT0_0/TIOA6_1/I2SWS1_0/MAD03_0
P24/SCK0_0/TIOB6_1/I2SDI1_0/MAD02_0
P25/I2SCK1_0/MAD01_0
PB4/GE_SDDQ15
PB5/GE_SDDQ14
PB6/GE_SDDQ13
PB7/GE_SDDQ12
C
VSS
VCC
P26/RTCCO_1/SUBOUT_1/MAD00_0
P27/ADTG_1/CROUT_1/MRDY_0
P50/WKUP1/MCSX0_0
P51/TIOB0_1/PNL_TSIG4/PNL_PWE
P52/TIOB1_1/PNL_DCLK
P53/TIOB2_1/PNL_TSIG2/PNL_DEN
P54/TIOB3_1/PNL_TSIG3/PNL_LE
P55/TIOB4_1/PNL_TSIG0/PNL_LH_SYNC
P56/TIOB5_1/PNL_TSIG1/PNL_FV_SYNC
PB8/GE_SDDQ11
PB9/GE_SDDQ10
PBA/GE_SDDQ9
PBB/GE_SDDQ8
PBC/GE_SDDQ7
PBD/GE_SDDQ6
INITX
P46/X0A
P47/X1A
VBATVCC
P48/VREGCTL
P49/VWAKEUP
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
176pin Package
Document Number: 002-05038 Rev.*C Page 12 of 183
S6E2DH Series
FDJ161
(TOP VIEW)
Note:
− The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
1 2 3 4 5 6 7 8 9 10 11 12 13
AVSS UDP0 UDM0
VCC VSS P66 VSS P0C P09 VSS TCK VCC VSS
BVSS P60 P61 P62 P64 P67 P0E P0B P08 TDO TMS TRSTX VSS
CVCC P3C P3B P63 P65 P68 P0D P0A P07 P05 TDI P96 P97
DP3F P3E P3D P7C VSS VSS VSS VSS P06 P92 P93 P94 P95
EP35 P34 P33 P7B VSS VSS VSS VSS VSS P1E P1F P90 P91
FP39 P38 P37 P36 VSS VSS VSS P1A P1B P1C P1D
GVCC P7A P3A VSS VSS VSS P16 P17 P18 P19
HVSS P72 P73 VSS VSS VSS P12 P13 P14 P15
JP70 P74 P75 VSS VSS VSS VSS VSS VSS VSS P11 AVRH AVRL
KP71 P76 P77 VSS P24 VSS P50 P52 P54 VSS P10 AVSS AVCC
LVCC P78 P79 P22 P25 VSS P51 P53 P55 P56 P48 P49 VCC
MVSS P20 P21 P23 P26 VSS VSS INITX VBAT VSS MD0 MD1 VSS
NVSS CVSS VCC P27 VSS X0A VSS X1A VSS X0 X1 VSS
Document Number: 002-05038 Rev.*C Page 13 of 183
S6E2DH Series
4. Pin Descriptions
List of Pin Functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No.
Pin name
I/O
circuit
type
Pin
state
type
LQFP176
LQFP120
LQFP120
FBGA161
Ex-LQFP120
(S6E2DH5GJA)
1
1
1
C1
VCC
－
－
2
－
－
－
PA0
K
I
GE_SDCKE
3
－
－
－
PA1
K
I
GE_SDCLK
4
－
－
－
PA2
L
I
GE_SDDQ31
5
－
－
－
PA3
L
I
GE_SDDQ30
6
2
2
C3
P3B
G
K
TIOA0_1
INT04_1
AIN0_1
I2SMCLK0_0
RTO00_0
(PPG00_0)
MAD10_0
7
3
3
C2
P3C
G
K
SCS70_0
TIOA1_1
INT05_1
BIN0_1
I2SDO0_0
RTO01_0
(PPG00_0)
MAD09_0
8
4
4
D3
P3D
G
K
SIN7_0
TIOA2_1
INT06_1
ZIN0_1
I2SWS0_0
RTO02_0
(PPG02_0)
MAD08_0
Document Number: 002-05038 Rev.*C Page 14 of 183
S6E2DH Series
Pin No.
Pin name
I/O
circuit
type
Pin
state
type
LQFP176
LQFP120
LQFP120
FBGA161
Ex-LQFP120
(S6E2DH5GJA)
9
5
5
D2
P3E
G
K
SOT7_0
(SDA7_0)
TIOA3_1
INT07_1
I2SDI0_0
RTO03_0
(PPG02_0)
MAD07_0
10
6
6
D1
P3F
G
I
SCK7_0
(SCL7_0)
TIOA4_1
I2SCK0_0
RTO04_0
(PPG04_0)
MAD06_0
11
7
7
D4
P7C
G
I
TIOA5_1
RTO05_0
(PPG04_0)
MWEX_0
12
8
－
E4
P7B
K
I
ADTG_2
GE_HBCSX1
MOEX_0
－
－
8
－
P7B
K
I
ADTG_2
MOEX_0
13
－
－
－
PA8
L
I
GE_SDDQ29
14
－
－
－
PA9
L
I
GE_SDDQ28
15
－
－
－
PAA
L
I
GE_SDDQ27
16
－
－
－
PAB
L
I
GE_SDDQ26
17
－
－
－
PAC
L
I
GE_SDDQ25
18
－
－
－
PAD
L
I
GE_SDDQ24
Document Number: 002-05038 Rev.*C Page 15 of 183
S6E2DH Series
Pin No.
Pin name
I/O
circuit
type
Pin
state
type
LQFP176
LQFP120
LQFP120
FBGA161
Ex-LQFP120
(S6E2DH5GJA)
19
9
9
E3
P33
D
K
SIN6_0
INT00_1
S_DATA1_0
20
10
10
E2
P34
D
I
SOT6_0
(SDA6_0)
FRCK0_0
S_DATA0_0
21
11
11
E1
P35
D
I
SCK6_0
(SCL6_0)
IC03_0
S_CLK_0
22
12
12
F4
P36
D
K
SCS60_0
INT01_1
IC02_0
S_CMD_0
23
13
13
G1
VCC
－
－
24
14
14
H1
VSS
－
－
25
15
－
F3
P37
D
K
RX2_1
GE_HBRESETX
INT02_1
IC01_0
S_DATA3_0
－
－
15
－
P37
D
K
RX2_1
INT02_1
IC01_0
S_DATA3_0
26
16
－
F2
P38
D
K
TX2_1
GE_HBINTX
INT03_1
IC00_0
S_DATA2_0
－
－
16
－
P38
D
K
TX2_1
INT03_1
IC00_0
S_DATA2_0
Document Number: 002-05038 Rev.*C Page 16 of 183
S6E2DH Series
Pin No.
Pin name
I/O
circuit
type
Pin
state
type
LQFP176
LQFP120
LQFP120
FBGA161
Ex-LQFP120
(S6E2DH5GJA)
27
17
－
F1
P39
E
I
ADTG_0
GE_HBRSTOX
DTTI0X_0
S_WP_0
－
－
17
－
P39
E
I
ADTG_0
DTTI0X_0
S_WP_0
28
18
－
G3
P3A
E
I
GE_HBWPX
S_CD_0
－
－
18
－
P3A
E
I
S_CD_0
29
－
－
－
PA4
L
I
GE_SDDQ23
30
－
－
－
PA5
L
I
GE_SDDQ22
31
－
－
－
PA6
L
I
GE_SDDQ21
32
－
－
－
PA7
L
I
GE_SDDQ20
33
19
－
G2
P7A
K
I
GE_HBRWDS
－
－
19
－
（N.C.)
－
－
34
20
－
J1
P70
K
I
GE_SPCK
GE_HBCK
－
－
20
－
（N.C.)
－
－
35
21
－
K1
P71
K
I
GE_SPDQ0
GE_HBCSX0
－
－
21
－
（N.C.)
－
－
36
22
－
H2
P72
K
K
GE_SPDQ3
GE_HBDQ0
INT00_0
－
－
22
－
VCC
－
－
37
23
－
H3
P73
K
K
GE_SPCSX0
GE_HBDQ1
INT01_0
－
－
23
－
(DNU0)
－
－
Document Number: 002-05038 Rev.*C Page 17 of 183
S6E2DH Series
Pin No.
Pin name
I/O
circuit
type
Pin
state
type
LQFP176
LQFP120
LQFP120
FBGA161
Ex-LQFP120
(S6E2DH5GJA)
38
24
－
J2
P74
K
K
GE_SPDQ1
GE_HBDQ2
INT02_0
－
－
24
－
(DNU1)
－
－
39
25
－
J3
P75
K
K
GE_SPDQ2
GE_HBDQ3
INT03_0
－
－
25
－
（N.C.)
－
－
40
26
－
K2
P76
K
K
GE_HBDQ4
INT04_0
－
－
26
－
（N.C.)
－
－
41
27
－
K3
P77
K
K
GE_HBDQ5
INT05_0
－
－
27
－
P77
K
K
INT05_0
42
28
－
L2
P78
K
K
GE_HBDQ6
INT06_0
－
－
28
－
P78
K
K
INT06_0
43
29
－
L3
P79
K
K
GE_HBDQ7
INT07_0
－
－
29
－
P79
K
K
INT07_0
44
30
30
L1
VCC
－
－
45
31
31
M1
VSS
－
－
46
32
32
M2
P20
I
F
NMIX
WKUP0
47
－
－
－
PB0
L
I
GE_SDDQ19
48
－
－
－
PB1
L
I
GE_SDDQ18
49
－
－
－
PB2
L
I
GE_SDDQ17
50
－
－
－
PB3
L
I
GE_SDDQ16
Document Number: 002-05038 Rev.*C Page 18 of 183
S6E2DH Series
Pin No.
Pin name
I/O
circuit
type
Pin
state
type
LQFP176
LQFP120
LQFP120
FBGA161
Ex-LQFP120
(S6E2DH5GJA)
51
33
33
M3
P21
E
I
I2SMCLK1_0
MAD05_0
52
34
34
L4
P22
E
K
CROUT_0
SIN0_0
INT08_0
I2SDO1_0
MAD04_0
53
35
35
M4
P23
E
I
SOT0_0
(SDA0_0)
TIOA6_1
I2SWS1_0
MAD03_0
54
36
36
K5
P24
E
I
SCK0_0
(SCL0_0)
TIOB6_1
I2SDI1_0
MAD02_0
55
37
37
L5
P25
E
I
I2SCK1_0
MAD01_0
56
－
－
－
PB4
L
I
GE_SDDQ15
57
－
－
－
PB5
L
I
GE_SDDQ14
58
－
－
－
PB6
L
I
GE_SDDQ13
59
－
－
－
PB7
L
I
GE_SDDQ12
60
38
38
N2
C
－
－
61
39
39
N3
VSS
－
－
62
40
40
N4
VCC
－
－
63
41
41
M5
P26
E
I
RTCCO_1
SUBOUT_1
MAD00_0
64
42
42
N5
P27
E
I
ADTG_1
CROUT_1
MRDY_0
Document Number: 002-05038 Rev.*C Page 19 of 183
S6E2DH Series
Pin No.
Pin name
I/O
circuit
type
Pin
state
type
LQFP176
LQFP120
LQFP120
FBGA161
Ex-LQFP120
(S6E2DH5GJA)
65
43
43
K7
P50
D
P
WKUP1
MCSX0_0
66
44
44
L7
P51
E
I
TIOB0_1
PNL_PWE
PNL_TSIG4
67
45
45
K8
P52
D
I
TIOB1_1
PNL_DCLK
68
46
46
L8
P53
E
I
TIOB2_1
PNL_DEN
PNL_TSIG2
69
47
47
K9
P54
E
I
TIOB3_1
PNL_LE
PNL_TSIG3
70
48
48
L9
P55
E
I
TIOB4_1
PNL_LH_SYNC
PNL_TSIG0
71
49
49
L10
P56
E
I
TIOB5_1
PNL_FV_SYNC
PNL_TSIG1
72
－
－
－
PB8
L
I
GE_SDDQ11
73
－
－
－
PB9
L
I
GE_SDDQ10
74
－
－
－
PBA
L
I
GE_SDDQ9
75
－
－
－
PBB
L
I
GE_SDDQ8
76
－
－
－
PBC
L
I
GE_SDDQ7
77
－
－
－
PBD
L
I
GE_SDDQ6
78
50
50
M8
INITX
B
C
79
51
51
N7
P46
P
S
X0A
80
52
52
N9
P47
Q
T
X1A
Document Number: 002-05038 Rev.*C Page 20 of 183
S6E2DH Series
Pin No.
Pin name
I/O
circuit
type
Pin
state
type
LQFP176
LQFP120
LQFP120
FBGA161
Ex-LQFP120
(S6E2DH5GJA)
81
53
53
M9
VBAT
－
－
82
54
54
L11
P48
O
U
VREGCTL
83
55
55
L12
P49
O
U
VWAKEUP
84
56
56
M12
PE0
C
E
MD1
85
57
57
M11
MD0
J
D
86
58
58
N11
PE2
A
A
X0
87
59
59
N12
PE3
A
B
X1
88
60
60
M13
VSS
－
－
89
61
61
L13
VCC
－
－
90
62
62
K13
AVCC
－
－
91
63
63
K12
AVSS
－
－
92
64
64
J13
AVRL
－
－
93
65
65
J12
AVRH
－
－
94
－
－
－
PC0
L
I
GE_SDDQ5
95
－
－
－
PC1
L
I
GE_SDDQ4
96
－
－
－
PC2
L
I
GE_SDDQ3
97
－
－
－
PC3
L
I
GE_SDDQ2
98
－
－
－
PC4
L
I
GE_SDDQ1
99
－
－
－
PC5
L
I
GE_SDDQ0
100
66
66
K11
P10
F
M
AN00
SIN1_0
TIOA0_0
INT09_0
AIN0_0
MADATA00_0
Document Number: 002-05038 Rev.*C Page 21 of 183
S6E2DH Series
Pin No.
Pin name
I/O
circuit
type
Pin
state
type
LQFP176
LQFP120
LQFP120
FBGA161
Ex-LQFP120
(S6E2DH5GJA)
101
67
67
J11
P11
F
L
AN01
SOT1_0
(SDA1_0)
TIOB0_0
BIN0_0
MADATA01_0
102
68
68
H10
P12
F
L
AN02
SCK1_0
(SCL1_0)
TIOA1_0
ZIN0_0
MADATA02_0
103
69
69
H11
P13
F
M
AN03
SIN2_0
TIOB1_0
INT10_0
FRCK0_1
MADATA03_0
104
70
70
H12
P14
F
L
AN04
SOT2_0
(SDA2_0)
TIOA2_0
DTTI0X_1
MADATA04_0
105
71
71
H13
P15
F
M
AN05
SCK2_0
(SCL2_0)
TIOB2_0
INT11_0
IC00_1
MADATA05_0
106
72
72
G10
P16
F
M
AN06
SIN3_0
TIOA3_0
INT12_0
IC01_1
MADATA06_0
Document Number: 002-05038 Rev.*C Page 22 of 183
S6E2DH Series
Pin No.
Pin name
I/O
circuit
type
Pin
state
type
LQFP176
LQFP120
LQFP120
FBGA161
Ex-LQFP120
(S6E2DH5GJA)
107
73
73
G11
P17
F
L
AN07
SOT3_0
(SDA3_0)
TIOB3_0
IC02_1
MADATA07_0
108
74
74
G12
P18
F
L
AN08
SCK3_0
(SCL3_0)
TIOA4_0
IC03_1
MADATA08_0
109
75
75
G13
P19
F
M
AN09
SIN5_0
TIOB4_0
INT13_0
AIN0_2
RTO00_1
(PPG00_1)
MADATA09_0
110
76
76
F10
P1A
F
L
AN10
SOT5_0
(SDA5_0)
TIOA5_0
BIN0_2
RTO01_1
(PPG00_1)
MADATA10_0
111
77
77
F11
P1B
F
L
AN11
SCK5_0
(SCL5_0)
TIOB5_0
ZIN0_2
RTO02_1
(PPG02_1)
MADATA11_0
112
－
－
－
PC6
K
I
GE_SDBA1
Document Number: 002-05038 Rev.*C Page 23 of 183
S6E2DH Series
Pin No.
Pin name
I/O
circuit
type
Pin
state
type
LQFP176
LQFP120
LQFP120
FBGA161
Ex-LQFP120
(S6E2DH5GJA)
113
－
－
－
PC7
K
I
GE_SDBA0
114
－
－
－
PC8
K
I
GE_SDA11
115
－
－
－
PC9
K
I
GE_SDA10
116
78
78
F12
P1C
F
M
AN12
SCS60_1
TIOA6_0
INT14_0
RTO03_1
(PPG02_1)
MADATA12_0
117
79
79
F13
P1D
F
M
AN13
SIN6_1
TIOB6_0
INT15_0
RTO04_1
(PPG04_1)
MADATA13_0
118
80
80
E10
P1E
F
L
AN14
SOT6_1
(SDA6_1)
TIOA7_0
RTO05_1
(PPG04_1)
MADATA14_0
119
81
81
E11
P1F
F
L
AN15
SCK6_1
(SCL6_1)
TIOB7_0
MADATA15_0
Document Number: 002-05038 Rev.*C Page 24 of 183
S6E2DH Series
Pin No.
Pin name
I/O
circuit
type
Pin
state
type
LQFP176
LQFP120
LQFP120
FBGA161
Ex-LQFP120
(S6E2DH5GJA)
120
82
82
E12
P90
F
O
AN16
SIN0_1
INT08_1
PNL_PD23
PNL_TSIG11
MCLKOUT_0
MNALE_0
TRACECLK
121
83
83
E13
P91
F
N
AN17
SOT0_1
(SDA0_1)
PNL_PD22
PNL_TSIG10
MAD23_0
MNCLE_0
TRACED0
122
84
84
D10
P92
F
N
AN18
SCK0_1
(SCL0_1)
PNL_PD21
PNL_TSIG9
MAD22_0
MNWEX_0
TRACED1
123
85
85
D11
P93
F
O
AN19
SIN1_1
INT09_1
PNL_PD20
PNL_TSIG8
MAD21_0
MNREX_0
TRACED2
124
86
86
D12
P94
F
N
AN20
SOT1_1
(SDA1_1)
PNL_PD19
PNL_TSIG7
MAD20_0
TRACED3
Document Number: 002-05038 Rev.*C Page 25 of 183
S6E2DH Series
Pin No.
Pin name
I/O
circuit
type
Pin
state
type
LQFP176
LQFP120
LQFP120
FBGA161
Ex-LQFP120
(S6E2DH5GJA)
125
87
87
D13
P95
F
L
AN21
SCK1_1
(SCL1_1)
PNL_PD18
PNL_TSIG6
MAD19_0
126
－
－
－
PCA
K
I
GE_SDA9
127
－
－
－
PCB
K
I
GE_SDA8
128
－
－
－
PCC
K
I
GE_SDA7
129
－
－
－
PCD
K
I
GE_SDA6
130
88
88
C12
P96
F
L
AN22
PNL_PD17
PNL_TSIG5
MRASX_0
131
89
89
C13
P97
F
L
AN23
PNL_PD16
MCASX_0
132
90
90
B13
VSS
－
－
133
91
91
A12
VCC
－
－
134
－
－
－
PD0
K
I
GE_SDA5
135
－
－
－
PD1
K
I
GE_SDA4
136
－
－
－
PD2
K
I
GE_SDA3
137
－
－
－
PD3
K
I
GE_SDA2
138
－
－
－
PD4
K
I
GE_SDA1
139
92
92
B12
P00
E
G
TRSTX
140
93
93
A11
P01
E
G
TCK
SWCLK
Document Number: 002-05038 Rev.*C Page 26 of 183
S6E2DH Series
Pin No.
Pin name
I/O
circuit
type
Pin
state
type
LQFP176
LQFP120
LQFP120
FBGA161
Ex-LQFP120
(S6E2DH5GJA)
141
94
94
C11
P02
E
H
TDI
MAD24_0
142
95
95
B11
P03
E
G
TMS
SWDIO
143
96
96
B10
P04
E
G
TDO
SWO
144
－
－
－
PD5
K
I
GE_SDA0
145
－
－
－
PD6
K
I
GE_SDDQM3
146
－
－
－
PD7
K
I
GE_SDDQM2
147
－
－
－
PD8
K
I
GE_SDDQM1
148
－
－
－
PD9
K
I
GE_SDDQM0
149
97
97
C10
P05
E
K
RX2_2
INT10_1
PNL_PD15
MAD18_0
150
98
98
D9
P06
E
I
TX2_2
PNL_PD14
MAD17_0
151
99
99
C9
P07
E
K
SIN2_1
INT11_1
PNL_PD13
MAD16_0
152
100
100
B9
P08
E
I
SOT2_1
(SDA2_1)
PNL_PD12
MAD15_0
153
101
101
A9
P09
E
I
SCK2_1
(SCL2_1)
PNL_PD11
MAD14_0
Document Number: 002-05038 Rev.*C Page 27 of 183
S6E2DH Series
Pin No.
Pin name
I/O
circuit
type
Pin
state
type
LQFP176
LQFP120
LQFP120
FBGA161
Ex-LQFP120
(S6E2DH5GJA)
154
102
102
C8
P0A
E
K
SIN5_1
TIOA7_1
INT12_1
PNL_PD10
MAD13_0
155
103
103
B8
P0B
E
I
SOT5_1
(SDA5_1)
TIOB7_1
PNL_PD9
MAD12_0
156
104
104
A8
P0C
E
I
SCK5_1
(SCL5_1)
PNL_PD8
MAD11_0
157
105
105
C7
P0D
D
I
PNL_PD7
MSDWEX_0
158
106
106
B7
P0E
D
P
WKUP2
PNL_PD6
MCSX8_0
159
107
107
A7
VSS
－
－
160
108
108
C6
P68
D
I
SCK3_1
(SCL3_1)
PNL_PD5
MSDCLK_0
161
109
109
B6
P67
D
I
SOT3_1
(SDA3_1)
PNL_PD4
MSDCKE_0
162
110
110
A6
P66
E
K
SIN3_1
INT13_1
PNL_PD3
163
111
111
C5
P65
E
I
PNL_PD2
164
112
112
B5
P64
E
I
CTS4_0
PNL_PD1
Document Number: 002-05038 Rev.*C Page 28 of 183
S6E2DH Series
Pin No.
Pin name
I/O
circuit
type
Pin
state
type
LQFP176
LQFP120
LQFP120
FBGA161
Ex-LQFP120
(S6E2DH5GJA)
165
113
113
C4
P63
E
I
ADTG_3
RTS4_0
PNL_PD0
166
－
－
－
PDA
K
I
GE_SDWEX
167
－
－
－
PDB
K
I
GE_SDRASX
168
－
－
－
PDC
K
I
GE_SDCASX
169
－
－
－
PDD
K
I
GE_SDCSX
170
114
114
B4
P62
N
K
RX2_0
SCK4_0
(SCL4_0)
INT14_1
MDQM1_0
171
115
115
B3
P61
N
I
UHCONX0
RTCCO_0
SUBOUT_0
TX2_0
SOT4_0
(SDA4_0)
MDQM0_0
172
116
116
B2
P60
I
Q
WKUP3
SIN4_0
INT15_1
MALE_0
173
117
117
A4
VCC
－
－
174
118
118
A3
P80
H
R
UDM0
175
119
119
A2
P81
H
R
UDP0
176
120
120
B1
VSS
－
－
Document Number: 002-05038 Rev.*C Page 29 of 183
S6E2DH Series
Pin No.
Pin name
I/O
circuit
type
Pin
state
type
LQFP176
LQFP120
LQFP120
FBGA161
Ex-LQFP120
(S6E2DH5GJA)
－
－
－
A1, A5, A10,
VSS
－
－
A13, D5, D6,
D7, D8, E5,
E6, E7, E8,
E9, F5, F6,
F9, G4, G5,
G9, H4, H5,
H9, J4, J5,
J6, J7, J8,
J9, J10, K4,
K6, K10, L6,
M6, M7, M10,
N1, N6, N8,
N10, N13
Document Number: 002-05038 Rev.*C Page 30 of 183
S6E2DH Series
Signal Description
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Module
Pin Name
Function
Pin No.
LQFP176
LQFP120
Ex-LQFP120
LQFP120
(S6E2DH5GJ
A)
FBGA161
ADC
ADTG_0
A/D converter external trigger input pin
27
17
17
F1
ADTG_1
64
42
42
N5
ADTG_2
12
8
8
E4
ADTG_3
165
113
113
C4
AN00
A/D converter analog input pin.
ANxx describes ADC ch.xx.
100
66
66
K11
AN01
101
67
67
J11
AN02
102
68
68
H10
AN03
103
69
69
H11
AN04
104
70
70
H12
AN05
105
71
71
H13
AN06
106
72
72
G10
AN07
107
73
73
G11
AN08
108
74
74
G12
AN09
109
75
75
G13
AN10
110
76
76
F10
AN11
111
77
77
F11
AN12
116
78
78
F12
AN13
117
79
79
F13
AN14
118
80
80
E10
AN15
119
81
81
E11
AN16
120
82
82
E12
AN17
121
83
83
E13
AN18
122
84
84
D10
AN19
123
85
85
D11
AN20
124
86
86
D12
AN21
125
87
87
D13
AN22
130
88
88
C12
AN23
131
89
89
C13
Base Timer
0
TIOA0_0
Base Timer ch.0 TIOA Pin
100
66
66
K11
TIOA0_1
6
2
2
C3
TIOB0_0
Base Timer ch.0 TIOB Pin
101
67
67
J11
TIOB0_1
66
44
44
L7
Base Timer
1
TIOA1_0
Base Timer ch.1 TIOA Pin
102
68
68
H10
TIOA1_1
7
3
3
C2
TIOB1_0
Base Timer ch.1 TIOB Pin
103
69
69
H11
TIOB1_1
67
45
45
K8
Document Number: 002-05038 Rev.*C Page 31 of 183
S6E2DH Series
Module
Pin Name
Function
Pin No.
LQFP176
LQFP120
Ex-LQFP120
LQFP120
(S6E2DH5GJ
A)
FBGA161
Base Timer
2
TIOA2_0
Base Timer ch.2 TIOA Pin
104
70
70
H12
TIOA2_1
8
4
4
D3
TIOB2_0
Base Timer ch.2 TIOB Pin
105
71
71
H13
TIOB2_1
68
46
46
L8
Base Timer
3
TIOA3_0
Base Timer ch.3 TIOA Pin
106
72
72
G10
TIOA3_1
9
5
5
D2
TIOB3_0
Base Timer ch.3 TIOB Pin
107
73
73
G11
TIOB3_1
69
47
47
K9
Base Timer
4
TIOA4_0
Base Timer ch.4 TIOA Pin
108
74
74
G12
TIOA4_1
10
6
6
D1
TIOB4_0
Base Timer ch.4 TIOB Pin
109
75
75
G13
TIOB4_1
70
48
48
L9
Base Timer
5
TIOA5_0
Base Timer ch.5 TIOA Pin
110
76
76
F10
TIOA5_1
11
7
7
D4
TIOB5_0
Base Timer ch.5 TIOB Pin
111
77
77
F11
TIOB5_1
71
49
49
L10
Base Timer
6
TIOA6_0
Base Timer ch.6 TIOA Pin
116
78
78
F12
TIOA6_1
53
35
35
M4
TIOB6_0
Base Timer ch.6 TIOB Pin
117
79
79
F13
TIOB6_1
54
36
36
K5
Base Timer
7
TIOA7_0
Base Timer ch.7 TIOA Pin
118
80
80
E10
TIOA7_1
154
102
102
C8
TIOB7_0
Base Timer ch.7 TIOB Pin
119
81
81
E11
TIOB7_1
155
103
103
B8
CAN
(CAN-FD)
TX2_0
CAN-FD interface TX output pin
171
115
115
B3
TX2_1
26
16
16
F2
TX2_2
150
98
98
D9
RX2_0
CAN-FD interface RX input pin
170
114
114
B4
RX2_1
25
15
15
F3
RX2_2
149
97
97
C10
Debugger
SWCLK
Serial wire debug interface clock input pin
140
93
93
A11
SWDIO
Serial wire debug interface data input / output pin
142
95
95
B11
SWO
Serial wire viewer output pin
143
96
96
B10
TCK
JTAG test clock input pin
140
93
93
A11
TDI
JTAG test data input pin
141
94
94
C11
TDO
JTAG debug data output pin
143
96
96
B10
TMS
JTAG test mode state output pin
142
95
95
B11
TRACECLK
Trace CLK output pin of ETM
120
82
82
E12
TRACED0
Trace data output pin of ETM
121
83
83
E13
TRACED1
122
84
84
D10
TRACED2
123
85
85
D11
TRACED3
124
86
86
D12
TRSTX
JTAG test reset Input pin
139
92
92
B12
Document Number: 002-05038 Rev.*C Page 32 of 183
S6E2DH Series
Module
Pin Name
Function
Pin No.
LQFP176
LQFP120
Ex-LQFP120
LQFP120
(S6E2DH5GJ
A)
FBGA161
External
Bus
MAD00_0
External bus interface address bus
63
41
41
M5
MAD01_0
55
37
37
L5
MAD02_0
54
36
36
K5
MAD03_0
53
35
35
M4
MAD04_0
52
34
34
L4
MAD05_0
51
33
33
M3
MAD06_0
10
6
6
D1
MAD07_0
9
5
5
D2
MAD08_0
8
4
4
D3
MAD09_0
7
3
3
C2
MAD10_0
6
2
2
C3
MAD11_0
156
104
104
A8
MAD12_0
155
103
103
B8
MAD13_0
154
102
102
C8
MAD14_0
153
101
101
A9
MAD15_0
152
100
100
B9
MAD16_0
151
99
99
C9
MAD17_0
150
98
98
D9
MAD18_0
149
97
97
C10
MAD19_0
125
87
87
D13
MAD20_0
124
86
86
D12
MAD21_0
123
85
85
D11
MAD22_0
122
84
84
D10
MAD23_0
121
83
83
E13
MAD24_0
141
94
94
C11
MCSX0_0
External bus interface chip select output pin
65
43
43
K7
MCSX8_0
158
106
106
B7
MADATA00_0
External bus interface data bus
100
66
66
K11
MADATA01_0
101
67
67
J11
MADATA02_0
102
68
68
H10
MADATA03_0
103
69
69
H11
MADATA04_0
104
70
70
H12
MADATA05_0
105
71
71
H13
MADATA06_0
106
72
72
G10
MADATA07_0
107
73
73
G11
MADATA08_0
108
74
74
G12
MADATA09_0
109
75
75
G13
MADATA10_0
110
76
76
F10
MADATA11_0
111
77
77
F11
MADATA12_0
116
78
78
F12
MADATA13_0
117
79
79
F13
MADATA14_0
118
80
80
E10
MADATA15_0
119
81
81
E11
Document Number: 002-05038 Rev.*C Page 33 of 183
S6E2DH Series
Module
Pin Name
Function
Pin No.
LQFP176
LQFP120
Ex-LQFP120
LQFP120
(S6E2DH5GJ
A)
FBGA161
External
Bus
MDQM0_0
External bus interface byte mask signal output pin
171
115
115
B3
MDQM1_0
170
114
114
B4
MALE_0
External bus interface Address Latch
enable output signal for multiplex
172
116
116
B2
MRDY_0
External bus interface external RDY input signal
64
42
42
N5
MCLKOUT_0
External bus interface external clock output pin
120
82
82
E12
MNALE_0
External bus interface ALE signal to
control NAND Flash output pin
120
82
82
E12
MNCLE_0
External bus interface CLE signal to
control NAND Flash output pin
121
83
83
E13
MNREX_0
External bus interface read enable signal to control
NAND Flash output pin
123
85
85
D11
MNWEX_0
External bus interface write enable signal to control
NAND Flash output pin
122
84
84
D10
MOEX_0
External bus interface read enable
signal for SRAM
12
8
8
E4
MWEX_0
External bus interface write enable
signal for SRAM
11
7
7
D4
MSDCLK_0
SDRAM interface SDRAM clock output pin
160
108
108
C6
MSDCKE_0
SDRAM interface SDRAM clock enable pin
161
109
109
B6
MRASX_0
SDRAM interface SDRAM row active strobe pin
130
88
88
C12
MCASX_0
SDRAM interface SDRAM column active strobe pin
131
89
89
C13
MSDWEX_0
SDRAM interface SDRAM write enable pin
157
105
105
C7
External
Interrupt
INT00_0
External interrupt request 00 input pin
36
22
-
H2
INT00_1
19
9
9
E3
INT01_0
External interrupt request 01 input pin
37
23
-
H3
INT01_1
22
12
12
F4
INT02_0
External interrupt request 02 input pin
38
24
-
J2
INT02_1
25
15
15
F3
INT03_0
External interrupt request 03 input pin
39
25
-
J3
INT03_1
26
16
16
F2
INT04_0
External interrupt request 04 input pin
40
26
-
K2
INT04_1
6
2
2
C3
INT05_0
External interrupt request 05 input pin
41
27
27
K3
INT05_1
7
3
3
C2
INT06_0
External interrupt request 06 input pin
42
28
28
L2
INT06_1
8
4
4
D3
INT07_0
External interrupt request 07 input pin
43
29
29
L3
INT07_1
9
5
5
D2
INT08_0
External interrupt request 08 input pin
52
34
34
L4
INT08_1
120
82
82
E12
INT09_0
External interrupt request 09 input pin
100
66
66
K11
INT09_1
123
85
85
D11
Document Number: 002-05038 Rev.*C Page 34 of 183
S6E2DH Series
Module
Pin Name
Function
Pin No.
LQFP176
LQFP120
Ex-LQFP120
LQFP120
(S6E2DH5GJ
A)
FBGA161
External
Interrupt
INT10_0
External interrupt request 10 input pin
103
69
69
H11
INT10_1
149
97
97
C10
INT11_0
External interrupt request 11 input pin
105
71
71
H13
INT11_1
151
99
99
C9
INT12_0
External interrupt request 12 input pin
106
72
72
G10
INT12_1
154
102
102
C8
INT13_0
External interrupt request 13 input pin
109
75
75
G13
INT13_1
162
110
110
A6
INT14_0
External interrupt request 14 input pin
116
78
78
F12
INT14_1
170
114
114
B4
INT15_0
External interrupt request 15 input pin
117
79
79
F13
INT15_1
172
116
116
B2
NMIX
Non-Maskable Interrupt input pin
46
32
32
M2
GPIO
P00
General-purpose I/O port 0
139
92
92
B12
P01
140
93
93
A11
P02
141
94
94
C11
P03
142
95
95
B11
P04
143
96
96
B10
P05
149
97
97
C10
P06
150
98
98
D9
P07
151
99
99
C9
P08
152
100
100
B9
P09
153
101
101
A9
P0A
154
102
102
C8
P0B
155
103
103
B8
P0C
156
104
104
A8
P0D
157
105
105
C7
P0E
158
106
106
B7
P10
General-purpose I/O port 1
100
66
66
K11
P11
101
67
67
J11
P12
102
68
68
H10
P13
103
69
69
H11
P14
104
70
70
H12
P15
105
71
71
H13
P16
106
72
72
G10
P17
107
73
73
G11
P18
108
74
74
G12
P19
109
75
75
G13
P1A
110
76
76
F10
P1B
111
77
77
F11
P1C
116
78
78
F12
P1D
117
79
79
F13
P1E
118
80
80
E10
P1F
119
81
81
E11
Document Number: 002-05038 Rev.*C Page 35 of 183
S6E2DH Series
Module
Pin Name
Function
Pin No.
LQFP176
LQFP120
Ex-LQFP120
LQFP120
(S6E2DH5GJ
A)
FBGA161
GPIO
P20
General-purpose I/O port 2
46
32
32
M2
P21
51
33
33
M3
P22
52
34
34
L4
P23
53
35
35
M4
P24
54
36
36
K5
P25
55
37
37
L5
P26
63
41
41
M5
P27
64
42
42
N5
P33
General-purpose I/O port 3
19
9
9
E3
P34
20
10
10
E2
P35
21
11
11
E1
P36
22
12
12
F4
P37
25
15
15
F3
P38
26
16
16
F2
P39
27
17
17
F1
P3A
28
18
18
G3
P3B
6
2
2
C3
P3C
7
3
3
C2
P3D
8
4
4
D3
P3E
9
5
5
D2
P3F
10
6
6
D1
P46
General-purpose I/O port 4
79
51
51
N7
P47
80
52
52
N9
P48
82
54
54
L11
P49
83
55
55
L12
P50
General-purpose I/O port 5
65
43
43
K7
P51
66
44
44
L7
P52
67
45
45
K8
P53
68
46
46
L8
P54
69
47
47
K9
P55
70
48
48
L9
P56
71
49
49
L10
P60
General-purpose I/O port 6
172
116
116
B2
P61
171
115
115
B3
P62
170
114
114
B4
P63
165
113
113
C4
P64
164
112
112
B5
P65
163
111
111
C5
P66
162
110
110
A6
P67
161
109
109
B6
P68
160
108
108
C6
Document Number: 002-05038 Rev.*C Page 36 of 183
S6E2DH Series
Module
Pin Name
Function
Pin No.
LQFP176
LQFP120
Ex-LQFP120
LQFP120
(S6E2DH5GJ
A)
FBGA161
GPIO
P70
General-purpose I/O port 7
34
20
－
J1
P71
35
21
－
K1
P72
36
22
－
H2
P73
37
23
－
H3
P74
38
24
－
J2
P75
39
25
－
J3
P76
40
26
－
K2
P77
41
27
27
K3
P78
42
28
28
L2
P79
43
29
29
L3
P7A
33
19
－
G2
P7B
12
8
8
E4
P7C
11
7
7
D4
P80
General-purpose I/O port 8
174
118
118
A3
P81
175
119
119
A2
P90
General-purpose I/O port 9
120
82
82
E12
P91
121
83
83
E13
P92
122
84
84
D10
P93
123
85
85
D11
P94
124
86
86
D12
P95
125
87
87
D13
P96
130
88
88
C12
P97
131
89
89
C13
PA0
General-purpose I/O port A
2
－
－
－
PA1
3
－
－
－
PA2
4
－
－
－
PA3
5
－
－
－
PA4
29
－
－
－
PA5
30
－
－
－
PA6
31
－
－
－
PA7
32
－
－
－
PA8
13
－
－
－
PA9
14
－
－
－
PAA
15
－
－
－
PAB
16
－
－
－
PAC
17
－
－
－
PAD
18
－
－
－
Document Number: 002-05038 Rev.*C Page 37 of 183
S6E2DH Series
Module
Pin Name
Function
Pin No.
LQFP176
LQFP120
Ex-LQFP120
LQFP120
(S6E2DH5GJ
A)
FBGA161
GPIO
PB0
General-purpose I/O port B
47
－
－
－
PB1
48
－
－
－
PB2
49
－
－
－
PB3
50
－
－
－
PB4
56
－
－
－
PB5
57
－
－
－
PB6
58
－
－
－
PB7
59
－
－
－
PB8
72
－
－
－
PB9
73
－
－
－
PBA
74
－
－
－
PBB
75
－
－
－
PBC
76
－
－
－
PBD
77
－
－
－
PC0
General-purpose I/O port C
94
－
－
－
PC1
95
－
－
－
PC2
96
－
－
－
PC3
97
－
－
－
PC4
98
－
－
－
PC5
99
－
－
－
PC6
112
－
－
－
PC7
113
－
－
－
PC8
114
－
－
－
PC9
115
－
－
－
PCA
126
－
－
－
PCB
127
－
－
－
PCC
128
－
－
－
PCD
129
－
－
－
PD0
General-purpose I/O port D
134
－
－
－
PD1
135
－
－
－
PD2
136
－
－
－
PD3
137
－
－
－
PD4
138
－
－
－
PD5
144
－
－
－
PD6
145
－
－
－
PD7
146
－
－
－
PD8
147
－
－
－
PD9
148
－
－
－
PDA
166
－
－
－
PDB
167
－
－
－
PDC
168
－
－
－
PDD
169
－
－
－
Document Number: 002-05038 Rev.*C Page 38 of 183
S6E2DH Series
Module
Pin Name
Function
Pin No.
LQFP176
LQFP120
Ex-LQFP120
LQFP120
(S6E2DH5GJ
A)
FBGA161
GPIO
PE0
General-purpose I/O port E
84
56
56
M12
PE2
86
58
58
N11
PE3
87
59
59
N12
Multi-
function serial
0
SIN0_0
Multi-function serial interface ch.0 input pin
52
34
34
L4
SIN0_1
120
82
82
E12
SOT0_0
(SDA0_0)
Multi-function serial interface ch.0 output pin
This pin operates as SOT0 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA0 when it is used in an I2C (operation mode 4).
53
35
35
M4
SOT0_1
(SDA0_1)
121
83
83
E13
SCK0_0
(SCL0_0)
Multi-function serial interface ch.0 clock I/O pin.
This pin operates as SCK0 when it is used in a
CSIO (operation mode 2) and as SCL0 when it is
used in an I2C (operation mode 4)
54
36
36
K5
SCK0_1
(SCL0_1)
122
84
84
D10
Multi-
function serial
1
SIN1_0
Multi-function serial interface ch.1 input pin
100
66
66
K11
SIN1_1
123
85
85
D11
SOT1_0
(SDA1_0)
Multi-function serial interface ch.1 output pin
This pin operates as SOT1 when it is used in a
UART/CSIO/LIN(operation modes 0 to 3) and as
SDA1 when it is used in an I2C (operation mode 4).
101
67
67
J11
SOT1_1
(SDA1_1)
124
86
86
D12
SCK1_0
(SCL1_0)
Multi-function serial interface ch.1 clock I/O pin.
This pin operates as SCK1 when it is used in a
CSIO (operation mode 2) and as SCL1 when it is
used in an I2C (operation mode 4).
102
68
68
H10
SCK1_1
(SCL1_1)
125
87
87
D13
Multi-
function serial
2
SIN2_0
Multi-function serial interface ch.2 input pin
103
69
69
H11
SIN2_1
151
99
99
C9
SOT2_0
(SDA2_0)
Multi-function serial interface ch.2 output pin
This pin operates as SOT2 when it is used in a
UART/CSIO/LIN (operation mode 0 to 3) and as
SDA2 when it is used in an I2C (operation mode 4).
104
70
70
H12
SOT2_1
(SDA2_1)
152
100
100
B9
SCK2_0
(SCL2_0)
Multi-function serial interface ch.2 clock I/O Pin.
This pin operates as SCK2 when it is used in a
CSIO (operation mode 2) and as SCL2 when it is
used in an I2C (operation mode 4).
105
71
71
H13
SCK2_1
(SCL2_1)
153
101
101
A9
Multi-
function serial
3
SIN3_0
Multi-function serial interface ch.3 input pin
106
72
72
G10
SIN3_1
162
110
110
A6
SOT3_0
(SDA3_0)
Multi-function serial interface ch.3 output pin.
This pin operates as SOT3 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA3 when it is used in an I2C (operation mode 4).
107
73
73
G11
SOT3_1
(SDA3_1)
161
109
109
B6
SCK3_0
(SCL3_0)
Multi-function serial interface ch.3 clock I/O pin.
This pin operates as SCK3 when it is used in a
CSIO (operation mode 2) and as SCL3 when it is
used in an I2C (operation mode 4).
108
74
74
G12
SCK3_1
(SCL3_1)
160
108
108
C6
Document Number: 002-05038 Rev.*C Page 39 of 183
S6E2DH Series
Module
Pin Name
Function
Pin No.
LQFP176
LQFP120
Ex-LQFP120
LQFP120
(S6E2DH5GJ
A)
FBGA161
Multi-
function serial
4
SIN4_0
Multi-function serial interface ch.4 input pin
172
116
116
B2
SOT4_0
(SDA4_0)
Multi-function serial interface ch.4 output pin.
This pin operates as SOT4 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA4 when it is used in an I2C (operation mode 4).
171
115
115
B3
SCK4_0
(SCL4_0)
Multi-function serial interface ch.4 clock I/O pin.
This pin operates as SCK4 when it is used in a
CSIO (operation mode 2) and as SCL4 when it is
used in an I2C (operation mode 4).
170
114
114
B4
CTS4_0
Multi-function serial interface ch.4 CTS input pin
164
112
112
B5
RTS4_0
Multi-function serial interface ch.4 RTS output pin
165
113
113
C4
Multi-
function serial
5
SIN5_0
Multi-function serial interface ch.5 input pin
109
75
75
G13
SIN5_1
154
102
102
C8
SOT5_0
(SDA5_0)
Multi-function serial interface ch.5 output pin.
This pin operates as SOT5 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA5 when it is used in an I2C (operation mode 4).
110
76
76
F10
SOT5_1
(SDA5_1)
155
103
103
B8
SCK5_0
(SCL5_0)
Multi-function serial interface ch.5 clock I/O pin.
This pin operates as SCK5 when it is used in a
CSIO (operation mode 2) and as SCL5 when it is
used in an I2C (operation mode 4).
111
77
77
F11
SCK5_1
(SCL5_1)
156
104
104
A8
Multi-
function serial
6
SIN6_0
Multi-function serial interface ch.6 input pin
19
9
9
E3
SIN6_1
117
79
79
F13
SOT6_0
(SDA6_0)
Multi-function serial interface ch.6 output pin.
This pin operates as SOT6 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA6 when it is used in an I2C (operation mode 4).
20
10
10
E2
SOT6_1
(SDA6_1)
118
80
80
E10
SCK6_0
(SCL6_0)
Multi-function serial interface ch.6 clock I/O pin.
This pin operates as SCK6 when it is used in a
CSIO (operation mode 2) and as SCL6 when it is
used in an I2C (operation mode 4).
21
11
11
E1
SCK6_1
(SCL6_1)
119
81
81
E11
SCS60_0
Multi-function serial interface ch.6 chip select 0
input/output pin
22
12
12
F4
SCS60_1
116
78
78
F12
Document Number: 002-05038 Rev.*C Page 40 of 183
S6E2DH Series
Module
Pin Name
Function
Pin No.
LQFP176
LQFP120
Ex-LQFP120
LQFP120
(S6E2DH5GJ
A)
FBGA161
Multi-
function serial
7
SIN7_0
Multi-function serial interface ch.7 input pin
8
4
4
D3
SOT7_0
(SDA7_0)
Multi-function serial interface ch.7 output pin.
This pin operates as SOT7 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA7 when it is used in an I2C (operation mode 4).
9
5
5
D2
SCK7_0
(SCL7_0)
Multi-function serial interface ch.7
clock I/O pin.
This pin operates as SCK7 when it is used in a
CSIO (operation mode 2) and as SCL7 when it is
used in an I2C (operation mode 4).
10
6
6
D1
SCS70_0
Multi-function serial interface ch.7 chip select 0
input/output pin
7
3
3
C2
Multi-function
Timer 0
DTTI0X_0
Input signal controlling wave form generator
outputs RTO00 to RTO05 of Multi-function timer 0.
27
17
17
F1
DTTI0X_1
104
70
70
H12
FRCK0_0
16-bit free-run timer ch.0 external clock input pin
20
10
10
E2
FRCK0_1
103
69
69
H11
IC00_0
16-bit input capture input pin of
Multi-function timer 0.
ICxx describes channel number.
26
16
16
F2
IC00_1
105
71
71
H13
IC01_0
25
15
15
F3
IC01_1
106
72
72
G10
IC02_0
22
12
12
F4
IC02_1
107
73
73
G11
IC03_0
21
11
11
E1
IC03_1
108
74
74
G12
RTO00_0
(PPG00_0)
Wave form generator output pin of Multi-function
timer 0.
This pin operates as PPG00 when it is used in
PPG0 output modes.
6
2
2
C3
RTO00_1
(PPG00_1)
109
75
75
G13
RTO01_0
(PPG00_0)
Wave form generator output pin of Multi-function
timer 0.
This pin operates as PPG00 when it is used in
PPG0 output modes.
7
3
3
C2
RTO01_1
(PPG00_1)
110
76
76
F10
RTO02_0
(PPG02_0)
Wave form generator output pin of Multi-function
timer 0.
This pin operates as PPG02 when it is used in
PPG0 output modes.
8
4
4
D3
RTO02_1
(PPG02_1)
111
77
77
F11
RTO03_0
(PPG02_0)
Wave form generator output pin of Multi-function
timer 0.
This pin operates as PPG02 when it is used in
PPG0 output modes.
9
5
5
D2
RTO03_1
(PPG02_1)
116
78
78
F12
Document Number: 002-05038 Rev.*C Page 41 of 183
S6E2DH Series
Module
Pin Name
Function
Pin No.
LQFP176
LQFP120
Ex-LQFP120
LQFP120
(S6E2DH5GJ
A)
FBGA161
Multi-function
Timer 0
RTO04_0
(PPG04_0)
Wave form generator output pin of Multi-function
timer 0.
This pin operates as PPG04 when it is used in
PPG0 output modes.
10
6
6
D1
RTO04_1
(PPG04_1)
117
79
79
F13
RTO05_0
(PPG04_0)
Wave form generator output pin of Multi-function
timer 0.
This pin operates as PPG04 when it is used in
PPG0 output modes.
11
7
7
D4
RTO05_1
(PPG04_1)
118
80
80
E10
Quadrature
Position/
Revolution
Counter
0
AIN0_0
QPRC ch.0 AIN input pin
100
66
66
K11
AIN0_1
6
2
2
C3
AIN0_2
109
75
75
G13
BIN0_0
QPRC ch.0 BIN input pin
101
67
67
J11
BIN0_1
7
3
3
C2
BIN0_2
110
76
76
F10
ZIN0_0
QPRC ch.0 ZIN input pin
102
68
68
H10
ZIN0_1
8
4
4
D3
ZIN0_2
111
77
77
F11
Real-time
clock
RTCCO_0
0.5 seconds pulse output pin of Real-time clock
171
115
115
B3
RTCCO_1
63
41
41
M5
SUBOUT_0
Sub clock output pin
171
115
115
B3
SUBOUT_1
63
41
41
M5
USB0
UDM0
USB ch.0 device/host D – pin
174
118
118
A3
UDP0
USB ch.0 device/host D + pin
175
119
119
A2
UHCONX0
USB ch.0 external pull-up control pin
171
115
115
B3
Low-Power
Consumption
Mode
WKUP0
Deep standby mode return signal input pin 0
46
32
32
M2
WKUP1
Deep standby mode return signal input pin 1
65
43
43
K7
WKUP2
Deep standby mode return signal input pin 2
158
106
106
B7
WKUP3
Deep standby mode return signal input pin 3
172
116
116
B2
VBAT
VREGCTL
On-board regulator control pin
82
54
54
L11
VWAKEUP
The return signal input pin from a hibernation state
83
55
55
L12
SD memory
card interface
S_CLK_0
SD memory card clock output pin
21
11
11
E1
S_CMD_0
SD memory card command output
22
12
12
F4
S_DATA1_0
SD memory card data bus
19
9
9
E3
S_DATA0_0
20
10
10
E2
S_DATA3_0
25
15
15
F3
S_DATA2_0
26
16
16
F2
S_CD_0
SD memory card detection pin
28
18
18
G3
S_WP_0
SD memory card write protection
27
17
17
F1
Document Number: 002-05038 Rev.*C Page 42 of 183
S6E2DH Series
Module
Pin Name
Function
Pin No.
LQFP176
LQFP120
Ex-LQFP120
LQFP120
(S6E2DH5GJ
A)
FBGA161
I2S 0
I2SMCLK0_0
I2S ch.0 external clock pin
6
2
2
C3
I2SDO0_0
I2S ch.0 serial transition data output pin
7
3
3
C2
I2SWS0_0
I2S ch.0 frame synchronization signal pin
8
4
4
D3
I2SDI0_0
I2S ch.0 serial received data input pin
9
5
5
D2
I2SCK0_0
I2S ch.0 bit clock pin
10
6
6
D1
I2S 1
I2SMCLK1_0
I2S ch.1 external clock pin
51
33
33
M3
I2SDO1_0
I2S ch.1 serial transition data output pin
52
34
34
L4
I2SWS1_0
I2S ch.1 frame synchronization signal pin
53
35
35
M4
I2SDI1_0
I2S ch.1 serial received data input pin
54
36
36
K5
I2SCK1_0
I2S ch.1 bit clock pin
55
37
37
L5
GDC
High-Speed
Quad SPI
GE_SPCK
SPI clock output pin
34
20
-
J1
GE_SPDQ0
SPI data input / output pin
35
21
-
K1
GE_SPDQ1
38
24
-
J2
GE_SPDQ2
39
25
-
J3
GE_SPDQ3
36
22
-
H2
GE_SPCSX0
SPI chip select output pin
37
23
-
H3
GDC
HyperBus I/F
GE_HBCK
HBI clock output pin
34
20
-
J1
GE_HBDQ0
HBI data input / output pin
36
22
-
H2
GE_HBDQ1
37
23
-
H3
GE_HBDQ2
38
24
-
J2
GE_HBDQ3
39
25
-
J3
GE_HBDQ4
40
26
-
K2
GE_HBDQ5
41
27
-
K3
GE_HBDQ6
42
28
-
L2
GE_HBDQ7
43
29
-
L3
GE_HBCSX0
HBI chip select output pin
35
21
-
K1
GE_HBCSX1
12
8
-
E4
GE_HBRWDS
HBI RWDS input / output pin
33
19
-
G2
GE_HBRESETX
HBI hardware reset output pin
25
15
-
F3
GE_HBINTX
HBI interrupt input pin
26
16
-
F2
GE_HBRSTOX
HBI reset input pin
27
17
-
F1
GE_HBWPX
HBI write protect output pin
28
18
-
G3
Document Number: 002-05038 Rev.*C Page 43 of 183
S6E2DH Series
Module
Pin Name
Function
Pin No.
LQFP176
LQFP120
Ex-LQFP120
LQFP120
(S6E2DH5GJ
A)
FBGA161
GDC
Panel
PNL_DCLK
GDC clock output pin
67
45
45
K8
PNL_DEN
GDC data enable output pin (blanking signal)
68
46
46
L8
PNL_PWE
GDC power enable control output pin
66
44
44
L7
PNL_LE
GDC line end output pin
69
47
47
K9
PNL_LH_SYNC
GDC horizontal synchronization output pin
70
48
48
L9
PNL_FV_SYNC
GDC vertical synchronization output pin
71
49
49
L10
PNL_PD0
GDC panel data output pin
165
113
113
C4
PNL_PD1
164
112
112
B5
PNL_PD2
163
111
111
C5
PNL_PD3
162
110
110
A6
PNL_PD4
161
109
109
B6
PNL_PD5
160
108
108
C6
PNL_PD6
158
106
106
B7
PNL_PD7
157
105
105
C7
PNL_PD8
156
104
104
A8
PNL_PD9
155
103
103
B8
PNL_PD10
154
102
102
C8
PNL_PD11
153
101
101
A9
PNL_PD12
152
100
100
B9
PNL_PD13
151
99
99
C9
PNL_PD14
150
98
98
D9
PNL_PD15
149
97
97
C10
PNL_PD16
131
89
89
C13
PNL_PD17
130
88
88
C12
PNL_PD18
125
87
87
D13
PNL_PD19
124
86
86
D12
PNL_PD20
123
85
85
D11
PNL_PD21
122
84
84
D10
PNL_PD22
121
83
83
E13
PNL_PD23
120
82
82
E12
PNL_TSIG0
GDC timing generator for panel control
PNL_TSIG signals are customized synchronization
signals for direct interfacing to the column and row
drivers of most panel types.
For more information, refer to Peripheral Manual
(GDC Core part).
70
48
48
L9
PNL_TSIG1
71
49
49
L10
PNL_TSIG2
68
46
46
L8
PNL_TSIG3
69
47
47
K9
PNL_TSIG4
66
44
44
L7
PNL_TSIG5
130
88
88
C12
PNL_TSIG6
125
87
87
D13
PNL_TSIG7
124
86
86
D12
PNL_TSIG8
123
85
85
D11
PNL_TSIG9
122
84
84
D10
PNL_TSIG10
121
83
83
E13
PNL_TSIG11
120
82
82
E12
Document Number: 002-05038 Rev.*C Page 44 of 183
S6E2DH Series
Module
Pin Name
Function
Pin No.
LQFP176
LQFP120
Ex-LQFP120
LQFP120
(S6E2DH5GJ
A)
FBGA161
GDC
SDRAM-IF
(176 pin only)
GE_SDA0
SDRAM-IF address output pin
144
-
-
-
GE_SDA1
138
-
-
-
GE_SDA2
137
-
-
-
GE_SDA3
136
-
-
-
GE_SDA4
135
-
-
-
GE_SDA5
134
-
-
-
GE_SDA6
129
-
-
-
GE_SDA7
128
-
-
-
GE_SDA8
127
-
-
-
GE_SDA9
126
-
-
-
GE_SDA10
115
-
-
-
GE_SDA11
114
-
-
-
GE_SDBA0
SDRAM-IF bank address output pin
113
-
-
-
GE_SDBA1
112
-
-
-
GE_SDCASX
SDRAM-IF column active output pin
168
-
-
-
GE_SDRASX
SDRAM-IF row active output pin
167
-
-
-
GE_SDWEX
SDRAM-IF write enable output pin
166
-
-
-
GE_SDCKE
SDRAM-IF clock enable output pin
2
-
-
-
GE_SDCLK
SDRAM-IF clock output pin
3
-
-
-
GE_SDCSX
SDRAM-IF chip select output pin
169
-
-
-
GE_SDDQ0
SDRAM-IF data input / output pin
99
-
-
-
GE_SDDQ1
98
-
-
-
GE_SDDQ2
97
-
-
-
GE_SDDQ3
96
-
-
-
GE_SDDQ4
95
-
-
-
GE_SDDQ5
94
-
-
-
GE_SDDQ6
77
-
-
-
GE_SDDQ7
76
-
-
-
GE_SDDQ8
75
-
-
-
GE_SDDQ9
74
-
-
-
GE_SDDQ10
73
-
-
-
GE_SDDQ11
72
-
-
-
GE_SDDQ12
59
-
-
-
GE_SDDQ13
58
-
-
-
GE_SDDQ14
57
-
-
-
GE_SDDQ15
56
-
-
-
GE_SDDQ16
50
-
-
-
GE_SDDQ17
49
-
-
-
GE_SDDQ18
48
-
-
-
GE_SDDQ19
47
-
-
-
GE_SDDQ20
32
-
-
-
GE_SDDQ21
31
-
-
-
GE_SDDQ22
30
-
-
-
GE_SDDQ23
29
-
-
-
Document Number: 002-05038 Rev.*C Page 45 of 183
S6E2DH Series
Module
Pin Name
Function
Pin No.
LQFP176
LQFP120
Ex-LQFP120
LQFP120
(S6E2DH5GJ
A)
FBGA161
GDC
SDRAM-IF
(176-pin only)
GE_SDDQ24
SDRAM-IF data input / output pin
18
-
-
-
GE_SDDQ25
17
-
-
-
GE_SDDQ26
16
-
-
-
GE_SDDQ27
15
-
-
-
GE_SDDQ28
14
-
-
-
GE_SDDQ29
13
-
-
-
GE_SDDQ30
5
-
-
-
GE_SDDQ31
4
-
-
-
GE_SDDQM0
SDRAM-IF input / output mask pin
148
-
-
-
GE_SDDQM1
147
-
-
-
GE_SDDQM2
146
-
-
-
GE_SDDQM3
145
-
-
-
Reset
INITX
External Reset Input pin.
A reset is valid when INITX = L.
78
50
50
M8
Mode
MD1
Mode 1 pin.
During serial programming to Flash memory, MD1
= L must be input.
84
56
56
M12
MD0
Mode 0 pin.
During normal operation, MD0 = L must be input.
During serial programming to Flash memory, MD0
= H must be input.
85
57
57
M11
Power
VCC
Power supply Pin
1
1
1
C1
23
13
13
G1
44
30
30
L1
62
40
40
N4
89
61
61
L13
133
91
91
A12
173
117
117
A4
GND
VSS
GND Pin
24
14
14
H1
45
31
31
M1
61
39
39
N3
88
60
60
M13
132
90
90
B13
159
107
107
A7
176
120
120
B1
Clock
X0
Main clock (oscillation) input pin
86
58
58
N11
X0A
Sub clock (oscillation) input pin
79
51
51
N7
X1
Main clock (oscillation) I/O pin
87
59
59
N12
X1A
Sub clock (oscillation) I/O pin
80
52
52
N9
CROUT_0
Built-in High-speed CR-osc clock output port
52
34
34
L4
CROUT_1
64
42
42
N5
Analog
Power
AVCC
A/D converter analog power supply pin
90
62
62
K13
AVRL
A/D converter analog reference voltage input pin
92
64
64
J13
AVRH
A/D converter analog reference voltage input pin
93
65
65
J12
Document Number: 002-05038 Rev.*C Page 46 of 183
S6E2DH Series
Module
Pin Name
Function
Pin No.
LQFP176
LQFP120
Ex-LQFP120
LQFP120
(S6E2DH5GJ
A)
FBGA161
VBAT
Power
VBAT
VBAT power supply pin.
Backup power supply (battery etc.) and system
power supply.
81
53
53
M9
Analog
GND
AVSS
A/D converter GND pin
91
63
63
K12
C Pin
C
Power supply stabilization capacity pin
60
38
38
N2
Note:
− While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to
all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-05038 Rev.*C Page 47 of 183
S6E2DH Series
5. I/O Circuit Type
Type
Circuit
Remarks
A
It is possible to select the main
oscillation / GPIO function
When the main oscillation
is selected.
・Oscillation feedback resistor
: Approximately 1 MΩ
・With Standby mode control
When the GPIO is selected.
・ CMOS level output.
・ CMOS level hysteresis input
・ With pull-up resistor control
・ With standby mode control
・ Pull-up resistor
: Approximately 80 kΩ
・ IOH = -2 mA, IOL = 2 mA
B
・CMOS level hysteresis input
・Pull-up resistor
: Approximately 80 kΩ
P-ch
P-ch
N-ch
R
R
P-ch
P-ch
N-ch
X0
X1
Pull-up
resistor
Feedback
resistor
Pull-up
resistor
Pull-up resistor control
Pull-up resistor
Digital input
Digital output
Digital output
Pull-up resistor control
Digital input
Standby mode control
Clock input
Standby mode control
Digital input
Standby mode control
Digital output
Digital output
Document Number: 002-05038 Rev.*C Page 48 of 183
S6E2DH Series
Type
Circuit
Remarks
C
・Open drain output
・CMOS level hysteresis input
D
・CMOS level output
・CMOS level hysteresis input
・With pull-up resistor control
・With standby mode control
・Pull-up resistor
: Approximately 80 kΩ
・IOH = -4 mA, IOL = 4 mA
・When this pin is used as an I2C pin,
the digital output P-ch transistor is always off.
E
・CMOS level output
・CMOS level hysteresis input
・With pull-up resistor control
・With standby mode control
・Pull-up resistor
: Approximately 80 kΩ
・IOH = -2 mA, IOL = 2 mA
・When this pin is used as an I2C pin,
the digital output P-ch transistor is always off.
N-ch
P-chP-ch
N-ch
R
P-chP-ch
N-ch
R
Digital input
Digital output
Digital output
Digital output
Pull-up resistor control
Digital input
Standby mode control
Digital output
Digital output
Pull-up resistor control
Digital input
Standby mode control
Document Number: 002-05038 Rev.*C Page 49 of 183
S6E2DH Series
Type
Circuit
Remarks
F
・CMOS level output
・CMOS level hysteresis input
・With input control
・Analog input
・With pull-up resistor control
・With standby mode control
・Pull-up resistor
: Approximately 80 kΩ
・IOH = -2 mA, IOL = 2 mA
・When this pin is used as an I2C pin,
the digital output P-ch transistor is always off.
G
・CMOS level output
・CMOS level hysteresis input
・With pull-up resistor control
・With standby mode control
・Pull-up resistor
: Approximately 80 kΩ
・IOH = -8 mA, IOL = 8 mA
・When this pin is used as an I2C pin,
the digital output P-ch transistor is always off.
P-chP-ch
N-ch
R
P-chP-ch
N-ch
R
Digital output
Digital output
Pull-up resistor control
Digital input
Standby mode control
Digital output
Digital output
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
Document Number: 002-05038 Rev.*C Page 50 of 183
S6E2DH Series
Type
Circuit
Remarks
H
It is possible to select the USB I/O / GPIO
function.
When the USB I/O is selected.
・Full-speed, Low-speed control
When the GPIO is selected.
・CMOS level output
・CMOS level hysteresis input
・With standby mode control
・IOH = -20.5 mA, IOL = 18.5 mA
I
・CMOS level output
・CMOS level hysteresis input
・5 V tolerant
・With pull-up resistor control
・With standby mode control
・Pull-up resistor
: Approximately 80 kΩ
・IOH = -2 mA, IOL = 2 mA
・Available to control of PZR registers.
J
・CMOS level hysteresis input
UDP/Pxx
UDM/Pxx
Differential
P-chP-ch
N-ch
R
Mode input
Digital output
Digital output
Pull-up resistor control
Digital input
Standby mode control
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
UDP output
UDP input
Differential input
USB/GPIO select
UDM input
UDM output
USB Digital input/output direction
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
USB Full-speed/Low-speed control
Document Number: 002-05038 Rev.*C Page 51 of 183
S6E2DH Series
Type
Circuit
Remarks
K
・CMOS level output
・CMOS level hysteresis input
・With pull-up resistor control
・With standby mode control
・Pull-up resistor
: Approximately 33 kΩ
・IOH = -11 mA, IOL = 11 mA
L
P-chP-ch
N-ch
R
・CMOS level output
・CMOS level hysteresis input
・TTL level hysteresis input
:SDRAM-IF Data Input only
・With pull-up resistor control
・With standby mode control
・Pull-up resistor
: Approximately 33 kΩ
・IOH = -11 mA, IOL = 11 mA
P-chP-ch
N-ch
R
Digital output
Digital output
Digital input
Standby mode control
Pull-up resistor control
Digital output
Digital output
Pull-up resistor
control
Digital input
(TTL)
Digital input
(CMOS)
Standby mode
control
Document Number: 002-05038 Rev.*C Page 52 of 183
S6E2DH Series
Type
Circuit
Remarks
N
・CMOS level output
・CMOS level hysteresis input
・5 V tolerant
・With pull-up resistor control
・With standby mode control
・Pull-up resistor
: Approximately 80 kΩ
・IOH = -3 mA, IOL = 3 mA (GPIO)
・IOL = 20 mA (Fast Mode Plus)
・Available to control of PZR registers.
・When this pin is used as an I2C pin,
the digital output P-ch transistor is always off
O
・CMOS level output
・CMOS level hysteresis input
・5 V tolerant
・With pull-up resistor control
・Pull-up resistor
: Approximately 80 kΩ
・IOH = -2 mA, IOL = 2 mA
・Available to control of PZR registers.
・Please refer to the "VBAT domain" setting of
the IO in the “Peripheral Manual main
part (002-04856)".
P
R
・CMOS level hysteresis input
・Please refer to the "VBAT domain" setting of
the IO in the “Peripheral Manual main
part (002-04856)".
P-ch
N-ch
R
P-ch
N-ch
Digital output
Digital output
Fast mode
control
Digital input
Standby mode
control
Pull-up resistor
control
Digital output
Digital output
Digital input
Pull-up resistor
control
Digital input
Sub OSC/GPIO
select
OSC
X0A
P-ch
P-ch
N-ch
R
Document Number: 002-05038 Rev.*C Page 53 of 183
S6E2DH Series
Type
Circuit
Remarks
Q
R
RX
It is possible to select the sub
oscillation / GPIO function
When the sub oscillation is selected.
・Oscillation feedback resistor
: Approximately 12 MΩ
When the GPIO is selected.
・CMOS level hysteresis input
・Please refer to the "VBAT domain" setting of
the IO in the “Peripheral Manual main
part (002-04856)".
R
・CMOS level output
・CMOS level hysteresis input
・With input control
・Analog input
・With pull-up resistor control
・With standby mode control
・Pull-up resistor
: Approximately 80 kΩ
・IOH = -4 mA, IOL = 4 mA
P-chP-ch
N-ch
R
Digital input
Sub OSC/ GPIO
select
OSC
Sub OSC enable
Clock input
X1A
Digital output
Digital output
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
Document Number: 002-05038 Rev.*C Page 54 of 183
S6E2DH Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Document Number: 002-05038 Rev.*C Page 55 of 183
S6E2DH Series
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
6.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Document Number: 002-05038 Rev.*C Page 56 of 183
S6E2DH Series
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1
MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
Document Number: 002-05038 Rev.*C Page 57 of 183
S6E2DH Series
6.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-05038 Rev.*C Page 58 of 183
S6E2DH Series
7. Handling Devices
Power Supply Pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each POWER pins and GND pins of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between VCC and VSS, between
AVCC and AVSS and between AVRH and AVRL near this device.
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed
operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the
fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard
VCC value, and the transient fluctuation rate does not exceed 0.1 V/μs at a momentary fluctuation such as switching the power
supply.
Crystal Oscillator Circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as
possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub Crystal Oscillator
This series sub oscillator circuit is low gain to keep the low current consumption.
The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.
Surface mount type
Size: More than 3.2 mm × 1.5 mm
Load capacitance: Approximately 6 pF to 7 pF
When the Standard setting (CCS/CCB=11001110)
Load capacitance: Approximately 4 pF to 7 pF
When the low power setting (CCS/CCB=00000100)
Lead type
Load capacitance: Approximately 6 pF to 7 pF
When the Standard setting (CCS/CCB=11001110)
Load capacitance: Approximately 4 pF to 7 pF
When the low power setting (CCS/CCB=00000100)
Document Number: 002-05038 Rev.*C Page 59 of 183
S6E2DH Series
Using an External Clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3)
can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to
X0A. X1A (P47) can be used as a general-purpose I/O port.
Handling when Using Multi-Function Serial Pin as I2C Pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with
power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use
by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7 μF would be recommended for this series.
Mode Pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays
low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Device
C
VSS
CS
GND
Example of Using an External Clock
Device
X0(X0A)
X1(PE3), X1A (P47)
Can be used as
general-purpose
I/O ports.
Set as External clock
input
Document Number: 002-05038 Rev.*C Page 60 of 183
S6E2DH Series
Notes on Power-on
Turn power on/off in the following order or at the same time. The device operates normally after all power on.
VBAT only Power-on is possible when VBAT and VCC turns Power-on and Hibernation control is setting and then turns Power-off.
About Hibernation control, see Chapter 7-3: VBAT Domain(B) in FM4 Family Peripheral Manual Main Part (002-04856).
Turning on :
VBAT → VCC→ AVCC → AVRH
Turning off :
AVRH → AVCC → VCC→ VBAT
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end.
If an error is detected, retransmit the data.
Differences in Features among the Products with Different Memory Sizes and between Flash Products and
MASK Products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among
the products with different memory sizes and between Flash products and MASK products are different because chip layout and
memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Pull-Up Function of 5V Tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O.
Pin Doubled as Debug Function
Please use as output only regarding the pin doubled as TDO/TMS/TDI/TCK/TRSTX, SWO/SWDIO/SWCLK.
Don't use as input.
S6E2DH5GJA
The following must correspond to S6E2DH5GJA.
1. Terminal DNU0 / 1 is short-circuited, and the pull-up of about 10kΩ is done.
2. Please do not connect the open end NC terminal.
3. Please have the following port settings.
PFR7: bit6=0, bit10=0
PDOR7: bit6=0, bit10=0
DDR7: bit6=1, bit10=1
See Chapter 12: I/O Port in FM4 Family Peripheral Manual Main Part (002-04856) for the details.
4. Please connect a bypass capacitor as close as possible to GND on the board and VCC in pin number 22.
DNU0
DNU1
R
Device
Document Number: 002-05038 Rev.*C Page 61 of 183
S6E2DH Series
8. Block Diagram
TRSTX,TCK,
TDI,TMS
TDO
TRACEDx,
TRACECLK
I
D
Sys
UDP0,UDM0
UHCONX0
INITX
CLK
X0 TX2,RX2
X1
X0A I2SMCLKx,
X1A I2SWSx,I2SCKx
I2SDIx
I2SDOx
CROUT
P0x,
P1x,
:
PFx
AVCC,AVSS,
AVRH,AVRL MD0,MD1
ANxx
ADTG S_CLK,S_CMD
S_DATAx
S_CD,S_WP
MADx
TIOAx MADATAx
MCSXx,MDQMx,
TIOBx MOEX,MWEX,
MALE,MRDY,
MNALE,MNCLE,
AIN0 MNWEX,MNREX,
BIN0
MCLKOUT,MSDWEX,
ZIN0 MSDCLK,MSDCKE,
MRASX,MCASX
■Panel I/F
PNL_DCLK, PNL_DEN, PNL_PWE,
PNL_LE, PNL_LH_SYNC, PNL_FV_SYNC,
PNL_PD[23:0], PNL_TSIG[11:0]
IC0x
■SDRAM I/F
GE_SDCLK,GE_SDCKE,GE_SDCSX,
FRCK0
GE_SDCASX,GE_SDRASX,GE_SDWEX,
GE_SDDQM[3:0],GE_SDBA[1:0],
GE_SDA[11:0],GE_SDDQ[31:0]
■HyperBus I/F
DTTI0X GE_HBCK, GE_HBDQ[7:0], GE_HBCSX0/1,
RTO0x GE_HBRWDS, GE_HBRESETX,
GE_HBINTX, GE_HBRSTOX, GE_HBWPX
■HighSpeed Quad SPI
GE_SPCK, GE_SPDQ[3:0], GE_SPCSX0
*S6E2DH5GJA Unavailable
*S6E2DH5GJA Only
VBAT
VWAKEUP
VREGCTL
RTCCO,SUBOUT
C
WKUPx
INTxx
NMIX
SCKx
SINx
SOTx
CTS4
RTS4
SCSx
SWJ-DP
TPIU* ROM
Table
FPU MPU NVIC
Cortex-M4Core
@160MHz(Max)
Dual-Timer
Watchdog Timer
(Software)
Clock Reset
Generator
Watchdog Timer
(Hardw are)
CSV
AHB-APB
Bridge:APB0(Max:80MHz)
SRAM0
32Kbytes
MainFlash
384Kbytes
USB2.0
(Host/Func)
PHY
DMAC
8ch.
DSTC
1unit(128ch.)
CAN
PRG-CRC
Accelerator
I2S
2units
GPIO
PIN-Function-Ctrl
SD-CARD I/F
Trace Buffer
(16Kbytes)
Security
MainFlash I/F
Multi-layer AHB (Max:160MHz)
Main
OSC PLL CR
100kHz
CR
4MHz
Sub
OSC
Source Clock
VBAT Domain
Unit 0
Unit 1
12bit A/D Converter 24ch.
Base Timer
16bit 16ch./
32bit 8ch
QPRC
1ch.
A/D Activation Compare
6ch.
16bit Input Capture
4ch.
16bit Free-run Timer
3ch.
16bit Output Compare
6ch.
Waveform Generator
3ch.
16bit PPG
3ch.
Multi-function Timer 1unit
Real-Time Clock
Port Cntl.
VBAT Domain
AHB-APB Bridge:APB1(Max:160MHz)
AHB-APB Bridge:APB2(Max:80MHz)
External Bus I/F
CAN Prescaler
USB Clock Cntl. PLL
I2S Clock Cntl. PLL
LVD Cntl.
IRQ-Monitor
CRC Accelerator
Watch Counter
Deep Standby Cntl.
Peripheral Clock Gating
Low-speed CR Prescaler
External Interrupt
Controller
16ch + NMI
Multi-function Serial I/F
8ch.
(w ith FIFO ch.0 to ch.7)
HW flow control(ch.4)
LVD
Power-On
Reset
Regulator
AHB-AHB Bridge (Slave)
AHB-AHB Bridge (Master)
S6E2DH5J0A / S6E2DH5G0A / S6E2DH5GJA
GDC Clock Cntl. PLL
Graphic
Engine core
SDRAM I/F
HighSpeed
Quad SPI
VRAM
512Kbytes
GDC unit
AHB-AHB Bridge (Slave)
ETM*
SRAM2
4Kbytes
HyperBus I/F
VFLASH
2Mbytes
MODE-Cntl.
Document Number: 002-05038 Rev.*C Page 62 of 183
S6E2DH Series
9. Memory Size
See Memory size in 1. Product Lineup to confirm the memory size.
10. Memory Map
Memory Map
GDC Area
0xDFFF_FFFF
0xD0A0_6000
0xD0A0_5000 GDC_HBIF
0xD0A0_4000 GDC_HSQSPI
0xD0A0_3000 GDC_SDRAMIF
0xFFFF_FFFF 0xD0A0_1000 Reserved
0xD0A0_0000 GDC
0xE010_0000 0xD008_0000 Reserved
0xD000_0000 VRAM
0xE000_0000 0xC000_0000
Memory Area for
GDC_HSQSPI or GDC_HBIF
0xB000_0000 External SDRAM
0xB000_0000 Peripherals Area
0x41FF_FFFF
0x8000_0000 0x4008_1000
0x4008_0000 Programable-CRC
External Device Area SDRAM 0x4007_0000 CAN-FD
256Mbytes 0x4006_F000 GPIO
0x7000_0000 0x4006_E000 SD-Card I/F
SRAM 0x4006_D000 Reserved
/NOR Flash Memory 0x4006_C000 I2S
/NAND Flash Memory 0x4006_2000 Reserved
0x6000_0000 256Mbytes 0x4006_1000 DSTC
0x4006_0000 DMAC
0x4005_0000 Reserved
0x4400_0000 0x4004_0000 USB ch.0
0x4003_F000 EXT-bus I/F
0x4200_0000 0x4003_E000 Reserved
0x4003_D100 GDC Prescaler
0x4000_0000 0x4003_D000 I2S Prescaler
0x4003_C800 Reserved
0x2400_0000 0x4003_C100 Peripheral Clock Gating
0x4003_C000 LowSpeed CR Prescaler
0x2200_0000 0x4003_B000
RTC/Port Ctrl
0x2004_1000 Reserved 0x4003_A000 Watch Counter
0x4003_9000 CRC
0x2004_0000 0x4003_8000 MFS
0x2000_0000 Reserved 0x4003_7000 CAN Prescaler
0x4003_6000 USB Clock Ctrl
0x1FFF_8000 0x4003_5000 LVD/DS mode
0x4003_2000 Reserved
0x4003_1000 Int-Req.Read
0x4003_0000 EXTI
0x0040_4000 0x4002_F000 Reserved
0x0040_2000 CR trimming 0x4002_E000 CR Trim
0x0040_0000 Security 0x4002_8000 Reserved
0x4002_7000 A/DC
0x4002_6000 QPRC
0x4002_5000 Base Timer
0x0006_0000 0x4002_4000 PPG
0x4002_1000 Reserved
0x4002_0000 MFT Unit0
0x4001_6000 Reserved
0x4001_5000 Dual Timer
0x4001_3000 Reserved
0x0000_0000 0x4001_2000 SW WDT
0x4001_1000 HW WDT
0x4001_0000 Clock/Reset
0x4000_1000 Reserved
0x4000_0000 Flash I/F
SRAM0
32Kbytes
Reserved
Reserved
Flash
384Kbytes
Reserved
Reserved
32Mbytes
Bit band alias
Peripherals
Reserved
32Mbytes
Bit band alias
SRAM2
4Kbytes
Reserved
Cortex-M4 Private
Peripherals
GDC
Reserved
Reserved
Document Number: 002-05038 Rev.*C Page 63 of 183
S6E2DH Series
Peripheral Address Map
Start address End address Bus Peripherals
0x4000_0000 0x4000_0FFF MainFlash I/F register
0x4000_1000 0x4000_FFFF Reserved
0x4001_0000 0x4001_0FFF Clock/Reset Control
0x4001_1000 0x4001_1FFF Hardware Watchdog timer
0x4001_2000 0x4001_2FFF Software Watchdog timer
0x4001_3000 0x4001_4FFF Reserved
0x4001_5000 0x4001_5FFF Dual-Timer
0x4001_6000 0x4001_FFFF Reserved
0x4002_0000 0x4002_0FFF Multi-function timer unit0
0x4002_1000 0x4002_3FFF Reserved
0x4002_4000 0x4002_4FFF PPG
0x4002_5000 0x4002_5FFF Base Timer
0x4002_6000 0x4002_6FFF Quadrature Position/Revolution Counter
0x4002_7000 0x4002_7FFF A/D Converter
0x4002_8000 0x4002_DFFF Reserved
0x4002_E000 0x4002_EFFF Internal CR trimming
0x4002_F000 0x4002_FFFF Reserved
0x4003_0000 0x4003_0FFF External Interrupt Controller
0x4003_1000 0x4003_1FFF Interrupt Request Batch-Read Function
0x4003_2000 0x4003_4FFF Reserved
0x4003_5000 0x4003_57FF Low Voltage Detector
0x4003_5800 0x4003_5FFF Deep standby mode Controller
0x4003_6000 0x4003_6FFF USB clock generator
0x4003_7000 0x4003_7FFF CAN prescaler
0x4003_8000 0x4003_8FFF Multi-function serial Interface
0x4003_9000 0x4003_9FFF CRC
0x4003_A000 0x4003_AFFF Watch Counter
0x4003_B000 0x4003_BFFF RTC/PortCtrl
0x4003_C000 0x4003_C0FF Low-speed CR Prescaler
0x4003_C100 0x4003_C7FF Peripheral Clock Gating
0x4003_C800 0x4003_CFFF Reserved
0x4003_D000 0x4003_D0FF I2S Prescaler
0x4003_D100 0x4003_DFFF GDC Prescaler
0x4003_E000 0x4003_EFFF Reserved
0x4003_F000 0x4003_FFFF External Memory interface
0x4004_0000 0x4004_FFFF USB ch.0
0x4005_0000 0x4005_FFFF Reserved
0x4006_0000 0x4006_0FFF DMAC register
0x4006_1000 0x4006_1FFF DSTC register
0x4006_2000 0x4006_BFFF Reserved
0x4006_C000 0x4006_CFFF I2S
0x4006_D000 0x4006_DFFF Reserved
0x4006_E000 0x4006_EFFF SD-Card I/F
0x4006_F000 0x4006_FFFF GPIO
0x4007_0000 0x4007_FFFF CAN-FD
0x4008_0000 0x4008_0FFF Programmable-CRC
0x4008_1000 0x41FF_FFFF Reserved
0xB000_0000 0xDFFF_FFFF AHB GDC unit
AHB
APB0
APB1
APB2
AHB
Document Number: 002-05038 Rev.*C Page 64 of 183
S6E2DH Series
11. Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the L level.
INITX=1
This is the period when the INITX pin is the H level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.
Input enabled
Indicates that the input function can be used.
Internal input fixed at 0
This is the status that the input function cannot be used. Internal input is fixed at L.
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
Setting prohibition
Prohibition of a setting by specification limitation.
Document Number: 002-05038 Rev.*C Page 65 of 183
S6E2DH Series
List of Pin Status
Pin status Type
Function
Group
Power-on
Reset or
Low-Voltage
Detection
State
INITX
Input
State
Device
Internal
Reset
State
Run Mode
or Sleep
Mode
State
Timer Mode
RTC Mode or
Stop Mode State
Deep Standby RTC
Mode or Deep Standby
Stop Mode State
Return
from Deep
Standby
Mode
State
Power
Supply
Unstable
Power
Supply
Stable
Power
Supply
Stable
Power
Supply
Stable
Power
Supply
Stable
Power
Supply
Stable
‐
INITX=0
INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
‐
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
A
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Main
crystal
oscillator
input pin/
External
main
clock
input
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
B
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
External
main
clock
input
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Main
crystal
oscillator
output pin
Hi-Z /
Internal
input
fixed
at 0/
or Input
enable
Hi-Z /
Internal
input
fixed
at 0
Hi-Z /
Internal
input
fixed
at 0
Maintain previous state/
When oscillation stops*1,Hi-Z /
Internal input fixed at 0
C
INITX
input pin
Pull-up /
input
enabled
Pull-up /
input
enabled
Pull-up /
input
enabled
Pull-up /
input
enabled
Pull-up /
input
enabled
Pull-up /
input
enabled
Pull-up /
input
enabled
Pull-up /
input
enabled
Pull-up /
input
enabled
D
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Document Number: 002-05038 Rev.*C Page 66 of 183
S6E2DH Series
Pin status Type
Function
Group
Power-on
Reset or
Low-Voltage
Detection
State
INITX
Input
State
Device
Internal
Reset
State
Run Mode
or Sleep
Mode
State
Timer Mode
RTC Mode or
Stop Mode State
Deep Standby RTC
Mode or Deep Standby
Stop Mode State
Return
from Deep
Standby
Mode
State
Power
Supply
Unstable
Power
Supply
Stable
Power
Supply
Stable
Power
Supply
Stable
Power
Supply
Stable
Power
Supply
Stable
‐
INITX=0
INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
‐
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
E
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
input
enabled
GPIO
selected
Hi-Z /
input
enabled
GPIO
selected
F
NMIX
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
Hi-Z /
WKUP
input
enabled
Maintain
previous
state
Resource
other than
above
selected
Hi-Z
Hi-Z /
input
enabled
Hi-Z /
input
enabled
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
GPIO
selected
G
JTAG
selected
Hi-Z
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
H
JTAG
selected
Hi-Z
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Resource
other than
above
selected
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
GPIO
selected
I
Resource
selected
Hi-Z
Hi-Z /
input
enabled
Hi-Z /
input
enabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
GPIO
selected
Document Number: 002-05038 Rev.*C Page 67 of 183
S6E2DH Series
Pin status Type
Function
Group
Power-on
Reset or
Low-Voltage
Detection
State
INITX
Input
State
Device
Internal
Reset
State
Run Mode
or Sleep
Mode
State
Timer Mode
RTC Mode or
Stop Mode State
Deep Standby RTC
Mode or Deep Standby
Stop Mode State
Return
from Deep
Standby
Mode
State
Power
Supply
Unstable
Power
Supply
Stable
Power
Supply
Stable
Power
Supply
Stable
Power
Supply
Stable
Power
Supply
Stable
‐
INITX=0
INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
‐
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
K
External
interrupt
enabled
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Resource
other than
above
selected
Hi-Z
Hi-Z /
input
enabled
Hi-Z /
input
enabled
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
L
Analog
input
selected
Hi-Z
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Resource
other than
above
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
GPIO
selected
Document Number: 002-05038 Rev.*C Page 68 of 183
S6E2DH Series
Pin status Type
Function
Group
Power-on
Reset or
Low-Voltage
Detection
State
INITX
Input
State
Device
Internal
Reset
State
Run Mode
or Sleep
Mode
State
Timer Mode
RTC Mode or
Stop Mode State
Deep Standby RTC
Mode or Deep Standby
Stop Mode State
Return
from Deep
Standby
Mode
State
Power
Supply
Unstable
Power
Supply
Stable
Power
Supply
Stable
Power
Supply
Stable
Power
Supply
Stable
Power
Supply
Stable
‐
INITX=0
INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
‐
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
M
Analog
input
selected
Hi-Z
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
External
interrupt
enabled
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Resource
other than
above
selected
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
N
Analog
input
selected
Hi-Z
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Trace
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Trace
output
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Resource
other than
above
selected
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Document Number: 002-05038 Rev.*C Page 69 of 183
S6E2DH Series
Pin status Type
Function
Group
Power-on
Reset or
Low-Voltage
Detection
State
INITX
Input
State
Device
Internal
Reset
State
Run Mode
or Sleep
Mode
State
Timer Mode
RTC Mode or
Stop Mode State
Deep Standby RTC
Mode or Deep Standby
Stop Mode State
Return
from Deep
Standby
Mode
State
Power
Supply
Unstable
Power
Supply
Stable
Power
Supply
Stable
Power
Supply
Stable
Power
Supply
Stable
Power
Supply
Stable
‐
INITX=0
INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
‐
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
O
Analog
input
selected
Hi-Z
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Trace
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Trace
output
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
External
interrupt
enabled
selected
Maintain
previous
state
Resource
other than
above
selected
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
P
WKUP
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
Hi-Z /
WKUP
input
enabled
GPIO
selected
Resource
other than
above
selected
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Document Number: 002-05038 Rev.*C Page 70 of 183
S6E2DH Series
Pin status Type
Function
Group
Power-on
Reset or
Low-Voltage
Detection
State
INITX
Input
State
Device
Internal
Reset
State
Run Mode
or Sleep
Mode
State
Timer Mode
RTC Mode or
Stop Mode State
Deep Standby RTC
Mode or Deep Standby
Stop Mode State
Return
from Deep
Standby
Mode
State
Power
Supply
Unstable
Power
Supply
Stable
Power
Supply
Stable
Power
Supply
Stable
Power
Supply
Stable
Power
Supply
Stable
‐
INITX=0
INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
‐
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
Q
WKUP
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
Hi-Z /
WKUP
input
enabled
WKUP
input
enabled
External
interrupt
enabled
selected
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Resource
other than
above
selected
Hi-Z
Hi-Z /
input
enabled
Hi-Z /
input
enabled
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
R
GPIO
selected
Hi-Z
Hi-Z /
input
enabled
Hi-Z /
input
enabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
USB I/O
pin
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z at
trans-
mission/
Internal
input fixed
at 0 at
reception
Hi-Z at
trans-
mission/
Internal
input fixed
at 0 at
reception
Hi-Z /
input
enabled
Hi-Z /
input
enabled
Hi-Z /
input
enabled
Hi-Z /
input
enabled
*1: Oscillation is stopped at Sub timer mode, low-speed CR timer mode, RTC mode, Stop mode, Deep standby RTC mode,
and Deep standby Stop mode.
Document Number: 002-05038 Rev.*C Page 71 of 183
S6E2DH Series
List of VBAT Domain Pin Status
VBAT Pin Status Type
Function
Group
Power-on
Reset*1
INITX
Input
State
Device
Internal
Reset
State
Run
Mode
or Sleep
Mode
State
Timer Mode
RTC Mode or
Stop Mode State
Deep Standby
RTC Mode or
Deep Standby Stop
Mode State
Return
from
Deep
Standby
Mode
State
VBAT
RTC
Mode
State
Return
from
VBAT
RTC
Mode
State
Power
Supply
Unstable
Power Supply
Stable
Power
Supply
Stable
Power Supply
Stable
Power Supply
Stable
Power
Supply
Stable
Power
Supply
Stable
Power
Supply
Sable
‐
INITX=0
INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
-
-
‐
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
-
-
S
GPIO
selected
Setting
disabled
Internal
input
fixed
at 0
Internal
input
fixed
at 0
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Setting
prohibition
-
Sub crystal
oscillator
input pin /
External
sub clock
input
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Maintain
previous
state
Maintain
previous
state
T
GPIO
selected
Setting
disabled
Internal
input
fixed
at 0
Internal
input
fixed
at 0
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Setting
prohibition
-
External
sub clock
input
selected
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Sub crystal
oscillator
output pin
Hi-Z/
Internal
input fixed
at 0 or input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state /
When
oscillation
stops,
Hi-Z*2
Maintain
previous
state /
When
oscillation
stops,
Hi-Z*2
Maintain
previous
state /
When
oscillation
stops,
Hi-Z*2
Maintain
previous
state /
When
oscillation
stops,
Hi-Z*2
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
U
Resource
selected
Hi-Z
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
selected
*1: When VBAT and VCC power on.
*2: When the SOSCNTL bit in the WTOSCCNT register is 0, Sub crystal oscillator output pin is maintain previous state.
When the SOSCNTL bit in the WTOSCCNT register is 1, Oscillation is stopped at Stop mode and Deep standby
Stop mode
Document Number: 002-05038 Rev.*C Page 72 of 183
S6E2DH Series
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
Power supply voltage *1, *2
VCC
VSS - 0.5
VSS + 4.6
V
Power supply voltage (VBAT) *1 ,*3
VBAT
VSS - 0.5
VSS + 4.6
V
Analog power supply voltage *1 ,*4
AVCC
VSS - 0.5
VSS + 4.6
V
Analog reference voltage *1 ,*4
AVRH
VSS - 0.5
VSS + 4.6
V
Input voltage *1
VI
VSS - 0.5
VCC + 0.5
(≤ 4.6 V)
V
VSS - 0.5
VSS + 6.5
V
5 V tolerant
Analog pin input voltage *1
VIA
VSS - 0.5
AVCC + 0.5
(≤ 4.6 V)
V
Output voltage *1
VO
VSS - 0.5
VCC + 0.5
(≤ 4.6 V)
V
L level maximum output current *5
IOL
-
10
mA
2 mA type
20
mA
4 mA type
20
mA
8 mA type
20
mA
11 mA type
22.4
mA
I2C Fm+
L level average output current *6
IOLAV
-
2
mA
2 mA type
4
mA
4 mA type
8
mA
8 mA type
11
mA
11 mA type
20
mA
I2C Fm+
L level total maximum output current
∑IOL
-
100
mA
L level total average output current *7
∑IOLAV
-
50
mA
H level maximum output current *5
IOH
-
- 10
mA
2 mA type
-20
mA
4 mA type
- 20
mA
8 mA type
- 20
mA
11 mA type
H level average output current *6
IOHAV
-
- 2
mA
2 mA type
-4
mA
4 mA type
- 8
mA
8 mA type
- 11
mA
11 mA type
H level total maximum output current
∑IOH
-
- 100
mA
H level total average output current *7
∑IOHAV
-
- 50
mA
Power consumption
PD
-
200
mW
Storage temperature
TSTG
- 55
+ 150
°C
*1: These parameters are based on the condition that VSS = AVSS = 0.0 V.
*2: VCC must not drop below VSS - 0.5 V.
*3: VBAT must not drop below VSS - 0.5 V.
*4: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on.
*5: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding
pins.
*6: The average output current is defined as the average current value flowing through any one of the corresponding pins for
a 100 ms period.
*7: The total average output current is defined as the average current value flowing through all of corresponding pins for a
100 ms.
WARNING:
− Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or
temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
Document Number: 002-05038 Rev.*C Page 73 of 183
S6E2DH Series
12.2 Recommended Operating Conditions
Parameter
Symbol
Conditions
Value
Unit
Remarks
Min
Max
Power supply voltage
VCC
-
3.0
3.6
V
*1
2.7 *5
3.6
*2
Power supply voltage (VBAT)
VBAT
-
1.65
3.6
V
Analog power supply voltage
AVCC
-
2.7
3.6
V
AVCC = VCC
Analog reference voltage
AVRH
-
*4
AVCC
V
AVRL
-
AVss
AVss
V
Smoothing capacitor
CS
-
1
10
μF
for built-in regulator *6
Operating
temperature
Junction temperature
TJ
-
-40
+ 125
°C
Ambient temperature
TA
-
-40
*3
°C
*1: When using the GDC part .
When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0).
*2: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80).
*3: The maximum temperature of the ambient temperature (TA) can guarantee a range that does not exceed the
junction temperature (TJ).
The calculation formula of the ambient temperature (TA) is shown below.
TA(Max) = TJ(Max) - Pd(Max) × θJA
Pd: Power dissipation (W)
θJA: Package thermal resistance (°C/W)
Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH))
IOL: L level output current
IOH: H level output current
VOL: L level output voltage
VOH: H level output voltage
*4: The minimum value of Analog reference voltage depends on the value of compare clock cycle
(tCCK). See 14.5 12-bit A/D Converter for the details.
*5: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more,
instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in
Low-speed CR is possible to operate only.
*6: See "C pin" in "7. Handling Devices" for the connection of the smoothing capacitor.
Document Number: 002-05038 Rev.*C Page 74 of 183
S6E2DH Series
Package thermal resistance and maximum permissible power for each package are shown below.
The operation is guaranteed maximum permissible power or less for semiconductor devices.
Table 12-1 Table for Package Thermal Resistance and Maximum Permissible Power
Package
Printed
Circuit
Board
Thermal
Resistance θJA
(°C/W)
Maximum Permissible Power
(mW)
TA= +85°C
TA= +105°C
LQFP: LQM120
(0.5 mm pitch)
4 layers
38
1053
526
LQFP: LQM120 *1
(0.5 mm pitch)
4 layers
39
1026
513
LQFP: LQP176
(0.5 mm pitch)
4 layers
35
1143
571
FBGA: FDJ161
(0.5 mm pitch)
4 layers
35
1143
571
Ex-LQFP: LEM120
(0.5 mm pitch)
4 layers
18*2
2222
1111
*1: When S6E2DH5GJA product.
*2: This is a case where the connection process was carried out back exposed die pad foundation.
Please connect directly to GND back exposed die pad.
Notes:
1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of
the device's electrical characteristics are warranted when the device is operated within these ranges.
2. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may
adversely affect reliability and could result in device failure.
3. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
4. Users considering application outside the listed conditions are advised to contact their representatives beforehand.
Document Number: 002-05038 Rev.*C Page 75 of 183
S6E2DH Series
Calculation Method of Power Dissipation (Pd)
The power dissipation is shown in the following formula.
Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH))
IOL: L level output current
IOH: H level output current
VOL: L level output voltage
VOH: H level output voltage
ICC is a current consumed in device.
It can be analyzed as follows.
ICC = ICC(INT) + ΣICC(IO)
ICC(INT): Current consumed in internal logic and memory, etc. through regulator
ΣICC(IO): Sum of current (I/O switching current) consumed in output pin
For ICC (INT), it can be anticipated by "(1) Current Rating" in "3. DC Characteristics" (This rating value does not include ICC (IO) for a
value at pin fixed).
For Icc (IO), it depends on system used by customers.
The calculation formula is shown below.
ICC(IO) = (CINT + CEXT) × VCC × fsw
CINT: Pin internal load capacitance
CEXT: External load capacitance of output pin
fSW: Pin switching frequency
Parameter
Symbol
Conditions
Capacitance Value
Pin internal load
capacitance
CINT
2 mA type
1.93 pF
4 mA type
3.45 pF
8 mA type
3.42 pF
Calculate ICC (Max) as follows when the power dissipation can be evaluated by yourself.
(1) Measure current value ICC (Typ) at normal temperature (+25°C).
(2) Add maximum leak current value ICC (leak_max) at operating on a value in (1).
ICC(Max) = ICC(Typ) + ICC(leak_max)
Parameter
Symbol
Conditions
Current Value
Maximum leak current at
operating
ICC(leak_max)
TJ = +125 °C
66.8 mA
TJ = +105 °C
33.7 mA
TJ = +85 °C
22.8 mA
Note:
− VFLASH of current is not included
Document Number: 002-05038 Rev.*C Page 76 of 183
S6E2DH Series
Current Explanation Diagram
A
V
・・・
・・・
・・・
V
A
A
Regulator
Logic
Flash
RAM
ICC
ICC(INT)
ΣICC(IO)
IOL
VOL
VOH
IOH
ICC(IO)
Chip
VCC
CEXT
Pd = VCC×ICC + Σ(IOL×VOL)＋Σ((VCC-VOH)×(－IOH))
ICC = ICC(INT)＋ΣICC(IO)
Document Number: 002-05038 Rev.*C Page 77 of 183
S6E2DH Series
12.3 DC Characteristics
12.3.1 Current Rating
Table 12-2 Typical and Maximum Current Consumption in Normal Operation (PLL), Code Running from Flash Memory
(Flash Accelerator Mode and Trace Buffer Function Enabled)
Parameter
Symbol
Pin
Name
Conditions
Frequency*4
(MHz)
Value
Unit
Remarks
Typ*1
Max*2
Power
supply
current
ICC
VCC
Normal
operation
*6,*7
(PLL)
*5
160 MHz
182
279
mA
*3
When all peripheral
clocks are ON
GDC clock 160 MHz
144 MHz
176
270
mA
120 MHz
167
256
mA
100 MHz
159
244
mA
80 MHz
151
233
mA
60 MHz
143
221
mA
40 MHz
136
210
mA
20 MHz
128
199
mA
8 MHz
123
191
mA
4 MHz
122
190
mA
Normal
operation ,
*6,*7
(PLL)
*5
160 MHz
43
117
mA
*3
When all peripheral
clocks are OFF
144 MHz
39
112
mA
120 MHz
34
106
mA
100 MHz
29
100
mA
80 MHz
24
95
mA
60 MHz
20
90
mA
40 MHz
15
84
mA
20 MHz
10
78
mA
8 MHz
7
74
mA
4 MHz
6
73
mA
*1: TA=+25°C, VCC=3.3 V
*2: TJ=+125°C, VCC=3.6 V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2
*5: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1)
*6: Data access is nothing to main flash memory and VFLASH memory
*7: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)
Document Number: 002-05038 Rev.*C Page 78 of 183
S6E2DH Series
Table 12-3 Typical and Maximum Current Consumption in Normal Operation (PLL), Code with Data Accessing Running
from Flash Memory (Flash Accelerator Mode and Trace Buffer Function Disabled)
Parameter
Symbol
Pin
Name
Conditions
Frequency*4
(MHz)
Value
Unit
Remarks
Typ*1
Max*2
Power
supply
current
ICC
VCC
Normal
operation
*6,*7,*8
(PLL)
*5
160 MHz
185
285
mA
*3
When all peripheral
clocks are ON
GDC clock 160 MHz
144 MHz
179
276
mA
120 MHz
169
261
mA
100 MHz
161
250
mA
80 MHz
154
239
mA
60 MHz
146
227
mA
40 MHz
138
215
mA
20 MHz
130
204
mA
8 MHz
125
196
mA
4 MHz
124
195
mA
Normal
operation
*6,*7,*8
(PLL)
*5
160 MHz
45
122
mA
*3
When all peripheral
clocks are OFF
144 MHz
41
117
mA
120 MHz
36
111
mA
100 MHz
31
105
mA
80 MHz
26
99
mA
60 MHz
22
94
mA
40 MHz
17
89
mA
20 MHz
12
83
mA
8 MHz
10
80
mA
4 MHz
9
79
mA
*1: TA=+25°C, VCC=3.3 V
*2: TJ=+125°C, VCC=3.6 V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0=PCLK2=HCLK/2, PCLK1=HCLK
*5: When not operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0)
*6: With data access to a main flash memory.
*7: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)
*8: Data access is nothing to VFLASH memory
Document Number: 002-05038 Rev.*C Page 79 of 183
S6E2DH Series
Table 12-4 Typical and Maximum Current Consumption in Normal Operation (PLL), Code with Data Accessing Running
from Flash Memory (Flash 0 Wait-cycle Mode and Read Access 0 Wait)
Parameter
Symbol
Pin
Name
Conditions
Frequency*4
(MHz)
Value
Unit
Remarks
Typ*1
Max*2
Power
supply
current
ICC
VCC
Normal
operation ,
*6,*7,*8
(PLL)
*5
72 MHz
168
251
mA
*3
When all peripheral
clocks are ON
GDC clock 160 MHz
60 MHz
161
242
mA
48 MHz
154
233
mA
36 MHz
147
224
mA
24 MHz
140
214
mA
12 MHz
133
205
mA
8 MHz
131
202
mA
4 MHz
128
199
mA
*5
72 MHz
41
114
mA
*3
When all peripheral
clocks are OFF
60 MHz
36
108
mA
48 MHz
32
104
mA
36 MHz
27
98
mA
24 MHz
23
94
mA
12 MHz
18
88
mA
8 MHz
17
87
mA
4 MHz
15
85
mA
*1: TA=+25°C, VCC=3.3 V
*2: TJ=+125°C, VCC=3.6 V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK
*5: When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FSYNDN.SD = 000)
*6: With data access to a main flash memory.
*7: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)
*8: Data access is nothing to VFLASH memory
Document Number: 002-05038 Rev.*C Page 80 of 183
S6E2DH Series
Table 12-5 Typical and Maximum Current Consumption in Normal Operation (other than PLL), Code with Data Accessing
Running from Flash Memory (Flash 0 Wait-cycle Mode and Read Access 0 Wait)
Parameter
Symbol
Pin
Name
Conditions
Frequency*4
(MHz)
Value
Unit
Remarks
Typ*1
Max*2
Power
supply
current
ICC
VCC
Normal
operation,
*6,*8
(built-in
High-spee
d CR)
*5
4 MHz
110
181
mA
*3
When all peripheral
clocks are ON
GDC clock 160 MHz
4.1
74
mA
*3
When all peripheral
clocks are OFF
Normal
operation ,
*6,*7,*8
(Sub
oscillation)
*5
32 kHz
0.7
76.65
mA
*3
When all peripheral
clocks are ON
0.69
71.65
mA
*3
When all peripheral
clocks are OFF
Normal
operation ,
*6,*8
(built-in
Low-speed
CR)
*5
100 kHz
0.74
88.65
mA
*3
When all peripheral
clocks are ON
0.73
74.65
mA
*3
When all peripheral
clocks are OFF
*1: TA=+25°C, VCC=3.3 V
*2: TJ=+125°C, VCC=3.6 V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2
*5: When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FSYNDN.SD = 000)
*6: With data access to a main flash memory.
*7: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit)
*8: Data access is nothing to VFLASH memory
Document Number: 002-05038 Rev.*C Page 81 of 183
S6E2DH Series
Table 12-6 Typical and Maximum Current Consumption in Sleep Operation (PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2
Parameter
Symbol
Pin
Name
Conditions
Frequency*4
(MHz)
Value
Unit
Remarks
Typ*1
Max*2
Power
supply
current
ICCS
VCC
Sleep *5,*6
operation
(PLL)
160 MHz
103
181
mA
*3
When all peripheral
clocks are ON
GDC clock 160 MHz
144 MHz
98
175
mA
120 MHz
91
168
mA
100 MHz
86
162
mA
80 MHz
80
155
mA
60 MHz
74
149
mA
40 MHz
69
143
mA
20 MHz
63
137
mA
8 MHz
59
132
mA
4 MHz
58
131
mA
Sleep *5,*6
operation
(PLL)
160 MHz
24
91
mA
*3
When all peripheral
clocks are OFF
144 MHz
22
89
mA
120 MHz
19
86
mA
100 MHz
16
83
mA
80 MHz
14
81
mA
60 MHz
11
78
mA
40 MHz
9
76
mA
20 MHz
6
73
mA
8 MHz
5
72
mA
4 MHz
4
71
mA
*1: TA=+25°C, VCC=3.3 V
*2: TJ=+125°C, VCC=3.6 V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2
*5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)
*6: Data access is nothing to VFLASH memory
Document Number: 002-05038 Rev.*C Page 82 of 183
S6E2DH Series
Table 12-7 Typical and Maximum Current Consumption in Sleep Operation (PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK
Parameter
Symbol
Pin
Name
Conditions
Frequency*4
(MHz)
Value
Unit
Remarks
Typ*1
Max*2
Power
supply
current
ICCS
VCC
Sleep *5,*6
operation
(PLL)
72 MHz
84
160
mA
*3
When all peripheral
clocks are ON
GDC clock 160 MHz
60 MHz
80
155
mA
48 MHz
75
150
mA
36 MHz
71
145
mA
24 MHz
67
141
mA
12 MHz
63
137
mA
8 MHz
61
134
mA
4 MHz
60
133
mA
72 MHz
15
82
mA
*3
When all peripheral
clocks are OFF
60 MHz
13
80
mA
48 MHz
12
79
mA
36 MHz
10
77
mA
24 MHz
8
75
mA
12 MHz
7
74
mA
8 MHz
6
73
mA
4 MHz
5
72
mA
*1: TA=+25°C, VCC=3.3 V
*2: TJ=+125°C, VCC=3.6 V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK
*5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)
*6: Data access is nothing to VFLASH memory
Document Number: 002-05038 Rev.*C Page 83 of 183
S6E2DH Series
Table 12-8 Typical and Maximum Current Consumption in Sleep Operation (other than PLL), when PCLK0 = PCLK1 =
PCLK2 = HCLK/2
Parameter
Symbol
Pin
Name
Conditions
Frequency*4
(MHz)
Value
Unit
Remarks
Typ*1
Max*2
Power
supply
current
ICCS
VCC
Sleep *6
operation
(built-in
High-speed CR)
4 MHz
56
126
mA
*3
When all peripheral
clocks are ON
GDC clock 160 MHz
2
72
mA
*3
When all peripheral
clocks are OFF
Sleep *5,*6
operation
(Sub oscillation)
32 kHz
0.52
69.65
mA
*3
When all peripheral
clocks are ON
0.51
69.65
mA
*3
When all peripheral
clocks are OFF
Sleep *6
operation
(built-in
Low-speed CR)
100 kHz
0.54
70.65
mA
*3
When all peripheral
clocks are ON
0.52
69.65
mA
*3
When all peripheral
clocks are OFF
*1: TA=+25°C, VCC=3.3 V
*2: TJ=+125°C, VCC=3.6 V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2
*5: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit)
*6: Data access is nothing to VFLASH memory
Document Number: 002-05038 Rev.*C Page 84 of 183
S6E2DH Series
Table 12-9 Typical and Maximum Current Consumption in Stop Mode, Timer Mode and RTC Mode
Parameter
Symbol
Pin
Name
Conditions
Frequency
(MHz)
Value
Unit
Remarks
Typ*1
Max*2
Power
supply
current
ICCH
VCC
Stop mode
-
0.41
2.07
mA
*3, *4
TA=+25°C
-
21.35
mA
*3, *4
TA=+85°C
-
30.57
mA
*3, *4
TA=+105°C
ICCT
Timer mode
(built-in
High-speed CR)
4 MHz
1.14
2.8
mA
*3, *4
TA=+25°C
-
22.08
mA
*3, *4
TA=+85°C
-
31.3
mA
*3, *4
TA=+105°C
Timer mode *5
(Sub oscillation)
32 kHz
0.43
2.09
mA
*3, *4
TA=+25°C
-
21.37
mA
*3, *4
TA=+85°C
-
30.59
mA
*3, *4
TA=+105°C
Timer mode
(built-in
Low-speed CR)
100 kHz
0.43
2.09
mA
*3, *4
TA=+25°C
-
21.37
mA
*3, *4
TA=+85°C
-
30.59
mA
*3, *4
TA=+105°C
ICCR
RTC mode
(Sub oscillation)
32 kHz
0.41
2.07
mA
*3, *4
TA=+25°C
-
21.35
mA
*3, *4
TA=+85°C
-
30.57
mA
*3, *4
TA=+105°C
*1: VCC=3.3 V
*2: VCC=3.6 V
*3: When all ports are fixed.
*4: When LVD is OFF
*5: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit)
Document Number: 002-05038 Rev.*C Page 85 of 183
S6E2DH Series
Table 12-10 Typical and Maximum Current Consumption in Deep Standby Stop Mode, Deep Standby RTC Mode and VBAT
Parameter
Symbol
Pin
Name
Conditions
Frequency
(MHz)
Value
Unit
Remarks
Typ*1
Max*2
Power
supply
current
ICCHD
VCC
Deep
Standby
Stop mode
(When RAM
is OFF)
-
108
173
μA
*3, *4
TA=+25°C
-
1774
μA
*3, *4
TA=+85°C
-
2208
μA
*3, *4
TA=+105°C
Deep
Standby
Stop mode
(When RAM
is ON)
-
112
177
μA
*3, *4
TA=+25°C
-
1778
μA
*3, *4
TA=+85°C
-
2212
μA
*3, *4
TA=+105°C
ICCRD
Deep
Standby
RTC mode
(When RAM
is OFF)
32 kHz
109
174
μA
*3, *4
TA=+25°C
-
1771
μA
*3, *4
TA=+85°C
-
2205
μA
*3, *4
TA=+105°C
Deep
Standby
RTC mode
(When RAM
is ON)
113
178
μA
*3, *4
TA=+25°C
-
1775
μA
*3, *4
TA=+85°C
-
2209
μA
*3, *4
TA=+105°C
ICCVBAT
VBAT
RTC stop *8
-
0.009
0.032
μA
*3, *4, *5
TA=+25°C
-
0.994
μA
*3, *4, *5
TA=+85°C
-
1.491
μA
*3, *4, *5
TA=+105°C
RTC *6, *8
operation
1.0
1.636
μA
*3, *4
TA=+25°C
-
2.828
μA
*3, *4
TA=+85°C
-
4.242
μA
*3, *4
TA=+105°C
RTC *7, *8
operation
0.7
1.153
μA
*3, *4
TA=+25°C
-
2.277
μA
*3, *4
TA=+85°C
-
3.416
μA
*3, *4
TA=+105°C
*1: VCC=3.3 V
*2: VCC=3.6 V
*3: When all ports are fixed.
*4: When LVD is OFF
*5: When sub oscillation is OFF
*6: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit)
When the Standard setting (CCS/CCB=11001110)
*7: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit)
When the low power setting (CCS/CCB=00000100)
*8: In the case of setting RTC after VCC power on
Document Number: 002-05038 Rev.*C Page 86 of 183
S6E2DH Series
Table 12-11 Typical and Maximum Current Consumption in Low-voltage Detection Circuit, Main Flash Memory Write/erase,
VFLASH Memory (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin
name
Conditions
Value
Unit
Remarks
Min
Typ
Max
Low-voltage
detection
circuit (LVD)
power supply
current
ICCLVD
VCC
At operation
-
4
7
μA
For occurrence of
interrupt
Main flash
memory
write/erase
current
ICCFLASH
At Write/Erase
-
13.4
15.8
mA
VFLASH
memory
Standby current
ICCVFLASH
At Standby
-
15
35
μA
VFLASH
memory
Read current
At Read
-
9
14
mA
40MHz
13
20
80MHz
VFLASH
memory
write/erase
current
At Write/Erase
-
20
25
mA
Peripheral Current Dissipation
Clock
system
Peripheral
Unit
Frequency (MHz)
Unit
Remarks
40
80
160
HCLK
GPIO
All ports
0.30
0.60
1.19
mA
TA=+25°C,
VCC=3.3 V
DMAC
-
0.99
1.95
3.82
DSTC
-
0.41
0.83
1.61
External bus I/F
-
0.18
0.35
0.70
SD card I/F
-
0.52
1.02
2.03
CAN-FD
1ch.
0.54
1.07
2.13
USB
1ch.
0.47
0.93
1.85
I2S
1 unit
0.36
0.71
1.42
Programmable CRC
-
0.04
0.09
0.18
PCLK1
Base timer
4ch.
0.20
0.39
0.76
mA
TA=+25°C,
VCC=3.3 V
Multi-functional
timer/PPG
1unit/4ch.
0.61
1.21
2.40
Quadrature
position/Revolution
counter
1ch.
0.04
0.09
0.18
A/DC
1 unit
0.25
0.50
1.00
PCLK2
Multi-function serial
1ch.
0.44
0.88
-
mA
TA=+25°C,
VCC=3.3 V
GECLK
GDC
unit
GDC
1 unit
31
57
109
mA
TA=+25°C,
VCC=3.3 V
High-Speed Quad SPI
1ch.
1.1
2.3
-
HyperBus I/F
1 unit
0.6
1.2
-
SDRAM-IF
1ch.
2.3
4.6
-
Document Number: 002-05038 Rev.*C Page 87 of 183
S6E2DH Series
12.3.2 Pin Characteristics (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Typ
Max
H level input
voltage
(hysteresis
input)
VIHS
CMOS hysteresis
input pin, MD0, MD1
-
VCC×0.8
-
VCC + 0.3
V
5 V tolerant input
pin
-
VCC×0.8
-
VSS + 5.5
V
Input pin doubled as
I2C Fm+
-
VCC×0.7
-
VSS + 5.5
V
TTL Schmitt
input pin
-
2.0
-
VCC+0.3
V
L level input
voltage
(hysteresis
input)
VILS
CMOS hysteresis
input pin, MD0, MD1
-
VSS - 0.3
-
VCC×0.2
V
5 V tolerant input
pin
-
VSS - 0.3
-
VCC×0.2
V
Input pin doubled as
I2C Fm+
-
VSS
-
VCC×0.3
V
TTL Schmitt
input pin
-
VSS - 0.3
-
0.8
V
H level output
voltage
VOH
2 mA type
IOH = - 2 mA
VCC - 0.5
-
VCC
V
4 mA type
IOH = - 4 mA
VCC - 0.5
-
VCC
V
8 mA type
IOH = - 8 mA
VCC - 0.5
-
VCC
V
11 mA type
IOH = - 11 mA
VCC - 0.5
-
VCC
V
High-spee
d IO
The pin
doubled as USB I/O
IOH = - 13.0 mA
VCC - 0.4
-
VCC
V
The pin doubled as
I2C Fm+
IOH = - 3 mA
VCC - 0.5
-
VCC
V
At GPIO
L level output
voltage
VOL
2 mA type
IOL = 2 mA
VSS
-
0.4
V
4 mA type
IOL = 4 mA
VSS
-
0.4
V
8 mA type
IOL = 8 mA
VSS
-
0.4
V
11 mA type
IOL = 11 mA
VSS
-
0.4
V
The pin doubled as
USB I/O
IOL = 10.5 mA
VSS
-
0.4
V
The pin doubled as
I2C Fm+
IOL = 3 mA
VSS
-
0.4
V
At GPIO
IOL = 20 mA
At I2C Fm+
Input leak
current
IIL
-
-
- 5
-
+ 5
μA
Pull-up resistor
value
RPU
Pull-up pin
-
30
80
200
kΩ
-
15
33
70
High-spee
d IO
Input
capacitance
CIN
Other than VCC,
VBAT, VSS,
AVCC, AVSS,
AVRH
-
-
5
15
pF
Document Number: 002-05038 Rev.*C Page 88 of 183
S6E2DH Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin
Name
Conditions
Value
Unit
Remarks
Min
Max
Input frequency
fCH
X0,
X1
-
4
20
MHz
When crystal oscillator is
connected
-
4
20
MHz
When using external clock
Input clock cycle
tCYLH
-
50
250
ns
When using external clock
Input clock pulse width
-
PWH/tCYLH,
PWL/tCYLH
45
55
%
When using external clock
Input clock rising time
and falling time
tCF,
tCR
-
-
5
ns
When using external clock
Internal operating clock*1
frequency
fCM
-
-
-
160
MHz
Master clock
fCC
-
-
-
160
MHz
Base clock (HCLK/FCLK)
fCP0
-
-
-
80
MHz
APB0 bus clock*2
fCP1
-
-
-
160
MHz
APB1 bus clock*2
fCP2
-
-
-
80
MHz
APB2 bus clock*2
Internal operating clock*1
cycle time
tCYCC
-
-
5
-
ns
Base clock (HCLK/FCLK)
tCYCP0
-
-
10
-
ns
APB0 bus clock*2
tCYCP1
-
-
5
-
ns
APB1 bus clock*2
tCYCP2
-
-
10
-
ns
APB2 bus clock*2
*1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM4 Family Peripheral
Manual Main part (002-04856).
*2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet.
X0
Document Number: 002-05038 Rev.*C Page 89 of 183
S6E2DH Series
12.4.2 Sub Clock Input Characteristics (VBAT = 1.65V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin
Name
Conditions
Value
Unit
Remarks
Min
Typ
Max
Input frequency
1/tCYLL
X0A,
X1A
-
-
32.768
-
kHz
When crystal
oscillator is
connected *
-
32
-
100
kHz
When using external
clock
Input clock cycle
tCYLL
-
10
-
31.25
μs
When using external
clock
Input clock pulse width
-
PWH/tCYLL,
PWL/tCYLL
45
-
55
%
When using external
clock
*: For more information about crystal oscillator, see Sub crystal oscillator in 9. Handling Devices.
12.4.3 Built-in CR Oscillation Characteristics
Built-in High-speed CR (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Conditions
Value
Unit
Remarks
Min
Typ
Max
Clock frequency
fCRH
TJ = - 20 °C to + 105 °C
3.92
4
4.08
MHz
When trimming *1
TJ = - 40 °C to + 125 °C
3.88
4
4.12
TJ = - 40 °C to + 125 °C
2.9
4
5
When not
trimming
Frequency
stabilization
time
tCRWT
-
-
-
30
μs
*2
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming.
*2: This is the time to stabilize the frequency of High-speed CR clock after setting trimming value.
This period is able to use High-speed CR clock as source clock.
Built-in Low-speed CR (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Condition
Value
Unit
Remarks
Min
Typ
Max
Clock frequency
fCRL
-
50
100
150
kHz
0.8 × VBAT
t
CYLL
0.8 × VBAT
0.2 × VBAT
0.2 × VBAT
0.8 × VBAT
P
WL
P
WH
X0A
Document Number: 002-05038 Rev.*C Page 90 of 183
S6E2DH Series
12.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL)
(VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Value
Unit
Remarks
Min
Typ
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
fPLLI
4
-
16
MHz
PLL multiplication rate
-
13
-
100
multiplier
PLL macro oscillation clock frequency
fPLLO
200
-
400
MHz
Main PLL clock frequency*2
fCLKPLL
-
-
200
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main part
(002-04856).
12.4.5 Operating Conditions of USB/I2S/GDC PLL (In the Case of Using Main Clock for Input Clock of PLL)
(VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Value
Unit
Remarks
Min
Typ
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
fPLLI
4
-
16
MHz
PLL multiplication rate
-
13
-
100
multiplier
PLL macro oscillation clock frequency
fPLLO
200
-
400
MHz
USB/GDC
384
MHz
I2S
USB clock frequency *2
fCLKPLL
-
-
50
MHz
After the M
frequency division
I2S clock frequency *3
fCLKPLL
-
-
12.288
MHz
After the M
frequency division
GDC clock frequency *4
fCLKPLL
-
-
160
MHz
After divided by
GDC part
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about USB clock, see Chapter 2-2: USB Clock Generation in FM4 Family Peripheral Manual
Communication Macro part (002-04862).
*3: For more information about I2S clock, see Chapter 7-1: I2S Clock Generation in FM4 Family Peripheral Manual
Communication Macro part (002-04862).
*4: For more information about GDC clock, see FM4 Family Peripheral Manual GDC part (002-04917).
Document Number: 002-05038 Rev.*C Page 91 of 183
S6E2DH Series
12.4.6 Operating Conditions of Main PLL (In the Case of Using Built-in High-Speed CR Clock for Input Clock of Main PLL)
(VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Value
Unit
Remarks
Min
Typ
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
fPLLI
3.8
4
4.2
MHz
PLL multiplication rate
-
50
-
95
multiplier
PLL macro oscillation clock frequency
fPLLO
190
-
400
MHz
Main PLL clock frequency*2
fCLKPLL
-
-
160
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral
Manual Main part (002-04856).
Note:
− The High-speed CR clock (CLKHC) should be set with frequency/temperature trimming to act as the
source clock of the Main PLL.
12.4.7 Reset Input Characteristics (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin
Name
conditions
Value
Unit
Remarks
Min
Max
Reset input time
tINITX
INITX
-
500
-
ns
Document Number: 002-05038 Rev.*C Page 92 of 183
S6E2DH Series
12.4.8 Power-on Reset Timing (VSS = 0V)
Parameter
Symbol
Pin
Name
Conditions
Value
Unit
Remarks
Min
Typ
Max
Power supply shut down time
tOFF
VCC
-
1
-
-
ms
*1
Power ramp rate
dV/dt
VCC: 0.2V to 2.70V
0.6
-
1000
mV/µs
*2
Time until releasing Power-on reset
tPRT
-
0.33
-
0.60
ms
*1: VCC must be held below 0.2V for a minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>1ms).
Note:
− If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 7.
Glossary
VDH: detection voltage of Low Voltage detection reset. See “12.7.Low-Voltage Detection Characteristics”.
12.4.9 GPIO Output Characteristics (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin
Name
Conditions
Value
Unit
Remarks
Min
Max
Output frequency
tPCYCLE
Pxx*
-
-
32
MHz
*: GPIO is a target.
Pxx
tPCYCLE
VDH
tPRT
Internal RST
VCC
CPU Operation start
RST Active release
0.2V 0.2V
tOFF
dV/dt
0.2V
2.7V
Document Number: 002-05038 Rev.*C Page 93 of 183
S6E2DH Series
12.4.10 External Bus Timing
External Bus Clock Output Characteristics (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Max
Output frequency
tCYCLE
MCLKOUT*1
-
50*2
MHz
*1: The external bus clock (MCLKOUT) is a divided clock of HCLK.
For more information about setting of clock divider, see Chapter 14: External Bus Interface in FM4 Family Peripheral
Manual Main part (002-04856).
*2: Generate MCLKOUT at setting more than 4 divisions when the AHB bus clock exceeds 100 MHz.
External Bus Signal Input/output Characteristics (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Conditions
Value
Unit
Remarks
Signal input characteristics
VIH
-
0.8 × VCC
V
VIL
0.2 × VCC
V
Signal output characteristics
VOH
0.8 × VCC
V
VOL
0.2 × VCC
V
0.8 × Vcc0.8 × Vcc
tCYCLE
VIH
VIL VIL
VIH
VOH
VOL VOL
VOH
MCLKOUT
Input signal
Output signal
Document Number: 002-05038 Rev.*C Page 94 of 183
S6E2DH Series
Separate Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Remarks
Min
Max
MOEX
Mininum pulse width
tOEW
MOEX
-
MCLK×n-3
-
ns
MCSX↓→Address
output delay time
tCSL – AV
MCSX,
MAD[24:0]
-
-9
+9
ns
MOEX↑→Address
hold time
tOEH - AX
MOEX,
MAD[24:0]
-
0
MCLK×m+9
ns
MCSX↓→
MOEX↓delay time
tCSL - OEL
MOEX,
MCSX
-
MCLK×m-9
MCLK×m+9
ns
MOEX↑→
MCSX↑time
tOEH - CSH
-
0
MCLK×m+9
ns
MCSX↓→
MDQM↓delay time
tCSL - RDQML
MCSX,
MDQM[1:0]
-
MCLK×m-9
MCLK×m+9
ns
Data setup→
MOEX↑time
tDS - OE
MOEX,
MADATA[15:0]
-
20
-
ns
MOEX↑→
Data hold time
tDH - OE
MOEX,
MADATA[15:0]
-
0
-
ns
MWEX
Mininum pulse width
tWEW
MWEX
-
MCLK×n-3
-
ns
MWEX↑→Address
output delay time
tWEH - AX
MWEX,
MAD[24:0]
-
0
MCLK×m+9
ns
MCSX↓→
MWEX↓delay time
tCSL - WEL
MWEX,
MCSX
-
MCLK×n-9
MCLK×n+9
ns
MWEX↑→
MCSX↑delay time
tWEH - CSH
-
0
MCLK×m+9
ns
MCSX↓→
MDQM↓delay time
tCSL-WDQML
MCSX,
MDQM[1:0]
-
MCLK×n-9
MCLK×n+9
ns
MCSX↓→
Data output time
tCSL-DX
MCSX,
MADATA[15:0]
-
MCLK-9
MCLK+9
ns
MWEX↑→
Data hold time
tWEH - DX
MWEX,
MADATA[15:0]
-
0
MCLK×m+9
ns
Note:
− When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16)
Document Number: 002-05038 Rev.*C Page 95 of 183
S6E2DH Series
Invalid
Address
tCSL-OEL
tCSL-AV
RD
Address
WD
tDH-OE
tDS-OE tWEH-DX
tOEW
tOEH-AX
tOEH-CSH
tWEW
tCYCLE
tCSL-WEL
tCSL-AV
tWEH-CSH
tWEH-AX
tCSL-WDQML
tCSL-RDQML
tCSL-DX
MCLK
MCSX
MAD[24:0]
MDQM[1:0]
MWEX
MADATA[15:0]
MOEX
Document Number: 002-05038 Rev.*C Page 96 of 183
S6E2DH Series
Separate Bus Access Synchronous SRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Max
Address delay time
tAV
MCLK,
MAD[24:0]
-
1
9
ns
MCSX delay time
tCSL
MCLK,
MCSX
-
1
9
ns
tCSH
-
1
9
ns
MOEX delay time
tREL
MCLK,
MOEX
-
1
9
ns
tREH
-
1
9
ns
Data set up
→MCLK↑ time
tDS
MCLK,
MADATA[15:0]
-
19
-
ns
MCLK↑→
Data hold time
tDH
MCLK,
MADATA[15:0]
-
0
-
ns
MWEX delay time
tWEL
MCLK,
MWEX
-
1
9
ns
tWEH
-
1
9
ns
MDQM[1:0]
delay time
tDQML
MCLK,
MDQM[1:0]
-
1
9
ns
tDQMH
-
1
9
ns
MCLK↑→
Data output time
tODS
MCLK,
MADATA[15:0]
-
MCLK+1
MCLK+18
ns
MCLK↑→
Data hold time
tOD
MCLK,
MADATA[15:0]
-
1
18
ns
Note:
− When the external load capacitance CL = 30 pF
Invalid
tDQML
tREH
Address
tCSL
tAV
tREL
RD
Address
WD
tDQMH
tWEH
tWEL
tDH
tDS tOD
tAV
tCSH
tCYCLE
tDQML tDQMH
tODS
MCLK
MCSX
MAD[24:0]
MOEX
MWEX
MADATA[15:0]
MDQM[1:0]
Document Number: 002-05038 Rev.*C Page 97 of 183
S6E2DH Series
Multiplexed Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Max
Multiplexed
address delay time
tALE-CHMADV
MALE,
MAD[24:0]
-
0
10
ns
Multiplexed address
hold time
tCHMADH
-
MCLK×n+0
MCLK×n+10
ns
Note:
− When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16)
MCLK
MCSX
MALE
MOEX
MWEX
MADATA[15:0]
MAD [24:0]
MDQM [1:0]
Document Number: 002-05038 Rev.*C Page 98 of 183
S6E2DH Series
Multiplexed Bus Access Synchronous SRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Max
MALE delay time
tCHAL
MCLK,
MALE
-
1
9
ns
tCHAH
-
1
9
ns
MCLK↑→Multiplexed
address delay time
tCHMADV
MCLK,
MADATA[15:0]
-
1
tOD
ns
MCLK↑→Multiplexed
data output time
tCHMADX
-
1
tOD
ns
Note:
− When the external load capacitance CL = 30 pF
MCLK
MCSX
MALE
MOEX
MWEX
MADATA[15:0]
MAD [24:0]
MDQM [1:0]
Document Number: 002-05038 Rev.*C Page 99 of 183
S6E2DH Series
NAND Flash Mode (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Max
MNREX
Min pulse width
tNREW
MNREX
-
MCLK×n-3
-
ns
Data set up
→MNREX↑time
tDS – NRE
MNREX,
MADATA[15:0]
-
20
-
ns
MNREX↑→
Data hold time
tDH – NRE
MNREX,
MADATA[15:0]
-
0
-
ns
MNALE↑→
MNWEX delay time
tALEH - NWEL
MNALE,
MNWEX
-
MCLK×m-9
MCLK×m+9
ns
MNALE↓→
MNWEX delay time
tALEL - NWEL
MNALE,
MNWEX
-
MCLK×m-9
MCLK×m+9
ns
MNCLE↑→
MNWEX delay time
tCLEH - NWEL
MNCLE,
MNWEX
-
MCLK×m-9
MCLK×m+9
ns
MNWEX↑→
MNCLE delay time
tNWEH - CLEL
MNCLE,
MNWEX
-
0
MCLK×m+9
ns
MNWEX
Min pulse width
tNWEW
MNWEX
-
MCLK×n-3
-
ns
MNWEX↓→
Data output time
tNWEL – DV
MNWEX,
MADATA[15:0]
-
-9
9
ns
MNWEX↑→
Data hold time
tNWEH – DX
MNWEX,
MADATA[15:0]
-
0
MCLK×m+9
ns
Note:
− When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16)
NAND Flash Read
MCLK
MNREX
MADATA[15:0]
Read
Document Number: 002-05038 Rev.*C Page 100 of 183
S6E2DH Series
NAND Flash Address Write
NAND Flash Command Write
MCLK
MNALE
MNCLE
MADATA[15:0]
MNWEX
Write
Write
MCLK
MNALE
MNCLE
MADATA[15:0]
MNWEX
Document Number: 002-05038 Rev.*C Page 101 of 183
S6E2DH Series
External Ready Input Timing (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Max
MCLK↑
MRDY input
setup time
tRDYI
MCLK,
MRDY
-
19
-
ns
When RDY is input
When RDY is released
······
2 cycles
tRDYI
0.5×VCC
··
·
Over 2cycles
t
RDYI
MCLK
Original
MOEX
MWEX
MRDY
MCLK
Extended
MOEX
MWEX
MRDY
Document Number: 002-05038 Rev.*C Page 102 of 183
S6E2DH Series
SDRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Value
Unit
Unit
Remarks
Min
Max
Output frequency
tCYCSD
MSDCLK
-
-
50
MHz
Address delay time
tAOSD
MSDCLK,
MAD[15:0]
-
2
12
ns
MSDCLK↑→
Data output delay time
tDOSD
MSDCLK,
MADATA[15:0]
-
2
12
ns
MSDCLK↑→
Data output Hi-Z time
tDOZSD
MSDCLK,
MADATA[15:0]
-
2
19.5
ns
MDQM[1:0] delay time
tWROSD
MSDCLK,
MDQM[1:0]
-
1
12
ns
MCSX delay time
tMCSSD
MSDCLK,
MCSX8
-
2
12
ns
MRASX delay time
tRASSD
MSDCLK,
MRASX
-
2
12
ns
MCASX delay time
tCASSD
MSDCLK,
MCASX
-
2
12
ns
MSDWEX delay time
tMWESD
MSDCLK,
MSDWEX
-
2
12
ns
MSDCKE delay time
tCKESD
MSDCLK,
MSDCKE
-
2
12
ns
Data setup time
tDSSD
MSDCLK,
MADATA[15:0]
-
19
-
ns
Data hold time
tDHSD
MSDCLK,
MADATA[15:0]
-
0
-
ns
Note:
− When the external load capacitance CL = 30 pF
Document Number: 002-05038 Rev.*C Page 103 of 183
S6E2DH Series
RD
WD
MSDCLK
MDQM[1:0]
MCSX
MRASX
MCASX
MSDWEX
MSDCKE
MADATA[15:0]
Address
MADATA[15:0]
MAD[24:0]
tCYCSD
tAOSD
tWROSD
tMCSSD
tRASSD
tCASSD
tMWESD
tCKESD
tDOSD tDOZSD
tDSSD tDHSD
SDRAM Access
Document Number: 002-05038 Rev.*C Page 104 of 183
S6E2DH Series
12.4.11 Base Timer Input Timing
Timer Input Timing (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Cond
itions
Value
Unit
Remarks
Min
Max
Input pulse width
tTIWH, tTIWL
TIOAn/TIOBn
(when using as ECK, TIN)
-
2tCYCP
-
ns
Trigger Input Timing (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Cond
itions
Value
Unit
Remarks
Min
Max
Input pulse width
tTRGH, tTRGL
TIOAn/TIOBn
(when using as TGIN)
-
2tCYCP
-
ns
Note:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see 8. Block Diagram in this data sheet.
tTIWH
VIHS VIHS VILS VILS
tTIWL
tTRGH
VIHS VIHS VILS VILS
tTRGL
ECK
TIN
TGIN
Document Number: 002-05038 Rev.*C Page 105 of 183
S6E2DH Series
12.4.12 CSIO Timing
Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin
Name
Conditions
Value
Unit
Min
Max
Baud rate
-
-
-
8
Mbps
Serial clock cycle time
tSCYC
SCKx
Internal shift clock
operation
4tCYCP
-
ns
SCK↓→SOT delay time
tSLOVI
SCKx,
SOTx
- 30
+ 30
ns
SIN→SCK↑
setup time
tIVSHI
SCKx,
SINx
50
-
ns
SCK↑→SIN hold time
tSHIXI
SCKx,
SINx
0
-
ns
Serial clock L pulse width
tSLSH
SCKx
External shift
clock
operation
2tCYCP - 10
-
ns
Serial clock H pulse width
tSHSL
SCKx
tCYCP + 10
-
ns
SCK↓→SOT delay time
tSLOVE
SCKx,
SOTx
-
50
ns
SIN→SCK↑
setup time
tIVSHE
SCKx,
SINx
10
-
ns
SCK↑→SIN hold time
tSHIXE
SCKx,
SINx
20
-
ns
SCK falling time
tF
SCKx
-
5
ns
SCK rising time
tR
SCKx
-
5
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet.
− These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
− When the external load capacitance CL = 30 pF.
Document Number: 002-05038 Rev.*C Page 106 of 183
S6E2DH Series
MS bit = 0
MS bit = 1
tSCYC
VOH
VOH
VOL
VOL
VOL
VIH
VIL
VIH
VIL
tSLOVI
tIVSHI tSHIXI
t
SLSH
t
SHSL
V
IH
t
F
tR
V
IH
V
OH
V
IH
V
IL
V
IL
V
OL
V
IH
V
IL
V
IH
V
IL
t
SLOVE
t
IVSHE
t
SHIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-05038 Rev.*C Page 107 of 183
S6E2DH Series
Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin
Name
Conditions
Value
Unit
Min
Max
Baud rate
-
-
-
-
8
Mbps
Serial clock cycle time
tSCYC
SCKx
Internal shift
clock operation
4tCYCP
-
ns
SCK↑→SOT delay time
tSHOVI
SCKx,
SOTx
- 30
+ 30
ns
SIN→SCK↓ setup time
tIVSLI
SCKx,
SINx
50
-
ns
SCK↓→SIN hold time
tSLIXI
SCKx,
SINx
0
-
ns
Serial clock L pulse width
tSLSH
SCKx
External shift
clock operation
2tCYCP - 10
-
ns
Serial clock H pulse width
tSHSL
SCKx
tCYCP + 10
-
ns
SCK↑→SOT delay time
tSHOVE
SCKx,
SOTx
-
50
ns
SIN→SCK↓ setup time
tIVSLE
SCKx,
SINx
10
-
ns
SCK↓→SIN hold time
tSLIXE
SCKx,
SINx
20
-
ns
SCK falling time
tF
SCKx
-
5
ns
SCK rising time
tR
SCKx
-
5
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet.
− These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
− When the external load capacitance CL = 30 pF.
Document Number: 002-05038 Rev.*C Page 108 of 183
S6E2DH Series
MS bit = 0
MS bit = 1
tSCYC
VOH VOH
VOH
VOL
VOL
VIH
VIL
VIH
VIL
tSHOVI
tIVSLI tSLIXI
t
SHSL
t
SLSH
V
IH
tF
tR
V
IH
V
OH
V
IL
V
IL
V
IL
V
OL
V
IH
V
IL
V
IH
V
IL
t
SHOVE
t
IVSLE
t
SLIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-05038 Rev.*C Page 109 of 183
S6E2DH Series
Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin
Name
Conditions
Value
Unit
Min
Max
Baud rate
-
-
-
-
8
Mbps
Serial clock cycle time
tSCYC
SCKx
Internal shift clock
operation
4tCYCP
-
ns
SCK↑→SOT delay time
tSHOVI
SCKx,
SOTx
- 30
+ 30
ns
SIN→SCK↓
setup time
tIVSLI
SCKx,
SINx
50
-
ns
SCK↓→SIN hold time
tSLIXI
SCKx,
SINx
0
-
ns
SOT→SCK↓ delay time
tSOVLI
SCKx,
SOTx
2tCYCP - 30
-
ns
Serial clock L pulse width
tSLSH
SCKx
External shift clock
operation
2tCYCP - 10
-
ns
Serial clock H pulse width
tSHSL
SCKx
tCYCP + 10
-
ns
SCK↑→SOT delay time
tSHOVE
SCKx,
SOTx
-
50
ns
SIN→SCK↓
setup time
tIVSLE
SCKx,
SINx
10
-
ns
SCK↓→SIN hold time
tSLIXE
SCKx,
SINx
20
-
ns
SCK falling time
tF
SCKx
-
5
ns
SCK rising time
tR
SCKx
-
5
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet.
− These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
− When the external load capacitance CL = 30 pF.
Document Number: 002-05038 Rev.*C Page 110 of 183
S6E2DH Series
MS bit = 0
MS bit = 1
*: Changes when writing to TDR register
tSOVLI
tSCYC
tSHOVI
VOL VOL
VOH
VOH
VOL VOH
VOL
VIH
VIL VIH
VIL
tIVSLI tSLIXI
tF
tR
t
SLSH
t
SHSL
t
SHOVE
V
IL
V
IL
V
IH
V
IH
V
IH
V
OH
*
V
OL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
t
IVSLE
t
SLIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-05038 Rev.*C Page 111 of 183
S6E2DH Series
Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Min
Max
Baud rate
-
-
-
-
8
Mbps
Serial clock cycle time
tSCYC
SCKx
Internal shift clock
operation
4tCYCP
-
ns
SCK↓→SOT delay time
tSLOVI
SCKx,
SOTx
- 30
+ 30
ns
SIN→SCK↑ setup time
tIVSHI
SCKx,
SINx
50
-
ns
SCK↑→SIN hold time
tSHIXI
SCKx,
SINx
0
-
ns
SOT→SCK↑ delay time
tSOVHI
SCKx,
SOTx
2tCYCP - 30
-
ns
Serial clock L pulse width
tSLSH
SCKx
External shift clock
operation
2tCYCP - 10
-
ns
Serial clock H pulse width
tSHSL
SCKx
tCYCP + 10
-
ns
SCK↓→SOT delay time
tSLOVE
SCKx,
SOTx
-
50
ns
SIN→SCK↑ setup time
tIVSHE
SCKx,
SINx
10
-
ns
SCK↑→SIN hold time
tSHIXE
SCKx,
SINx
20
-
ns
SCK falling time
tF
SCKx
-
5
ns
SCK rising time
tR
SCKx
-
5
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet.
− These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
− When the external load capacitance CL = 30 pF.
Document Number: 002-05038 Rev.*C Page 112 of 183
S6E2DH Series
MS bit = 0
MS bit = 1
tSCYC
tSLOVI
VOL
VOH VOH
VOH
VOL VOH
VOL
VIH
VIL VIH
VIL
tIVSHI tSHIXI
tSOVHI
t
SHSL
tR
t
SLSH
tF
t
SLOVE
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
OH
V
OL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
t
IVSHE
t
SHIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-05038 Rev.*C Page 113 of 183
S6E2DH Series
When Using Synchronous Serial Chip Select (SCINV = 0, CSLVL=1) (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Conditions
Value
Unit
Min
Max
SCS↓→SCK↓ setup time
tCSSI
Internal shift clock
operation
(*1)-50
(*1)+0
ns
SCK↑→SCS↑ hold time
tCSHI
(*2)+0
(*2)+50
ns
SCS deselect time
tCSDI
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
ns
SCS↓→SCK↓ setup time
tCSSE
External shift clock
operation
3tCYCP+30
-
ns
SCK↑→SCS↑ hold time
tCSHE
0
-
ns
SCS deselect time
tCSDE
3tCYCP+30
-
ns
SCS↓→SOT delay time
tDSE
-
40
ns
SCS↑→SOT delay time
tDEE
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet.
− About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part
(002-04856).
− When the external load capacitance CL = 30 pF.
Document Number: 002-05038 Rev.*C Page 114 of 183
S6E2DH Series
MS bit = 0
MS bit = 1
tCSSItCSHI
tCSDI
tCSSEtCSHE
tCSDE
tDEE
tDSE
SCS
output
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS input
SCK input
SOT
(SPI=0)
SOT
(SPI=1)
Document Number: 002-05038 Rev.*C Page 115 of 183
S6E2DH Series
When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL=1) (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Conditions
Value
Unit
Min
Max
SCS↓→SCK↑ setup time
tCSSI
Internal shift
clock
operation
(*1)-50
(*1)+0
ns
SCK↓→SCS↑ hold time
tCSHI
(*2)+0
(*2)+50
ns
SCS deselect time
tCSDI
(*3)-50+5tCYCP
(*3)+50+5tCYCP
ns
SCS↓→SCK↑ setup time
tCSSE
External shift
clock
operation
3tCYCP+30
-
ns
SCK↓→SCS↑ hold time
tCSHE
0
-
ns
SCS deselect time
tCSDE
3tCYCP+30
-
ns
SCS↓→SOT delay time
tDSE
-
40
ns
SCS↑→SOT delay time
tDEE
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet.
− About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part
(002-04856).
− When the external load capacitance CL = 30 pF.
Document Number: 002-05038 Rev.*C Page 116 of 183
S6E2DH Series
MS bit = 0
MS bit = 1
tCSSItCSHI
tCSDI
tCSSEtCSHE
tCSDE
tDEE
tDSE
SCK
input
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
SOT
(SPI=0)
SOT
(SPI=1)
SCS
output
SCK
output
Document Number: 002-05038 Rev.*C Page 117 of 183
S6E2DH Series
When Using Synchronous Serial Chip Select (SCINV = 0, CSLVL=0) (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Conditions
Value
Unit
Min
Max
SCS↑→SCK↓ setup time
tCSSI
Internal shift
clock
operation
(*1)-50
(*1)+0
ns
SCK↑→SCS↓ hold time
tCSHI
(*2)+0
(*2)+50
ns
SCS deselect time
tCSDI
(*3)-50+5tCYCP
(*3)+50+5tCYCP
ns
SCS↑→SCK↓ setup time
tCSSE
External shift
clock
operation
3tCYCP+30
-
ns
SCK↑→SCS↓ hold time
tCSHE
0
-
ns
SCS deselect time
tCSDE
3tCYCP+30
-
ns
SCS↑→SOT delay time
tDSE
-
40
ns
SCS↓→SOT delay time
tDEE
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet.
− About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part
(002-04856).
− When the external load capacitance CL = 30 pF.
Document Number: 002-05038 Rev.*C Page 118 of 183
S6E2DH Series
MS bit = 0
MS bit = 1
tCSSItCSHI
tCSDI
tCSSE tCSHE
tCSDE
tDEE
tDSE
SCS
output
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
SCK
input
SOT
(SPI=0)
SOT
(SPI=1)
Document Number: 002-05038 Rev.*C Page 119 of 183
S6E2DH Series
When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL=0) (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Conditions
Value
Unit
Min
Max
SCS↑→SCK↑ setup time
tCSSI
Internal shift clock
operation
(*1)-50
(*1)+0
ns
SCK↓→SCS↓ hold time
tCSHI
(*2)+0
(*2)+50
ns
SCS deselect time
tCSDI
(*3)-50+5tCYCP
(*3)+50+5tCYCP
ns
SCS↑→SCK↑ setup time
tCSSE
External shift clock
operation
3tCYCP+30
-
ns
SCK↓→SCS↓ hold time
tCSHE
0
-
ns
SCS deselect time
tCSDE
3tCYCP+30
-
ns
SCS↑→SOT delay time
tDSE
-
40
ns
SCS↓→SOT delay time
tDEE
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet.
− About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part
(002-04856).
− When the external load capacitance CL = 30 pF.
Document Number: 002-05038 Rev.*C Page 120 of 183
S6E2DH Series
MS bit = 0
MS bit = 1
tCSSItCSHI
tCSDI
tCSSE tCSHE
tCSDE
tDEE
tDSE
SCS
output
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
SCK
input
SOT
(SPI=0)
SOT
(SPI=1)
Document Number: 002-05038 Rev.*C Page 121 of 183
S6E2DH Series
High-Speed Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin
Name
Conditions
Value
Unit
Min
Max
Serial clock cycle time
tSCYC
SCKx
Internal shift clock
operation
4tCYCP
-
ns
SCK↓→SOT delay time
tSLOVI
SCKx,
SOTx
- 10
+ 10
ns
SIN→SCK↑ setup time
tIVSHI
SCKx,
SINx
14
-
ns
12.5*
SCK↑→SIN hold time
tSHIXI
SCKx,
SINx
5
-
ns
Serial clock L pulse width
tSLSH
SCKx
External shift clock
operation
2tCYCP - 5
-
ns
Serial clock H pulse width
tSHSL
SCKx
tCYCP + 10
-
ns
SCK↓→SOT delay time
tSLOVE
SCKx,
SOTx
-
15
ns
SIN→SCK↑ setup time
tIVSHE
SCKx,
SINx
5
-
ns
SCK↑→SIN hold time
tSHIXE
SCKx,
SINx
5
-
ns
SCK falling time
tF
SCKx
-
5
ns
SCK rising time
tR
SCKx
-
5
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet.
− These characteristics only guarantee the following pins.
SIN6_0, SOT6_0, SCK6_0, SCS60_0
− When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 002-05038 Rev.*C Page 122 of 183
S6E2DH Series
MS bit = 0
MS bit = 1
tSCYC
VOH
VOH
VOL
VOL
VOL
VIH
VIL
VIH
VIL
tSLOVI
tIVSHI tSHIXI
t
SLSH
t
SHSL
V
IH
t
F
tR
V
IH
V
OH
V
IH
V
IL
V
IL
V
OL
V
IH
V
IL
V
IH
V
IL
t
SLOVE
t
IVSHE
t
SHIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-05038 Rev.*C Page 123 of 183
S6E2DH Series
High-Speed Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Max
Serial clock cycle time
tSCYC
SCKx
Internal shift clock
operation
4tCYCP
-
ns
SCK↑→SOT delay time
tSHOVI
SCKx,
SOTx
- 10
+ 10
ns
SIN→SCK↓ setup time
tIVSLI
SCKx,
SINx
14
-
ns
12.5*
SCK↓→SIN hold time
tSLIXI
SCKx,
SINx
5
-
ns
Serial clock L pulse width
tSLSH
SCKx
External shift clock
operation
2tCYCP - 5
-
ns
Serial clock H pulse width
tSHSL
SCKx
tCYCP + 10
-
ns
SCK↑→SOT delay time
tSHOVE
SCKx,
SOTx
-
15
ns
SIN→SCK↓ setup time
tIVSLE
SCKx,
SINx
5
-
ns
SCK↓→SIN hold time
tSLIXE
SCKx,
SINx
5
-
ns
SCK falling time
tF
SCKx
-
5
ns
SCK rising time
tR
SCKx
-
5
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet.
− These characteristics only guarantee the following pins.
SIN6_0, SOT6_0, SCK6_0, SCS60_0
− When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 002-05038 Rev.*C Page 124 of 183
S6E2DH Series
MS bit = 0
MS bit = 1
tSCYC
VOH VOH
VOH
VOL
VOL
VIH
VIL
VIH
VIL
tSHOVI
tIVSLI tSLIXI
t
SHSL
t
SLSH
V
IH
tF
tR
V
IH
V
OH
V
IL
V
IL
V
IL
V
OL
V
IH
V
IL
V
IH
V
IL
t
SHOVE
t
IVSLE
t
SLIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-05038 Rev.*C Page 125 of 183
S6E2DH Series
High-Speed Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Max
Serial clock cycle time
tSCYC
SCKx
Internal shift clock
operation
4tCYCP
-
ns
SCK↑→SOT delay time
tSHOVI
SCKx,
SOTx
- 10
+ 10
ns
SIN→SCK↓ setup time
tIVSLI
SCKx,
SINx
14
-
ns
12.5*
SCK↓→SIN hold time
tSLIXI
SCKx,
SINx
5
-
ns
SOT→SCK↓ delay time
tSOVLI
SCKx,
SOTx
2tCYCP - 10
-
ns
Serial clock L pulse width
tSLSH
SCKx
External shift clock
operation
2tCYCP - 5
-
ns
Serial clock H pulse width
tSHSL
SCKx
tCYCP + 10
-
ns
SCK↑→SOT delay time
tSHOVE
SCKx,
SOTx
-
15
ns
SIN→SCK↓ setup time
tIVSLE
SCKx,
SINx
5
-
ns
SCK↓→SIN hold time
tSLIXE
SCKx,
SINx
5
-
ns
SCK falling time
tF
SCKx
-
5
ns
SCK rising time
tR
SCKx
-
5
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet.
− These characteristics only guarantee the following pins.
SIN6_0, SOT6_0, SCK6_0, SCS60_0
− When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 002-05038 Rev.*C Page 126 of 183
S6E2DH Series
MS bit = 0
MS bit = 1
*: Changes when writing to TDR register
tSOVLI
tSCYC
tSHOVI
VOL VOL
VOH
VOH
VOL VOH
VOL
VIH
VIL VIH
VIL
tIVSLI tSLIXI
tF
tR
t
SLSH
t
SHSL
t
SHOVE
V
IL
V
IL
V
IH
V
IH
V
IH
V
OH
*
V
OL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
t
IVSLE
t
SLIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-05038 Rev.*C Page 127 of 183
S6E2DH Series
High-Speed Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Max
Serial clock cycle time
tSCYC
SCKx
Internal shift clock
operation
4tCYCP
-
ns
SCK↓→SOT delay time
tSLOVI
SCKx,
SOTx
- 10
+ 10
ns
SIN→SCK↑ setup time
tIVSHI
SCKx,
SINx
14
-
ns
12.5*
SCK↑→SIN hold time
tSHIXI
SCKx,
SINx
5
-
ns
SOT→SCK↑ delay time
tSOVHI
SCKx,
SOTx
2tCYCP - 10
-
ns
Serial clock L pulse width
tSLSH
SCKx
External shift clock
operation
2tCYCP - 5
-
ns
Serial clock H pulse width
tSHSL
SCKx
tCYCP + 10
-
ns
SCK↓→SOT delay time
tSLOVE
SCKx,
SOTx
-
15
ns
SIN→SCK↑ setup time
tIVSHE
SCKx,
SINx
5
-
ns
SCK↑→SIN hold time
tSHIXE
SCKx,
SINx
5
-
ns
SCK falling time
tF
SCKx
-
5
ns
SCK rising time
tR
SCKx
-
5
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet.
− These characteristics only guarantee the following pins.
SIN6_0, SOT6_0, SCK6_0, SCS60_0
− When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 002-05038 Rev.*C Page 128 of 183
S6E2DH Series
MS bit = 0
MS bit = 1
tSCYC
tSLOVI
VOL
VOH VOH
VOH
VOL VOH
VOL
VIH
VIL VIH
VIL
tIVSHI tSHIXI
tSOVHI
t
SHSL
tR
t
SLSH
tF
t
SLOVE
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
OH
V
OL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
t
IVSHE
t
SHIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-05038 Rev.*C Page 129 of 183
S6E2DH Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL=1) (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Conditions
Value
Unit
Min
Max
SCS↓→SCK↓ setup time
tCSSI
Internal shift
clock operation
(*1)-20
(*1)+0
ns
SCK↑→SCS↑ hold time
tCSHI
(*2)+0
(*2)+20
ns
SCS deselect time
tCSDI
(*3)-20+5tCYCP
(*3)+20+5tCYCP
ns
SCS↓→SCK↓ setup time
tCSSE
External shift
clock operation
3tCYCP+15
-
ns
SCK↑→SCS↑ hold time
tCSHE
0
-
ns
SCS deselect time
tCSDE
3tCYCP+15
-
ns
SCS↓→SOT delay time
tDSE
-
25
ns
SCS↑→SOT delay time
tDEE
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet.
− About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part
(002-04856).
− When the external load capacitance CL = 30 pF.
Document Number: 002-05038 Rev.*C Page 130 of 183
S6E2DH Series
MS bit = 0
MS bit = 1
tCSSItCSHI
tCSDI
tCSSEtCSHE
tCSDE
tDEE
tDSE
SCS
output
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
SCK
input
SOT
(SPI=0)
SOT
(SPI=1)
Document Number: 002-05038 Rev.*C Page 131 of 183
S6E2DH Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 1, CSLVL=1) (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Conditions
Value
Unit
Min
Max
SCS↓→SCK↑ setup time
tCSSI
Internal shift clock
operation
(*1)-20
(*1)+0
ns
SCK↓→SCS↑ hold time
tCSHI
(*2)+0
(*2)+20
ns
SCS deselect time
tCSDI
(*3)-20+5tCYCP
(*3)+20+5tCYCP
ns
SCS↓→SCK↑ setup time
tCSSE
External shift clock
operation
3tCYCP+15
-
ns
SCK↓→SCS↑ hold time
tCSHE
0
-
ns
SCS deselect time
tCSDE
3tCYCP+15
-
ns
SCS↓→SOT delay time
tDSE
-
25
ns
SCS↑→SOT delay time
tDEE
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet.
− About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part
(002-04856).
− When the external load capacitance CL = 30 pF.
Document Number: 002-05038 Rev.*C Page 132 of 183
S6E2DH Series
MS bit = 0
MS bit = 1
tCSSItCSHI
tCSDI
tCSSEtCSHE
tCSDE
tDEE
tDSE
SCS
output
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
intpu
SCK
input
SOT
(SPI=0)
SOT
(SPI=1)
Document Number: 002-05038 Rev.*C Page 133 of 183
S6E2DH Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL=0) (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Conditions
Value
Unit
Min
Max
SCS↑→SCK↓ setup time
tCSSI
Internal shift clock
operation
(*1)-20
(*1)+0
ns
SCK↑→SCS↓ hold time
tCSHI
(*2)+0
(*2)+20
ns
SCS deselect time
tCSDI
(*3)-20+5tCYCP
(*3)+20+5tCYCP
ns
SCS↑→SCK↓ setup time
tCSSE
External shift clock
operation
3tCYCP+15
-
ns
SCK↑→SCS↓ hold time
tCSHE
0
-
ns
SCS deselect time
tCSDE
3tCYCP+15
-
ns
SCS↑→SOT delay time
tDSE
-
25
ns
SCS↓→SOT delay time
tDEE
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet.
− About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part
(002-04856).
− When the external load capacitance CL = 30 pF.
Document Number: 002-05038 Rev.*C Page 134 of 183
S6E2DH Series
MS bit = 0
MS bit = 1
tCSSItCSHI
tCSDI
tCSSE tCSHE
tCSDE
tDEE
tDSE
SCS
output
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
SCK
input
SOT
(SPI=0)
SOT
(SPI=1)
Document Number: 002-05038 Rev.*C Page 135 of 183
S6E2DH Series
When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL=0) (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Conditions
Value
Unit
Min
Max
SCS↑→SCK↑ setup time
tCSSI
Internal shift
clock operation
(*1)-20
(*1)+0
ns
SCK↑→SCS↓ hold time
tCSHI
(*2)+0
(*2)+20
ns
SCS deselect time
tCSDI
(*3)-20+5tCYCP
(*3)+20+5tCYCP
ns
SCS↑→SCK↑ setup time
tCSSE
External shift
clock operation
3tCYCP+15
-
ns
SCK↓→SCS↓ hold time
tCSHE
0
-
ns
SCS deselect time
tCSDE
3tCYCP+15
-
ns
SCS↑→SOT delay time
tDSE
-
40
ns
SCS↓→SOT delay time
tDEE
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet.
− About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part
(002-04856).
− When the external load capacitance CL = 30 pF.
Document Number: 002-05038 Rev.*C Page 136 of 183
S6E2DH Series
MS bit = 0
MS bit = 1
tCSSItCSHI
tCSDI
tCSSE tCSHE
tCSDE
tDEE
tDSE
SCS
output
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
SCK
input
SOT
(SPI=0)
SOT
(SPI=1)
Document Number: 002-05038 Rev.*C Page 137 of 183
S6E2DH Series
External Clock (EXT = 1): when in Asynchronous Mode Only (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Condition
Value
Unit
Remarks
Min
Max
Serial clock L pulse width
tSLSH
CL = 30 pF
tCYCP + 10
-
ns
Serial clock H pulse width
tSHSL
tCYCP + 10
-
ns
SCK falling time
tF
-
5
ns
SCK rising time
tR
-
5
ns
t
SHSL
V
I
L
V
I
L
V
I
L
V
IH
V
IH
V
IH
tR
tF
t
SLSH
SCK
Document Number: 002-05038 Rev.*C Page 138 of 183
S6E2DH Series
12.4.13 External Input Timing (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Max
Input pulse
width
tINH, tINL
ADTG
-
2tCYCP*1
-
ns
A/D converter trigger input
FRCK0
Free-run timer input clock
IC0x
Input capture
DTTI0X
-
2tCYCP*1
-
ns
Waveform generator
INTxx, NMIX
-
2tCYCP +
100(*1)
-
ns
External interrupt,
NMI
500(*2)
-
ns
WKUPx
-
500(*3)
-
ns
Deep standby wake up
(*1): tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in timer mode.
About the APB bus number which the Multi-function Timer and External interrupt are connected to, see 8.
Block Diagram in this data sheet.
(*2): When in Stop mode, in timer mode.
(*3): When in deep standby RTC mode, in deep standby Stop mode.
Document Number: 002-05038 Rev.*C Page 139 of 183
S6E2DH Series
12.4.14 Quadrature Position/Revolution Counter Timing (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Conditions
Value
Unit
Min
Max
AIN pin H width
tAHL
-
2tCYCP*
-
ns
AIN pin L width
tALL
-
BIN pin H width
tBHL
-
BIN pin L width
tBLL
-
BIN rising time from
AIN pin H level
tAUBU
PC_Mode2 or
PC_Mode3
AIN falling time from
BIN pin H level
tBUAD
PC_Mode2 or
PC_Mode3
BIN falling time from
AIN pin L level
tADBD
PC_Mode2 or
PC_Mode3
AIN rising time from
BIN pin L level
tBDAU
PC_Mode2 or
PC_Mode3
AIN rising time from
BIN pin H level
tBUAU
PC_Mode2 or
PC_Mode3
BIN falling time from
AIN pin H level
tAUBD
PC_Mode2 or
PC_Mode3
AIN falling time from
BIN pin L level
tBDAD
PC_Mode2 or
PC_Mode3
BIN rising time from
AIN pin L level
tADBU
PC_Mode2 or
PC_Mode3
ZIN pin H width
tZHL
QCR:CGSC=0
ZIN pin L width
tZLL
QCR:CGSC=0
AIN/BIN rising and falling
time from determined ZIN
level
tZABE
QCR:CGSC=1
Determined ZIN level from
AIN/BIN rising and falling
time
tABEZ
QCR:CGSC=1
*: tCYCP indicates the APB bus clock cycle time except when in Stop mode, in timer mode.
About the APB bus number which Quadrature Position/Revolution Counter is connected to, see 8. Block
Diagram in this data sheet.
AIN
BIN
tAUBU tBUAD tADBD tBDAU
tAHL tALL
tBHL tBLL
Document Number: 002-05038 Rev.*C Page 140 of 183
S6E2DH Series
BIN
tBUAU tAUBD tBDAD tADBU
tBHL tBLL
tAHL tALL
AIN
ZIN
Document Number: 002-05038 Rev.*C Page 141 of 183
S6E2DH Series
ZIN
AIN/BIN
Document Number: 002-05038 Rev.*C Page 142 of 183
S6E2DH Series
12.4.15 I2C Timing
Standard Mode, Fast Mode (VCC = 2.7V to 3.6, VSS = 0V)
Parameter
Symbol
Conditions
Standard Mode
Fast Mode
Unit
Remarks
Min
Max
Min
Max
SCL clock frequency
fSCL
CL = 30 pF,
R = (Vp/IOL)*1
0
100
0
400
kHz
(Repeated) START condition hold
time
SDA ↓ → SCL ↓
tHDSTA
4.0
-
0.6
-
μs
SCL clock L width
tLOW
4.7
-
1.3
-
μs
SCL clock H width
tHIGH
4.0
-
0.6
-
μs
(Repeated) Start condition setup
time
SCL ↑ → SDA ↓
tSUSTA
4.7
-
0.6
-
μs
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
0
3.45*2
0
0.9*3
μs
Data setup time
SDA ↓ ↑ → SCL ↑
tSUDAT
250
-
100
-
ns
STOP condition setup time
SCL ↑ → SDA ↑
tSUSTO
4.0
-
0.6
-
μs
Bus free time between
Stop condition and Start condition
tBUF
4.7
-
1.3
-
μs
Noise filter
tSP
2 MHz ≤
tCYCP＜40 MHz
2 tCYCP*4
-
2
tCYCP*4
-
ns
*5
40 MHz ≤
tCYCP＜60 MHz
4 tCYCP*4
-
4
tCYCP*4
-
ns
60 MHz ≤
tCYCP＜80 MHz
6 tCYCP*4
-
6
tCYCP*4
-
ns
80 MHz ≤
tCYCP ≤ 100
MHz
8 tCYCP*4
-
8
tCYCP*4
-
ns
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates
the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal.
*3: A Fast mode I2C bus device can be used on a Standard mode I2C bus system as long as the device satisfies the
requirement of tSUDAT ≥ 250 ns.
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see 8. Block Diagram in this data sheet.
When the standard mode is used, please set to 2 MHz or more peripheral bus clock.
When fast mode is used, please set to 8MHz or more peripheral bus clock.
*5: The noise filter time can be changed by register settings.
Change the number of the noise filter steps according to APB bus clock frequency.
Document Number: 002-05038 Rev.*C Page 143 of 183
S6E2DH Series
Fast Mode Plus (Fm+) (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Conditions
Fast Mode Plus (Fm+)*6
Unit
Remarks
Min
Max
SCL clock frequency
fSCL
CL = 30 pF,
R = (Vp/IOL)*1
0
1000
kHz
(Repeated) Start condition hold
time
SDA ↓ → SCL ↓
tHDSTA
0.26
-
μs
SCL clock L width
tLOW
0.5
-
μs
SCL clock H width
tHIGH
0.26
-
μs
(Repeated) Start condition setup
time
SCL ↑ → SDA ↓
tSUSTA
0.26
-
μs
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
0
0.45*2, *3
μs
Data setup time
SDA ↓ ↑ → SCL ↑
tSUDAT
50
-
ns
Stop condition setup time
SCL ↑ → SDA ↑
tSUSTO
0.26
-
μs
Bus free time between
Stop condition and Start condition
tBUF
0.5
-
μs
Noise filter
tSP
60 MHz ≤
tCYCP＜80 MHz
6 tCYCP*4
-
ns
*5
80 MHz ≤
tCYCP ≤100 MHz
8 tCYCP*4
-
ns
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates
the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal.
*3: A Fast mode I2C bus device can be used on a Standard mode I2C bus system as long as the device satisfies the
requirement of "tSUDAT ≥ 250 ns".
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see 8. Block Diagram in this data sheet.
To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more.
*5: The noise filter time can be changed by register settings.
Change the number of the noise filter steps according to APB bus clock frequency.
*6: When using fast mode plus (Fm+), set the I/O pin to the mode corresponding to I2C Fm+ in the EPFR register.
See Chapter 12 : I/O Port in "FM4 Family Peripheral Manual Main part (002-04856)" for the details.
SDA
SCL
Document Number: 002-05038 Rev.*C Page 144 of 183
S6E2DH Series
12.4.16 SD Card Interface Timing
Default-Speed Mode
Clock CLK (All values are referred to VIH and VIL) (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Remarks
Min
Max
Clock frequency Data
Transfer Mode
fPP
S_CLK
CCARD ≤ 10
pF
(1 card)
0
25
MHz
Clock frequency
Identification Mode
fOD
S_CLK
0*/100
400
kHz
Clock low time
tWL
S_CLK
10
-
ns
Clock high time
tWH
S_CLK
10
-
ns
Clock rising time
tTLH
S_CLK
-
10
ns
Clock falling time
tTHL
S_CLK
-
10
ns
*: 0 Hz means the clock is stopped. The given minimum frequency range is for cases where a continuous clock is required.
Card Inputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol
Pin Name
Conditions
Value
Remarks
Min
Max
Input setup time
tISU
S_CMD,
S_DATA3:0
CCARD ≤ 10 pF
(1 card)
5
-
ns
Input hold time
tIH
S_CMD,
S_DATA3:0
5
-
ns
Card Outputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol
Pin Name
Conditions
Value
Remarks
Min
Max
Output Delay time during
Data Transfer Mode
tODLY
S_CMD,
S_DATA3:0
CCARD ≤ 40 pF
(1 card)
0
14
ns
Output Delay time during
Identification Mode
tODLY
S_CMD,
S_DATA3:0
0
50
ns
Default-Speed Mode
Notes:
− The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the
Host.
− Please refer to: SD card interface Chapter 15 in FM4 Family Peripheral Manual Main part (002-04856) for Clock frequency
(fPP).
VIL
VIL
tWL
tWH
VIH
VIH
VIH
tTHL
tTLH
tISU
VIH
VIL
VIH
VIL
tIH
VOH
VOL
VOH
VOL
tODLY(Max)
tODLY(Min)
S_CMD,
S_DATA3:0
(Card Output)
S_CMD,
S_DATA3:0
(Card Input)
S_CLK
(SD Clock)
Document Number: 002-05038 Rev.*C Page 145 of 183
S6E2DH Series
High-Speed Mode
Clock CLK (All values are referred to VIH and VIL) (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Remarks
Min
Max
Clock frequency Data
Transfer Mode
fPP
S_CLK
CCARD ≤ 10 pF
(1 card)
0
50
MHz
Clock low time
tWL
S_CLK
7
-
ns
Clock high time
tWH
S_CLK
7
-
ns
Clock rising time
tTLH
S_CLK
-
3
ns
Clock falling time
tTHL
S_CLK
-
3
ns
Card Inputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol
Pin Name
Conditions
Value
Remarks
Min
Max
Input setup time
tISU
S_CMD,
S_DATA3:0
CCARD ≤ 10 pF
(1 card)
6
-
ns
Input hold time
tIH
S_CMD,
S_DATA3:0
2
-
ns
Card Outputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol
Pin Name
Conditions
Value
Remarks
Min
Max
Output Delay time during
Data Transfer Mode
tODLY
S_CMD,
S_DATA3:0
CL ≤ 40 pF
(1 card)
0
14
ns
Output Hold time
tOH
S_CMD,
S_DATA3:0
CL ≥ 15 pF
(1 card)
2.5
-
ns
Total System capacitance for
each line*
CL
-
1 card
-
40
pF
*: In order to satisfy severe timing, host shall drive only one card.
High-Speed Mode
Notes:
− The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this
model is the Host.
− Please refer to: SD card interface Chapter 15 in FM4 Family Peripheral Manual Main part (002-04856) for Clock
frequency (fPP).
VIL
VIL
tWL
tWH
VIH
VIH
VIH
tTHL
tTLH
tISU
VIH
VIL
VIH
VIL
tIH
VOH
VOL
VOH
VOL
tODLY(Max)
tOH(Min)
50%VCC
50%VCC
S_CMD,
S_DATA3:0
(Card Output)
S_CMD,
S_DATA3:0
(Card Input)
S_CLK
(SD Clock)
Document Number: 002-05038 Rev.*C Page 146 of 183
S6E2DH Series
12.4.17 ETM Timing (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Max
Data hold
tETMH
TRACECLK,
TRACED[3:0]
-
2
15
ns
TRACECLK
frequency
1/tTRACE
TRACECLK
-
32
MHz
TRACECLK
clock cycle
tTRACE
-
31.25
-
ns
Note:
− When the external load capacitance CL= 30 pF.
HCLK
TRACECLK
TRACED[3:0]
Document Number: 002-05038 Rev.*C Page 147 of 183
S6E2DH Series
12.4.18 JTAG Timing (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Max
TMS, TDI setup time
tJTAGS
TCK,
TMS, TDI
-
15
-
ns
TMS, TDI hold time
tJTAGH
TCK,
TMS, TDI
-
15
-
ns
TDO delay time
tJTAGD
TCK,
TDO
-
-
45
ns
Note:
− When the external load capacitance CL= 30 pF.
TCK
TMS/TDI
TDO
Document Number: 002-05038 Rev.*C Page 148 of 183
S6E2DH Series
12.4.19 I2S Timing
Master Mode Timing (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Max
Output frequency
tMCYC
I2SCK
-
-
12.288
MHz
Output clock pulse width
tMHW
I2SCK
-
45
55
%
tMLW
45
55
%
I2SCK→I2SWS
delay time
tDFS
I2SCK,
I2SWS
-
0
24.0
ns
I2SCK→I2SDO
delay time*
tDDO
I2SCK,
I2SDO
-
0
24.0
ns
I2SDI→I2SCK
setup time
tHSDI
I2SCK,
I2SDI
-
25.0
-
ns
I2SDI→I2SCK
hold time
tHDI
-
0
-
ns
Input signal rising time
tRI
I2SDI
-
-
5
ns
Input signal falling time
tFI
-
-
5
ns
*: Except for the first bit of transmission frame
Notes:
− When the external load capacitance CL = 20 pF
− When I2SWS=48 kHz, I2MCLK=256
×
I2SWS
Frame synchronization signal (I2SWS) is settable to 48 kHz, 32 kHz, 16 kHz.
See Chapter 7-2: I2S(Inter-IC Sound bus)Interface in FM4 Family Peripheral Manual Communication part (002-04862) for the
details.
Document Number: 002-05038 Rev.*C Page 149 of 183
S6E2DH Series
Note:
− See Chapter 7-2: I2S(Inter-IC Sound bus)Interface in FM4 Family Peripheral Manual Communication part (002-04862) for the
details of CPOL, FSPH, FSLIN, SMPL .
I
2
SDI
0
.
8
×V
CC
0
.
8
×V
CC
0
.
2
×V
CC
0
.
2
×V
CC
0
.
8
×V
CC
t
FI
t
RI
I
2
SCK
(
CPOL
=
0
)
t
MHW
t
MLW
t
MCYC
I
2
SCK
(
CPOL
=
1
)
t
DFS
t
DFS
I
2
SWS
(
FSPH
=
0
,
FSLN
=
0
)
t
t
I
2
SWS
(
FSPH
=
1
,
FSLN
=
0
)
DFS
DFS
DFS
DFS
DFS
DFS
t
I
2
SWS
(
FSPH
=
0
,
FSLN
=
1
)
t
t
t
I
2
SWS
(
FSPH
=
1
,
FSLN
=
1
)
t
DDO
I
2
SDO
I
2
SDI
(
SMPL
=
0
)
t
SDI
t
HDI
t
t
SDI
HDI
SDI
HDI
I
2
SDI
(
SMPL
=
1
)
t
t
Document Number: 002-05038 Rev.*C Page 150 of 183
S6E2DH Series
Slave Mode Timing (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Max
Input frequency
tSCYC
I2SCK
-
-
12.288
MHz
Input clock pulse width
tSHW
I2SCK
-
45
55
%
tSLW
45
55
%
I2SWS→I2SCK
Setup time
tSFI
I2SCK,
I2SWS
-
8
-
ns
I2SWS→I2SCK
Hold time
tHFI
I2SCK,
I2SWS
-
0
-
ns
I2SCK↑→I2SDO
Delay time*1
tDDO
I2SCK, I2SDO
-
0
32
ns
I2SCK↑→I2SDO
Delay Time*2
tDFB1
-
0
32
ns
I2SDI→I2SCK↓
Setup time
tSDI
I2SCK, I2SDI
-
8
-
ns
I2SDI→I2SCK↓
Hold time
tHDI
-
0
-
ns
Input signal rising time
tRI
I2SCK,
I2SWS,I2SDI
-
-
5
ns
Input signal falling time
tFI
-
-
5
ns
*1: Except for the first bit of transmission frame
*2: When FSPH register 1.
Notes:
− When the external load capacitance CL = 20 pF
− When I2SWS=48 kHz, I2MCLK=256
×
I2SWS
Frame synchronization signal (I2SWS) is settable to 48 kHz, 32 kHz, 16 kHz.
See Chapter 7-2: I2S(Inter-IC Sound bus)Interface in FM4 Family Peripheral Manual Communication part (002-04862) for the
details.
Document Number: 002-05038 Rev.*C Page 151 of 183
S6E2DH Series
Notes:
− See Chapter 7-2: I2S(Inter-IC Sound bus)Interface in FM4 Family Peripheral Manual Communication part (002-04862) for the
details of FSPH, FSLN, SMPL
− I2SCK input is selectable polarity by CPOL bit of CNTREG register
I
2
SCK
I
2
SWS
I
2
SDI
0
.
8
×V
CC
0
.
8
×V
CC
0
.
2
×V
CC
0
.
2
×V
CC
0
.
8
×V
CC
t
FI
t
RI
I
2
SCK
(
CPOL
=
0
)
t
SHW
t
SLW
t
SCYC
I
2
SCK
(
CPOL
=
1
)
t
SFI
t
HFI
I
2
SWS
(
FSPH
=
0
,
FSLN
=
0
)
t
t
I
2
SWS
(
FSPH
=
1
,
FSLN
=
0
)
SFI
HFI
SFI
SFI
t
I
2
SWS
(
FSPH
=
0
,
FSLN
=
1
)
I
2
SWS
(
FSPH
=
1
,
FSLN
=
1
)
t
DDO
I
2
SDO
I
2
SDI
(
SMPL
=
0
)
t
SDI
t
HDI
t
SDI
t
HDI
I
2
SDI
(
SMPL
=
1
)
t
SDI
t
HDI
t
t
DFB1
1
Document Number: 002-05038 Rev.*C Page 152 of 183
S6E2DH Series
・I2SMCLK Input Characteristics (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin
Name
Conditions
Value
Unit
Remarks
Min
Max
Input frequency
fCHS
I2SCK
-
-
25
MHz
Input clock cycle
tCYLHS
-
-
40
-
ns
Input clock pulse width
-
-
PWHS/tCYLHS
PWLS/tCYLHS
45
55
%
When using
external clock
Input clock rising time and
falling time
tCFS
tCRS
-
-
-
5
ns
When using
external clock
・I2SMCLK Output Characteristics (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin
Name
Conditions
Value
Unit
Remarks
Min
Max
Input frequency
fCHS
I2SCK
-
-
12.288
MHz
I2SMCLK 0.8×VCC 0.8×VCC
0.2×VCC 0.2×VCC
0.8×VCC
tCFS tCRS
PWHS PWLS
tCYLHS
Document Number: 002-05038 Rev.*C Page 153 of 183
S6E2DH Series
12.4.20 GDC:Panel Output Timing (VCC = 3.0V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Max
Output frequency
tCYCPNGE
PNL_DCLK
-
-
40
MHz
PNL_DCLK↓→PNL_PD[23:0]
Output delay time
tPDOPDGE
PNL_PD[23:0]
-
-4.5
4.5
ns
PNL_DCLK↓→PNL_LH_SYN
C
Output delay time
tHDOPDGE
PNL_LH_SYNC
-
-4.5
4.5
ns
PNL_DCLK↓→PNL_FV_SYN
C Output delay time
tVDOPDGE
PNL_FV_SYNC
-
-4.5
4.5
ns
PNL_DCLK↓→PNL_LE
Output delay time
tLDOPDGE
PNL_LE
-
-4.5
4.5
ns
PNL_DCLK↓→PNL_DEN
Output delay time
tDDOPDGE
PNL_DEN
-
-4.5
4.5
ns
PNL_DCLK↓→PNL_PWE
Output delay time
tPDOPDGE
PNL_PWE
-4.5
4.5
ns
−
PNL_DCLK
PNL_PD[23:0]
tPDOPDGE
tHDOPDGE
PNL_LHSYNC
PNL_FVSYNC
tVDOPDGE
PNL_LE
tLDOPDGE
PNL_DEN
tDDOPDGE
PNL_PWE
tPDOPDGE
tCYCPNGE
Document Number: 002-05038 Rev.*C Page 154 of 183
S6E2DH Series
12.4.21 GDC: SDRAM-IF Timing
(VCC = 3.0V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Value
Unit
Min
Max
Output frequency
tCYCSD
GE_SDCLK
-
80
MHz
Address delay time
tAOSD
GE_SDCLK
GE_SDA[11:0]
1
5
ns
Bank address delay time
tBAOSD
GE_SDCLK
GE_SDBA[1:0]
1
5
ns
GE_SDCLK↑→ Data output delay time
tDOSD
GE_SDCLK
GE_SDDQ[31:0]
1
5
ns
GE_SDCLK↑→ Data output Hi-Z time
tDOZSD
GE_SDCLK
GE_SDDQ[31:0]
1
5
ns
GE_SDDQM[3:0] delay time
tWROSD
GE_SDCLK
GE_SDDQM[3:0]
1
5
ns
GE_SDCSX delay time
tSCSSD
GE_SDCLK
GE_SDCSX
1
5
ns
GE_SDRASX delay time
tRASSD
GE_SDCLK
GE_SDRASX
1
5
ns
GE_SDCASX delay time
tCASSD
GE_SDCLK
GE_SDCASX
1
5
ns
GE_SDWEX delay time
tSWESD
GE_SDCLK
GE_SDWEX
1
5
ns
GE_SDCKE delay time
tCKESD
GE_SDCLK
GE_SDCKE
1
5
ns
Data setup time
tDSSD
GE_SDCLK
GE_SDDQ[31:0]
4
-
ns
Data hold time
tDHSD
GE_SDCLK
GE_SDDQ[31:0]
0
-
ns
Document Number: 002-05038 Rev.*C Page 155 of 183
S6E2DH Series
GE_SDCLK
GE_SDBA[1:0]
GE_SDCSX
GE_SDRASX
GE_SDCASX
GE_SDWEX
GE_SDCKE
GE_SDA[11:0]
Address
Address
GE_SDRASX
RD
GE_SDRASX
WD
tCYCSD
tAOSD
tBAOSD
tDOSD
tDOZSD
tWROSD
tSCSSD
tRASSD
tCASSD
tSWESD
tCKESD
tDSSD
tDHSD
GE_SDDQM[3:0]
Document Number: 002-05038 Rev.*C Page 156 of 183
S6E2DH Series
12.4.22 GDC: High-Speed Quad SPI Timing (VCC = 3.0V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Max
Serial clock
frequency
tSCYCM
GE_SPCK
CL=20 pF
-
80
MHz
Enabled CS→
CLK Starting Time
(mode0/mode2)
tOSLSK02
GE_SPCK,
GE_SPCSX0
1.5×tSCYCM - 4.25
-
ns
Enabled CS→
CLK Starting Time
(mode1/mode3)
tOSLSK13
tSCYCM - 4.25
-
ns
CLK Last→
Disabled CS Time
(mode0/mode2)
tOSKSL02
tSCYCM
-
ns
CLK Last→
Disabled CS Time
(mode1/mode3)
tOSKSL13
1.5×tSCYCM
-
ns
SIO Data output time
tOSDAT
GE_SPCK,
GE_SPDQ0,
GE_SPDQ1,
GE_SPDQ2,
GE_SPDQ3
-1.25
4.25
ns
SIO Setup
tDSSET
4
-
ns
SIO Hold
tSDHOLD
0.5×tSCYCM
-
ns
Note:
− See Chapter 8-3: High-Speed Quad SPI controller in FM4 Family Peripheral Manual Communication part (002-04862) for the
detail of RTM mode.
Document Number: 002-05038 Rev.*C Page 157 of 183
S6E2DH Series
GE_SPCSX0
tOSLSK02
tDSSET
GE_SPCK
mode0
mode2
mode1
mode3
tOSLSK13
tSCYCM
tOSKSL02
tOSKSL13
input
tSDHOLD
output
tOSDAT
GE_SPDQ0,
GE_SPDQ1,
GE_SPDQ2,
GE_SPDQ3
Document Number: 002-05038 Rev.*C Page 158 of 183
S6E2DH Series
12.4.23 GDC: HyperBus I/F Timing
HyperFlash Write (VCC = 3.0V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Max
Hyper Bus clock cycle
tCKCYC
GE_HBCK
CL=30 pF
10
-
ns
CS↑↓→CK↑
Chip Select setup time
tCSS
GE_HBCSX1
GE_HBCSX0
3
-
ns
CS↓→RDS↓
Chip select active to RDS valid(Low)
tDSV
GE_HBRWDS
-
8
ns
DQ → CK↑↓
Input setup time
tIS
GE_HBDQ7-
GE_HBDQ0
0.8
-
ns
CK↑↓→ DQ
Input hold time
tIH
GE_HBDQ7-
GE_HBDQ0
0.8
-
ns
CK↓ → CS↑
Chip select hold time
tCSH
GE_HBCSX1
GE_HBCSX0
0
-
ns
CS↑→ RDS(Hi-z)
Chip select Inactive to RDS High-Z
tDSZ
GE_HBCSX1
GE_HBCSX0
-
7
ns
CS↑ → CS↓
Chip select HIGH between operation
tCSHI
GE_HBCSX1
GE_HBCSX0
8
-
ns
VIH
VOH
tCSS
VOL
VIL
CA0
47-40
CA0
39-32
CA1
31-24
CA1
23-16
CA2
15-8
CA2
7-0
Dn
15-8
Dn
7-0
VOL
tDSV
tCSHI
tIS
tDSZ
VOH
tCSS
tCSH
tIH
tCKCYC
GE_HBCK
GE_HBRWDS
GE_HBDQ7-0
GE_HBCSX0,1
Document Number: 002-05038 Rev.*C Page 159 of 183
S6E2DH Series
HyperFlash Read (VCC = 3.0V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Max
Hyper Bus clock cycle
tRDSCYC
GE_HBCK
CL=30pF
10
-
ns
Read initial Access Time
tACC
GE_HBCK
-
120
ns
CS↑↓→CK↑
Chip Select setup time
tCSS
GE_HBCSX1
GE_HBCSX0
3
-
ns
CS↓ → RDS↓
Chip select active to RDS valid (Low)
tDSV
GE_HBRWDS
-
8
ns
DQ → CK↑↓
Input setup time
tIS
GE_HBDQ7-
GE_HBDQ0
0.8
-
ns
CK↑↓→ DQ
Input hold time
tIH
GE_HBDQ7-
GE_HBDQ0
0.8
-
ns
CK↓ → CS↑
Chip select hold time
tCSH
GE_HBCSX1
GE_HBCSX0
0
-
ns
CS↑ → RDS(Hi-Z)
Chip select Inactive to RDS High-Z
tDSZ
GE_HBRWDS
-
7
ns
CK↑↓ → DQ (Low Z)
Clock to DQs Low Z
tDQLZ
GE_HBDQ7-
GE_HBDQ0
0
-
ns
RDS↑↓→ DQ (valid)
RDS transition to DQ valid
tDSS
GE_HBDQ7-
GE_HBDQ0
-0.8
+0.8
ns
RDS↑↓→ DQ (invalid)
RDS transition to DQ invalid
tDSH
GE_HBDQ7-
GE_HBDQ0
-0.8
+0.8
ns
CS↑→ DQ (Hi-Z)
Chip select Inactive to DQs High-Z
tOZ
GE_HBDQ7-
GE_HBDQ0
-
7
ns
CK↑↓→ RDS↑↓
CK transition to RDS transition
tCKDS
GE_HBRWDS
1
7
ns
CS↑→ CS↓
Chip select HIGH between Operation
tCSHI
GE_HBCSX1
GE_HBCSX0
8
-
ns
VIH
VOH
tCSS
VOL
VIL
CA0
47-40
CA0
39-32
CA1
31-24
CA1
23-16
CA2
15-8
CA2
7-0
Dn
15-8
Dn
7-0
VOL
tDSV
tCSHI
tACC
tIH tDSH
tDQLZ
VOH
VOH
tCSS
tCSH
Dn+1
15-8
Dn+1
7-0
tIS tDSS
tOZ
tDSZ
tCKDS
tRDSCYC
VOH
VOL
GE_HBCSX0,1
GE_HBCK
GE_HBRWDS
GE_HBDQ7-0
Document Number: 002-05038 Rev.*C Page 160 of 183
S6E2DH Series
12.5 12-bit A/D Converter
Electrical Characteristics for the A/D Converter (VCC = AVCC = 2.7V to 3.6V, VSS = AVSS = AVRL = 0V)
Parameter
Symbol
Pin
Name
Value
Unit
Remarks
Min
Typ
Max
Resolution
-
-
-
-
12
bit
Integral Nonlinearity
-
-
-
-
± 4.5
LSB
AVRH=2.7 V to
3.6 V
Offset calibration
when used
Differential Nonlinearity
-
-
-
-
± 2.5
LSB
Zero transition voltage
VZT
ANxx
-
± 2
± 7
LSB
Full-scale transition
voltage
VFST
ANxx
-
AVRH ± 2
AVRH ± 7
LSB
Total error
-
-
-
± 3
± 8
LSB
Conversion time
-
-
1.0*1
-
-
μs
Sampling time *2
tS
-
0.3
-
10
μs
Compare clock cycle*3
tCCK
-
50
-
1000
ns
State transition time to
operation permission
tSTT
-
-
-
1.0
μs
Power supply current
(analog + digital)
-
AVCC
-
0.30
0.45
mA
A/D 1unit
operation
-
0.1
9.5
μA
When A/D stop
Reference power
supply current(AVRH)
-
AVRH
-
0.66
1.18
mA
A/D 1unit
operation
AVRH=3.3 V
-
0.2
3.2
μA
When A/D stop
Analog input capacity
CAIN
-
-
-
12.05
pF
Analog input resistance
RAIN
-
-
-
1.8
kΩ
Interchannel disparity
-
-
-
-
4
LSB
Analog port input leak
current
-
ANxx
-
-
5
μA
Analog input voltage
-
ANxx
AVSS
-
AVRH
V
AVSS
-
AVCC
V
Reference voltage
-
AVRH
2.7
-
AVCC
V
tCCK ≥ 50 ns
-
AVRL
AVSS
-
AVSS
V
*1: The conversion time is the value of sampling time (tS) + compare time (tC).
Ensure that it satisfies the value of sampling time (tS) and compare clock cycle (tCCK).
For setting of sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM4 Family Peripheral Manual
Analog Macro Part (002-04860). The register setting of the A/D converter is reflected by the APB bus clock timing.
For more information about the APB bus signal to which the A/D converter is connected, see 10. Block Diagram in this
data sheet.
The sampling clock and compare clock are set at base clock (HCLK).
*2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1).
*3: The compare time (tC) is the value of (Equation 2).
Document Number: 002-05038 Rev.*C Page 161 of 183
S6E2DH Series
(Equation 1) tS ≥ (RAIN + REXT) × CAIN × 9
tS: Sampling time
RAIN: Input resistance of A/D = 1.8 kΩ
CAIN: Input capacity of A/D = 12.05 pF
REXT: Output impedance of external circuit
(Equation 2) tC = tCCK × 14 tC: Compare time
tCCK: Compare clock cycle
REXT
Cin
Analog signal
source
ANxx
Analog input pin
Comparator
RAIN
CAIN
Document Number: 002-05038 Rev.*C Page 162 of 183
S6E2DH Series
Definition of 12-bit A/D Converter Terms
Resolution: Analog variation that is recognized by an A/D converter.
Integral Nonlinearity: Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition point
(0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.
Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code
by 1 LSB.
Integral Nonlinearity of digital output N =
VNT - {1LSB × (N - 1) + VZT}
[LSB]
1LSB
Differential Nonlinearity of digital output N =
V(N + 1) T - VNT
- 1 [LSB]
1LSB
1LSB =
VFST - VZT
4094
N: A/D converter digital output value.
VZT: Voltage at which the digital output changes from 0x000 to 0x001.
VFST : Voltage at which the digital output changes from 0xFFE to 0xFFF.
VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Integral Nonlinearity
Differential Nonlinearity
Digital output
Digital output
Actual conversion
characteristics
Actual conversion
characteristics
Ideal characteristics
(Actually-
measured
value)
Actual conversion
characteristics
Actual conversion characteristics
(Actually-measured
value)
(Actually-measured value)
Ideal characteristics
(Actually-measured
value)
Analog input
Analog input
(Actually-measured
value)
0x001
0x002
0x003
0x004
0xFFD
0xFFE
0xFFF
AVss
AVRH
AVss
AVRH
0x(N-2)
0x(N-1)
0x(N+1)
0xN
{1 LSB(N-1) + VZT}
VNT
VFST
VZT
VNT
V(N+1)T
Document Number: 002-05038 Rev.*C Page 163 of 183
S6E2DH Series
Total error: A difference between actual value and theoretical value.
The overall error includes zero-transition voltage, full-scale transition voltage and linearity error.
VFST’=1.5LSB’
Actual conversion
characteristics
{1LSB’ x (N-1) + 0.5 LSB’}
Ideal characterisics
VZT’=0.5LSB’
0x001
0x002
0x003
0x004
0xFFD
0xFFE
0xFFF
Total error
Digital output
AVRL AVRH
Analog input
VNT
(Actually-measured
value)
Actual conversion
characteristics
Total error of digital output N = VNT – {1 LSB’ X (N-1) + 0.5 LSB’}
1 LSB’[LSB]
1 LSB’ (ideal value) = AVRH – AVRL
4096 [V]
VZT’ (ideal value) = AVRL + 0.5 LSB’[V]
VFST’ (ideal value) = AVRH - 1.5 LSB’
VNT’: A voltage for causing transition of digital output from (N-1) to N
[V]
Document Number: 002-05038 Rev.*C Page 164 of 183
S6E2DH Series
12.6 USB Characteristics (VCC = 3.0V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin
Name
Conditions
Value
Unit
Remarks
Min
Max
Input
characteristi
cs
Input H level voltage
VIH
UDP0/
UDM0
-
2.0
VCC + 0.3
V
*1
Input L level voltage
VIL
-
VSS - 0.3
0.8
V
*1
Differential input sensitivity
VDI
-
0.2
-
V
*2
Different common mode
range
VCM
-
0.8
2.5
V
*2
Output
characteristi
cs
Output H level voltage
VOH
External
pull-up
resistance =
15kΩ
2.8
3.6
V
*3
Output L level voltage
VOL
External
pull-up
resistance =
15kΩ
0.0
0.3
V
*3
Crossover voltage
VCRS
-
1.3
2.0
V
*4
Rising time
tFR
Full-Speed
4
20
ns
*5
Falling time
tFF
Full-Speed
4
20
ns
*5
Rising/falling time matching
tFRFM
Full-Speed
90
111.11
%
*5
Output impedance
ZDRV
Full-Speed
28
44
Ω
*6
Rising time
tLR
Low-Speed
75
300
ns
*7
Falling time
tLF
Low-Speed
75
300
ns
*7
Rising/falling time matching
tLRFM
Low-Speed
80
125
%
*7
*1: The switching threshold voltage of Single-end-receiver of USB I/O buffer is set as within VIL (Max) = 0.8 V,
VIH (Min) = 2.0 V (TTL input standard).
There are some hysteresis to lower noise sensitivity.
*2: Use differential-Receiver to receive USB differential data signal.
Differential-receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8 V to
2.5 V to the local ground reference level.
Above voltage range is the common mode input voltage range.
Common mode input voltage [V]
*3: The output drive capability of the driver is below 0.3 V at Low-state (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or
above (to the VSS and 15 kΩ load) at High-State (VOH).
*4: The cross voltage of the external differential output signal (D + /D − ) of USB I/O buffer is within 1.3 V to 2.0 V.
Minimum differential input
sensitivity [V]
Document Number: 002-05038 Rev.*C Page 165 of 183
S6E2DH Series
*5: They indicate Rising time (tFR) and Falling time (tFF) of the Full-speed differential data signal.
They are defined by the time between 10 % and 90 % of the output signal voltage.
For Full-speed buffer, tFR/tFF ratio is regulated as within ± 10 % to minimize RFI emission.
Rs=27Ω
Full-speed Buffer
TxD+
TxD-
3-State Enable
Rs=27Ω
C
L
=50pF
C
L
=50pF
D+
90%
tFR
tFF
90%
10%
10%
D-
Max 2.0 V
D+
D-
Min 1.3 V
VCRS specified range
Rising time
Falling time
Document Number: 002-05038 Rev.*C Page 166 of 183
S6E2DH Series
*6: USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15 % characteristic impedance (Differential
Mode).
USB standard defines that output impedance of USB driver must be in range from 28 Ω to 44 Ω. So, discrete series
resistor (Rs) addition is defined in order to satisfy the above definition and keep balance.
When using this USB I/O, use it with 25 Ω to 30 Ω (recommendation value 27 Ω) Series resistor Rs.
Rs series resistor 25 Ω to 30 Ω
Series resistor of 27 Ω (recommendation value) must be added.
And, use "resistance with an uncertainty of 5% by E24 sequence".
*7: They indicate rising time (tLR) and Falling time (tLF) of the Low-speed differential data signal.
They are defined by the time between 10 % and 90 % of the output signal voltage.
Note:
− See Low-speed load (Compliance load) for conditions of external load.
D+
90%
tLR
tLF
90%
10%
10%
D-
Mount it as external resistance.
28Ω to 44Ω Equiv. Imped.
28Ω to 44Ω Equiv. Imped.
Rising time
Falling time
Document Number: 002-05038 Rev.*C Page 167 of 183
S6E2DH Series
Low-speed load (Upstream port load) - Reference 1
Low-speed load (Downstream port load) - Reference 2
Low-speed load (Compliance load)
CL = 50pF to 150pF
CL = 50pF to 150pF
CL =
200pF to 600pF
CL =
200pF to 600pF
CL = 200pF to 450pF
CL = 200pF to 450pF
Document Number: 002-05038 Rev.*C Page 168 of 183
S6E2DH Series
12.7 Low-Voltage Detection Characteristics
12.7.1 Low-Voltage Detection Reset
Parameter
Symbol
Conditions
Value
Unit
Remarks
Min
Typ
Max
Detected voltage
VDL
-
2.46
2.55
2.64
V
When voltage
drops
Released voltage
VDH
-
2.51
2.60
2.69
V
When voltage
rises
12.7.2 Interrupt of Low-Voltage Detection
Parameter
Symbol
Conditions
Value
Unit
Remarks
Min
Typ
Max
Detected voltage
VDL
SVHI = 00111
2.80
2.90
3.00
V
When voltage
drops
Released voltage
VDH
2.90
3.00
3.11
V
When voltage
rises
Detected voltage
VDL
SVHI = 00100
2.99
3.10
3.21
V
When voltage
drops
Released voltage
VDH
3.09
3.20
3.31
V
When voltage
rises
Detected voltage
VDL
SVHI = 01100
3.18
3.30
3.42
V
When voltage
drops
Released voltage
VDH
3.28
3.40
3.52
V
When voltage
rises
LVD stabilization wait
time
tLVDW
-
-
-
4800×tCYCP*
μs
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05038 Rev.*C Page 169 of 183
S6E2DH Series
12.8 MainFlash Memory Write/Erase Characteristics (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Value
Unit
Remarks
Min
Typ
Max
Sector erase
time
Large Sector
-
0.7
3.7
s
Includes write time prior to internal
erase
Small Sector
-
0.3
1.1
s
Half word
(16-bit)
write time
Write cycles ≤ 100
times
-
12
100
μs
Not including system-level overhead
time
Write cycles > 100
times
200
Chip erase time
-
6.6
31
s
Includes write time prior to internal
erase
Write Cycles and Data Hold Time
Erase/Write Cycles (cycle)
Data Hold Time (year)
1,000
20*
10,000
10*
100,000
5*
*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature
acceleration test result into average temperature value at + 85°C) .
12.9 VFLASH Memory Write/Erase Characteristics (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Value
Unit
Remarks
Min
Typ
Max
Sector erase time (4 KB)
-
50
450
ms
Block Erase Time (64 KB)
-
500
2000
ms
Page Program Time
-
0.7
3
ms
Chip erase time
-
11.2
64
s
Erase Endurance
Parameter
Value
Unit
Remarks
Min
Typ
Max
Erase per sector
100k
-
-
cycle
*: Data retention of 20 years is based on 1k erase cycle or less.
Document Number: 002-05038 Rev.*C Page 170 of 183
S6E2DH Series
12.10 Standby Recovery Time
12.10.1 Recovery Cause: Interrupt/WKUP
The time from recovery cause reception of the internal circuit to the program operation start is shown.
Recovery Count Time (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Value
Unit
Remarks
Typ
Max*
Sleep mode
tICNT
HCLK×1
μs
High-speed CR Timer mode
Main Timer mode
PLL Timer mode
40
80
μs
Low-speed CR timer mode
450
900
μs
Sub timer mode
896
1136
μs
RTC mode
Stop mode
(High-speed CR /Main/PLL run mode return)
316
581
μs
RTC mode
Stop mode
(Low-speed CR/sub run mode return)
270
540
μs
Deep standby RTC mode
Deep standby Stop mode
365
667
μs
without RAM
retention
365
667
μs
with RAM
retention
*: The maximum value depends on the built-in CR accuracy.
Example of standby recovery operation (when in external interrupt recovery*)
Ext.INT
tICNT
Interrupt factor
accept
CPU
Operation Start
Active
Interrupt factor
clear by CPU
*: External interrupt is set to detecting fall edge.
Document Number: 002-05038 Rev.*C Page 171 of 183
S6E2DH Series
Example of Standby Recovery Operation (when in Internal Resource Interrupt Recovery*)
Internal
Resource INT
tICNT
Interrupt factor
accept
CPU
Operation Start
Active
Interrupt factor
clear by CPU
*: Depending on the standby mode, interrupt from the internal resource is not included in the recovery cause.
Notes:
− The return factor is different in each Low-Power consumption modes.
See Chapter 6: The return factor from each low power consumption modes in “FM4 Family Peripheral Manual Main Part
(002-04856).
− When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power
consumption mode transition. See Chapter 6: Low Power Consumption Mode" in "FM4 Family Peripheral Manual Main
part (002-04856).
Document Number: 002-05038 Rev.*C Page 172 of 183
S6E2DH Series
12.10.2 Recovery Cause: Reset
The time from reset release to the program operation start is shown.
Recovery Count Time (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Value
Unit
Remarks
Typ
Max*
Sleep mode
tRCNT
155
266
μs
High-speed CR Timer mode
Main Timer mode
PLL Timer mode
155
266
μs
Low-speed CR timer mode
315
567
μs
Sub timer mode
315
567
μs
RTC mode
Stop mode
315
567
μs
Deep standby RTC mode
Deep standby Stop mode
336
667
μs
without RAM
retention
336
667
μs
with RAM
retention
*: The maximum value depends on the built-in CR accuracy.
Example of Standby Recovery Operation (when in INITX Recovery)
INITX
tRCNT
Internal RST
CPU
Operation Start
RST Active Release
Document Number: 002-05038 Rev.*C Page 173 of 183
S6E2DH Series
Example of Standby Recovery Operation (when in Internal Resource Reset Recovery*)
Internal
Resource RST
tRCNT
Internal RST
CPU
Operation Start
RST Active Release
*: Depending on the Low-Power consumption mode, the reset issue from the internal resource is not included in the
recovery cause.
Notes:
− The return factor is different in each low power consumption mode.
See Chapter 6: The return factor from each low power consumption modes in “FM4 Family Peripheral Manual Main Part
(002-04856).
− The recovery process is unique for each operating mode. See Chapter 6: Low Power Consumption mode in FM4 Family
Peripheral Manual Main Part (002-04856)
− When the power-on reset/low-voltage detection reset, they are not included in the return factor. See 12.4.8 Power-on
Reset Timing.
− In recovering from reset, CPU changes to High-speed Run mode. In the case of using the main clock and PLL clock,
they need further main clock oscillation stabilization wait time and oscillation stabilization wait time of Main PLL clock.
− Internal resource reset indicates Watchdog reset and CSV reset.
Document Number: 002-05038 Rev.*C Page 174 of 183
S6E2DH Series
13. Ordering Information
Part Number
Package
S6E2DH5G0AGV20000
Plastic・LQFP (0.5 mm pitch), 120 pin
(LQM 120)
S6E2DH5GJAMV20000
S6E2DH5J0AGV2000A
Plastic・LQFP (0.5 mm pitch), 176 pin
(LQP 176)
S6E2DH5G0AGB3000A
Plastic・FBGA (0.5 mm pitch), 161 pin
(FDJ 161)
S6E2DH5G0AGE20000
Plastic・Ex-LQFP (0.5 mm pitch), 120 pin
(LEM 120)
Document Number: 002-05038 Rev.*C Page 175 of 183
S6E2DH Series
14. Package Dimensions
Package Type
Package Code
LQFP 120
LQM 120
M IN. NOM . M AX.
07.1A
A1 0.05 0.15
b 0.17 0.22 0.27
c0.115 0.195
D 18.00 BSC
D1 16.00 BSC
e0.50 BSC
E
E1
L 0.45 0.60 0.75
18.00 BSC
16.00 BSC
DIM ENSIONS
SYM BOL
θ0°8°
SIDE VIEW
BOTTOM VIEW
TOP VIEW
1
120
D1
D
e
EE1
0.20 C A-B D
0.10 C A-B D
0.08 C A -B D
b
0.08 C
SEATI NG
PLA NE
A
A'
θ
A
A1
0.25 10
L
b
SEC TION A -A'
c
9
4
57
3
4
5
7
3
8
7
5
2
2
6
30
31
60
6190
91
130
31
60
0916
91
PACKAGE OUTLINE, 120 LEAD LQFP
18.0X18.0X1.7 M MLQM120 REV**
002-16172 **
Document Number: 002-05038 Rev.*C Page 176 of 183
S6E2DH Series
Package Type
Package Code
LQFP 176
LQP 176
D IM EN SI ON S
SYMBOL M IN . N OM . M AX.
A1.70
A1 0.05 0.15
b 0.17 0.22 0.27
c 0.09 0.20
D 26.00 BSC
D1 24.00 BSC
e0.50 BSC
E
E1
L 0.45 0.60 0.75
L1
26.00 BSC
24.00 BSC
0.30 0.50 0.70
0°8°
θ
1
176
e
D1
D
EE1
3
3
0.08 C A-B D
b
0.10 C A-B D
8
7
5
2
2
0.08 C
A
A'
SEA TIN G
PLAN E
4
5 7
4
5
7
A
A1
0.2 5
10
L1
L
b
SECTION A -A'
c
9
6
0.20 C A-B D
SIDE VIEW
TOP VIEW
BOTTOM VIEW
1
176
θ
44
45
88
89132
133
44
45
88
23198
133
PACKAGE OUTLINE, 176 LEAD LQFP
24.0X24.0X1.7 MM LQP176 REV**
002-15150 **
Document Number: 002-05038 Rev.*C Page 177 of 183
S6E2DH Series
Package Type
Package Code
FBGA 161
FDJ 161
2. D IM ENSIONS AND TOLERANCES M ETHODS PER ASM E Y14.5-2009 .
THIS OUTLIN E CON FORM S TO JEP95, SECTION 4.5.
3. BA LL POSITION D ESIGNATIONPER JEP95, SECTION 3, SPP-010.
4. "e" REPRESENTS THE SO LD ER BALL GRID PITCH .
5. SYMBOL "MD" IS THE BALL MA TRIX SIZE INTH E "D" D IRECTION.
SYM BOL "M E" IS THE BALL MATRIX SIZE INTH E "E"DIRECTION.
nIS THE NUM BER OF POPULATED SOLDER BALL POSITIONS FOR M ATRIX
SIZE M D X M E.
6. D IM ENSION "b " IS M EASURED AT THE M AXIM UM BALL D IAM ETER
IN A PLANE PARALLEL TO DATUM C.
7. "SD" AND "SE" ARE M EASURED W ITH RESPECT TO DATUMSA AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL INTH E OUTER ROW .
W HEN THERE IS AN ODD N UM BER OF SOLDER BALLS IN THE OUTER ROW ,
"SD" OR "SE"= 0.
W HEN THERE IS AN EVEN NUMBER OF SOLDER BALLS I N THE O UTER ROW ,
"SD" = eD/2 AND "SE" = eE/2.
1. ALL DIM ENSIONS ARE IN M ILLIM ETERS.
8. A1 CORN ER TO BE IDENTIFIED BY CHAM FER, LASER OR INK M ARK.
M ETALLIZED M ARK IN DEN TATION O R O THER M EANS.
9. "+ " INDICATES THE THEORETICAL CENTER O F DEPOPULATED BALLS.
NOTES
10. JEDEC SPECIFICATION NO. REF: N/A.
NOM .M IN .
E8.00 BSC
D
A
1
A
8.00 BSC
SYM BOL
MAX.
1.20
DIM ENSIONS
0.20
D1
E1
M E
M D
n
13
13
161
Φb0.25 0.350.30
eE
eD
SD / SE
0.50 BSC
0.50 BSC
0.00
6.00 BSC
6.00 BSC
0.25 0.30
D
A
0.08 C
2X
E
B
0.08 C
2X
IND EX M ARK
PIN A1
CORNER 8
D1
E1
eD
1
2
3
4
5
6
7
8
9
10
11
ABCDEFGH
J
KL
161xφb0.15 C A B
0.05 C
6
eE
SE
7
7
A
DETAIL A
SIDE VIEW
0.20 C
0.08 C
A1
C
DETAIL A
BOTTOM VIEW
TOP VIEW
SD
MN
12
13
8.00X8 .00X1.20 MM FDJ161 REV**
PACKAGE OUTLINE, 161 BALL FBGA
002-16413 **
Document Number: 002-05038 Rev.*C Page 178 of 183
S6E2DH Series
Package Type
Package Code
Ex-LQFP 120
LEM 120
D1
D
4
57
E1 E
0.20 C A-B D 0.10 C A-B D
D3
D2
E3 E2
AA2
A1
2
11
DETAIL A
e0.08 C
SEATING
PLANE
A
A'
b
0.08 C A-B D
8
SIDE VIEW
TOPVIEW BOTTOM VIEW
b
SECTION A-A'
c
10
L1
L
θ
R1
R2
GAUGE
PLANE
DETAIL A
L2
EXPOSED PAD
L11.00 REF
L
c
0.4 5
0.0 9
0.6 0 0.7 5
0.2 0
NOM .M IN .
16.00 BSC.
D1
R2
E1
E
0°
0.0 8
4°
16.00 BSC.
18.00 BSC.
D
2A
A
1A
1.3 5
18.00 BSC.
1.4 0
0.0 0
SYM BOL
MAX.
8°
0.2 0
1.4 5
1.7 0
0.2 0
θ
D2
D3
E2
E3
6.50 REF
5.30 REF
6.50 REF
5.30 REF
b0.1 7 0.2 2 0.2 7
e0.50 BSC.
DIM EN SION
1
R0.0 8
L20.2 5
PACKAGE OUTLINE, 120 LEAD TEQFP
16.0X16.0X1.7 M MLEM120 REV**
002-12611 **
Document Number: 002-05038 Rev.*C Page 179 of 183
S6E2DH Series
15. Errata
This chapter describes the errata for S6E2DH series. Details include errata trigger conditions, scope of impact, available
workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions.
15.1 Part Numbers Affected
Part Number
S6E2DH5J0AGV20000, S6E2DH5J0AGV2000A
15.2 Qualification Status
Product Status: In Production
15.3 Errata Summary
This table defines the errata applicability to available devices.
Items
Part Number
Silicon Revision
Fix Status
SDRAM cannot be used as
destination buffer of the GDC
Refer to 15.1
Rev A
No silicon fix planned.
Workaround required.
SDRAM cannot be used as destination buffer of the GDC
1. PROBLEM DEFINITION
Unnecessary data is written on the before and after the correct addresses if the GDC writes data to the external
SDRAM, the CPU’s internal SRAM0, SRAM2, or any memory devices connected to the External Bus Interface.
2. PARAMETERS AFFECTED
N/A
3. TRIGGER CONDITION(S)
The GDC generates either write data that is NOT size of multiples of 8 bytes multiplied by Burst Length or write
address that is NOT aligned with 8 bytes multiplied by Burst Length to the external SDRAM, the CPU's internal
SRAM0, SRAM2, or any memory devices connected to the External Bus Interface. The Burst Length means length of
write burst transaction, and you can set it as 2 (16 bytes), or 4 (32 bytes).
4. SCOPE OF IMPACT
The external SDRAM, the CPU’s internal SRAM0, SRAM2, or any memory devices connected to the External Bus
Interface cannot be used as destination buffer of the GDC.
5. WORKAROUND
Keep Write data size and Base address according as following table when the GDC writes to the external SDRAM, the
CPU’s internal SRAM0, SRAM2, or any memory devices connected to the External Bus Interface.
Burst Length for write
access
Write data size
Base address alignment for write data
2
Multiples of 16 bytes
16 bytes aligned address. E.g. 0xB000_0010,
0xB000_0020.
4
Multiples of 32 bytes
32 bytes aligned address. E.g. 0xB000_0020,
0xB000_0040.
6. FIX STATUS
There is no fix planned. The workaround listed above should be used.
Document Number: 002-05038 Rev.*C Page 180 of 183
S6E2DH Series
16. Major Changes
Spansion Publication Number: DS709-00029
Page
Section
Change Results
Revision 0.1
-
-
Initial release
Revision 1.0
1, 3
13, 14
15
178
Title
3. Product Lineup
4. Packages
15. Ordering Information
Deleted the following products.
S6E2DH5JAA/ S6E2DH5GAA
6
2. Features
External Bus Interface
Added the following description:
Maximum area size : Up to 256 Mbytes
Modified the following description:
0x6000_0000 to 0xDFFF_FFFF to 0x6000_0000 to 0x7FFF_FFFF
7
13
2. Features
3. Product Lineup
Added that CAN-FD Interface supported non-CAN FD.
8
2. Features
Modified the ch. Number of I2C ( ch.7→ch.4)
15
16
20 to 52
81
178
4. Packages
5. Pin Assignment
6. Pin Descriptions
14.2. Recommended Operating
15. Ordering Information
Added the Ex-LQFP(TEQFP)(LEM120)
53
7. I/O Circuit Type
Modified the Type-A Circuit
54,55,58
7. I/O Circuit Type
Added the comment in TypeD/E/F/G/N
59
7. I/O Circuit Type
Modified theType-Q Remarks
CMOS level output → CMOS level hysteresis input
67
10. Block Diagram
Deleted the following products.
S6E2DH5JAA/ S6E2DH5GAA
68
12. Memory Map
Modified the External Device Area / GDC Area
80
165
14.2. Recommended Operating
14.5 12-bit A/D Converter
Added the AVRL in Analog reference voltage.
82
14.2. Recommended Operating
Modified the TBD in Current Value
Added the Note
84 to 93
14.3.1 Current Rating
Modified the TBD in Max spec
Added the comment of VFLASH memory
93
14.3.1 Current Rating
Table 14-11
Added the VFLASH memory current
95
14.4 AC Characteristics
14.4.1 Main Clock Input
Added the Master clock
97
14.4 AC Characteristics
14.4.5 Operating Conditions
Modified the I2S PLL frequency (307.2→384)
Modified the GDC clock frequency (400→160)
165
14.5 12-bit A/D Converter
Modified the Spec
Modified the comment of Conversion time
172
14.7.2 Interrupt of Low-Voltage
Detection
Modified the max value in LVD stabilization wait time. (6000→4800)
173
14.9 VFLASH Memory
Added the new
178
15. Ordering Information
Modified the Part Number (S6E2DH5G0AGB10000→
S6E2DH5G0AGB30000)
Added the Package (Ex_LQFP)
181, 182
16. Package Dimensions
Added the FDJ161/LEM120
NOTE: Please see “Document History” about later revised information.
Document Number: 002-05038 Rev.*C Page 181 of 183
S6E2DH Series
Document History
Document Title: S6E2DH Series 32-bit ARM® Cortex®-M4F, FM4 Microcontroller
Document Number: 002-05038
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
-
AKIH
04/21/2015
New Spec.
*A
5123103
SHOY
03/04/2016
Added CCS/CCB settings in 7. HandlingDevices (Page58) and Table 12-10
Typical…*6,*7 (page 85).
Changed PN: S6E2DH5G0AGZ20000 to S6E2DH5G0AGE20000 in 13.
Ordering… (Page 174).
Changed “GE_SPCSX_0” to “GE_SPCSX0” in 3. PinAssignment (Page 9,
11), 4. PinDescriptions (Page16, 42), 8. BlockDiagram (Page 61) and
12.4.22 GDC: … (Page 156,157)
Changed “GE_HBCSX_0” to “GE_HBCSX0” in 3. PinAssignment (Page 9,
11), 4. PinDescriptions (Page 16, 42) , 8. BlockDiagram (Page 61) and
12.4.23 GDC: ... (Page 158,159)
Changed “GE_HBCSX_1” to “GE_HBCSX1” in 3. PinAssignment (Page
9,11), 4. PinDescriptions (Page 14, 42), 8. BlockDiagram (Page 61) and
12.4.23 GDC: … (Page 158,159)
Updated VFLASH memory Standby current value to 35uA in Table 12-11
Typical… (Page 86).
Changed “Ex_LQFP” to “Ex-LQFP” in 2. Packages (Page 8), 4. Pin
Descriptions (Page 13 to 46), 12.2 Recommended… (Page 74) and 13.
Ordering… (Page 174).
Changed “VMAKEUP” to “VWAKEUP” in 8. BlockDiagram (Page 61).
Changed “HW flow control (ch. 4, 5)” to “HW flow control (ch. 4)” in 8.
BlockDiagram (Page 61).
Added “(N.C.): Do not connect anything” in 3. Pin Assignment (Page 10).
Added the Note in 4. Pin Descriptions (Page 46).
Added Function of PNL_TSIG in 4. Pin Descriptions (Page 43).
Changed “PFBGA” to “FBGA” in 12.2 Recommended… (Page 74) and 13.
Ordering… (Page 174).
New added errata in 15. Errata (Page 179 to 180).
*B
5634638
YSKA
2/21/2017
Changed an explanation from “from 01 to 99” to “from 00 to 99” in Real-Time Clock
(RTC) (Page 3) of Features.
Added an explanation in Notes on Power-on (Page 60) of 7. Handling Devices.
Changed “VBAT Power-on Reset” to “Power-on Reset” in List of VBAT Domain Pin
Status (Page 71) of 11. Pin Status in Each CPU State, and Added Remark *1.
Added Remark *8 in Table 12-10 Typical and Maximum Current Consumption in
Deep Standby Stop Mode, Deep Standby RTC Mode and VBAT (Page 85).
Changed Parameter “Power supply rising time (tVCCR)” to “Power ramp rate (dV/dt)” in
12.4.8 Power-on Reset Timing, Changed the minimum to 0.6mV/μs, Changed the
maximum to 1000mV/μs, and Added Remarks and Note.
Deleted setting value “SPI=1” and “MS=0” at using chip select in 12.4.12 CSIO
Timing, and Added “MS bit = 0” and “MS bit = 1” on the Figure (P113-120, P129-136).
Deleted MPNs below from “13. Ordering Information” (Page 174)
Document Number: 002-05038 Rev.*C Page 182 of 183
S6E2DH Series
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
S6E2DH5J0AGV20000, S6E2DH5G0AGB30000
Added MPNs below to “13. Ordering Information” (Page 174)
S6E2DH5J0AGV2000A, S6E2DH5G0AGB3000A
Updated package diagrams in “14. Package Dimensions”(Page 175)
Updated the part number in “15. Errata”(Page 179)
Deleted Baud rate spec for High-Speed Synchronous Serial in “12.4.12 CSIO
Timing”(Page 121-127)
*C
5761473
AESATP12
06/28/2017
Updated logo and copyright.
Document Number: 002-05038 Rev.*C June 28, 2017 Page 183 of 183
S6E2DH Series
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