SULA AL/SVI CMOS uP-Compatible 12-Bit DAC ___s Genera! Description The MxX7542 is a CMOS 12-Bit digital-to-analag can- verter (DAC) which directly interfaces to both 8-bit and 4-bit microprocessors. Input data is loaded as three 4-bit bytes, and is then transferred to an internal l2-hit DAC register. Data load and transfer interface uming is similar to that of a static RAM write cycle. A clear input is also provided which resets the DAC register ta all zeros. This can be used to initialize the device an power up ar during software calibration routines. Low pawer consumption, +5V operation, and multi- plying capability make thea MX7542 suitable for numerous high precision processor cantrolled DAG applications. The MX7542 |s supplied in 16-iead DIP and Small Outline packages. Applications Programmable Power Sources Portable Test Equipment Digntally Contralled Filters Auto-Calibration Circuitry Motion Control Systems ____. Functional Diagram Veer A AXIS Mx 7S? he BIT MULTIPLYING DAG 12-7 OAC REGISTER Features # 12-Bii Resolution # +1/2 LSB Linearity Over Temperature # +1 LSB Gain Accuracy (MX7542G) @ Spom/C Max. Gain Drift # = Microprocessor Compatible @ 40mW Max. Power Dissipation # = +5V Operation _ ss Ordering Information PART TEMP. RANGE PACKAGE? ERROR MX?542N O to 70C Plastic DIP 11 LSB MX7542KN | cFCto+70C Plastic DIP +. LSB | Wx7542GKN aC to+70O Plastic DIP +. LSB MX7S42JCWE C to -70G Small Gutline +1 LSB WX7542KCWE OPC to -70S Small Outhne =. LSB! MXTSH2GKOWE OC 10-707 Small Gulline + LSB] | Mx7642/0 OCto-70C Dice +1 LSB MX7S49 AD -P5"C to +H5C Ceramic -1 LSB MX 7542RD 25C to +H6C Ceramic -') LSB MX7642GBD -26C to +85C Ceramic LSB MXFS42A0 25C ta -85C CERDIP -> L8G MX 754280 -25C to -a5C CEROIP" +. LSB MX7542GBOQ -26C to -85S = CERDIP"* 1. LSB Mx7542SD 56C ta 125C Ceramic 11 LSB Mx?7542TD -56C to +125C |= Ceramic ' . LSB MxF5A2GTO --88C to +126C Ceramic i. 38 Mx 754250 -55C ta +125"C =CERDIP +1 LSB MX 7542?TO -55C io rise | |6CERDIP +' LSB MX7542GTO -55C to +125C =CERDIP +') LAB AN devwees 16 fead packages * Maxim reserves 'he mgaf ta ship Ceram packages on dei of CEROIP packages Pin Configuration Top View . qUuTIT] Rea wi HAYTE W-BYTE quT2 =] TE] Veer us AADAESS AKEISTER REGISTER AGND DECOOE MAXIM on , 4a LOGIC O3[s] atx7542 CLA al o2 fs 2) DGND Ml ai] Al DO so] AD CS La WR #vLAALA Maxim integrated Products 1 Call toll free 1-800-998-8800 for free samples or literature. 2PSZXNMX7542 CMOS uP-Compatible 12-Bit DAC ABSOLUTE MAXIMUM RATINGS Vou (2 AGNO 0 cece ects 03, -7V Van 12 DGND woke ee ee eee cee -O.3V, +7V AGNO tw OGND oo... Cnet nett ce tenes Von DGND to AGND 2.2... cect ences Vo5 Digital Input Voltage 16 DGND ........ -O3V, Van + 0.8V (Pins 4-11, 13) Von Meng ( AGND occ -0 3, Vag + OV VO Col XC], | +25 Varg LO AGND 01ers #25 Power Dissipation .........-..5 (derate 6mW/'C above +70C} Operating Temperature Range Cammercial MX7542.1, K, GK... . Industrial MX75424,B, GB. ........-.- Military MX7542S, T. GT Storage Temperature ........2...0..005 Lead Temperature (Saldering 10 sec} ..... -...-.. . 450mWw roa OG ta FOG 25C Lo -85C -85C to 125C -65C to +150C 300C Stresses above those hsted under Absolute Maximum Ratings may cause parmanant damage to the device. These are strass ratings only ang luncnonal operaron of the device al these or any other conditions abave those indicated i the operational sections of the specifications ts nut imphied Exposure to absolute maximum ratings conditions for extended pencds may affact device reftadulity. ELECTRICAL CHARACTERISTICS (T. = Tyan tO Taax: Yoo = 84 Vaer = +10V. Vour. = Veute = GND, unless otherwise specified) PARAMETER [symBOL | CONDITIONS MIN TyP MAX | UNITS OC ACCURACY Resolution 12 Bits Mx7542)/A/S 41 Mon-Linearity Mx7542K/B/T 405 LSB Mx7542GK/AGB8/GT +05 MxX7542)/AS (Nate 1} +2 Offerental Non-Linearity MX7542K/B/T (Note 2) 41 LSB MXxX7542GK/GB/GT (Note 2) +4 MX7542J/K/A/B/S/T T, = 26C 4412.3 MxX7542J/K/A/B Tan tO Trax 113.5 MxX7542S/T Tray to T, +145 Gain Errar Mun Maw - LSB MX7542GK/GB/GT Ty = 25C -1 MX7542GK/GB Taira 10 Tra 44 MX7542GT wy 12 Tran +2 Gain Temperature Coefficient ie AGain/ATemperature (Note 4) 2 pemic Power Supply Rejection PSRA | Vpn 7 +4.75V lo #5.25V pot 9.005 | oi/2Vi op min '0 Tyrax 001 Ty = 26C 1 Output Leakage Current Mx 7542U/K/GK Twin tO Trax 10 nA louie loyrs (Note 3) MX75424/B/GB Tran [0 Tyra 10 MX7542S/T/GT Tray t2 Trax 200 DYNAMIC PERFORMANCE [Noite 4) Output Current Settling Time To 1/2 LSB, Outl Load = 1000 re ys Feedthrough Error Vaep = 10 10kHz sine wave 2.5 mpp REFERENCE INPUT Input Resistance (pin 15) | Rrer 8 15 25 kQ ANALOG OUTPUT [Note 4) Cat, | DAC Register 0000 a000 0000 75 Cour, | DAC Register 1111 7111 1174 260 Output Capacitance Cone | DAC Register 1114 1111 7111 75 pF _ | Gouts | DAC Register C000 0000 CD00 _ 260 AVISJIAL SEICMOS uP-Compatible 12-Bit DAC ELECTRICAL CHARACTERISTICS (Continued) (T= Tara t@ Tyas Yoo - 784! Veer - 710M Your = Yours = GND, unless otherwise specified) MAX PARAMETER [SYMBOL | CONDITIONS MIN TYP UNITS LOGIC INPUTS Logic HIGH Voltage Vine 130 v Logic LOW Voltage Vint +0.8 Logie Input Current ley OV or Yop 1 uA Input Capacitance (Note 4) Cy 8 pF SWITCHING CHARACTERISTICS (see Figure 6} (Note 5) . . Ty = 26C 120 Write Pulse Width ty & | WR Tray tO Tax 220 : . Ty = 26C 50 Address-to-Write Hald Time lawn Toany tO Typax 65 nc : / T, = 25C 50 Chip Select-to-Write Hald tow, A Cw Turin tO Trax 100 . T, - 26C 200 Minimum CLEAR Pulse Width | t A | SLR | Tray tO Trax 300 ; BYTE LOADING T, = 25C 60 Chip Select-toWRITE Setu t A P P CWS | Thay to Trax 130 . T, = 25C a0 Address Valid-to-Write Setu t A Pp AWS Trin to Tax 180 ng . Ty - 25C 50 Data Setup Time i A p PS | Thay 19 Thanx 85 Ty, = 25C 50 Data Hold Time i A pom Tin tO Trax 65 DAC LOADING , T, 25C 60 Chip Select-to-WRITE Setup tows Team tO. Taga 150 |. : T, = 25C 120 Address valid-to-Write Setup taws | Than 10 Trax 240 POWER SUPPLY Supply Voltage Yoo | SY I 5% 475 525 Vv Supply Current lan | 2.4 mA Note 1: Monotonic ta 11 bits from Ty tO Trax Note 2; Monotonic to 12 bits from Tyan tO Tyax Note 3: I, 7, tested with DAC register ioaded to all 0's louta tested with DAC register loaded to all 1's. Note 4: Guaranteed by design but not tasted. Nate 5: Sample tested at +25C to ensure compliance MU AAISVI a crpSZxWMX7542 CMOS P-Compatible 12-Bit DAC Detailed Description The basic MX7542 DAG circuit consists of a laser- trimmed, thin-film R-2R resistor array with NMOS current switches as shown in Figure 1. Binarily weighted currents are switched to either OUT1 or OUT? depending on the status of each input bit. Although the current at QUT1 or OUT2 will depend on the digital input code, the sum of the two output currents is always equal to the input current at Voe- minus the termination resistor current (Ry). Either current output can be converted into a valtage externally by adding an output amplifier (Figure 4). The Vee, input accepts a wide range of signals in- cluding fixed and time varying voltage or current inputs, If a current source is used for the reference mput, then a low temperature coefficient external resistor shauld be used for Reg to minimize gain variation with temperature. Equivalent Circuit Analysis Figures 2 and 3 show the equivalent circuits for the R-2R ladder when all digital inputs are LOW and HIGH respectively. The input resistance at Vper is nominally 15kQ and does not change with digital input code. The Ipep4096 current source. which is actually the ladder termination resistor (Ry7, Figure 1), results in an intentional 1-bit current loss to GND. The lieakace Current Sources represent junction and surface Jeakage currents. Capacitors Cay, and Coys, represent the switches ON and OFF capacitances respectively. When all inputs are switched from LOW to HIGH, the capaci- tance at OUT1 changes from approximately 7SpF to 260pF. This capacitance is code-dependent and is a function of the number of ON switches that are con- nected to a specific output. Vaer a0K Tar + Ld BIT 1 (MSB) BI BIT3 ~ BIT N (LSB) | Switches Shown For Inputs High Figure 1. MX7542 Functional Diagram ___ Circuit Configurations Unipolar Operation The most common configuration for the Mx7542 is shown In Figure 4. The circuit is used for unipolar binary operation and/or 2-quadrant multiplication, The code table is given in Table 1. Note that the polarity of the output is the inverse of the reference input. In many applications, gain adjustment of the Mx7542 will not be necessary. In those cases, and also when gain is trimmed but only at the reference source, resistors R1 and R2 in Figure 4 can be omitted. However, if the trims are desired and the DAC is to operate over a wide temperature range, then low tempco (<300ppm/ C) resistors should be used at R1 and Re. - 15K VREF moe \ f IaeF REF 4096 * DOUT2 foqure 2 MxYSd2 DAC Equnvatent Crcutt, 40 Tigital tapubis LOW R= 15K VREF 4 ! > | IREF ir ~a Rep I we OUT Jer 1 260pF 4098 ig LEAKAGE T ouT2 te ILEAKAGE 7SpF HHO | Frquve 3) Mx F542? DAC Equivwlent Creu Al Diqvat inputs AHGH _, #VIAXIL 1CMOS uP-Compatible 12-Bit DAC +5 R2* 1OpF-33pF 15 - Vin LE Vrer Hl X11 ot Vout Al | Mx7542 OUT2/9 oO" WAAR OGND AGND MAX400 12 3 *TRIM RESISTOR JAS KrB/T Ae oan 1000 Ae 47 340 Pique 4. Untpolar Binary Operatian DGND AGN hE: 3 ; = + Sk? 10% TRIM | resistor | 2/5 | K/BrT Fl 1000 1900) L 2 47] aaa Figure 5, Bipotar Operaron (4-Quacrant Muinpication: Bipolar Operation With the circuit configuration in Figure 5, the Mx7542 operates in the bipolar, or 4-quadrant multiplying mode. A second amplifier and three matched resistors are required Matching to 0.01% is recommended for 12 bit performance. The code table for the output, which is offset binary, is listed in Table 2. In multi- plying applications, the MSB determines qutput po- larity while the other 11 bits control amplitude. AVIAXL/VI Table 1. Code Table Unipolar Binary DIGITAL INPUT MSB LSB ANALOG OUTPUT TT_tto1tt4o4444 -, 4098 REF \ 4096 1000 0009 oo08 V | 2048 | Vace oo ee] "FE ange | 2 1 cqo0o0 0000 o901 -Vaer sce | caqc0o 0000 ca00 ov Table 2. Code Table Bipolar (Offset Binary} Operation DIGITAL INPUT ' MSB LSB ; ANALOG OUTPUT \ t I ; 2047 | 171777949771 774141 +Vore 2048 | | \ 1900 00000001 Vier | | | 2048 | 1900 0000 0000 ov otitatat aids ( Yue | 2048 | i 90000000 00900 n= | Sa 2048 To adjust the circuit, load the DAC with a code of 1000 0000 0060 and trim R1 for a OV output. With R14 and R2 omitted, an alternative zero trim is ta adjust the ratio of R3 and R4 for OV out. Full scale can be trimmed by loading the DAC with all zeros ar all ones and adjusting the amplitude of Veep or varying RS until the desired positive or negative output is obtained. If gain and offset trims are not required, Ri and R2 in Figure 5 can be omitted. crpSZxXWMX7542 CMOS .P-Compatiblie 12-Bit DAC interface Logic interface Lagic information The MX7542 Truth Table is shown in Table 3. The high, middle and low byte, 4 bit data registers are loaded separately. The 12-bit DAC register is then loaded with the contents of the 3 data registers. The interface timing (Figure 6) is the same as writing to static RAM. The CLR input asynchronously resets the 12-Bit DAC Register to Code 0000 0000 0000. In a unipolar mode the DAC output will be set to 0 volts. In the bipolar mode a CLA input resets the DAC output to -Vper. Notes: 1. 1 indicates logic HIGH O indicates logic LOW 3. X indicates don't care 4 7 indicates LOW to HIGH transition 5 MSB XXXX XXXX -XXXX ~ LSB high middle low byte byte byte 6 These control signals are level triggered. Table 3. MX7542 Truth Table MX7542 Control Inputs a a MX7542 Operation A, | A, | CS | WR CLR XxX: x x G Resets DAC 12-Bit Register to Code 0000 G000 0000 No Operation Device Not Selected | XIX 1 x 1 Data Register On Edge As Shown 1 | Load 12-Bit DAC Register With Data In LOW Byte. MIOBLE Byte & HIGH Byte Data 6/o} a f 1 | Load LOW Byte ' Data Register On Edge As Shown Load 0} 1] 0 |g] + [Load MIDDLE Byte" APPICable Data Register On Rearste | Edge As Shawn gster + With Data , i/o] 9 i 1 |Load HIGH Byte | At O,-D, LT Registers |_~___ ADDRESS BUS VALID+ A0-At AN (PINS 10. 11) Vin | | late] tats | cs | (PIN 44 = lows \<~_ 'ow | WR ! | ~e fas |<| tap 03-0 Vir (PINS 47} Vit DATA BUS 'VaLio NOTE TIMING MPASUREMENT AEFERENCE LEVEL IS V4 - Vu Pura fo MNES? Trning Magram WU A AL/VICMOS P-Compatible 12-Bit DAC _. _..... Application information Output Amplifier Offset For best linearity, OUT1 and OUT2 should be termi- nated exactly OV In most applications OUT1 is con- nected to the summing junction Gf an inverting op- amp. The amplifiers input offset voltage can degrade the linearity of the DAC by causing OUT? to be terminated to a non-zero voltage. The resulting error is: Error Voltage = Vos(1 + Reg/Ro). where Vag is the op-amps Offset voltage and Ra 1s the output resistance of tne DAC. Ry is a function of the digital input code, and varies from appraximately i5kO to 45kO. The error voltage range is then typically 4/3V 9g to 2Vog, a change of 2/3Ve6.. An amplifier with 3m of offset will therefore degrade the linearity by 2mv, almost a fuli LSB with a 10V reference voltage. For best linearity, a low-offset amplifier such as the MAX400 should be used, or the amplifier offset must be trimmed to zero A good rule of thumb is that V5, should be no more than 1/10 of an LSB's value. The output amplifier input biaS current (Ig) can also limit performance since I, * Reg generates an offset error, ly should therefore be much less than the DAC output current for 1 LSB, typically 250nA with Va_, ~ 10V. One tenth of this value, 25nA, is recommended. Offset and linearity can also be impaired if the output amplifiers noninverting input is grounded through a bias current campensation resistor. This resistor adds to offset at this pin and should not be used. Best performance is obtained when the noninverting input ig directly cannected ta ground. Dynamic Considerations In static or DC applications, the AC characteristics of the output amplifier are not critical. In higher speed applications. where either the reference input is an AC signal or the DAC output must quickly settle to a new programmed value, the AC parameters of the output op-amp must be considered. Another error source in dynamic applications is para- sitic coupling of signal from the Voep terminal to OUT1 or OUT2. This is normally a function of board layout and package lead-to-lead capacitance. Signals can also be injected into the DAC outputs when the digital inputs are switched. This digital feedthrough is usually dependent on circuit board layout and on- chip capacitive coupling. Layout induced feedthraugh can he winimized with guard traces between digital inputs, Vere, and the DAC outputs. AVLAXLAVI - - Compensations A compensation capacitor, C1, may be needed when the DAC is used with a high speed output amplitier. The purpose of the capacitor is ta cancel the pale formed by the DACs output capacitance and internal feedback resistance. its value depends on the type of Op-amp used but typical values range fram 10 to 33pF. Too small a value causes cutput ringing while excess capacitance overdamps the output. The size of Ct can be minimized, and output settling perform- ance improved, by keeping the PC board trace and stray capacitance at OUT1 as small as possible. Grounding and Bypassing Since OUT1, OUT2 and the output amps noninverting inputs are sensitive to offset voltages, nodes that are ta be grounded should be connected directly ts single point ground through a separate, very low resistance (less than 0.20) path. The current at OUT1 and OUT? varies with input code, creating a code dependent error if these terminals are connected to ground (or a virtual ground) through a resistive path & 1uF bypass capacitor. in parallel with a 0.01pF ceramic cap, should be connected as close ta the DAC's V5 and GND pins as possible. The MxX7542 has high-impedance digital inpuls To minimize noise pick-up, they should be tied to either Voo or GND when not used. 11 is also good practice to connect active inputs ta Va, or GND thraugh high valued resistars (1MOQ} to prevent static charge accumulation if these pins are left floating, such as when a circuit card is left unconnected. __ Chip Topography 40 14. 12 nN Yoo cLA CGND Ai VREF 15 J Rre 16 _ 100 254mm Out 1 OuT2 2 AGND Yo3 ePSZXW