Micron Serial NOR Flash Memory
3V, Multiple I/O, 4KB, 32KB, 64KB, Sector Erase
MT25QL512ABB
Features
• SPI-compatible serial bus interface
• Single and double transfer rate (STR/DTR)
• Clock frequency
– 133 MHz (MAX) for all protocols in STR
– 90 MHz (MAX) for all protocols in DTR
• Dual/quad I/O commands for increased through-
put up to 90 MB/s
• Supported protocols in both STR and DTR
– Extended I/O protocol
– Dual I/O protocol
– Quad I/O protocol
• Execute-in-place (XIP)
• PROGRAM/ERASE SUSPEND operations
• Volatile and nonvolatile configuration settings
• Software reset
• Reset pin available
• 3-byte and 4-byte address modes – enable memory
access beyond 128Mb
• Dedicated 64-byte OTP area outside main memory
– Readable and user-lockable
– Permanent lock with PROGRAM OTP command
• Erase capability
– Bulk erase
– Sector erase 64KB uniform granularity
– Subsector erase 4KB, 32KB granularity
• Security and write protection
– Volatile and nonvolatile locking and software
write protection for each 64KB sector
– Nonvolatile configuration locking
– Password protection
– Hardware write protection: nonvolatile bits
(BP[3:0] and TB) define protected area size
– Program/erase protection during power-up
– CRC detects accidental changes to raw data
• Electronic signature
– JEDEC-standard 3-byte signature (BA20h)
– Extended device ID: two additional bytes identify
device factory options
• JESD47H-compliant
– Minimum 100,000 ERASE cycles per sector
– Data retention: 20 years (TYP)
Options Marking
• Voltage
– 2.7–3.6V L
• Density
– 512Mb 512
• Device stacking
– Monolithic A
• Device generation B
• Die revision B
• Pin configuration
– HOLD# 1
– RESET# and HOLD# 8
• Sector Size
– 64KB E
• Packages – JEDEC-standard, RoHS-
compliant
– 24-ball T-PBGA 05/6mm × 8mm
(TBGA24)
12
– 16-pin SOP2, 300 mil
(SO16W, SO16-Wide, SOIC-16)
SF
– W-PDFN-8 8mm × 6mm
(MLP8 8mm × 6mm)
W9
• Security features
– Standard security 0
• Special options
– Standard S
– Automotive A
• Operating temperature range
– From –40°C to +85°C IT
– From –40°C to +105°C AT
– From –40°C to +125°C UT
512Mb, 3V Multiple I/O Serial Flash Memory
Features
09005aef864f8d51
MT25Q_QLKT_L_512_ABB_0.pdf - Rev. F 1/18 EN 1Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Part Number Ordering
Micron Serial NOR Flash devices are available in different configurations and densities. Verify valid part numbers
by using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,
visit www.micron.com/products. Contact the factory for devices not found.
Figure 1: Part Number Ordering Information
Production Status
Blank = Production
ES = Engineering samples
QS = Qualification samples
Operating Temperature
IT = –40°C to +85°C
AT = –40°C to +105°C
UT = –40°C to +125°C
Special Options
S = Standard
A = Automotive grade AEC-Q100
Security Features
0 = Standard default security
Package Codes
12 = 24-ball T-PBGA, 05/6 x 8mm (5 x 5 array)
14 = 24-ball T-PBGA, 05/6 x 8mm (4 x 6 array)
SC = 8-pin SOP2, 150 mil
SE = 8-pin SOP2, 208 mil
SF = 16-pin SOP2, 300 mil
W7 = 8-pin W-PDFN, 6 x 5mm
W9 = 8-pin W-PDFN, 8 x 6mm
5x = WLCSP package 1
Sector size
E = 64KB sectors, 4KB and 32KB sub-sectors
Micron Technology
Part Family
25Q = SPI NOR
Voltage
L = 2.7–3.6V
U = 1.7–2.0V
Density
064 = 64Mb (8MB)
128 = 128Mb (16MB)
256 = 256Mb (32MB)
512 = 512Mb (64MB)
01G = 1Gb (128MB)
02G = 2Gb (256MB)
Stack
A = 1 die/1 S#
B = 2 die/1 S#
C = 4 die/1 S#
Device Generation
B = 2nd generation
Die Revision
A = Rev. A
B = Rev. B
Pin Configuration Option
1 = HOLD# pin
3 = RESET# pin
8 = RESET# and HOLD# pin
MT 25Q L xxx A BA 1 E SF IT0- S ES
Note: 1. WLCSP package codes, package size, and
availability are density-specific. Contact the
factory for availability.
512Mb, 3V Multiple I/O Serial Flash Memory
Features
09005aef864f8d51
MT25Q_QLKT_L_512_ABB_0.pdf - Rev. F 1/18 EN 2Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Contents
Important Notes and Warnings ......................................................................................................................... 9
Device Description ......................................................................................................................................... 10
Device Logic Diagram ................................................................................................................................. 11
Advanced Security Protection ..................................................................................................................... 11
Signal Assignments – Package Code: 12 ........................................................................................................... 12
Signal Assignments – Package Code: SF ........................................................................................................... 13
Signal Assignments – Package Code: W9 .......................................................................................................... 13
Signal Descriptions ......................................................................................................................................... 14
Package Dimensions – Package Code: 12 ......................................................................................................... 16
Package Dimensions – Package Code: SF ......................................................................................................... 17
Package Dimensions – Package Code: W9 ........................................................................................................ 18
Memory Map – 512Mb Density ....................................................................................................................... 19
Status Register ................................................................................................................................................ 20
Block Protection Settings ............................................................................................................................ 21
Flag Status Register ......................................................................................................................................... 22
Extended Address Register .............................................................................................................................. 23
Internal Configuration Register ....................................................................................................................... 24
Nonvolatile Configuration Register .................................................................................................................. 25
Volatile Configuration Register ........................................................................................................................ 27
Supported Clock Frequencies ..................................................................................................................... 28
Enhanced Volatile Configuration Register ........................................................................................................ 31
Security Registers ........................................................................................................................................... 32
Sector Protection Security Register .................................................................................................................. 33
Nonvolatile and Volatile Sector Lock Bits Security ............................................................................................ 34
Volatile Lock Bit Security Register .................................................................................................................... 34
Device ID Data ............................................................................................................................................... 35
Serial Flash Discovery Parameter Data ............................................................................................................. 36
Command Definitions .................................................................................................................................... 37
Software RESET Operations ............................................................................................................................ 43
RESET ENABLE and RESET MEMORY Commands ....................................................................................... 43
READ ID Operations ....................................................................................................................................... 44
READ ID and MULTIPLE I/O READ ID Commands ...................................................................................... 44
READ SERIAL FLASH DISCOVERY PARAMETER Operation .............................................................................. 45
READ SERIAL FLASH DISCOVERY PARAMETER Command ......................................................................... 45
READ MEMORY Operations ............................................................................................................................ 46
4-BYTE READ MEMORY Operations ................................................................................................................ 47
READ MEMORY Operations Timings ............................................................................................................... 48
WRITE ENABLE/DISABLE Operations ............................................................................................................. 55
READ REGISTER Operations ........................................................................................................................... 56
WRITE REGISTER Operations ......................................................................................................................... 57
CLEAR FLAG STATUS REGISTER Operation ..................................................................................................... 59
PROGRAM Operations .................................................................................................................................... 60
4-BYTE PROGRAM Operations ........................................................................................................................ 61
PROGRAM Operations Timings ....................................................................................................................... 61
ERASE Operations .......................................................................................................................................... 64
SUSPEND/RESUME Operations ..................................................................................................................... 66
PROGRAM/ERASE SUSPEND Operations .................................................................................................... 66
PROGRAM/ERASE RESUME Operations ...................................................................................................... 66
ONE-TIME PROGRAMMABLE Operations ....................................................................................................... 68
READ OTP ARRAY Command ...................................................................................................................... 68
512Mb, 3V Multiple I/O Serial Flash Memory
Features
09005aef864f8d51
MT25Q_QLKT_L_512_ABB_0.pdf - Rev. F 1/18 EN 3Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
PROGRAM OTP ARRAY Command .............................................................................................................. 68
ADDRESS MODE Operations .......................................................................................................................... 70
ENTER and EXIT 4-BYTE ADDRESS MODE Command ................................................................................ 70
DEEP POWER-DOWN Operations ................................................................................................................... 71
ENTER DEEP POWER-DOWN Command .................................................................................................... 71
RELEASE FROM DEEP POWER-DOWN Command ....................................................................................... 71
DEEP POWER-DOWN Timings .................................................................................................................... 72
QUAD PROTOCOL Operations ........................................................................................................................ 74
ENTER or RESET QUAD INPUT/OUTPUT MODE Command ....................................................................... 74
CYCLIC REDUNDANCY CHECK Operations .................................................................................................... 75
State Table ..................................................................................................................................................... 77
XIP Mode ....................................................................................................................................................... 78
Activate and Terminate XIP Using Volatile Configuration Register ................................................................. 78
Activate and Terminate XIP Using Nonvolatile Configuration Register .......................................................... 78
Confirmation Bit Settings Required to Activate or Terminate XIP .................................................................. 79
Terminating XIP After a Controller and Memory Reset ................................................................................. 79
Power-Up and Power-Down ............................................................................................................................ 80
Power-Up and Power-Down Requirements .................................................................................................. 80
Active, Standby, and Deep Power-Down Modes ................................................................................................ 82
Power Loss and Interface Rescue ..................................................................................................................... 83
Recovery .................................................................................................................................................... 83
Power Loss Recovery ................................................................................................................................... 83
Interface Rescue ......................................................................................................................................... 83
Initial Delivery Status ..................................................................................................................................... 84
Absolute Ratings and Operating Conditions ..................................................................................................... 85
DC Characteristics and Operating Conditions .................................................................................................. 87
AC Characteristics and Operating Conditions .................................................................................................. 89
AC Reset Specifications ................................................................................................................................... 92
Program/Erase Specifications ......................................................................................................................... 96
Revision History ............................................................................................................................................. 97
Rev. F - 1/18 ............................................................................................................................................... 97
Rev. E – 06/17 ............................................................................................................................................. 97
Rev. D – 06/16 ............................................................................................................................................. 97
Rev. C – 06/16 ............................................................................................................................................. 97
Rev. B – 02/16 ............................................................................................................................................. 97
Rev. A – 06/15 ............................................................................................................................................. 97
512Mb, 3V Multiple I/O Serial Flash Memory
Features
09005aef864f8d51
MT25Q_QLKT_L_512_ABB_0.pdf - Rev. F 1/18 EN 4Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
List of Figures
Figure 1: Part Number Ordering Information .................................................................................................... 2
Figure 2: Block Diagram ................................................................................................................................ 10
Figure 3: Logic Diagram ................................................................................................................................. 11
Figure 4: 24-Ball T-BGA, 5 × 5 (Balls Down) ..................................................................................................... 12
Figure 5: 16-Pin, Plastic Small Outline – SO16 (Top View) ................................................................................ 13
Figure 6: 8-Pin, W-PDFN (Top View) .............................................................................................................. 13
Figure 7: 24-Ball T-PBGA (5 × 5 ball grid array) – 6mm × 8mm ......................................................................... 16
Figure 8: 16-Pin SOP2 – 300 mil Body Width ................................................................................................... 17
Figure 9: W-PDFN-8 (MLP8) – 8mm × 6mm .................................................................................................... 18
Figure 10: Memory Array Segments ................................................................................................................ 23
Figure 11: Internal Configuration Register ...................................................................................................... 24
Figure 12: Sector and Password Protection ..................................................................................................... 32
Figure 13: RESET ENABLE and RESET MEMORY Command ........................................................................... 43
Figure 14: READ ID and MULTIPLE I/O READ ID Commands ......................................................................... 44
Figure 15: READ SERIAL FLASH DISCOVERY PARAMETER Command – 5Ah ................................................... 45
Figure 16: READ – 03h/13h3 ........................................................................................................................... 48
Figure 17: FAST READ – 0Bh/0Ch3 ................................................................................................................. 48
Figure 18: DUAL OUTPUT FAST READ – 3Bh/3Ch3 ......................................................................................... 49
Figure 19: DUAL INPUT/OUTPUT FAST READ – BBh/BCh3 ............................................................................ 49
Figure 20: QUAD OUTPUT FAST READ – 6Bh/6Ch3 ........................................................................................ 50
Figure 21: QUAD INPUT/OUTPUT FAST READ – EBh/ECh3 ............................................................................ 50
Figure 22: QUAD INPUT/OUTPUT WORD READ – E7h3 ................................................................................. 51
Figure 23: DTR FAST READ – 0Dh/0Eh3 .......................................................................................................... 52
Figure 24: DTR DUAL OUTPUT FAST READ – 3Dh3 ........................................................................................ 52
Figure 25: DTR DUAL INPUT/OUTPUT FAST READ – BDh3 ............................................................................ 53
Figure 26: DTR QUAD OUTPUT FAST READ – 6Dh3 ........................................................................................ 54
Figure 27: DTR QUAD INPUT/OUTPUT FAST READ – EDh3 ............................................................................ 54
Figure 28: WRITE ENABLE and WRITE DISABLE Timing ................................................................................. 55
Figure 29: READ REGISTER Timing ................................................................................................................ 56
Figure 30: WRITE REGISTER Timing .............................................................................................................. 58
Figure 31: CLEAR FLAG STATUS REGISTER Timing ........................................................................................ 59
Figure 32: PAGE PROGRAM Command .......................................................................................................... 61
Figure 33: DUAL INPUT FAST PROGRAM Command ...................................................................................... 62
Figure 34: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 62
Figure 35: QUAD INPUT FAST PROGRAM Command ..................................................................................... 63
Figure 36: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 63
Figure 37: SUBSECTOR and SECTOR ERASE Timing ....................................................................................... 65
Figure 38: BULK ERASE Timing ...................................................................................................................... 65
Figure 39: PROGRAM/ERASE SUSPEND and RESUME Timing ........................................................................ 67
Figure 40: READ OTP Command Timing ........................................................................................................ 68
Figure 41: PROGRAM OTP Command Timing ................................................................................................. 69
Figure 42: ENTER DEEP POWER-DOWN Timing ............................................................................................. 72
Figure 43: RELEASE FROM DEEP POWER-DOWN Timing ............................................................................... 73
Figure 44: XIP Mode Directly After Power-On .................................................................................................. 78
Figure 45: Power-Up Timing .......................................................................................................................... 81
Figure 46: AC Timing Input/Output Reference Levels ...................................................................................... 86
Figure 47: Reset AC Timing During PROGRAM and ERASE Cycle ..................................................................... 93
Figure 48: Reset Enable and Reset Memory Timing ......................................................................................... 93
Figure 49: Serial Input Timing STR ................................................................................................................. 93
Figure 50: Serial Input Timing DTR ................................................................................................................ 94
512Mb, 3V Multiple I/O Serial Flash Memory
Features
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MT25Q_QLKT_L_512_ABB_0.pdf - Rev. F 1/18 EN 5Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Figure 51: Write Protect Setup and Hold During WRITE STATUS REGISTER Operation (SRWD = 1) ................... 94
Figure 52: Hold Timing .................................................................................................................................. 94
Figure 53: Output Timing for STR ................................................................................................................... 95
Figure 54: Output Timing for DTR .................................................................................................................. 95
512Mb, 3V Multiple I/O Serial Flash Memory
Features
09005aef864f8d51
MT25Q_QLKT_L_512_ABB_0.pdf - Rev. F 1/18 EN 6Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
List of Tables
Table 1: Signal Descriptions ........................................................................................................................... 14
Table 2: Memory Map .................................................................................................................................... 19
Table 3: Status Register .................................................................................................................................. 20
Table 4: Protected Area .................................................................................................................................. 21
Table 5: Flag Status Register ........................................................................................................................... 22
Table 6: Extended Address Register ................................................................................................................ 23
Table 7: Nonvolatile Configuration Register .................................................................................................... 25
Table 8: Volatile Configuration Register .......................................................................................................... 27
Table 9: Sequence of Bytes During Wrap ......................................................................................................... 27
Table 10: Clock Frequencies – STR (in MHz) for IT and AT parts ...................................................................... 28
Table 11: Clock Frequencies – STR (in MHz) for UT parts ................................................................................ 28
Table 12: Clock Frequencies – DTR (in MHz) for IT and AT parts ...................................................................... 29
Table 13: Clock Frequencies – DTR (in MHz) for UT parts ............................................................................... 29
Table 14: Enhanced Volatile Configuration Register ........................................................................................ 31
Table 15: Sector Protection Register ............................................................................................................... 33
Table 16: Global Freeze Bit ............................................................................................................................. 33
Table 17: Nonvolatile and Volatile Lock Bits .................................................................................................... 34
Table 18: Volatile Lock Bit Register ................................................................................................................. 34
Table 19: Device ID Data ............................................................................................................................... 35
Table 20: Extended Device ID Data, First Byte ................................................................................................. 35
Table 21: Command Set ................................................................................................................................. 37
Table 22: RESET ENABLE and RESET MEMORY Operations ............................................................................ 43
Table 23: READ ID and MULTIPLE I/O READ ID Operations ........................................................................... 44
Table 24: READ MEMORY Operations ............................................................................................................ 46
Table 25: 4-BYTE READ MEMORY Operations ................................................................................................ 47
Table 26: WRITE ENABLE/DISABLE Operations ............................................................................................. 55
Table 27: READ REGISTER Operations ........................................................................................................... 56
Table 28: WRITE REGISTER Operations .......................................................................................................... 57
Table 29: CLEAR FLAG STATUS REGISTER Operation ..................................................................................... 59
Table 30: PROGRAM Operations .................................................................................................................... 60
Table 31: 4-BYTE PROGRAM Operations ........................................................................................................ 61
Table 32: ERASE Operations ........................................................................................................................... 64
Table 33: SUSPEND/RESUME Operations ...................................................................................................... 66
Table 34: OTP Control Byte (Byte 64) .............................................................................................................. 69
Table 35: ENTER and EXIT 4-BYTE ADDRESS MODE Operations .................................................................... 70
Table 36: DEEP POWER-DOWN Operations .................................................................................................... 71
Table 37: ENTER and RESET QUAD PROTOCOL Operations ............................................................................ 74
Table 38: CRC Command Sequence on Entire Device ...................................................................................... 75
Table 39: CRC Command Sequence on a Range .............................................................................................. 76
Table 40: Operations Allowed/Disallowed During Device States ...................................................................... 77
Table 41: XIP Confirmation Bit ....................................................................................................................... 79
Table 42: Effects of Running XIP in Different Protocols .................................................................................... 79
Table 43: Power-Up Timing and VWI Threshold ............................................................................................... 81
Table 44: Absolute Ratings ............................................................................................................................. 85
Table 45: Operating Conditions ...................................................................................................................... 85
Table 46: Input/Output Capacitance .............................................................................................................. 85
Table 47: AC Timing Input/Output Conditions ............................................................................................... 86
Table 48: DC Current Characteristics and Operating Conditions ...................................................................... 87
Table 49: DC Voltage Characteristics and Operating Conditions ...................................................................... 88
Table 50: Max frequency supported ................................................................................................................ 89
512Mb, 3V Multiple I/O Serial Flash Memory
Features
09005aef864f8d51
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© 2013 Micron Technology, Inc. All rights reserved.
Table 51: AC Characteristics and Operating Conditions ................................................................................... 89
Table 52: AC RESET Conditions ...................................................................................................................... 92
Table 53: Program/Erase Specifications .......................................................................................................... 96
512Mb, 3V Multiple I/O Serial Flash Memory
Features
09005aef864f8d51
MT25Q_QLKT_L_512_ABB_0.pdf - Rev. F 1/18 EN 8Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Important Notes and Warnings
Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-
ment if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-
cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-
utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-
automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-
ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-
demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo-
nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-
mental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-
cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-
URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-
vironmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.
512Mb, 3V Multiple I/O Serial Flash Memory
Important Notes and Warnings
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MT25Q_QLKT_L_512_ABB_0.pdf - Rev. F 1/18 EN 9Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Device Description
The MT25Q is a high-performance multiple input/output serial Flash memory device. It
features a high-speed SPI-compatible bus interface, execute-in-place (XIP) functionali-
ty, advanced write protection mechanisms, and extended address access. Innovative,
high-performance, dual and quad input/output commands enable double or quadru-
ple the transfer bandwidth for READ and PROGRAM operations.
Figure 2: Block Diagram
HOLD#
S#
W# Control logic High voltage
generator
Memory
Address register
and counter
256 byte
data buffer
256 bytes (page size)
X decoder
Y decoder
C
Status
register
64 OTP bytes
I/O shift register
DQ0
DQ1
DQ2
DQ3
RESET#
Note: 1. Each page of memory can be individually programmed, but the device is not page-eras-
able.
512Mb, 3V Multiple I/O Serial Flash Memory
Device Description
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© 2013 Micron Technology, Inc. All rights reserved.
Device Logic Diagram
Figure 3: Logic Diagram
DQ[3:0]
VCC
C
VSS
S#
W#
RESET#
HOLD#
Notes: 1. Depending on the selected device (see Part Numbering Ordering Information), DQ3 =
DQ3/RESET# or DQ3/HOLD#.
2. A separate RESET pin is available on dedicated part numbers (see Part Numbering Order-
ing Information).
Advanced Security Protection
The device offers an advanced security protection scheme where each sector can be in-
dependently locked, by either volatile or nonvolatile locking features. The nonvolatile
locking configuration can also be locked, as well password-protected. See Block Protec-
tion Settings and Sector and Password Protection for more details.
512Mb, 3V Multiple I/O Serial Flash Memory
Device Description
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MT25Q_QLKT_L_512_ABB_0.pdf - Rev. F 1/18 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Signal Assignments – Package Code: 12
Figure 4: 24-Ball T-BGA, 5 × 5 (Balls Down)
A
B
C
D
E
1 2 3 4 5
MT25QXXXXXXX8E12-XXXX
RESET#
DQ3/HOLD#
NC RFU
VSS
RFU
RFU
A
B
C
D
E
1 2 3 4 5
MT25QXXXXXXX1E12-XXXX
DNU
W#/DQ2
VCC
DQ3/HOLD#
VSS
DQ0
A
B
C
D
E
1 2 3 4 5
MT25QXXXXXXX3E12-XXXX
DNU
W#/DQ2
VCC
DQ3/RESET#
VSS
DQ0
RFU
RFU
RFU RFU RFU RFU RFU
RFU
RFU
RFUC
W#/DQ2
VCC
S#
DQ0
RFU
DQ1
NC RFU RFU
RFU
RFU
RFU
RFU RFU RFU RFU RFU
CRFU
S# RFU RFU
DQ1 RFU
NC RFU RFU
RFU
RFU
RFU
RFU
RFU RFU RFU RFU
RFU
RFU
RFU C
S# RFU
DQ1
Notes: 1. RESET# or HOLD# signals can share Ball D4 with DQ3, depending on the selected device
(see Part Numbering Ordering Information). When using single and dual I/O commands
on these parts, DQ3 must be driven high by the host, or an external pull-up resistor must
be placed on the PCB, in order to avoid allowing the HOLD# or RESET# input to float.
2. Ball A4 = RESET# or DNU, depending on the part number. This signal has an internal
pull-up resistor and may be left unconnected if not used.
512Mb, 3V Multiple I/O Serial Flash Memory
Signal Assignments – Package Code: 12
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Signal Assignments – Package Code: SF
Figure 5: 16-Pin, Plastic Small Outline – SO16 (Top View)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C
DQ0
VSS
W#/DQ2
DQ3/HOLD#
VCC
RESET#
DNU
DNU
DNU
DNU
DNU
DNU
DNU
C
DQ0
VSS
W#/DQ2
DNU
DNU
DNU
DNU
C
DQ0
VSS
W#/DQ2
DNU
DNU
DNU
DNU
S#
DQ1
DQ3/HOLD#
VCC
DNU
DNU
DNU
DNU
S#
DQ1
DQ3/RESET#
VCC
DNU
DNU
DNU
DNU
S#
DQ1
MT25QXXXXXXX8EXX-XXXX
MT25QXXXXXXX3EXX-XXXX
MT25QXXXXXXX1EXX-XXXX
Notes: 1. RESET# or HOLD# signals can share Pin 1 with DQ3, depending on the selected device
(see Part Numbering Ordering Information). When using single and dual I/O commands
on these parts, DQ3 must be driven high by the host, or an external pull-up resistor must
be placed on the PCB, in order to avoid allowing the HOLD# or RESET# input to float.
2. Pin 3 = RESET# or DNU, depending on the part number. This signal has an internal pull-
up resistor and may be left unconnected if not used.
Signal Assignments – Package Code: W9
Figure 6: 8-Pin, W-PDFN (Top View)
1
2
3
4
8
7
6
5
S#
DQ1
W#/DQ2
VSS
MT25QXXXXXXX1EXX-XXXX
MT25QXXXXXXX3EXX-XXXX
S#
DQ1
W#/DQ2
VSS
VCC
DQ3/HOLD#
C
DQ0
VCC
DQ3/RESET#
C
DQ0
Notes: 1. RESET# or HOLD# signals can share Pin 7 with DQ3, depending on the selected device
(see Part Numbering Ordering Information). When using single and dual I/O commands
on these parts, DQ3 must be driven high by the host, or an external pull-up resistor must
be placed on the PCB, in order to avoid allowing the HOLD# or RESET# input to float.
2. On the underside of the W-PDFN package, there is an exposed central pad that is pulled
internally to VSS. It can be left floating or can be connected to VSS. It must not be con-
nected to any other voltage or signal line on the PCB.
3. MT25QXXXXXXX8EXX-XXXX not available on 8 pin package
512Mb, 3V Multiple I/O Serial Flash Memory
Signal Assignments – Package Code: SF
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Signal Descriptions
The signal description table below is a comprehensive list of signals for the MT25Q fam-
ily devices. All signals listed may not be supported on this device. See Signal Assign-
ments for information specific to this device.
Table 1: Signal Descriptions
Symbol Type Description
S# Input Chip select: When S# is driven HIGH, the device will enter standby mode, unless an internal
PROGRAM, ERASE, or WRITE STATUS REGISTER cycle is in progress. All other input pins are ig-
nored and the output pins are tri-stated. On parts with the pin configuration offering a dedica-
ted RESET# pin, however, the RESET# input pin remains active even when S# is HIGH.
Driving S# LOW enables the device, placing it in the active mode.
After power-up, a falling edge on S# is required prior to the start of any command.
C Input Clock: Provides the timing of the serial interface. Command inputs are latched on the rising
edge of the clock. In STR commands or protocol, address and data inputs are latched on the
rising edge of the clock, while data is output on the falling edge of the clock. In DTR com-
mands or protocol, address and data inputs are latched on both edges of the clock, and data is
output on both edges of the clock.
RESET# Input RESET#: When RESET# is driven LOW, the device is reset and the outputs are tri-stated. If RE-
SET# is driven LOW while an internal WRITE, PROGRAM, or ERASE operation is in progress, da-
ta may be lost. The RESET# functionality can be disabled using bit 4 of the nonvolatile configu-
ration register or bit 4 of the enhanced volatile configuration register.
For pin configurations that share the DQ3 pin with RESET#, the RESET# functionality is disabled
in QIO-SPI mode.
HOLD# Input HOLD: Pauses serial communications with the device without deselecting or resetting the de-
vice. Outputs are tri-stated and inputs are ignored. The HOLD# functionality can be disabled
using bit 4 of the nonvolatile configuration register or bit 4 of the enhanced volatile configura-
tion register.
For pin configurations that share the DQ3 pin with HOLD#, the HOLD# functionality is disabled
in QIO-SPI mode or when DTR operation is enabled.
W# Input Write protect: Freezes the status register in conjunction with the enable/disable bit of the sta-
tus register. When the enable/disable bit of the status register is set to 1 and the W# signal is
driven LOW, the status register nonvolatile bits become read-only and the WRITE STATUS REG-
ISTER operation will not execute. During the extended-SPI protocol with QOFR and QIOFR in-
structions, and with QIO-SPI protocol, this pin function is an input/output as DQ2 functionality.
This signal does not have internal pull-ups, it cannot be left floating and must be driven, even
if none of W#/DQ2 function is used.
DQ[3:0] I/O Serial I/O: The bidirectional DQ signals transfer address, data, and command information.
When using legacy (x1) SPI commands in extended I/O protocol (XIO-SPI), DQ0 is an input and
DQ1 is an output. DQ[3:2] are not used.
When using dual commands in XIO-SPI or when using DIO-SPI, DQ[1:0] are I/O. DQ[3:2] are not
used.
When using quad commands in XIO-SPI or when using QIO-SPI, DQ[3:0] are I/O.
VCC Supply Core and I/O power supply.
512Mb, 3V Multiple I/O Serial Flash Memory
Signal Descriptions
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Table 1: Signal Descriptions (Continued)
Symbol Type Description
VSS Supply Core and I/O ground connection.
DNU – Do not use: Do not connect to any other signal, or power supply; must be left floating.
RFU – Reserved for future use: Reserved by Micron for future device functionality and enhance-
ment. Recommend that these be left floating. May be connected internally, but external con-
nections will not affect operation.
NC – No connect : No internal connection; can be driven or floated.
512Mb, 3V Multiple I/O Serial Flash Memory
Signal Descriptions
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Package Dimensions – Package Code: 12
Figure 7: 24-Ball T-PBGA (5 × 5 ball grid array) – 6mm × 8mm
0.3 ±0.05
1.1 ±0.1
4 CTR
6 ±0.1
1 TYP
8 ±0.1
1 TYP
Ball A1 IDBall A1 ID
Seating plane
0.1 A
A
24X Ø0.4
Dimensions
apply to solder
balls post-reflow
on Ø0.40 SMD
ball pads.
4 CTR
A
B
C
D
E
135 24
Notes: 1. All dimensions are in millimeters.
2. See Part Number Ordering Information for complete package names and details.
512Mb, 3V Multiple I/O Serial Flash Memory
Package Dimensions – Package Code: 12
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Package Dimensions – Package Code: SF
Figure 8: 16-Pin SOP2 – 300 mil Body Width
16
0.23 MIN/
0.32 MAX
18
9
0.40 MIN/
1.27 MAX
0.20 ±0.1
2.5 ±0.15
10.30 ±0.20
7.50 ±0.10
10.00 MIN/
10.65 MAX
0.33 MIN/
0.51 MAX
0.1 Z
0° MIN/8° MAX
1.27 TYP
h x 45°
Z
Notes: 1. All dimensions are in millimeters.
2. See Part Number Ordering Information for complete package names and details.
512Mb, 3V Multiple I/O Serial Flash Memory
Package Dimensions – Package Code: SF
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Package Dimensions – Package Code: W9
Figure 9: W-PDFN-8 (MLP8) – 8mm × 6mm
Seating plane
0.08 A
A
0 MIN
0.75 ±0.05
3.81
CTR
6 ±0.1
8X 0.5 ±0.05
8 ±0.1
1.27
TYP 8X 0.4 ±0.05
CTR
Pin A1 ID
4.3 ±0.1
CTR
3.4 ±0.1
CTR
Exposed die
attach pad.
Pin A1 ID
Micron logo
to be lazed.
4
3
2
1
5
6
7
8
Notes: 1. All dimensions are in millimeters.
2. See Part Number Ordering Information for complete package names and details.
512Mb, 3V Multiple I/O Serial Flash Memory
Package Dimensions – Package Code: W9
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Memory Map – 512Mb Density
Table 2: Memory Map
Sector Subsector (32KB) Subsector (4KB)
Address Range
Start End
1023 2047 16383 03FF F000h 03FF FFFFh
⋮ ⋮ ⋮
16376 03FF 8000h 03FF 8FFFh
2046 16375 03FF 7000h 03FF 7FFFh
⋮ ⋮ ⋮
16368 03FF 0000h 03FF 0FFFh
⋮ ⋮ ⋮ ⋮ ⋮
511 1023 8191 01FF F000h 01FF FFFFh
⋮ ⋮ ⋮
8184 01FF 8000h 01FF 8FFFh
1022 8183 01FF 7000h 01FF 7FFFh
⋮ ⋮ ⋮
8176 01FF 0000h 01FF 0FFFh
⋮ ⋮ ⋮ ⋮ ⋮
255 511 4095 00FF F000h 00FF FFFFh
⋮ ⋮ ⋮
4088 00FF 8000h 00FF 8FFFh
510 4087 00FF 7000h 00FF 7FFFh
⋮ ⋮ ⋮
4080 00FF 0000h 00FF 0FFFh
⋮ ⋮ ⋮ ⋮ ⋮
0 1 15 0000 F000h 0000 FFFFh
⋮ ⋮ ⋮
8 0000 8000h 0000 8FFFh
0 7 0000 7000h 0000 7FFFh
⋮ ⋮ ⋮
0 0000 0000h 0000 0FFFh
Note: 1. See Part Number Ordering Information, Sector Size – Part Numbers table for options.
512Mb, 3V Multiple I/O Serial Flash Memory
Memory Map – 512Mb Density
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Status Register
Status register bits can be read from or written to using READ STATUS REGISTER or
WRITE STATUS REGISTER commands, respectively. When the status register enable/
disable bit (bit 7) is set to 1 and W# is driven LOW, the status register nonvolatile bits
become read-only and the WRITE STATUS REGISTER operation will not execute. The
only way to exit this hardware-protected mode is to drive W# HIGH.
Table 3: Status Register
Bit Name Settings Description Notes
7 Status register
write enable/disa-
ble
0 = Enabled (Default)
1 = Disabled
Nonvolatile control bit: Used with W# to enable or
disable writing to the status register.
5 Top/bottom 0 = Top (Default)
1 = Bottom
Nonvolatile control bit: Determines whether the pro-
tected memory area defined by the block protect bits
starts from the top or bottom of the memory array.
6, 4:2 BP[3:0] See Protected Area ta-
bles
Nonvolatile control bit: Defines memory to be soft-
ware protected against PROGRAM or ERASE operations.
When one or more block protect bits is set to 1, a desig-
nated memory area is protected from PROGRAM and
ERASE operations.
1
1 Write enable latch 0 = Clear (Default)
1 = Set
Volatile control bit: The device always powers up with
this bit cleared to prevent inadvertent WRITE, PRO-
GRAM, or ERASE operations. To enable these operations,
the WRITE ENABLE operation must be executed first to
set this bit.
0 Write in progress 0 = Ready (Default)
1 = Busy
Volatile status bit: Indicates if one of the following
command cycles is in progress:
WRITE STATUS REGISTER
WRITE NONVOLATILE CONFIGURATION REGISTER
PROGRAM
ERASE
2
Notes: 1. The BULK ERASE command is executed only if all bits = 0.
2. Status register bit 0 is the inverse of flag status register bit 7.
512Mb, 3V Multiple I/O Serial Flash Memory
Status Register
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Block Protection Settings
Table 4: Protected Area
Status Register Content Protected Area
Top/Bottom BP3 BP2 BP1 BP0 64KB Sectors
0 0 0 0 0 None
0 0 0 0 1 1023:1023
0 0 0 1 0 1023:1022
0 0 0 1 1 1023:1020
0 0 1 0 0 1023:1016
0 0 1 0 1 1023:1008
0 0 1 1 0 1023:992
0 0 1 1 1 1023:960
0 1 0 0 0 1023:896
0 1 0 0 1 1023:768
0 1 0 1 0 1023:512
0 1 0 1 1 1023:0
0 1 1 0 0 1023:0
0 1 1 0 1 1023:0
0 1 1 1 0 1023:0
0 1 1 1 1 1023:0
1 0 0 0 0 None
1 0 0 0 1 0:0
1 0 0 1 0 1:0
1 0 0 1 1 3:0
1 0 1 0 0 7:0
1 0 1 0 1 15:0
1 0 1 1 0 31:0
1 0 1 1 1 63:0
1 1 0 0 0 127:0
1 1 0 0 1 255:0
1 1 0 1 0 511:0
1 1 0 1 1 1023:0
1 1 1 0 0 1023:0
1 1 1 0 1 1023:0
1 1 1 1 0 1023:0
1 1 1 1 1 1023:0
512Mb, 3V Multiple I/O Serial Flash Memory
Status Register
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Flag Status Register
Flag status register bits are read by using READ FLAG STATUS REGISTER command. All
bits are volatile and are reset to zero on power-up.
Status bits are set and reset automatically by the internal controller. Error bits must be
cleared through the CLEAR STATUS REGISTER command.
Table 5: Flag Status Register
Bit Name Settings Description
7 Program or
erase
controller
0 = Busy
1 = Ready
Status bit: Indicates whether one of the following
command cycles is in progress: WRITE STATUS
REGISTER, WRITE NONVOLATILE CONFIGURATION
REGISTER, PROGRAM, or ERASE.
6 Erase suspend 0 = Clear
1 = Suspend
Status bit: Indicates whether an ERASE operation has been
or is going to be suspended.
5 Erase 0 = Clear
1 = Failure or protection error
Error bit: Indicates whether an ERASE operation has suc-
ceeded or failed.
4 Program 0 = Clear
1 = Failure or protection error
Error bit: Indicates whether a PROGRAM operation has suc-
ceeded or failed. It indicates, also, whether a CRC check has
succeeded or failed.
3 Reserved 0 Reserved
2 Program sus-
pend
0 = Clear
1 = Suspend
Status bit: Indicates whether a PROGRAM operation has
been or is going to be suspended.
1 Protection 0 = Clear
1 = Failure or protection error
Error bit: Indicates whether an ERASE or PROGRAM opera-
tion has attempted to modify the protected array sector, or
whether a PROGRAM operation has attempted to access the
locked OTP space.
0 Addressing 0 = 3-byte addressing
1 = 4-byte addressing
Status bit: Indicates whether 3-byte or 4-byte address
mode is enabled.
512Mb, 3V Multiple I/O Serial Flash Memory
Flag Status Register
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Extended Address Register
The 3-byte address mode can only access 128Mb of memory. To access the full device in
3-byte address mode, the device includes an extended address register that indirectly
provides a fourth address byte A[31:24]. The extended address register bits [1:0] operate
as memory address bit A[25:24] to select one of the four 128Mb segments of the memo-
ry array.
If 4-byte addressing is enabled, the extended address register settings are ignored.
Table 6: Extended Address Register
Bit Name Settings Description
7:2 A[31:26] 000000 Reserved
1:0 A[25:24] 11 = Highest 128Mb segment
10 = Third 128Mb segment
01 = Second 128Mb segment
00 = Lowest 128Mb segment (default)
Enables specified 128Mb memory segment. The de-
fault (lowest) setting can be changed to the high-
est 128Mb segment using bit 1 of the nonvolatile
configuration register.
Figure 10: Memory Array Segments
A[25:24] = 00
A[25:24] = 01
A[25:24] = 10
A[25:24] = 11
00FFFFFFh
00000000h
01FFFFFFh
01000000h
02FFFFFFh
02000000h
03FFFFFFh
03000000h
The PROGRAM and ERASE operations act upon the 128Mb segment selected in the ex-
tended address register. The BULK ERASE operation erases the entire device.
The READ operation begins reading in the selected 128Mb segment, but is not bound
by it.
In a continuous READ, when the last byte of the segment is read, the next byte output is
the first byte of the next segment. The operation wraps to 0000000h; therefore, a down-
load of the whole array is possible with one READ operation.
The value of the extended address register does not change when a READ operation
crosses the selected 128Mb boundary.
512Mb, 3V Multiple I/O Serial Flash Memory
Extended Address Register
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Internal Configuration Register
The memory configuration is set by an internal configuration register that is not directly
accessible to users.
The user can change the default configuration at power up by using the WRITE NON-
VOLATILE CONFIGURATION REGISTER. Information from the nonvolatile configura-
tion register overwrites the internal configuration register during power-on or after a re-
set.
The user can change the configuration during operation by using the WRITE VOLATILE
CONFIGURATION REGISTER or the WRITE ENHANCED VOLATILE CONFIGURATION
REGISTER commands. Information from the volatile configuration registers overwrite
the internal configuration register immediately after the WRITE command completes.
Figure 11: Internal Configuration Register
Register download is executed only during
the power-on phase or after a reset,
overwriting configuration register settings
on the internal configuration register.
Register download is executed after a
WRITE VOLATILE OR ENHANCED VOLATILE
CONFIGURATION REGISTER command,
overwriting configuration register
settings on the internal configuration register.
Nonvolatile configuration register
Internal configuration
register
Device behavior
Volatile configuration register and
enhanced volatile configuration register
512Mb, 3V Multiple I/O Serial Flash Memory
Internal Configuration Register
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Nonvolatile Configuration Register
This register is read from and written to using the READ NONVOLATILE CONFIGURA-
TION REGISTER and the WRITE NONVOLATILE CONFIGURATION REGISTER com-
mands, respectively. A register download is executed during power-on or after reset,
overwriting the internal configuration register settings that determine device behavior.
Table 7: Nonvolatile Configuration Register
Bit Name Settings Description Notes
15:12 Number of
dummy clock cy-
cles
0000 = Identical to 1111
0001 = 1
0010 = 2
⋮
1101 = 13
1110 = 14
1111 = Default
Sets the number of dummy clock cycles subse-
quent to all FAST READ commands.
(See the Command Set Table for default setting
values.)
1
11:9 XIP mode at
power-on reset
000 = XIP: Fast read
001 = XIP: Dual output fast read
010 = XIP: Dual I/O fast read
011 = XIP: Quad output fast read
100 = XIP: Quad I/O fast read
101 = Reserved
110 = Reserved
111 = Disabled (Default)
Enables the device to operate in the selected XIP
mode immediately after power-on reset.
8:6 Output driver
strength
000 = Reserved
001 = 90 Ohms
010 = Reserved
011 = 45 Ohms
100 = Reserved
101 = 20 Ohms
110 = Reserved
111 = 30 Ohms (Default)
Optimizes the impedance at VCC/2 output volt-
age.
5 Double transfer
rate protocol
0 = Enabled
1 = Disabled (Default)
Set DTR protocol as current one. Once enabled,
all commands will work in DTR.
4 Reset/hold 0 = Disabled
1 = Enabled (Default)
Enables or disables HOLD# or RESET# on DQ3.
3 Quad I/O
protocol
0 = Enabled
1 = Disabled (Default)
Enables or disables quad I/O command input
(4-4-4 mode).
2
2 Dual I/O
protocol
0 = Enabled
1 = Disabled (Default)
Enables or disables dual I/O command input
(2-2-2 mode).
2
1 128Mb
segment select
0 = Highest 128Mb segment
1 = Lowest 128Mb segment (De-
fault)
Selects the power-on default 128Mb segment for
3-byte address operations. See also the extended
address register.
512Mb, 3V Multiple I/O Serial Flash Memory
Nonvolatile Configuration Register
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Table 7: Nonvolatile Configuration Register (Continued)
Bit Name Settings Description Notes
0 Number of
address bytes
during command
entry
0 = Enable 4-byte address mode
1 = Enable 3-byte address mode
(Default)
Defines the number of address bytes for a com-
mand.
Notes: 1. The number of cycles must be set to accord with the clock frequency, which varies by the
type of FAST READ command (See Supported Clock Frequencies table). Insufficient dum-
my clock cycles for the operating frequency causes the memory to read incorrect data.
2. When bits 2 and 3 are both set to 0, the device operates in quad I/O protocol.
512Mb, 3V Multiple I/O Serial Flash Memory
Nonvolatile Configuration Register
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