SLE5518D - Infineon Technologies AG

Chip Card & Security ICs

SLE 5518

Intelligent 1024 Byte EEPROM

with Write Protection

Preliminary

Short Product Information November 2006

SLE 5518 Short Product Information, Preliminary

Revision History: Current Version 2006-11-24

Previous Releases:

Page Subjects (changes since last revision)

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Chip Card & Security ICs,

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E-Mail: security.chipcard.ics@infineon.com

Published by Infineon Technologies AG, AIM CC Applications Group

D-81726 München

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P R E L I M I N A R Y SLE 5518

Short Product Information 3 / 6 2006-11-24

Intelligent 1024 Byte EEPROM

with Write Protection

Features

• 100% functional compatibility to SLE 4418

• 1024 x 8 bit EEPROM organization of Data Memory

• 1024 x 1 bit Protection Memory

– Byte-wise write protection of Data Memory (one time programmable)

– Not alterable Manufacturer Code (chip coding and unique coding by application identifier

RID according to ISO/IEC 7816-5)

• Serial synchronous three-wire link protocol according to ISO 7816

– Byte-wise addressing

– End of processing indicated at data output

• Contact configuration and Answer-to-Reset (synchronous transmission) in accordance

to standard ISO/IEC 7816

• Electrical characteristics

– Ambient temperature range -40 … +100°C for chip, -25 … +80°C for module

– Supply voltage 5V ± 10%

– Supply current < 1mA

– EEPROM erase / write time 2.5ms / 2.5ms

– ESD protection typically 4,000V

– EEPROM Endurance minimum 10,000 erase / write cycles1)

– Data retention for minimum of 10 years1)

• Advanced CMOS-technology optimized for security layout

– EEPROM-cells protected by shield

– Shielding of deeper layers via metal

– Sensory- and logical security functions

– No insulation of backside necessary

1) Values are temperature dependent.

P R E L I M I N A R Y SLE 5518

Short Product Information 4 / 6 2006-11-24

1 Ordering and Packaging information

Table 1 Ordering Information

Type Package1) Remark Ordering Code

SLE 5518 C Die (on Wafer) not sawn on request

SLE 5518 D Die (on Wafer) Sawn on request

SLE 5518 M2 T-M2.2-6 on request

SLE 5518 M3 T-M3.2-6 on request

SLE 5518 MFC3 S-MFC3.1-6-1 FCoS™ on request

Pin Description

Figure 1 Pin Configuration Wire-bonded Module M3.2 (top view)

Figure 2 Pin Configuration Module Flip Chip MFC3.1 (top view)

1) Available as a Module Flip Chip (MFC3), wire-bonded module (M2 and M3) for embedding in plastic cards or as a die

on non-sawn (C) / sawn wafer (D) for customer packaging

P R E L I M I N A R Y SLE 5518

Short Product Information 5 / 6 2006-11-24

SLE 5518

GND

I/O

VCC

RST

CLK

Figure 1 Pad Configuration Die

Table 2 Pin Definitions and Functions M3 / MFC3

Card Contact Symbol Function

C1 VCC Supply voltage

C2 RST Reset (Chip Enable)

C3 CLK Clock input

C5 GND Ground

C6 N.C. Not connected

C7 I/O Bi-directional data line (open drain)

P R E L I M I N A R Y SLE 5518

Short Product Information 6 / 6 2006-11-24

2 Circuit Description

Memory Organization

The memory is organized in a Data Memory of 1024 byte.

Write Protection of Data Memory

Write Protection Bits: Each byte of the Data Memory can be irreversibly protected against data

change by writing the corresponding bit in the Write Protection Memory. Dependent on the state

of the protection bit the Data Memory is read only (ROM) or may be erased and written again

(EEPROM). The manufacturer code (Application ID and Chip Coding) is programmed unalterable

by the chip manufacturer.

Figure 2 Memory Configuration SLE 5518