A6282
Description
The A6282 device is designed for LED display applications. This
CMOS device includes an input shift register, accompanying
data latches, and 16 MOS constant current sink drivers.
The CMOS shift registers and latches allow direct interfacing
with microprocessor-based systems. With a 3.3 or 5 V logic
supply, typical serial data input rates can reach up to 30 MHz.
The LED drive current level can be set by a single external
resistor, selected by the application designer. A serial data
output permits cascading of multiple devices in applications
requiring additional drive lines.
The A6282 is available in two 24-terminal packages: QFN
(package ES) and TSSOP (LP), which have an exposed
thermal pad. Both packages are lead (Pb) free with 100% matte
tin leadframe plating.
Applications include the following:
▪ Monocolor, multicolor, or full-color LED display
▪ Monocolor, multicolor, or full-color LED signboard
▪ Display backlighting
▪ Multicolor LED lighting
6282-DS, Rev. 4
Features and Benefits
▪ 16 constant-current outputs, up to 50 mA each
▪ LED output voltage up to 12 V
▪ 3.0 to 5.5 V logic supply range
▪ Schmitt trigger inputs for improved noise immunity
▪ Power-On Reset (POR), all register bits = 0
▪ Low-power CMOS logic and latches
▪ High data input rate: 30 MHz
▪ Output current accuracy: between channels < ±3% and
between ICs ±7%, over the full operating temperature
range
▪ Internal UVLO and thermal shutdown (TSD) circuitry
16-Channel Constant-Current LED Driver
Typical Application
Controller
CLK
LE
SDO
REXT
A6282
IC 1
A6282
IC 2
OE
SDI SDI
10 μF
100 nF
OUT0 OUT15
VLED
VDD
CLK
LE
OE
CLK
LE
OE
REXT
100 nF
VDD
10 μF
OUT0 OUT15 SDO
SDI
GND GND
VDD VDD
Not to scale
24-contact QFN
4 mm × 4 mm × 0.75 mm
(Package ES)
24-pin TSSOP
with exposed thermal pad
(Package LP)
Cascaded A6282 devices
Packages:
16-Channel Constant-Current LED Driver
A6282
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Unit
Supply Voltage* VDD –0.3 to 5.5 V
OUTx Current (any single output) IO60 mA
Input Voltage Range* VI VOE, VLE, VCLK, VSDI –0.3 to VDD + 0.3 V
LED Load Supply Range* VLED –0.3 to 13.2 V
ESD Rating HBM (JEDEC JESD22-A114, Human Body Model) 2.0 kV
CDM (JEDEC JESD22-C101, Charged Device Model) 1.0 kV
Operating Temperature Range (E) TA–40 to 85 °C
Junction Temperature TJ(max) 150 °C
Storage Temperature Range Tstg –55 to 150 °C
*With respect to ground.
Selection Guide
Part Number Package Packing
A6282EESTR-T 4 mm × 4 mm QFN, 24 pins, exposed thermal pad 1500 pieces per 7-in. reel
A6282ELPTR-T TSSOP, 24 pins, exposed thermal pad 4000 pieces per 13 in. reel
Thermal Characteristics
Characteristic Symbol Test Conditions1Value Units
Package Thermal Resistance RJA
ES package, 4-layer PCB based on JEDEC standard 37 °C/W
LP packge, 4-layer PCB based on JEDEC standard 28 °C/W
*Additional thermal information available on the Allegro website.
50 75 100 125 15025
Allowable Package Power Dissipation (W)
Ambient Temperature (°C)
5.0
0
1.0
2.0
3.0
4.0
Package LP, RQJA = 28 °C/W
Package ES, RQJA = 37 °C/W
16-Channel Constant-Current LED Driver
A6282
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Block Diagram
Inputs and Outputs Equivalent Circuits
Resistor values are equivalent resistance and not tested
VDD
CLK, SDI,
LE,
O
¯ ¯ E¯500 ΩSDO
VDD
10 Ω
SDO
SDI
LE
OUT0 OUT1 OUT15
UVLO and TSD
VDD
I
O
Regulator
REXT
Serial - Parallel Shift Register
Control Logic
Block
CLK
Output Control Drivers
V
LED
Exposed Pad
(ET and LP packages)
OE
GND
La
t
ches
16-Channel Constant-Current LED Driver
A6282
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Terminal List Table
Name Number Description
ES LP
CLK 6 3 Clock; data shift clock input terminal
GND 4 1 Logic supply ground and load supply ground
LE 7 4 Latch Enable input terminal
¯
O
¯
¯¯
E
¯ 24 21 Output Enable input terminal, active low (when ¯
O
¯
¯¯
E
¯
= high, all OUTx outputs are forced off; when ¯
O
¯
¯¯
E
¯
= low,
on/off status of OUTx outputs is controlled by the state of the latches
OUT0 8 5
Constant current outputs
OUT1 9 6
OUT2 10 7
OUT3 11 8
OUT4 12 9
OUT5 13 10
OUT6 14 11
OUT7 15 12
OUT8 16 13
OUT9 17 14
OUT10 18 15
OUT11 19 16
OUT12 20 17
OUT13 21 18
OUT14 22 19
OUT15 23 20
PAD – – Exposed pad for enhanced thermal dissipation; not connected internally, connect to GND
REXT 2 23 Reference current terminal; sets output current for all channels
SDI 5 2 Serial Data In terminal
SDO 1 22 Serial Data Out terminal
VDD 3 24 Logic Supply terminal
Pin-out Diagrams
Top-down views
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
REXT
SDO
OE
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
PAD
GND
SDI
CLK
LE
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
PAD
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
OE
OUT15
OUT14
OUT13
OUT12
OUT11
LE
OUT0
OUT1
OUT2
OUT3
OUT4
OUT10
OUT9
OUT8
OUT7
OUT6
OUT5
SDO
REXT
VDD
GND
SDI
CLK
ES Package LP Package
16-Channel Constant-Current LED Driver
A6282
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS at TA1 = 25°C, VDD = 3.0 to 5.5 V, unless otherwise noted
Characteristic Symbol Test Conditions Min. Typ.2Max. Unit
Logic Supply Voltage Range VDD Operating 3.0 5.0 5.5 V
LED Load Supply Output Voltage VLED Operating – – 12.0 V
Undervoltage Lockout VDD(UV)
VDD 0 5.0 V 2.5 2.7 2.9 V
VDD 5 0.0 V 2.3 2.5 2.7 V
Output Current IO
VDD = 4.5 to 5.5 V, VDS(x) = 1 V,
REXT = 374 47.4 51.1 54.5 mA
VDD = 3.0 to 3.6 V, VDS(x) = 1 V,
REXT = 374 46.5 50.1 53.5 mA
VDD = 4.5 to 5.5 V, VDS(x) = 1 V,
REXT = 910 19.8 21.4 22.8 mA
VDD = 3.0 to 3.6 V, VDS(x) = 1 V,
REXT = 910 19.5 21.0 22.4 mA
Output Current Shift %IO
VDD = 5.5 V, VDS(x) = 1 V, REXT = 910 ,
TA = 25°C; between one output on and
all outputs on
– – ±1 %
Output to Output Matching Error3Err VDS = 1 V, REXT = 374 , all outputs on – +1.0 +3.0 %
VDS = 1 V, REXT = 910 , all outputs on – +1.0 +3.0 %
Output Current Regulation %IO(reg)
VDD = 5.5 V, VDS(x) = 1 to 3 V,
REXT = 374 , all outputs on – 1.7 3 %/V
VDD = 5.5 V, VDS(x) = 1 to 3 V,
REXT = 910 , all outputs on – 2.4 4 %/V
VDD = 3.6 V, VDS(x) = 1 to 3 V,
REXT = 374 , all outputs on – 1.2 2 %/V
VDD = 3.6 V, VDS(x) = 1 to 3 V,
REXT = 910 , all outputs on – 1.8 3 %/V
Output Leakage Current IDSS VOH = 12 V – – 0.5 A
Logic Input Voltage VIH 0.8×VDD –V
DD V
VIL GND – 0.2×VDD V
Logic Input Voltage Hysteresis VIhys All digital inputs 250 – 900 mV
Logic Input Current IIAll digital inputs –1 – 1 A
SDO Voltage VOL IOL = 1 mA – – 0.5 V
VOH IOH = –1 mA VDD
– 0.5 – – V
Supply Current4
IDD(OFF)
REXT = 3.8 k, VOE = 5 V – – 6 mA
REXT = 910 , VOE = 5 V – – 16 mA
REXT = 374 , VOE = 5 V – – 40 mA
IDD(ON)
All outputs on, REXT = 910 , VO = 1 V,
data transfer 30 MHz – – 20 mA
All outputs on, REXT = 374 , VO = 1 V,
data transfer 30 MHz – – 45 mA
Continued on the next page…
16-Channel Constant-Current LED Driver
A6282
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS (continued), at TA1 = 25°C, VDD = 3.0 to 5.5 V, unless otherwise noted
Characteristic Symbol Test Conditions Min. Typ.2Max. Unit
SWITCHING CHARACTERISTICS at TA1 = 25°C, VDD = VIH = 5.0 V, VDS = 1 V, VIL = 0 V, REXT = 910 , IO = 21.4 mA, VL = 2 V,
RL = 51 , CL = 15 pF (see also Timing Diagrams section)
Characteristic Symbol Test Conditions Min. Typ.2Max. Unit
Clock Frequency fCLK CLK – – 30 MHz
Clock Frequency (cascaded devices) fCLKC CLK – – 25 MHz
Clock Pulse Duration twh0 CLK = high 16 – – ns
LE Pulse Duration twh1 LE = high 20 – – ns
Setup Time tsu0 SDI to CLK10 – – ns
tsu1 CLK to LE 10 – – ns
Hold Time th0 CLK to SDI 10 – – ns
th1 LE to CLK 10 – – ns
Rise Time tr0 SDO, 10/90% points (measurement circuit A) – – 16 ns
tr1 OUTx, VDD = 5 V,10/90% points (measurement circuit B) – 10 30 ns
Fall Time tf0 SDO, 10/90% points (measurement circuit A) – – 16 ns
tf1 OUTx, VDD = 5 V,10/90% points (measurement circuit B) – 10 30 ns
Propagation Delay Time
tpd0 CLK to SDO (measurement circuit A) – – 30 ns
tpd1 ¯
O
¯
¯¯
E
¯
to OUTx (measurement circuit B) – – 60 ns
tpd2 LE to OUTx (measurement circuit B) – – 60 ns
Output Enable Pulse Duration tw(OE) (see Timing Diagrams section) 60 – – ns
1Tested at 25°C. Specifications are assured by design and characterization over the operating temperature range of –40°C to 85°C.
2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
Thermal Shutdown Temperature TJTSD Temperature increasing – 165 – °C
Thermal Shutdown Hysteresis TJTSDhys –15–°C
Reference Voltage at External
Resistor REXT VEXT REXT = 374 – 1.21 – V
1Tested at 25°C. Specifications are assured by design and characterization over the operating temperature range of –40°C to 85°C.
2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
3Err = (IO(min or max) – IO(av)) / IO(av). IO(av) is the average current of all outputs. IO(min or max) is the output current with the greatest
difference from IO(av).
4Recommended operating range: VO = 1.0 to 3.0 V.
SDO
15 pF OUTx
A6282 RL
VL
CL
A6282
Parameter Measurement Circuits
(A) Circuit for tf0
, tpd0
, and tr0 (B) Circuit for tf1
, tpd1
, tpd2
, and tr1
.
16-Channel Constant-Current LED Driver
A6282
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
wh0
t
su0
th0
t
pd0
t
wh1
t
su1
t
CLK
SDI
SDO
LE
OUTx
(current)
pd2
t
OE Low = All Outputs Enabled
High = Output on
Low = Output off
OUTx
(current)
OE
pd1
tpd1
t
50%
50%
50%
r0
tf0
t
10%
90%
f1
tr1
t
90%
10%
50%
w (OE)
t
Timing Diagrams
Disabling Outputs
Normal Operation
16-Channel Constant-Current LED Driver
A6282
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Operating Characteristics
REXT = 470 Ω
REXT = 910 Ω
0
50
45
40
35
30
25
20
15
10
5
0
60
50
40
30
20
10
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.00.3 1.0 2.0 3.0 4.0 5.0
VDS (V)
IO(max) (mA)
IO (mA)
REXT (kΩ)
VDD (V)
4.5 to 5.0
3.0 to 3.6
Channel Maximum Constant Output Current
versus External Reference Resistance
Input-Output Truth Table
Serial
Data
Input
(SDI)
Clock
Input
(CLK)
Shift Register Contents Serial
Data
Out
(SDO)
Latch
Enable
Input
(LE)
Latch Contents Output
Enable
Input
(¯
O
¯
¯¯
E
¯
)
Output Contents
I
0 I1 I2 … I15 I
0 I1 I2 … I15 I
0 I1 I2 …
I15
H H R0 R1 … R15 R14
L L R0 R1 … R15 R14
X R
0 R1 R2 … R15 R15
X X X … X X L R0 R1 R2 … R15
P
0 P1 P2 … P15 P15 H P
0 P1 P2 …
P15
L
(Outputs on)
P
0 P1 P2 …
P15
X X X … X H
(Outputs off) H H H … H
L = Low logic (voltage) level, H = High logic (voltage) level, X = Don’t care, P = Present state, R = Previous state
Channel Output Current versus Output Voltage
VDD = 5.0 V
16-Channel Constant-Current LED Driver
A6282
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Normal Operation
Serial data present at the SDI (Serial Data In) input is transferred
to the shift register on the transition from logic 0 to logic 1 of the
CLK (Clock) input pulse. On succeeding CLK pulses, the register
shifts data towards the SDO (Serial Data Out) output. The serial
data must appear at the input prior to the rising edge of the CLK
waveform.
Data present in any register is transferred to the respective latch
when the LE (Latch Enable) input is high (serial-to-parallel con-
version). The latches continue to accept new data as long as LE is
held high (level triggered).
Applications where the latches are bypassed (LE tied high)
require that the ¯
O
¯
¯¯
E
¯
(Output Enable) input be high during serial
data entry. When ¯
O
¯
¯¯
E
¯
is high, the output sink drivers are disabled
(off). The data stored in the latches is not affected by the state
of ¯
O
¯
¯¯
E
¯
. With ¯
O
¯
¯¯
E
¯
active (low), the outputs are controlled by the
state of their respective latches.
Setting Maximum Channel Current
The maximum output current per channel is set by a single exter-
nal resistor, REXT, which is placed between the REXT pin and
GND. The voltage on REXT, VEXT, is set by an internal band gap
and is 1.21 V, typical.
The maximum channel output current can be calculated as:
I
O(max) = (18483.1/ REXT) + 0.67 , for VDD = 3.0 to 3.6 V ,
or
I
O(max) = (18841.2/ REXT) + 0.68 , for VDD = 4.5 to 5.5 V ,
where REXT is the value of the user-selected external resistor,
which should not be less than 374 Ω.
A chart of the maximum per channel (OUT0 to OUT15) constant
output current, IO(max), at various values of REXT , is shown in
the Operating Characteristics section.
Undervoltage Lockout
The A6282 includes an internal undervoltage lockout (UVLO)
circuit that disables the outputs in the event that the logic supply
voltage drops below a minimum acceptable level. This feature
prevents the display of erroneous information, a necessary func-
tion for some critical applications. Upon recovery of the logic
supply voltage after a UVLO event, all internal shift registers and
latches are set to 0. The A6282 is then in normal mode.
Thermal Shutdown Protection
If the junction temperature exceeds the threshold temperature,
TJTSD
, 165°C typical, the outputs will be turned off until the junc-
tion temperature cools down through the thermal shutdown hys-
teresis, 15°C typical. The shift register and output latches register
will remain active during a thermal shutdown event. Therefore,
there is no need to reset the data in the output latches.
Functional Description
16-Channel Constant-Current LED Driver
A6282
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Load Supply Voltage (VLED)
This device is designed to operate with driver voltage drops (VDS)
of 1.0 to 3.0V. If higher voltages are dropped across the driver,
package power dissipation will increase. To minimize package
power dissipation, it is recommended to use the lowest possible
load supply voltage, VLED, or to set a series voltage drop, VDROP ,
according to the following formula:
VDROP = VLED – VF – VDS ,
where VF is the LED forward voltage. For reference, typical LED
forward voltages are:
LED Type VF (V)
White 3.5 to 4.0
Blue 3.0 to 5.5
Green 1.8 to 2.5
Yellow 2.0 to 2.5
Amber 1.9 to 3.0
Red 1.6 to 2.5
Infrared 1.2 to 1.8
UV 3.0 to 4.0
VDROP = IO× RDROP for a single driver, for a Zener diode (VZ),
or for a series string of silicon diodes (approximately 0.7 V per
diode) for a group of drivers (these configurations are shown
in the figure below). If the available voltage source will cause
unacceptable power dissipation and series resistors or diodes are
undesirable, a voltage regulator can be used to provide VLED.
Pattern Layout
To save pins and board space, the A6282 uses one pin for both
logic ground and power ground. Therefore, achieving optimal
performance requires careful attention to layout. Following the
suggestions below will improve the analog performance and logic
noise immunity.
1. Place the REXT resistor as close as possible to the REXT
pin and GND pin. This will minimize parasitic inductance and
capacitance.
2. Use a separate line to the device GND pin for REXT, and sepa-
rate lines for the decoupling capacitors. The lines should join at
ground. This star grounding will improve output load regulation
and minimize any chance of oscillation.
The REXT ground line should carry only the small current from
the internal voltage reference at REXT. The high AC currents
flowing through the decoupling capacitors and their resistive and
inductive PCB lines cause noise (ground bounce) on the capacitor
ground lines. Such noise could disturb the reference voltage at
REXT and promote oscillation. Connect the exposed thermal pad
of the ES and LP packages to the power ground, along with the
decoupling capacitors, and not to the ground line for REXT.
3. Keep the output drive lines (OUT0 through OUT15) away
from the REXT pin to avoid coupling of the output signal into
the reference for the current sources. Output lines should not run
adjacent to the REXT pin or directly under the REXT pin.
4. Use decoupling capacitors on the VDD pin and the LED sup-
ply bus. Place the logic decoupling capacitor (0.1 μF, one for
each A6282) as close as possible to the VDD pin. Use at least one
10 μF capacitor from the LED supply line to device ground for at
least every two A6282s.
5. Use multilayer boards if possible.
Package Power Dissipation
The maximum allowable package power dissipation based on
package type is determined by:
PD(max) = (150 – TA) / RJA
,
where RJA is the thermal resistance of the package, determined
experimentally. Power dissipation levels based on the package are
shown in the Thermal Characteristics table.
The actual package power dissipation is determined by:
PD(act) = DC × (VDS × IO× 16) + (VDD× IDD) ,
where DC is the duty cycle. The value 16 is the maximum
number of available device outputs, representing the worst-case
scenario (displaying all 16 LEDs). When the load supply voltage,
VLED, is greater than 3 to 5 V, and PD(act) > PD(max), an external
voltage reducer (VDROP) must be used (figure at left). Reducing
DC will also reduce power dissipation. The ES and LP packages
contain an exposed thermal pad on the bottom of the package
for enhanced heat dissipation. Connect this pad to a large power
ground plane using thermal vias. JEDEC documents JESD51-3
and JESD51-5 give suggestions for PCB and thermal via designs.
VDS
VF
VDROP
VLED
VDS
VF
VDROP
VLED
VDS
VF
VDROP
VLED
Application Information
Typical application voltage drops
16-Channel Constant-Current LED Driver
A6282
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package ES, 4 mm x 4 mm, 24-pin QFN with Exposed Thermal Pad
0.90
C
SEATING
PLANE
C0.08
25X
24
24
2
1
1
2
24
2
1
A
ATerminal #1 mark area
Coplanarity includes exposed thermal pad and terminals
BExposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
For Reference Only
(reference JEDEC MO-220WGGD)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
C
D
D
C
Reference land pattern layout (reference IPC7351
QFN50P400X400X80-25W6M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
4.00 ±0.15
4.00 ±0.15 4.10
0.30
0.50
4.10
0.50
0.75 ±0.05
2.10
2.10
2.10
2.10
0.25 +0.05
–0.07
0.40 +0.15
–0.10 B
PCB Layout Reference View
16-Channel Constant-Current LED Driver
A6282
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package LP, 24-pin TSSOP with Exposed Thermal Pad
1.20 MAX
C
SEATING
PLANE
0.15 MAX
C0.10
24X
0.65
6.103.00
4.32
1.65
0.45
0.65
0.25
21
24
3.00
4.32
(1.00)
GAUGE PLANE
SEATING PLANE
B
A
ATerminal #1 mark area
B
For reference only
(reference JEDEC MO-153 ADT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Reference land pattern layout (reference IPC7351
TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
PCB Layout Reference View
Exposed thermal pad (bottom surface)
C
C
7.80 ±0.10
4.40 ±0.10 6.40 ±0.20 0.60 ±0.15
4° ±4
0.25 +0.05
–0.06
0.15 +0.05
–0.06
16-Channel Constant-Current LED Driver
A6282
13
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
For the latest version of this document, visit our website:
www.allegromicro.com
Copyright ©2008-2010, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
