The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
© 2000
MOS INTEGRATED CIRCUIT
µ
µµ
µ
PD4443362
4M-BIT CMOS SYNCHRONOUS FAST STATIC RAM
128K-WORD BY 36-BIT
H
S
TL INTERFA
C
E
/
RE
G
I
S
TER-RE
G
I
S
TER
/
LATE WRITE
PRELIMINARY DATA SHEET
Document No. M14439EJ1V0DSJ1 (1st edition)
Date Published December 2000 NS CP(K)
Printed in Japan
The mar k •
••
• shows major revised points.
Description
The
µ
PD4443362 is a 131,072 words by 36 bits synchronous static RAM fabricated with advanced CMOS
technology using Full-CMOS six-transistor memory cell.
The
µ
PD4443362 is suitable for applications which require synchronous operation, high-speed, low voltage, high-
density memory and wide bit configuration, such as cache and buffer memory.
The
µ
PD4443362 is packaged in 100-pin plastic LQFP with a 1.4 mm package thickness for high density and low
capacitive loading.
Features
• Fully synchronous operation
• HSTL Input / Output levels
• Fast clock access time : 3.0 ns (200 MHz), 3.5 ns (167 MHz)
• Asynchronous output enable control : /G
• Byte write control : /SBa (DQa1-9), /SBb (DQb1-9), /SBc (DQc1-9), /SBd (DQd1-9)
• Common I/O using three-state outputs
• Internally self-timed write cycle
• Late write with 1 dead cycle between Read-Write
• 3.3 V (Chip) / 1.5 V (I/O) supply
• 100-pin plastic LQFP package, 14 mm x 20 mm
• Sleep Mode : ZZ (Enables sleep mode, active high)
Ordering Information
Part number Access ti me Clock frequency Package
µ
PD4443362GF-A50 3.0 ns 200 MHz 100-PIN PLA STIC LQFP (14 x 20)
µ
PD4443362GF-A60 3.5 ns 167 MHz
2
µ
µµ
µ
PD4443362
Preliminary Data Sheet M14439EJ1V0DS
Pin Configuration (Marking Side)
/xxx ind icates active low signal.
100-PIN PLASTIC LQFP (14 x 20)
[
µ
µµ
µ
PD4443362GF ]
DQc9
DQc8
DQc7
V
DD
Q
V
SS
Q
DQc6
DQc5
DQc4
DQc3
V
SS
Q
V
DD
Q
DQc2
DQc1
NC
V
DD
NC
V
SS
DQd1
DQd2
V
DD
Q
V
SS
Q
DQd3
DQd4
DQd5
DQd6
V
SS
Q
V
DD
Q
DQd7
DQd8
DQd9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQb9
DQb8
DQb7
V
DD
Q
V
SS
Q
DQb6
DQb5
DQb4
DQb3
V
SS
Q
V
DD
Q
DQb2
DQb1
V
SS
NC
V
DD
ZZ
DQa1
DQa2
V
DD
Q
V
SS
Q
DQa3
DQa4
DQa5
DQa6
V
SS
Q
V
DD
Q
DQa7
DQa8
DQa9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
SA6
SA7
/SS
/SBd
/SBc
/SBb
NC
/SBa
NC
V
DD
V
SS
K
/K
V
REF
/G
/SW
NC
NC
SA8
SA9
NC
SA5
SA4
SA3
SA2
SA1
SA0
V
REF
NC
V
SS
V
DD
NC
V
REF
SA10
SA11
SA12
SA13
SA14
SA15
SA16
Remark Refer to Package Drawing for 1-pin index mark.
3
µ
µµ
µ
PD4443362
Preliminary Data Sheet M14439EJ1V0DS
Pin Name and Functions
Pin nam e Pin No. Descript i on
SA0 to S A16 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous A ddress Input
45, 46, 47, 48, 49, 50
DQa1 to DQa9 63, 62, 59, 58, 57, 56, 53, 52, 51 Synchronous Data Input / Output
DQb1 to DQb9 68, 69, 72, 73, 74, 75, 78, 79, 80
DQc1 to DQc 9 13, 12, 9, 8, 7, 6, 3, 2, 1
DQd1 to DQd9 18, 19, 22, 23, 24, 25, 28, 29, 30
/SS 98 Synchronous Chi p Select
/SW 85 Synchronous Byte Write Enable
/SBa Note1 93 Synchronous Byte "a" Write Enable
/SBb Note1 95 Synchronous Byte "b" Write Enable
/SBc Note1 96 Synchronous Byte "c" Writ e E nabl e
/SBd Note1 97 Synchronous Byte "d" Write Enable
/G 86 Asynchronous Output E nabl e
ZZ Note2 64 As ynchronous Sl eep Mode
K, /K 89, 88 Main Clock I nput
VDD 15, 41, 65, 91 Core Power Supply
VSS 17, 40, 67, 90 Ground
VDDQ 4, 11, 20, 27, 54, 61, 70, 77 Output Buffer Power Supply
VSSQ 5, 10, 21, 26, 55, 60, 71, 76 Output Buffer Ground
VREF 38, 43, 87 Input Reference
NC 14, 16, 31, 39, 42, 66, 83, 84, 92, 94 No Connection
Notes 1. If Byte Write Operation is not used, Byte Write Pin (/SBa, /SBb, /SBc, /SBd) are to be tied to VSS.
2. If Sleep Mode is not used, ZZ Pin is to be tied to VSS.
Remark This device only supports Single Differential Clock, R/R Mode.
(R/R stands for Registered Input/Registered Output.)
4
µ
µµ
µ
PD4443362
Preliminary Data Sheet M14439EJ1V0DS
Late Write Block Diagram
K
/SBa
K
/K
/SS
/SW
/SBa
/SBb
/SBc
/SBd
Data
in
register
Write
control
logic
Address
register
Write address
register
Read
comp.
Memory
cell array
4,718,592 bits
Data
in Data
out
Mux
Output
Register
/SW
/SBc
/SBb
DQa1 to DQa9
DQb1 to DQb9
DQc1 to DQc9
DQd1 to DQd9
/SBd
/G
/K
/SS
SA0 to SA16
Mux
ZZ
Write
clock
generator
/G
ZZ
17
36
5
µ
µµ
µ
PD4443362
Preliminary Data Sheet M14439EJ1V0DS
Synchronous Truth Table
ZZ /SS /SW /SBa /SBb /SBc /SBd Mode DQa1–9DQb1
–9DQc1
–9DQd1
–9Power
LH×××××
Not sele cted Hi-Z Hi-Z Hi-Z Hi-Z Active
LLH×××× Read Dout Dout Dout Dout Active
LLLLLLL Write DinDinDinDinActive
L L L L H H H Write Din Hi-Z Hi-Z Hi-Z Active
L L L H L L L Write Hi-Z Din Din Din Active
LLLHHHHAbort WriteHi-ZHi-ZHi-ZHi-ZActive
H××××××
Sleep Mode Hi-Z Hi-Z Hi-Z Hi-Z Standby
Remark × : Don’t care
Output Enable Truth Table
Mode /G DQ
Read L Dout
Read H Hi-Z
Sleep (ZZ=H) ×Hi-Z
Write (/SW=L) ×Hi-Z
Deselect (/SS=H) ×Hi-Z
Remark × : Don’t care
6
µ
µµ
µ
PD4443362
Preliminary Data Sheet M14439EJ1V0DS
Electrical Specifications
Absolute Maximum Ratings
Parameter Symbol Condition MIN. TYP. MAX. Unit Note
Supply volt age VDD –0.5 +4.6 V 1
Output suppl y vol tage VDDQ –0.5 +4.6 V 1
Input volt age VIN –0.5 VDD + 0.3 V 1
Input / Output volt age VI/O –0.5 VDDQ + 0.3 V 1
Operating temperature TA070°C
Storage temperature Tstg –55 +125 °C
Note 1. –2.0 V MIN. (Pulse width : 2 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to 70 °
°°
°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Core supply volt age VDD 3.135 3.3 3.465 V
Output buffer supply voltage VDDQ 1.4 1.5 1.6 V
Input reference voltage VREF 0.70.750.8V
Low level input voltage VIL –0.3 Note VREF–0.1 V
High level input voltage VIH VREF+0.1 VDDQ+0.3 V
Note –0.8 V MIN. (Pulse width : 2 ns)
Recommended AC Operating Conditions (TA = 0 to 70 °
°°
°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input reference voltage VREF (RMS) –5% +5% V
Low level input voltage VIL –0.3 VREF–0.2 V
High level input voltage VIH VREF+0.2 VDDQ+0.3 V
Capacitance (TA = 25 °
°°
°C, f = 1 MHz)
Parameter Note S ymbol Test c ondi t i ons MAX. Unit
Input capacitanc e CIN VIN = 0 V 4.5 pF
Input / Output capacitanc e CI/O VI/O = 0 V 7.0 pF
Clock i nput capaci tance Cclk Vclk = 0 V 6.0 pF
Note These parameters are sampled and not 100% tested.
7
µ
µµ
µ
PD4443362
Preliminary Data Sheet M14439EJ1V0DS
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Param eter Sym bol Conditions MIN. TYP. MAX. Unit
Input leak age current ILI VIN = 0 to VDD –5 +5
µ
A
DQ leakage current ILO VI/O = 0 to VDDQ–5+5
µ
A
Operating suppl y current IDD VIN = VIH or VIL, /SS = VIL, ZZ = VIL, 420 mA
Cycle = MAX., IDQ = 0 mA
Sleep m ode power supply I SBZZ ZZ = VIH, Al l other inputs = V IH or V IL,10mA
current Cycle = DC, IDQ = 0 m A
Output Voltage on Push-Pull Output Buffer Mode
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Low level output voltage VOL IOL = + 2 mA – 0.3 V
High level out put voltage VOH IOH = – 2 m A VDDQ–0.3 – V
8
µ
µµ
µ
PD4443362
Preliminary Data Sheet M14439EJ1V0DS
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Characteristics Test Conditions
Input waveform (rise and fall time = 0.5 ns (20 to 80%))
V
DD
Q / 2
0.25 V
1.25 V
V
DD
Q / 2
Test Points
Remarks 1. Clock input differential voltage
2. Clock input common mode voltage range
Output waveform
V
DD
Q / 2 V
DD
Q / 2
Test Points
9
µ
µµ
µ
PD4443362
Preliminary Data Sheet M14439EJ1V0DS
Single Differential Clock, Registered Input / Registered Output Mode
Param eter Sym bol -A 50 (200 MHz) -A60 (167 MHz) Unit Notes
MIN. MAX. MIN. MAX.
Clock cycle time tKHKH 5.0–6.0–ns
Clock phase time tKHKL /
tKLKH
1.6–1.8–ns
Setup ti mes Address tAVKH 1.5–1.5–ns
Write data tDVKH
Write enabl e tWVKH
Chip select tSVKH
Hold times Address tKHAX 0.5–0.5–ns
Write data tKHDX
Write enabl e tKHWX
Chip select tKHSX
Clock access time tKHQV –3.0–3.5ns1
K high to Q c hange tKHQX 1.0–1.0–ns2
/G low to Q valid tGLQV –3.0–3.5ns1
/G low to Q change tGLQX 0–0–ns2
/G high to Q Hi-Z tGHQZ 03.003.5ns2
K high to Q Hi-Z (/SW) tKHQZ 1.0 3.0 1.0 3.5 ns 2
K high to Q Hi-Z (/SS) tKHQZ2 1.0 3.0 1.0 3.5 ns 2
K high to Q Lo-Z tKHQX2 1.0–1.0–ns2
Power Down Ent ry Time tZZR – 10.0 – 12.0 ns
Power Down Recovery Time tZZE – 10.0 – 12.0 ns
Notes 1. See figure. (VTT=0.75 V)
DQ (Output) ZO = 50 Ω
20 pF
50 Ω
VTT
2. See figure. (VTT=0.75 V)
DQ (Output)
5 pF
50 Ω
VTT
10
µ
µµ
µ
PD4443362
Preliminary Data Sheet M14439EJ1V0DS
a
Qa Qc Qe Qf Qg
bcdefghi jk
Qi
t
KHAX
t
AVKH
t
KHKH
t
KHKL
t
KLKH
t
KHSX
t
SVKH
t
WVKH
t
KHWX
t
GHQZ
t
GLQX
t
GLQV
t
KHQZ2
t
KHQV
t
KHQX
t
KHQX2
Read Operation
/K
K
Address
/SS
/SW
/G
DQ Qb
11
µ
µµ
µ
PD4443362
Preliminary Data Sheet M14439EJ1V0DS
l
Ql Qo Qp Qq
mnopqrstuv
t
KHAX
t
AVKH
t
KHKH
t
KHKL
t
KLKH
t
KHSX
t
SVKH
t
WVKH
t
KHWX
t
GLQX
t
GLQV
t
KHQZ
t
KHDX
t
DVKH
t
KHQX2
Write Operation
/K
K
Address
/SS
/SW
/G
DQ Dn QtDs
t
GHQZ
/SBa - /SBd
t
KHWX
t
WVKH
12
µ
µµ
µ
PD4443362
Preliminary Data Sheet M14439EJ1V0DS
a
Qa Qc
bcdefghi jk
t
ZZE
t
ZZR
Sleep Mode
/K
K
Address
/SS
/ZZ
DQ Qb
l
Qj
/SW
13
µ
µµ
µ
PD4443362
Preliminary Data Sheet M14439EJ1V0DS
Package Drawing
100-PIN PLASTIC LQFP (14x20)
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
D
G
22.0±0.2
20.0±0.2
0.65 (T.P.)
0.575
J
16.0±0.2
K
C 14.0±0.2
I 0.13
1.0±0.2
L0.5±0.2
F 0.825
N
P
Q
0.10
1.4
0.125±0.075
S100GF-65-8ET-1
S 1.7 MAX.
H 0.32+0.08
−0.07
M 0.17+0.06
−0.05
R3°+7°
−3°
M
80
81 51
50
30
31
100
1
S
SN
J
detail of lead end
C D
A
B
R
K
M
L
P
I
S
Q
G
F
H
14
µ
µµ
µ
PD4443362
Preliminary Data Sheet M14439EJ1V0DS
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
µ
PD4443362.
Type of Surface Mount Device
µ
PD4443362GF: 100-PIN PLAS T I C LQFP (14 x 20)
15
µ
µµ
µ
PD4443362
Preliminary Data Sheet M14439EJ1V0DS
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
µ
µµ
µ
PD4443362
M8E 00. 4
The information in this document is current as of December, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
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systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
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to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
•
•
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