LM613
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LM613 Dual Operational Amplifiers, Dual Comparators, and Adjustable Reference
Check for Samples: LM613
1FEATURES DESCRIPTION
The LM613 consists of dual op-amps, dual
23OP AMP comparators, and a programmable voltage reference
• Low Operating Current (Op Amp): 300 μAin a 16-pin package. The op-amps out-performs most
• Wide Supply Voltage Range: 4V to 36V single-supply op-amps by providing higher speed and
bandwidth along with low supply current. This device
• Wide Common-Mode Range: V−to (V+−1.8V) was specifically designed to lower cost and board
• Wide Differential Input Voltage: ±36V space requirements in transducer, test,
• Available in Plastic Package Rated for Military measurement, and data acquisition systems.
Temp. Range Operation Combining a stable voltage reference with wide
REFERENCE output swing op-amps makes the LM613 ideal for
• Adjustable Output Voltage: 1.2V to 6.3V single supply transducers, signal conditioning and
bridge driving where large common-mode-signals are
• Tight Initial Tolerance Available: ±0.6% common. The voltage reference consists of a reliable
• Wide Operating Current Range: 17 μA to 20 band-gap design that maintains low dynamic output
mA impedance (1Ωtypical), excellent initial tolerance
• Tolerant of Load Capacitance (0.6%), and the ability to be programmed from 1.2V
to 6.3V via two external resistors. The voltage
reference is very stable even when driving large
APPLICATIONS capacitive loads, as are commonly encountered in
• Transducer Bridge Driver CMOS data acquisition systems.
• Process and Mass Flow Control Systems As a member of TI's Super-Block™ family, the LM613
• Power Supply Voltage Monitor is a space-saving monolithic alternative to a multi-
chip solution, offering a high level of integration
• Buffered Voltage References for A/D's without sacrificing performance.
Connection Diagrams
Top View
Figure 1. CDIP and SOIC Packages Figure 2. E Package Pinout
See Package Numbers NFE0016A and DW0016B
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Super-Block is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2000–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LM613
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
See (3) 36V (Max)
Voltage on Any Pin Except VR(referred to V−pin) See (4) −0.3V (Min)
Current through Any Input Pin & VRPin ±20 mA
Military and Industrial ±36V
Differential Input Voltage Commercial ±32V
Storage Temperature Range −65°C ≤TJ≤+150°C
Maximum Junction Temperature(5) 150°C
N Package 100°C/W
Thermal Resistance, Junction-to-Ambient (6) DW0016B Package 150°C/W
N Package 260°C
Soldering Information (10 Sec.) DW0016B Package 220°C
ESD Tolerance(7) ±1 kV
(1) Absolute maximum ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply
when operating the device beyond its rated operating conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Input voltage above V+is allowed. As long as one input pin voltage remains inside the common-mode range, the comparator will deliver
the correct output.
(4) More accurately, it is excessive current flow, with resulting excess heating, that limits the voltages on all pins. When any pin is pulled a
diode drop below V−, a parasitic NPN transistor turns ON. No latch-up will occur as long as the current through that pin remains below
the Maximum Rating. Operation is undefined and unpredictable when any parasitic diode or transistor is conducting.
(5) Simultaneous short-circuit of multiple comparators while using high supply voltages may force junction temperature above maximum,
and thus should not be continuous.
(6) Junction temperature may be calculated using TJ= TA+ PDθJA.The given thermal resistance is worst-case for packages in sockets in
still air. For packages soldered to copper-clad board with dissipation from one comparator or reference output transistor, nominal θJA is
90°C/W for the N package, and 135°C/W for the DW0016B package.
(7) Human body model, 100 pF discharged through a 1.5 kΩresistor.
Operating Temperature Range
LM613AI, LM613BI −40°C to +85°C
LM613AM, LM613M −55°C to +125°C
LM613C 0°C ≤TJ≤+70°C
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Electrical Characteristics
These specifications apply for V−= GND = 0V, V+= 5V, VCM = VOUT = 2.5V, IR= 100 μA, FEEDBACK pin shorted to GND,
unless otherwise specified. Limits in standard typeface are for TJ= 25°C; limits in boldface type apply over the Operating
Temperature Range.LM613M
LM613AM LM613I
Parameter Test Conditions Typ(1) LM613AI Units
LM613C
Limits(2) Limits(2)
ISTotal Supply Current RLOAD =∞, 450 940 1000 μA (Max)
4V ≤V+≤36V (32V for LM613C) 550 1000 1070 μA (Max)
VSSupply Voltage Range 2.2 2.8 2.8 V (Min)
2.9 3 3 V (Min)
46 36 32 V (Max)
43 36 32 V (Max)
OPERATIONAL AMPLIFIERS
VOS1 VOS Over Supply 4V ≤V+≤36V 1.5 3.5 5.0 mV (Max)
(4V ≤V+≤32V for LM613C) 2.0 6.0 7.0 mV (Max)
VOS2 VOS Over VCM VCM = 0V through VCM = 1.0 3.5 5.0 mV (Max)
(V+−1.8V), V+= 30V, V−= 0V 1.5 6.0 7.0 mV (Max)
VOS3 Average VOS Drift See (2) 15 μV/°C
ΔT (Max)
IBInput Bias Current 10 25 35 nA (Max)
11 30 40 nA (Max)
IOS Input Offset Current 0.2 4 4 nA (Max)
0.3 5 5 nA (Max)
IOS1 Average Offset Current 4pA/°C
ΔT
RIN Input Resistance Differential 1000 MΩ
CIN Input Capacitance Common-Mode 6 pF
enVoltage Noise f = 100 Hz, Input Referred 74 nV/√Hz
InCurrent Noise f = 100 Hz, Input Referred 58 fA/√Hz
CMRR Common-Mode V+= 30V, 0V ≤VCM ≤(V+−1.8V) 95 80 75 dB (Min)
Rejection Ratio CMRR = 20 log (ΔVCM/ΔVOS)90 75 70 dB (Min)
PSRR Power Supply 4V ≤V+≤30V, VCM = V+/2, 110 80 75 dB (Min)
Rejection Ratio PSRR = 20 log (ΔV+/VOS)100 75 70 dB (Min)
AVOpen Loop Voltage Gain RL= 10 kΩto GND, V+= 30V, 500 100 94 V/mV
5V ≤VOUT ≤25V 50 40 40 (Min)
SR Slew Rate V+= 30V(3) 0.70 0.55 0.50 V/μs
0.65 0.45 0.45
GBW Gain Bandwidth CL= 50 pF 0.8 MHz
0.5 MHz
VO1 Output Voltage RL= 10 kΩto GND, V+−1.4 V+−1.7 V+−1.8 V (Min)
Swing High V+= 36V (32V for LM613C) V+−1.6 V+−1.9 V+−1.9 V (Min)
VO2 Output Voltage RL= 10 kΩto V+, V−+ 0.8 V−+ 0.9 V−+ 0.95 V (Max)
Swing Low V+= 36V (32V for LM613C) V−+ 0.9 V−+ 1.0 V−+ 1.0 V (Max)
IOUT Output Source Current VOUT = 2.5V, V+IN = 0V, 25 20 16 mA (Min)
V−IN =−0.3V 15 13 13 mA (Min)
ISINK Output Sink Current VOUT = 1.6V, V+IN = 0V, 17 14 13 mA (Min)
V−IN = 0.3V 9 8 8 mA (Min)
ISHORT Short Circuit Current VOUT = 0V,V+IN = 3V, 30 50 50 mA (Max)
V−IN = 2V 40 60 60 mA (Max)
VOUT = 5V, V+IN = 2V, 30 60 70 mA (Max)
V−IN = 3V 32 80 90 mA (Max)
(1) Typical values in standard typeface are for TJ= 25°C; values in bold face type apply for the full operating temperature range. These
values represent the most likely parametric norm.
(2) All limits are ensured at room temperature (standard type face) or at operating temperature extremes (bold type face).
(3) Slew rate is measured with the op amp in a voltage follower configuration. For rising slew rate, the input voltage is driven from 5V to
25V, and the output voltage transition is sampled at 10V and @ 20V. For falling slew rate, the input voltage is driven from 25V to 5V,
and the output voltage transition is sampled at 20V and 10V.
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Electrical Characteristics (continued)
These specifications apply for V−= GND = 0V, V+= 5V, VCM = VOUT = 2.5V, IR= 100 μA, FEEDBACK pin shorted to GND,
unless otherwise specified. Limits in standard typeface are for TJ= 25°C; limits in boldface type apply over the Operating
Temperature Range.LM613M
LM613AM LM613I
Parameter Test Conditions Typ(1) LM613AI Units
LM613C
Limits(2) Limits(2)
COMPARATORS
VOS Offset Voltage 4V ≤V+≤36V (32V for LM613C), 1.0 3.0 5.0 mV (Max)
RL= 15 kΩ2.0 6.0 7.0 mV (Max)
VOS Offset Voltage 0V ≤VCM ≤36V 1.0 3.0 5.0 mV (Max)
VCM over VCM V+= 36V, (32V for LM613C) 1.5 6.0 7.0 mV (Max)
VOS Average Offset 15 μV/°C
ΔT Voltage Drift (Max)
IBInput Bias Current 5 25 35 nA (Max)
8 30 40 nA (Max)
IOS Input Offset Current 0.2 4 4 nA (Max)
0.3 5 5 nA (Max)
AVVoltage Gain RL= 10 kΩto 36V (32V for LM613C) 500 V/mV
2V ≤VOUT ≤27V 100 V/mV
trLarge Signal V+IN = 1.4V, V−IN = TTL Swing, 1.5 μs
Response Time RL= 5.1 kΩ2.0 μs
ISINK Output Sink Current V+IN = 0V, V−IN = 1V, 20 10 10 mA (Min)
VOUT = 1.5V 13 8 8 mA (Min)
VOUT = 0.4V 2.8 1.0 0.8 mA (Min)
2.4 0.5 0.5 mA (Min)
ILEAK Output Leakage V+IN = 1V, V−IN = 0V, 0.1 10 10 μA (Max)
Current VOUT = 36V (32V for LM613C) 0.2 μA (Max)
VOLTAGE REFERENCE
VRVoltage Reference See(4) 1.244 1.2365 1.2191 V (Min)
1.2515 1.2689 V (Max)
(±0.6%) (±2%)
ΔVRAverage Temp. Drift See(5) 10 80 150 ppm/°C
ΔT (Max)
ΔVRHysteresis See(6) 3.2 μV/°C
ΔTJ
ΔVRVRChange VR(100 μA) −VR(17 μA) 0.05 1 1 mV (Max)
ΔIRwith Current 0.1 1.1 1.1 mV (Max)
VR(10 mA) −VR(100 μA) 1.5 5 5 mV (Max)
See(7) 2.0 5.5 5.5 mV (Max)
R Resistance ΔVR(10→0.1 mA)/9.9 mA 0.2 0.56 0.56 Ω(Max)
ΔVR(100→17 μA)/83 μA0.6 13 13 Ω(Max)
VRVRChange VR(Vro = Vr) −VR(Vro = 6.3V) 2.5 7 7 mV (Max)
ΔVRO with High VRO (5.06V between Anode and 2.8 10 10 mV (Max)
FEEDBACK)
VRVRChange with VR(V+ = 5V) −VR(V+ = 36V) 0.1 1.2 1.2 mV (Max)
ΔV+ VANODE Change (V+= 32V for LM613C) 0.1 1.3 1.3 mV (Max)
VR(V+ = 5V) −VR(V+ = 3V) 0.01 1 1 mV (Max)
0.01 1.5 1.5 mV (Max)
IFB FEEDBACK Bias VANODE ≤VFB ≤5.06V 22 35 50 nA (Max)
Current 29 40 55 nA (Max)
(4) VRis the Cathode-to-feedback voltage, nominally 1.244V.
(5) Average reference drift is calculated from the measurement of the reference voltage at 25°C and at the temperature extremes. The drift,
in ppm/°C, is 106•ΔVR/(VR[25°C]•ΔTJ), where ΔVRis the lowest value subtracted from the highest, VR[25°C] is the value at 25°C, and ΔTJis
the temperature range. This parameter is ensured by design and sample testing.
(6) Hysteresis is the change in VRcaused by a change in TJ, after the reference has been “dehysterized”. To dehysterize the reference; that
is minimize the hysteresis to the typical value, its junction temperature should be cycled in the following pattern, spiraling in toward
25°C: 25°C, 85°C, −40°C, 70°C, 0°C, 25°C.
(7) Low contact resistance is required for accurate measurement.
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Electrical Characteristics (continued)
These specifications apply for V−= GND = 0V, V+= 5V, VCM = VOUT = 2.5V, IR= 100 μA, FEEDBACK pin shorted to GND,
unless otherwise specified. Limits in standard typeface are for TJ= 25°C; limits in boldface type apply over the Operating
Temperature Range.LM613M
LM613AM LM613I
Parameter Test Conditions Typ(1) LM613AI Units
LM613C
Limits(2) Limits(2)
enVRNoise 10 Hz to 10 kHz, 30 μVRMS
VRO = VR
Simplified Schematic Diagrams
Figure 4. Op Amp
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TYPICAL PERFORMANCE CHARACTERISTICS (Reference)
TJ= 25°C, FEEDBACK pin shorted to V−= 0V, unless otherwise noted
Reference Voltage vs Temp. Reference Voltage Drift
Figure 7. Figure 8.
Accelerated Reference Reference Voltage vs
Voltage Drift vs Time Current and Temperature
Figure 9. Figure 10.
Reference Voltage vs Reference Voltage vs
Current and Temperature Reference Current
Figure 11. Figure 12.
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TYPICAL PERFORMANCE CHARACTERISTICS (Reference) (continued)
TJ= 25°C, FEEDBACK pin shorted to V−= 0V, unless otherwise noted
Reference Voltage vs Reference AC
Reference Current Stability Range
Figure 13. Figure 14.
FEEDBACK Current vs FEEDBACK Current vs
FEEDBACK-to-Anode Voltage FEEDBACK-to-Anode Voltage
Figure 15. Figure 16.
Reference Noise Voltage Reference Small-Signal
vs Frequency Resistance vs Frequency
Figure 17. Figure 18.
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TYPICAL PERFORMANCE CHARACTERISTICS (Reference) (continued)
TJ= 25°C, FEEDBACK pin shorted to V−= 0V, unless otherwise noted Reference Voltage with
Reference Power-Up Time FEEDBACK Voltage Step
Figure 19. Figure 20.
Reference Step Response
Reference Voltage with for 100 μA∼∼ 10 mA
100 ∼∼ 12 μA Current Step Current Step
Figure 21. Figure 22.
Reference Voltage Change Reference Change vs
with Supply Voltage Step Common-Mode Voltage
Figure 23. Figure 24.
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TYPICAL PERFORMANCE CHARACTERISTICS (Op Amps)
V+= 5V, V−= GND = 0V, VCM = V+/2, VOUT = V+/2, TJ= 25°C, unless otherwise noted
Input Common-Mode VOS vs Junction
Voltage Range vs Temperature Temperature
Figure 25. Figure 26.
Input Bias Current vs Large-Signal
Common-Mode Voltage Step Response
Figure 27. Figure 28.
Output Voltage Swing Output Source Current vs
vs Temp. and Current Output Voltage and Temp.
Figure 29. Figure 30.
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TYPICAL PERFORMANCE CHARACTERISTICS (Op Amps) (continued)
V+= 5V, V−= GND = 0V, VCM = V+/2, VOUT = V+/2, TJ= 25°C, unless otherwise noted
Output Sink Current vs Output Swing,
Output Voltage Large Signal
Figure 31. Figure 32.
Output Impedance vs Small Signal Pulse
Frequency and Gain Response vs Temp.
Figure 33. Figure 34.
Small-Signal Pulse Op Amp Voltage Noise
Response vs Load vs Frequency
Figure 35. Figure 36.
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TYPICAL PERFORMANCE CHARACTERISTICS (Op Amps) (continued)
V+= 5V, V−= GND = 0V, VCM = V+/2, VOUT = V+/2, TJ= 25°C, unless otherwise noted
Op Amp Current Noise Small-Signal Voltage Gain vs
vs Frequency Frequency and Temperature
Figure 37. Figure 38.
Small-Signal Voltage Gain Follower Small-Signal
vs Frequency and Load Frequency Response
Figure 39. Figure 40.
Common-Mode Input Power Supply Current
Voltage Rejection Ratio vs Power Supply Voltage
Figure 41. Figure 42.
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TYPICAL PERFORMANCE CHARACTERISTICS (Op Amps) (continued)
V+= 5V, V−= GND = 0V, VCM = V+/2, VOUT = V+/2, TJ= 25°C, unless otherwise noted
Positive Power Supply Negative Power Supply
Voltage Rejection Ratio Voltage Rejection Ratio
Figure 43. Figure 44.
Input Offset Current vs
Slew Rate vs Temperature Junction Temperature
Figure 45. Figure 46.
Input Bias Current vs
Junction Temperature
Figure 47.
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TYPICAL PERFORMANCE CHARACTERISTICS (Comparators)
Input Bias Current vs
Output Sink Current Common-Mode Voltage
Figure 48. Figure 49.
Comparator Response Times— Comparator Response Times—
Inverting Input, Positive Transition Inverting Input, Negative Transition
Figure 50. Figure 51.
Comparator Response Times— Comparator Response Times—
Non-Inverting Input, Positive Transition Non-Inverting Input, Negative Transition
Figure 52. Figure 53.
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TYPICAL PERFORMANCE CHARACTERISTICS (Comparators) (continued)
Comparator Response Times— Comparator Response Times—
Inverting Input, Positive Transition Inverting Input, Negative Transition
Figure 54. Figure 55.
Comparator Response Times— Comparator Response Times—
Non-Inverting Input, Positive Transition Non-Inverting Input, Negative Transition
Figure . Figure 56.
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TYPICAL PERFORMANCE DISTRIBUTIONS
Average VOS Drift Average VOS Drift
Military Temperature Range Industrial Temperature Range
Figure 57. Figure 58.
Average VOS Drift Average IOS Drift
Commercial Temperature Range Military Temperature Range
Figure 59. Figure 60.
Average IOS Drift Op Amp Voltage
Industrial Temperature Range Noise Distribution
Figure 61. Figure 62.
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TYPICAL PERFORMANCE DISTRIBUTIONS (continued)
Average IOS Drift Op Amp Current
Commercial Temperature Range Noise Distribution
Figure 63. Figure 64.
Voltage Reference Broad-Band
Noise Distribution
Figure 65.
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APPLICATION INFORMATION
VOLTAGE REFERENCE
Reference Biasing
The voltage reference is of a shunt regulator topology that models as a simple zener diode. With current Ir
flowing in the “forward” direction there is the familiar diode transfer function. Irflowing in the reverse direction
forces the reference voltage to be developed from cathode to anode. The cathode may swing from a diode drop
below V−to the reference voltage or to the avalanche voltage of the parallel protection diode, nominally 7V. A
6.3V reference with V+= 3V is allowed.
Figure 66. Voltage Associated with Reference
(current source Iris external)
The reference equivalent circuit reveals how Vris held at the constant 1.2V by feedback, and how the
FEEDBACK pin passes little current.
To generate the required reverse current, typically a resistor is connected from a supply voltage higher than the
reference voltage. Varying that voltage, and so varying Ir, has small effect with the equivalent series resistance of
less than an ohm at the higher currents. Alternatively, an active current source, such as the LM134 series, may
generate Ir.
Figure 67. Reference Equivalent Circuit
Figure 68. 1.2V Reference
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Capacitors in parallel with the reference are allowed. See the Reference AC Stability Range typical curve for
capacitance values—from 20 μA to 3 mA any capacitor value is stable. With the reference's wide stability range
with resistive and capacitive loads, a wide range of RC filter values will perform noise filtering.
Adjustable Reference
The FEEDBACK pin allows the reference output voltage, Vro, to vary from 1.24V to 6.3V. The reference attempts
to hold Vrat 1.24V. If Vris above 1.24V, the reference will conduct current from Cathode to Anode; FEEDBACK
current always remains low. If FEEDBACK is connected to Anode, then Vro = Vr= 1.24V. For higher voltages
FEEDBACK is held at a constant voltage above Anode—say 3.76V for Vro = 5V. Connecting a resistor across the
constant Vrgenerates a current I=R1/Vrflowing from Cathode into FEEDBACK node. A Thevenin equivalent
3.76V is generated from FEEDBACK to Anode with R2=3.76/I. Keep I greater than one thousand times larger
than FEEDBACK bias current for <0.1% error—I≥32 μA for the military grade over the military temperature range
(I≥5.5 μA for a 1% untrimmed error for a commercial part).
Figure 69. Thevenin Equivalent of Reference
with 5V Output
R1 = Vr/I = 1.24/32μ= 39k
R2 = R1 {(Vro/Vr) −1} = 39k {(5/1.24) −1)} = 118k
Figure 70. Resistors R1 and R2 Program Reference Output Voltage to be 5V
Understanding that Vris fixed and that voltage sources, resistors, and capacitors may be tied to the FEEDBACK
pin, a range of Vrtemperature coefficients may be synthesized.
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Figure 71. Output Voltage has Negative Temperature Coefficient (TC) if R2 has Negative TC
Figure 72. Output Voltage has Positive TC
if R1 has Negative TC
Figure 73. Diode in Series with R1 Causes Voltage Across R1 and R2 to be Proportional to Absolute
Temperature (PTAT)
Connecting a resistor across Cathode-to-FEEDBACK creates a 0 TC current source, but a range of TCs may be
synthesized.
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I = Vr/R1 = 1.24/R1
Figure 74. Current Source is Programmed by R1
Figure 75. Proportional-to-Absolute-Temperature Current Source
Figure 76. Negative-TC Current Source
Reference Hysteresis
The reference voltage depends, slightly, on the thermal history of the die. Competitive micro-power products
vary— always check the data sheet for any given device. Do not assume that no specification means no
hysteresis.
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OPERATIONAL AMPLIFIERS AND COMPARATORS
Any amp, comparator, or the reference may be biased in any way with no effect on the other sections of the
LM613, except when a substrate diode conducts, see (1) in Electrical Characteristics. For example, one amp
input may be outside the common-mode range, another amp may be operating as a comparator, and all other
sections may have all terminals floating with no effect on the others. Tying inverting input to output and non-
inverting input to V−on unused amps is preferred. Unused comparators should have non-inverting input and
output tied to V+, and inverting input tied to V−. Choosing operating points that cause oscillation, such as driving
too large a capacitive load, is best avoided.
Op Amp Output Stage
These op amps, like the LM124 series, have flexible and relatively wide-swing output stages. There are simple
rules to optimize output swing, reduce cross-over distortion, and optimize capacitive drive capability:
1. Output Swing: Unloaded, the 42 μA pull-down will bring the output within 300 mV of V−over the military
temperature range. If more than 42 μA is required, a resistor from output to V−will help. Swing across any
load may be improved slightly if the load can be tied to V+, at the cost of poorer sinking open-loop voltage
gain.
2. Cross-Over Distortion: The LM613 has lower cross-over distortion (a 1 VBE deadband versus 3 VBE for the
LM124), and increased slew rate as shown in the characteristic curves. A resistor pull-up or pull-down will
force class-A operation with only the PNP or NPN output transistor conducting, eliminating cross-over
distortion.
3. Capacitive Drive: Limited by the output pole caused by the output resistance driving capacitive loads, a pull-
down resistor conducting 1 mA or more reduces the output stage NPN reuntil the output resistance is that of
the current limit 25Ω. 200 pF may then be driven without oscillation.
Comparator Output Stage
The comparators, like the LM139 series, have open-collector output stages. A pull-up resistor must be added
from each output pin to a positive voltage for the output transistor to switch properly. When the output transistor
is OFF, the output voltage will be this external positive voltage.
For the output voltage to be under the TTL-low voltage threshold when the output transistor is ON, the output
current must be less than 8 mA (over temperature). This impacts the minimum value of pull-up resistor.
The offset voltage may increase when the output voltage is low and the output current is less than 30 μA. Thus,
for best accuracy, the pull-up resistor value should be low enough to allow the output transistor to sink more than
30 μA.
Op Amp and Comparator Input Stage
The lateral PNP input transistors, unlike those of most op amps, have BVEBO equal to the absolute maximum
supply voltage. Also, they have no diode clamps to the positive supply nor across the inputs. These features
make the inputs look like high impedances to input sources producing large differential and common-mode
voltages.
(1) Absolute maximum ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply
when operating the device beyond its rated operating conditions.
Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LM613
LM613
SNOSC11B –AUGUST 2000–REVISED MARCH 2013
www.ti.com
Typical Applications
Figure 77. High Current, High Voltage Switch
Figure 78. High Speed Level Shifter. Response Time is Approximately
1.5 μs, Where Output is Either Approximately +V or −V.
*10k must be low
t.c. trimpot
Figure 79. Ultra Low Noise, 10.00V Reference. Total Output Noise is Typically 14 μVRMS.
24 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: LM613
LM613
www.ti.com
SNOSC11B –AUGUST 2000–REVISED MARCH 2013
Figure 80. Basic Comparator
Figure 81. Basic Comparator with External Strobe
Figure 82. Wide-Input Range
Comparator with TTL Output
Figure 83. Comparator with
Hysteresis (ΔVH=+V(1k/1M))
Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: LM613
LM613
SNOSC11B –AUGUST 2000–REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Revision A (March 2013) to Revision B Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 25
26 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: LM613
PACKAGE OPTION ADDENDUM
www.ti.com 15-Aug-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM613IWM LIFEBUY SOIC DW 16 45 TBD Call TI Call TI -40 to 85 LM613IWM
LM613IWM/NOPB LIFEBUY SOIC DW 16 45 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LM613IWM
LM613IWMX LIFEBUY SOIC DW 16 1000 TBD Call TI Call TI -40 to 85 LM613IWM
LM613IWMX/NOPB LIFEBUY SOIC DW 16 1000 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LM613IWM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Aug-2017
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM613IWMX SOIC DW 16 1000 330.0 16.4 10.9 10.7 3.2 12.0 16.0 Q1
LM613IWMX/NOPB SOIC DW 16 1000 330.0 16.4 10.9 10.7 3.2 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Mar-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM613IWMX SOIC DW 16 1000 367.0 367.0 38.0
LM613IWMX/NOPB SOIC DW 16 1000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Mar-2013
Pack Materials-Page 2
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
DW 16 SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
4040000-2/H
www.ti.com
PACKAGE OUTLINE
C
TYP
10.63
9.97
2.65 MAX
14X 1.27
16X 0.51
0.31
2X
8.89
TYP
0.33
0.10
0 - 8 0.3
0.1
(1.4)
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
10.5
10.1
BNOTE 4
7.6
7.4
4220721/A 07/2016
SOIC - 2.65 mm max heightDW0016A
SOIC
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
116
0.25 C A B
9
8
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.500
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
(9.3)
14X (1.27)
R0.05 TYP
16X (2)
16X (0.6)
4220721/A 07/2016
SOIC - 2.65 mm max heightDW0016A
SOIC
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
OPENING
SOLDER MASK METAL
SOLDER MASK
DEFINED
LAND PATTERN EXAMPLE
SCALE:7X
SYMM
1
89
16
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
R0.05 TYP
16X (2)
16X (0.6)
14X (1.27)
(9.3)
4220721/A 07/2016
SOIC - 2.65 mm max heightDW0016A
SOIC
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
SYMM
SYMM
1
89
16
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