CAT24C64WIGT-QQ - ON SEMICONDUCTOR

October, 2017 − Rev. 26 1Publication Order Number:

CAT24C64/D

CAT24C64

64 Kb I2C CMOS Serial

EEPROM

Description

The CAT24C64 is a 64 Kb CMOS Serial EEPROM device,

internally organized as 8192 words of 8 bits each.

It features a 32−byte page write buffer and supports the Standard

(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocol.

External address pins make it possible to address up to eight

CAT24C64 devices on the same bus.

Features

•Supports Standard, Fast and Fast−Plus I2C Protocol

•1.7 V to 5.5 V Supply Voltage Range

•32−Byte Page Write Buffer

•Hardware Write Protection for Entire Memory

•Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs

(SCL and SDA)

•Low Power CMOS Technology

•1,000,000 Program/Erase Cycles

•100 Year Data Retention

•Industrial and Extended Temperature Range

•PDIP, SOIC, TSSOP, US 8−lead, UDFN 8−pad and Ultra−thin

WLCSP 4−bump Packages

•This Device is Pb−Free, Halogen Free/BFR Free, and RoHS

Compliant

Figure 1. Functional Symbol

SDA

SCL

CAT24C64

VCC

VSS

A2, A1, A0

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PIN CONFIGURATIONS (Top Views)

See detailed ordering and shipping information in the package

dimensions section on page 15 of this data sheet.

ORDERING INFORMATION

SOIC−8

W SUFFIX

CASE 751BD

PDIP (L), SOIC (W, X),

TSSOP (Y), UDFN (HU4)

PDIP−8

L SUFFIX

CASE 646AA

TSSOP−8

Y SUFFIX

CASE 948AL

Device AddressA0, A1, A2Serial DataSDA Serial ClockSCL Write ProtectWP Power SupplyVCC GroundVSS

FunctionPin Name

PIN FUNCTION

For the location of Pin 1, please consult the

corresponding package drawing.

UDFN−8

HU4 SUFFIX

CASE 517AZ

SOIC−8*

X SUFFIX

CASE 751BE

WLCSP−4

C4C SUFFIX

CASE 567JY

SDA

VCC

VSS

A01

SCL

WLCSP

A1 A2

B1 B2 SD

VSS

SCL

VCC

* Not recommended for new designs

X = Specific Device Code

= (see ordering information)

Y = Production Year (Last Digit)

M = Production Month (1−9, O, N, D)

W = Production Week Code

MARKING

DIAGRAMS

(WLCSP−4)

WLCSP−4

C4U SUFFIX

CASE 567PB

(C4C) (C4U)

For serial EEPROM in a US8 package, please

consult the N24C64 datasheet.

CAT24C64

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Table 1. ABSOLUTE MAXIMUM RATINGS

Parameters Ratings Units

Storage Temperature –65 to +150 °C

Voltage on Any Pin with Respect to Ground (Note 1) –0.5 to +6.5 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be af fected.

1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may

undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.

Table 2. RELIABILITY CHARACTERISTICS (Note 2)

Symbol Parameter Min Units

NEND (Note 3) Endurance 1,000,000 Program/Erase Cycles

TDR Data Retention 100 Years

2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

3. Page Mode, VCC = 5 V, 25°C.

Table 3. D.C. OPERATING CHARACTERISTICS

(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise speciﬁed.)

Symbol Parameter Test Conditions Min Max Units

ICCR Read Current Read, fSCL = 400 kHz 1 mA

ICCW Write Current Write, fSCL = 400 kHz 2 mA

ISB Standby Current All I/O Pins at GND or VCC TA = −40°C to +85°C

VCC ≤ 3.3 V 1mA

TA = −40°C to +85°C

VCC > 3.3 V 3

TA = −40°C to +125°C 5

ILI/O Pin Leakage Pin at GND or VCC 2mA

VIL Input Low Voltage −0.5 VCC x 0.3 V

VIH Input High Voltage VCC x 0.7 VCC + 0.5 V

VOL1 Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA 0.4 V

VOL2 Output Low Voltage VCC < 2.5 V, IOL = 1.0 mA 0.2 V

Table 4. PIN IMPEDANCE CHARACTERISTICS

(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise speciﬁed.)

Symbol Parameter Conditions Max Units

CIN (Note 4) SDA I/O Pin Capacitance VIN = 0 V 8 pF

CIN (Note 4) Input Capacitance (other pins) VIN = 0 V 6 pF

IWP (Note 5) WP Input Current VIN < VIH, VCC = 5.5 V 130 mA

VIN < VIH, VCC = 3.3 V 120

VIN < VIH, VCC = 1.8 V 80

VIN > VIH 2

IA (Note 5) Address Input Current

(A0, A1, A2)

Product Rev F

VIN < VIH, VCC = 5.5 V 50 mA

VIN < VIH, VCC = 3.3 V 35

VIN < VIH, VCC = 1.8 V 25

VIN > VIH 2

4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

5. When n ot d riven, th e W P, A 0, A 1 a nd A 2 p ins a re p ulled d own t o G ND i nternally. F or i mproved noise i mmunity, th e i nternal p ull− down i s relatively

strong; therefore the external driver must be able t o s upply t he p ull− down c urrent w hen a ttempting to d rive the i nput H IGH. To conserve p ower,

as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source.

CAT24C64

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Table 5. A.C. CHARACTERISTICS

(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C.) (Note 6)

Symbol Parameter

Standard

VCC = 1.7 V − 5.5 V Fast

VCC = 1.7 V − 5.5 V

Fast−Plus (Note 9)

VCC = 2.5 V − 5.5 V

TA = −405C to +855C

Units

Min Max Min Max Min Max

FSCL Clock Frequency 100 400 1,000 kHz

tHD:STA START Condition Hold Time 4 0.6 0.25 ms

tLOW Low Period of SCL Clock 4.7 1.3 0.45 ms

tHIGH High Period of SCL Clock 4 0.6 0.40 ms

tSU:STA START Condition Setup Time 4.7 0.6 0.25 ms

tHD:DAT Data In Hold Time 000ms

tSU:DAT Data In Setup Time 250 100 50 ns

tR (Note 7) SDA and SCL Rise Time 1,000 300 100 ns

tF (Note 7) SDA and SCL Fall Time 300 300 100 ns

tSU:STO STOP Condition Setup Time 4 0.6 0.25 ms

tBUF Bus Free Time Between

STOP and START 4.7 1.3 0.5 ms

tAA SCL Low to Data Out Valid 3.5 0.9 0.40 ms

tDH Data Out Hold Time 100 100 50 ns

Ti (Note 7) Noise Pulse Filtered at SCL

and SDA Inputs 100 100 100 ns

tSU:WP WP Setup Time 000ms

tHD:WP WP Hold Time 2.5 2.5 1 ms

tWR Write Cycle Time 5 5 5 ms

tPU (Notes 7, 8) Power−up to Ready Mode 1 1 0.1 1 ms

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

6. Test conditions according to “A.C. Test Conditions” table.

7. Tested initially and after a design or process change that affects this parameter.

8. tPU is the delay between the time VCC is stable and the device is ready to accept commands.

9. Fast−Plus (1 MHz) speed class available for product revision “F”. The die revision “F” is identified by letter “F” or a dedicated marking code

on top of the package.

Table 6. A.C. TEST CONDITIONS

Input Levels 0.2 x VCC to 0.8 x VCC

Input Rise and Fall Times ≤ 50 ns

Input Reference Levels 0.3 x VCC, 0.7 x VCC

Output Reference Levels 0.5 x VCC

Output Load Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF

CAT24C64

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Power−On Reset (POR)

Each CAT24C64 incorporates Power−On Reset (POR)

circuitry which protects the internal logic against powering

up in the wrong state. The device will power up into Standby

mode after VCC exceeds the POR trigger level and will

power down into Reset mode when VCC drops below the

POR trigger level. This bi−directional POR behavior

protects the device against ‘brown−out’ failure following a

temporary loss of power.

Pin Description

SCL: The Serial Clock input pin accepts the clock signal

generated by the Master.

SDA: The Serial Data I/O pin accepts input data and delivers

output data. In transmit mode, this pin is open drain. Data is

acquired on the positive edge, and is delivered on the

negative edge of SCL.

A0, A1 and A2: The Address inputs set the device address

that must be matched by the corresponding Slave address

bits. The Address inputs are hard−wired HIGH or LOW

allowing for up to eight devices to be used (cascaded) on the

same bus. When left floating, these pins are pulled LOW

internally. The Address inputs are not available for use with

WLCSP 4−bumps.

WP: When pulled HIGH, the Write Protect input pin

inhibits all write operations. When left floating, this pin is

pulled LOW internally. The WP input is not available for the

WLCSP 4−bumps, therefore all write operations are allowed

for the device in this package.

Functional Description

The CAT24C64 supports the Inter−Integrated Circuit

(I2C) Bus protocol. The protocol relies on the use of a Master

device, which provides the clock and directs bus traffic, and

Slave devices which execute requests. The CAT24C64

operates as a Slave device. Both Master and Slave can

transmit or receive, but only the Master can assign those

roles.

I2C Bus Protocol

The 2−wire I2C bus consists of two lines, SCL and SDA,

connected to the VCC supply via pull−up resistors. The

Master provides the clock to the SCL line, and either the

Master o r the Slaves drive the SDA line. A ‘0’ is transmitted

by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data

transfer may be initiated only when the bus is not busy (see

A.C. Characteristics). During data transfer, SDA must

remain stable while SCL is HIGH.

START/STOP Condition

An SDA transition while SCL is HIGH creates a START

or STOP condition (Figure 2). The START consists of a

HIGH to LOW SDA transition, while SCL is HIGH. Absent

the START, a Slave will not respond to the Master. The

STOP completes all commands, and consists of a LOW to

HIGH SDA transition, while SCL is HIGH.

Device Addressing

The Master addresses a Slave by creating a START

condition and then broadcasting an 8−bit Slave address. For

the CAT24C64, the first four bits of the Slave address are set

to 1010 (Ah); the next three bits, A2, A1 and A0, must match

the logic state of the similarly named input pins. The devices

in WLCSP 4−bumps respond only to the Slave Address with

A2 A1 A0 = 000 (CAT24C64C4CTR) or to A2 A1 A0 = 100

(CAT24C64AC4CTR). The R/W bit tells the Slave whether

the Master intends to read (1) or write (0) data (Figure 3).

Acknowledge

During the 9th clock cycle following every byte sent to the

bus, the transmitter releases the SDA line, allowing the

receiver to respond. The receiver then either acknowledges

(ACK) by pulling SDA LOW, or does not acknowledge

(NoACK) by letting SDA stay HIGH (Figure 4). Bus timing

is illustrated in Figure 5.

START

CONDITION STOP

CONDITION

SDA

SCL

Figure 2. Start/Stop Timing

Figure 3. Slave Address Bits

1010

DEVICE ADDRESS*

A2A1A0R/W

* The devices in WLCSP 4−bumps respond only to the Slave Address with: A2 A1 A0 = 000, CAT24C64C4CTR

* The devices in WLCSP 4−bumps respond only to the Slave Address with: A2 A1 A0 = 100, CAT24C64AC4CTR

CAT24C64

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Figure 4. Acknowledge Timing

189

START

SCL FROM

MASTER

BUS RELEASE DELAY (TRANSMITTER) BUS RELEASE DELAY (RECEIVER)

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

ACK SETUP (≥ tSU:DAT)

ACK DELAY (≤ tAA)

Figure 5. Bus Timing

SCL

SDA IN

SDA OUT

tBUF

tSU:STO

tSU:DAT

tAA tDH

tLOW

tHIGH

tLOW

tSU:STA tHD:STA

tHD:DAT

WRITE OPERATIONS

Byte Write

To write data to memory, the Master creates a START

condition on the bus and then broadcasts a Slave address

with the R/W bit set to ‘0’. The Master then sends two

address bytes and a data byte and concludes the session by

creating a STOP condition on the bus. The Slave responds

with ACK after every byte sent by the Master (Figure 6). The

STOP starts the internal Write cycle, and while this

operation is in progress (tWR), the SDA output is tri−stated

and the Slave does not acknowledge the Master (Figure 7).

Page Write

The Byte Write operation can be expanded to Page Write,

by sending more than one data byte to the Slave before

issuing the STOP condition (Figure 8). Up to 32 distinct data

bytes can be loaded into the internal Page Write Buffer

starting at the address provided by the Master. The page

address is latched, and as long as the Master keeps sending

data, the internal byte address is incremented up to the end

of page, where it then wraps around (within the page). New

data can therefore replace data loaded earlier. Following the

STOP, data loaded during the Page Write session will be

written to memory in a single internal Write cycle (tWR).

Acknowledge Polling

As soon (and as long) as internal Write is in progress, the

Slave will not acknowledge the Master. This feature enables

the Master to immediately follow−up with a new Read or

Write request, rather than wait for the maximum specified

Write time (tWR) to elapse. Upon receiving a NoACK

response from the Slave, the Master simply repeats the

request until the Slave responds with ACK.

Hardware Write Protection

With the WP pin held HIGH, the entire memory is

protected against Write operations. If the WP pin is left

floating or is grounded, it has no impact on the Write

operation. The state of the WP pin is strobed on the last

falling edge of SCL immediately preceding the 1st data byte

(Figure 9). If the WP pin is HIGH during the strobe interval,

the Slave will not acknowledge the data byte and the Write

request will be rejected.

Delivery State

The CAT24C64 is shipped erased, i.e., all bytes are FFh.

CAT24C64

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SLAVE

ADDRESS

***

BUS ACTIVITY :

MASTER

SLAVE

ADDRESS

BYTE ADDRESS

BYTE DATA

BYTE

Figure 6. Byte Write Sequence

*a15 − a13 are don’t care bits.

a15 − a8a7 − a0d7 − d0

Figure 7. Write Cycle Timing

STOP

CONDITION START

CONDITION ADDRESS

ACK8th Bit

Byte n

SCL

SDA

tWR

SLAVE

ADDRESS

BUS

ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE ADDRESS

BYTE

DATA

BYTE

DATA

BYTE

n+1

DATA

BYTE

n+P

Figure 8. Page Write Sequence

Figure 9. WP Timing

189

ADDRESS

BYTE DATA

BYTE

SCL

SDA

tSU:WP

tHD:WP

a7a0d7d0

CAT24C64

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READ OPERATIONS

Immediate Read

To read data from memory, the Master creates a START

condition on the bus and then broadcasts a Slave address

with the R/W bit set to ‘1’. The Slave responds with ACK

and starts shifting out data residing at the current address.

After receiving the data, the Master responds with NoACK

and terminates the session by creating a STOP condition on

the bus (Figure 10). The Slave then returns to Standby mode.

Selective Read

To read data residing at a speciﬁc address, the selected

address must ﬁrst be loaded into the internal address register .

This is done by starting a Byte Write sequence, whereby the

Master creates a START condition, then broadcasts a Slave

address with the R/W bit set to ‘0’ and then sends two

address bytes to the Slave. Rather than completing the Byte

Write sequence by sending data, the Master then creates a

START condition and broadcasts a Slave address with the

R/W bit set to ‘1’. The Slave responds with ACK after every

byte sent by the Master and then sends out data residing at

the selected address. After receiving the data, the Master

responds with NoACK and then terminates the session by

creating a STOP condition on the bus (Figure 11).

Sequential Read

If, after receiving data sent by the Slave, the Master

responds with ACK, then the Slave will continue

transmitting until the Master responds with NoACK

followed by S TOP (Figure 12). During Sequential Read the

internal byte address is automatically incremented up to the

end of memory, where it then wraps around to the beginning

of memory.

Figure 10. Immediate Read Sequence and Timing

SCL

SDA 8th Bit

STOP

NO ACKDATA OUT

SLAVE

ADDRESS

KDATA

BYTE

BUS ACTIVITY :

MASTER

SLAVE

Figure 11. Selective Read Sequence

SLAVE

ADDRESS

TSLAVE

ADDRESS

BYTE ADDRESS

DATA

BYTE

BUS ACTIVITY :

MASTER

SLAVE

Figure 12. Sequential Read Sequence

SLAVE

ADDRESS

DATA

BYTE

DATA

BYTE

n+1

DATA

BYTE

n+2

DATA

BYTE

n+x

BUS ACTIVITY :

MASTER

SLAVE

CAT24C64

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PACKAGE DIMENSIONS

PDIP−8, 300 mils

CASE 646AA−01

ISSUE A

TOP VIEW

SIDE VIEW END VIEW

PIN # 1

IDENTIFICATION

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC MS-001.

SYMBOL MIN NOM MAX

0.38

2.92

0.36

6.10

1.14

0.20

9.02

2.54 BSC

3.30

5.33

4.95

0.56

7.11

1.78

0.36

10.16

eB 7.87 10.92

E 7.62 8.25

2.92 3.80

3.30

0.46

6.35

1.52

0.25

9.27

7.87

CAT24C64

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PACKAGE DIMENSIONS

SOIC 8, 150 mils

CASE 751BD−01

ISSUE O

E1 E

PIN # 1

IDENTIFICATION

TOP VIEW

SIDE VIEW END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-012.

SYMBOL MIN NOM MAX

0º 8º

0.10

0.33

0.19

0.25

4.80

5.80

3.80

1.27 BSC

1.75

0.25

0.51

0.25

0.50

5.00

6.20

4.00

L0.40 1.27

1.35

CAT24C64

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PACKAGE DIMENSIONS

SOIC−8, 208 mils

CASE 751BE−01

ISSUE O

SIDE VIEW

TOP VIEW

PIN#1 IDENTIFICATION

END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with EIAJ EDR-7320.

SYMBOL MIN NOM MAX

0º 8º

0.05

0.36

0.19

5.13

7.75

5.13

1.27 BSC

2.03

0.25

0.48

0.25

5.33

8.26

5.38

L0.51 0.76

CAT24C64

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PACKAGE DIMENSIONS

TSSOP8, 4.4x3

CASE 948AL−01

ISSUE O

E1 E

TOP VIEW

SIDE VIEW END VIEW

L1 L

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MO-153.

SYMBOL

MIN NOM MAX

0º 8º

0.05

0.80

0.19

0.09

0.50

2.90

6.30

4.30

0.65 BSC

1.00 REF

1.20

0.15

1.05

0.30

0.20

0.75

3.10

6.50

4.50

0.90

0.60

3.00

6.40

4.40

CAT24C64

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PACKAGE DIMENSIONS

UDFN8, 2x3 EXTENDED PAD

CASE 517AZ−01

ISSUE O

0.065 REF

Copper Exposed

PIN #1 INDEX AREA

PIN #1

IDENTIFICATION

DAP SIZE 1.8 x 1.8

DETAIL A

TOP VIEW SIDE VIEW

FRONT VIEW

DETAIL A

BOTTOM VIEW

0.065 REF

0.0 - 0.05A3

Notes:

(1) All dimensions are in millimeters.

(2) Refer JEDEC MO-236/MO-252.

SYMBOL MIN NOM MAX

A 0.45 0.50 0.55

A1 0.00 0.02 0.05

A3 0.127 REF

b 0.20 0.25 0.30

D 1.95 2.00 2.05

D2 1.35 1.40 1.45

E 3.00

E2 1.25 1.30 1.35

2.95

0.50 REF

3.05

L 0.25 0.30 0.35

CAT24C64

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PACKAGE DIMENSIONS

ÈÈ

WLCSP4, 0.76x0.76

CASE 567JY

ISSUE O

SEATING

PLANE

0.05 C

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. COPLANARITY APPLIES TO SPHERICAL

CROWNS OF SOLDER BALLS.

2X DIM

AMIN MAX

−−−

MILLIMETERS

D0.76 BSC

b0.15 0.16

e0.40 BSC

0.35

PIN A1

REFERENCE

A0.05 BC

0.03 C

0.05 C

4X b

0.05 C

0.0415 0.0715

0.76 BSC

0.05 C

2X TOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 3

A2 0.255 REF

PITCH 0.16

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.40 0.40

RECOMMENDED

A1 PACKAGE

OUTLINE

PITCH

DIE COAT

DETAIL A

(OPTIONAL) A2

A3 0.025 REF

DET AIL A

CAT24C64

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PACKAGE DIMENSIONS

ÈÈ

WLCSP4, 0.76x0.76

CASE 567PB

ISSUE O

SEATING

PLANE

PIN A1

REFERENCE

A0.05 BC

0.03 C

0.05 C

4X b

0.05 C

TOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 4

PITCH 0.16

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.40 0.40

RECOMMENDED

1PACKAGE

OUTLINE

PITCH

DET AIL A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DATUM C, THE SEATING PLANE, IS DEFINED BY THE

SPHERICAL CROWNS OF THE SOLDER BALLS.

4. COPLANARITY APPLIES TO SPHERICAL CROWNS OF

THE SOLDER BALLS.

5. DIMENSION b IS MEASURED AT THE MAXIMUM

CONTACT BALL DIAMETER PARALLEL TO DATUM C.

6. BACKSIDE COATING IS OPTIONAL.

DIM

AMIN NOM

−−−

MILLIMETERS

b0.15 0.155

e0.40 BSC

−−−

0.04 0.055

A2 0.19 REF

A3 0.025 REF

0.71 0.76

MAX

0.16

0.30

0.07

0.81

DETAIL A

NOTE 6

DIE COAT

(OPTIONAL) A3

NOTE 5

NOTE 3

CAT24C64

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ORDERING INFORMATION

Device Order Number

Specific

Device

Marking Package Type Temperature Range Lead Finish Shipping

CAT24C64LI−G 24C64F PDIP−8 I = Industrial

(−40°C to +85°C) NiPdAu Tube, 50 Units / Tube

CAT24C64WE−GT3 (Note 12) 24C64F SOIC−8, JEDEC E = Extended

(−40°C to +125°C) NiPdAu Tape & Reel,

3,000 Units / Reel

CAT24C64WI−GT3 24C64F SOIC−8, JEDEC I = Industrial

(−40°C to +85°C) NiPdAu Tape & Reel,

3,000 Units / Reel

CAT24C64WI−G 24C64F SOIC−8, JEDEC I = Industrial

(−40°C to +85°C) NiPdAu Tube, 100 Units / Tube

CAT24C64XI−T2 24C64F SOIC−8, EIAJ I = Industrial

(−40°C to +85°C) Matte−Tin Tape & Reel,

2,000 Units / Reel

CAT24C64YE−GT3 (Note 12) C64F TSSOP−8 E = Extended

(−40°C to +125°C) NiPdAu Tape & Reel,

3,000 Units / Reel

CAT24C64YI−GT3 C64F TSSOP−8 I = Industrial

(−40°C to +85°C) NiPdAu Tape & Reel,

3,000 Units / Reel

CAT24C64YI−G C64F TSSOP−8 I = Industrial

(−40°C to +85°C) NiPdAu Tube, 100 Units / Tube

CAT24C64HU4E−GT3 (Note 12) C6U UDFN−8 E = Extended

(−40°C to +125°C) NiPdAu Tape & Reel,

3,000 Units / Reel

CAT24C64HU4I−GT3 C6U UDFN−8 I = Industrial

(−40°C to +85°C) NiPdAu Tape & Reel,

3,000 Units / Reel

CAT24C64C4CTR AWLCSP−4

with Die Coat Industrial

(−40°C to +85°C) N/A Tape & Reel,

5,000 Units / Reel

CAT24C64AC4CTR (Note 14) TBD WLCSP−4

with Die Coat Industrial

(−40°C to +85°C) N/A Tape & Reel,

5,000 Units / Reel

CAT24C64C4UTR AWLCSP−4

with Die Coat Industrial

(−40°C to +85°C) N/A Tape & Reel,

5,000 Units / Reel

10.All packages are RoHS−compliant (Lead−free, Halogen−free).

11.The standard lead finish is NiPdAu.

12.Contact factory for availability.

13.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

14.Product in development; this WLCSP−4 option responds to a different Slave Address compared to CAT24C64C4CTR.

15.Caution: The EEPROM devices delivered in WLCSP must never be exposed to ultra violet light. When exposed to ultra violet light

the EEPROM cells lose their stored data.

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Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

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Phone: 81−3−5817−1050

CAT24C64/D

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