All Silicon Delay Line series: 3D 7010 10 Taps PIN DESCRIPTION DESCRIPTION The 3D7000* series delay line is a completely silicon delay line, which features unique circuits to compensate for temperature and power supply variations. It offers 5 & 10 equally spaced taps providing delays from 5 ns to 500 ns. This series comes in a standard 14 pin DIP package, which is compatible with other standard Hybrid delay lines. It is also offered in a 16 pin SOIC package for surface mount technology to reduce P.C. board area. The 3D7000* series is designed to produce both leading and trailing edge delay time with equal precision. Each tap capable of driving up to ten 74LS type loads. 14-Pin DIP (300 mil) 1] |taP 5 3D7010- FEATURES @ High operating frequency (100 MHz). w Very low ground-bounce noise. w Voltage & temperature compensated. m Auto-insertable. m@ TTL/CMOS compatible, Low power CMOS. 2 oO [ ~ co LJ 3 m Vapor phase, IR and wave solderable. wT} r6[_]vee SPECIFICATIONS nef] |? tsL_Jne w Standard 14 pin DIP & 16 pin SOIC. ne[_] 5 v4 rar 1 @ Leading & trailing edge accuracy. tap 2[_| | 13[_]TAP 3 mg Delay tolerance: + 5% or + 2 ns, whichever is greater (others on request). tap [| 5 3D7010S- ta[_]vaP 5 uw Custom delays available: Any increment from Tap 6[_| |e uiL_Jrar 7 5 to 50 ns not listed. # Minimum input pulse width: 20% of total delay. tap a[_| |7 tof _]taPs m Delay time vs. Vee: 1.5 ns or 2% for 5 Vde + 5%, @ Temperature coefficient of delay: +1 ns or+3%, whichever nol o{ Tr 1 is greater (0 to 70C). (Others on request.) 16-Pin SOIC (300 mil) WA +a o il q a a o= 0 ull al mat TABLE Part Number Total Part Number Totat Delay Delay/Tap |Max Operating Delay Oelay/Tap | Max Operating DIP soic (ns) (ns) Freq (MHx) biP Ssoic (ns) (ns) Freq (MHz) **3D7010-50 **3D7010S-50 45 5 67 3D7010-175 3D7010S-175 4175 17.6 19 3D7010-60 3D7010S-60 60 6 55 3D7010-200 3D7010S-200 200 20 16 3D7010-75 3D7010S-75 75 75 43 307010-250 3D7010S-250 250 25 15 3D7010-80 3D7010S-80 80 8 41 3D7010-300 3D7010S-300 300 30 11 3D7010-90 3D7010S-90 90 9 37 3D7010-400 3D7010S-400 400 40 8 3D7010-100 3D7010S-100 100 10 33 3D7010-450 3D7010S-450 450 45 7 3D7010-125 3D7010S-125 125 12.5 26 3D7010-500 3D7010S8-500 500 50 6 3D7010-150 3D70108-150 150 15 22 *Patented Data Delay Devices Taps delay referenced to 1st tap. Input to 1st tap =7.5+ 5Sns. DDDIS007 3 Mt. Prospect Avenue, Clifton, New Jersey 07013 m (201) 773-2299 m FAX (201) 773-9672 m TWX 710-989-7008 series: 3D 7010 (10 Taps) ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER MIN MAX UNITS NOTES Vdd DC Supply Voltage 0.3 7.0 Vv Vin Input Pin Voltage -0.3 Vdd + 0.3 Vv lin Input Pin Current 1.0 1.0 mA 25C Tstrg Storage Temperature 55 150 Cc Tlead Lead Temperature 300 Cc 10 sec OPERATING CONDITIONS SYMBOL PARAMETER MIN MAX UNITS NOTES Vdd DC Supply Voltage 4.75 5.25 Vv *Idd Static Supply 15 mA Vss Circuit Ground 0.0 0.0 Ta Ambient Temperature 0.0 70.0 Vih High Level Input Voltage 2.0 Vv Vil Low Level Input Voltage 0.8 Vv loh High Level Output Vec=Min Current -4.0 mA Voh=2.4 lol Low Level Output Vec=Min Current 4.0 mA Vol=0.4 tie High Level Input Current 10 HA Vi = Vop lie Low Level Input Current 250 HA V,=0 Tr & Tr Output Rise & Fall Time 2 ns lbp (Dynamic) = C,, (n) VF Where: Cp, = Average capitance load/tap; n = # taps; V= Vpp max.; F = Frequency Input Capacitance = 10.0 pf typical. Output Load Capacitance = 25 pf Max. SCHEMATIC DIAGRAM TAP 1 TAP 2 TAP 3 TAP 4 TAP 5 TAP 6 TAP 7 TAP 9 TAP 10 3 Mt. Prospect Avenue, Clifton, New Jersey 07013 m (201) 773-2299 m FAX (201) 773-9672 m TWX 710-989-7008 series: 3D 7010 (10 Taps) TEST CONDITIONS INPUT: Ambient Temperature: 25C +3C Supply Voltage (Vec): 5.0V +0.1V Input Pulse: High = 3.0V+0.1V Low = 0.0V+0.1V Source impedance: 50 ohm Max. Rise and Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V) Pulse Width: 1.5 X total delay Period: 10 X total delay OUTPUT: Each output is loaded with the equivalent of one 74F04 Input gate. Delay is measured at the 1.5V level on the rising and falling edge. NOTE: Above conditions are for test only and do not restrict the operation of the device under other data sheet conditions. TEST CIRCUIT PULSE GENERATOR TIME INTERVAL COUNTER sToP VHF SWITCH CONTROL UNIT DEVICE UNDER TEST TIMING DIAGRAM + PERIOD a tRISE4 tFALL viq#} o6v y 1.5V IN| VWL" ptt Pp <__- 'PLH 1.5V 1.5V TAP 3 Mt. Prospect Avenue, Clifton, New Jersey 07013 m (201) 773-2299 m FAX (201) 773-9672 m TWX 710-989-7008 series: 3D 7010 (10 Taps) PACKAGES 14-PIN DIP (300 MIL) 240 (6.08) -260 (6.50) 55 (7.40) >| be 065 (1.65) .290 (7.37) -310 (7.87) .008 (0.20) 012 (0.30) \ Ah .150 (3.81) | 170 (431) q A 115 (2.92) 135 (3.43) 100 (2.54) | | > .014 (036) 020 (0.51) TYP. 022 (0.58) 040 (1.02) Dimensions in inches and (Millimeters) 16-PIN SOIC ( 300 MIL) 8.9 (350) > 1 10.65 (.419} 60 (299) 10.26 (404) 7.40 (.291) Fue EL 4 oo 1.27 (050) BSC 10.50 (.413) ___] 70.10 (398) 2.65 (104) = Dimensions in millimeters and (inches) 49 (.019) 36 (014) 75 {.080) yy gs. 50 (.020) 32 (.013) 23 {.009) 1.07 (.042} 0.86 (034) 30 (.012) 10 (004) 3 Mt. Prospect Avenue, Clifton, New Jersey 07013 m (201) 773-2299 m FAX (201) 773-9672 m TWX 710-989-7008 5M 594