2004 Microchip Technology Inc. Preliminary DS70082G
dsPIC30F Data Sheet
Motor Control and
Power Conversion Family
High Performance
Digital Signal Controllers
DS70082G-page ii Preliminary 2004 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2004 Microchip Technology Inc. Preliminary DS70082G-page 1
dsPIC30F
High Performance Modified RISC CPU:
• Modified Harvard architecture
• C compiler optimized instruction set architecture
• 84 base instructions
• 24-bit wide instructions, 16-bit wide data path
• Linear program memory addressing up to 4M
Instruction Words
• Linear data memory addressing up to 64 Kbytes
• Up to 144 Kbytes on-chip Flash program space
• Up to 48K Instruction Words
• Up to 8 Kbytes of on-chip data RAM
• Up to 4 Kbytes of non-volatile data EEPROM
• 16 x 16-bit working register array
• Three Address Generation Units that enable:
- Dual data fetch
- Accumulator write back for DSP operations
• Flexible Addressing modes supporting:
- Indirect, Modulo and Bit-Reversed modes
• Two, 40-bit wide accumulators with optional
saturation logic
• 17-bit x 17-bit single cycle hardware fractional/
integer multiplier
• Single cycle Multiply-Accumulate (MAC) operation
• 40-stage Barrel Shifter
• Up to 30 MIPs operation:
- DC to 40 MHz external clock input
- 4 MHz-10 MHz oscillator input with
PLL active (4x, 8x, 16x)
• Up to 42 interrupt sources
- 8 user selectable priority levels
• Vector table with up to 62 vectors
- 54 interrupt vectors
- 8 processor exceptions and software traps
Peripheral Features:
• High current sink/source I/O pins: 25 mA/25 mA
• Up to 5 external interrupt sources
•Timer module with programmable prescaler:
- Up to five 16-bit timers/counters; optionally
pair up 16-bit timers into 32-bit timer modules
• 16-bit Capture input functions
• 16-bit Compare/PWM output functions
- Dual Compare mode available
•3-wire SPI
TM modules (supports 4 Frame modes)
•I
2CTM module supports Multi-Master/Slave mode
and 7-bit/10-bit addressing
• Addressable UART modules supporting:
- Interrupt on address bit
- Wake-up on Start bit
- 4 characters deep TX and RX FIFO buffers
• CAN bus modules
Motor Control PWM Module Features:
• Up to 8 PWM output channels
- Complementary or Independent Output
modes
- Edge and Center Aligned modes
• Up to 4 duty cycle generators
• Dedicated time base with 4 modes
• Programmable output polarity
• Dead-time control for Complementary mode
• Manual output control
• Trigger for A/D conversions
Quadrature Encoder Interface Module
Features:
• Phase A, Phase B and Index Pulse input
• 16-bit up/down position counter
• Count direction status
• Position Measurement (x2 and x4) mode
• Programmable digital noise filters on inputs
• Alternate 16-bit Timer/Counter mode
• Interrupt on position counter rollover/underflow
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the dsPIC30F Family Reference
Manual (DS70046). For more information on the device
instruction set and programming, refer to the dsPIC30F
Programmer’s Reference Manual (DS70030).
dsPIC30F Enhanced Flash 16-bit Digital Signal Controllers
Motor Control and Power Conversion Family
dsPIC30F
DS70082G-page 2 Preliminary 2004 Microchip Technology Inc.
Input Capture Module Features:
• Captures 16-bit timer value
- Capture every 1st, 4th or 16th rising edge
- Capture every falling edge
- Capture every rising and falling edge
• Resolution of 33 ns at 30 MIPs
• Timer2 or Timer3 time base selection
• Input Capture during Idle
• Interrupt on input capture event
Analog Features:
• 10-bit Analog-to-Digital Converter (A/D) with:
- 500 Ksps (for 10-bit A/D) conversion rate
- Up to 16 input channels
- Conversion available during Sleep and Idle
• Programmable Low Voltage Detection (PLVD)
• Programmable Brown-out Detection and Reset
generation
Special Microcontroller Features:
• Enhanced Flash program memory:
- 10,000 erase/write cycle (min.) for
industrial temperature range, 100K (typical)
• Data EEPROM memory:
- 100,000 erase/write cycle (min.) for
industrial temperature range, 1M (typical)
• Self-reprogrammable under software control
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Flexible Watchdog Timer (WDT) with on-chip low
power RC oscillator for reliable operation
• Fail-Safe clock monitor operation
• Detects clock failure and switches to on-chip low
power RC oscillator
• Programmable code protection
• In-Circuit Serial Programming™ (ICSP™) via 3
pins and power/ground
• Selectable Power Management modes
- Sleep, Idle and Alternate Clock modes
CMOS Technology:
• Low power, high speed Flash technology
• Wide operating voltage range (2.5V to 5.5V)
• Industrial and Extended temperature ranges
• Low power consumption
dsPIC30F Motor Control and Power Conversion Family
Device Pins
Program
Mem. Bytes/
Instructions
SRAM
Bytes
EEPROM
Bytes
Timer
16-bit
Input
Cap
Output
Comp/Std
PWM
Motor
Control
PWM
A/D 10-bit
500 Ksps
Quad
Enc
UART
SPITM
I2CTM
CAN
dsPIC30F2010 28 12K/4K 512 1024 3 4 2 6 ch 6 ch Yes 1 1 1 -
dsPIC30F3010 28 24K/8K 1024 1024 5 4 2 6 ch 6 ch Yes 1 1 1 -
dsPIC30F4012 28 48K/16K 2048 1024 5 4 2 6 ch 6 ch Yes 1 1 1 1
dsPIC30F3011 40/44 24K/8K 1024 1024 5 4 4 6 ch 9 ch Yes 2 1 1 -
dsPIC30F4011 40/44 48K/16K 2048 1024 5 4 4 6 ch 9 ch Yes 2 1 1 1
dsPIC30F5015 64 66K/22K 2048 1024 5 4 4 8 ch 16 ch Yes 1 2 1 1
dsPIC30F6010 80 144K/48K 8192 4096 5 8 8 8 ch 16 ch Yes 2 2 1 2
2004 Microchip Technology Inc. Preliminary DS70082G-page 3
dsPIC30F
Pin Diagrams
28-Pin QFN
Note: Pinout subject to change. See specific device data sheet for the most current design information.
dsPIC30F2010
2
3
6
1
18
19
20
21
15
7
16
17
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
5
4
AVDD
AVSS
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
VDD
VSS
PGC/EMUC/U1RX/SDI1/SDA/RF2
PGD/EMUD/U1TX/SDO1/SCL/RF3
FLTA/INT0/SCK1/OCFA/RE8
EMUC2/OC0/IC1/INT0/RD0
MCLR
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF- /CN3/RB1
AN2/SS1/CN4/RB2
AN3/INDX/CN5 RB3
AN4/QEA/IC7/CN6/RB4
AN5/QEB/IC8/CN7/RB5
VSS
OSC1/CLKIN
OSC2/CLKO/RC15
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
VDD
EMUD2/OC1/IC1/INT1/RD0
10
11
12
13
14
8
9
22
23
24
25
26
27
28
dsPIC30F
DS70082G-page 4 Preliminary 2004 Microchip Technology Inc.
Pin Diagrams
MCLR
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
VSS
VDD
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AVDD
AVSS
AN2/SS1/CN4/RB2
EMUD2/OC2/IC2/INT2/RD1 EMUC2/OC1/IC1/INT1/RD0
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1//RC13
VSS
OSC2/CLKO/RC15
OSC1/CLKI VDD
FLTA/INT0/SCK1/OCFA/RE8
PGC/EMUC/U1RX/SDI1/SDA/RF2
PGD/EMUD/U1TX/SDO1/SCL/RF3
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
AN3/INDX/CN5/RB3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-Pin SDIP and SOIC
dsPIC30F2010
dsPIC30F3010
MCLR
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5VSS
VDD
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AVDD
AVSS
AN2/SS1/CN4/RB2
EMUD2/OC2/IC2/INT2/RD1 EMUC2/OC1/IC1/INT1/RD0
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1//RC13
VSS
OSC2/CLKO/RC15
OSC1/CLKI VDD
FLTA/INT0/SCK1/OCFA/RE8
PGC/EMUC/U1RX/SDI1/SDA/C1RX/RF2
PGD/EMUD/U1TX/SDO1/SCL/C1TX/RF3
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
AN3/INDX/CN5/RB3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-Pin SDIP and SOIC
dsPIC30F4012
Note: Pinout subject to change. See specific device data sheet for the most current design information.
Note: Pinout subject to change. See specific device data sheet for the most current design information.
2004 Microchip Technology Inc. Preliminary DS70082G-page 5
dsPIC30F
Pin Diagrams (Continued)
AN7/RB7
AN6/OCFA/RB6
C1RX/RF0
C1TX/RF1
OC3/RD2
EMUC2/OC1/IC1/INT1/RD0
AN8/RB8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
MCLR
VDD
VSS
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
EMUD2/OC2/IC2/INT2/RD1
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
OSC2/CLKO/RC15
OSC1/CLKI
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
AN3/INDX/CN5/RB3
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3H/RE5
AVDD
AVSS
OC4/RD3
VSS
VDD
SCK1/RF6
PGC/EMUC/U1RX/SDI1/SDA/RF2
PGD/EMUD/U1TX/SDO1/SCK/RF3
PWM3L/RE4
VSS VDD
U2RX/RF4
U2TX/RF5
FLTA/INT0/RE8
40-Pin PDIP
dsPIC30F4011
AN7/RB7
AN6/OCFA/RB6
RF0
RF1
OC3/RD2
EMUC2/OC1/IC1/INT1/RD0
AN8/RB8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
MCLR
VDD
VSS
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
EMUD2/OC2/IC2/INT2/RD1
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
OSC2/CLKO/RC15
OSC1/CLKI
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
AN3/INDX/CN5/RB3
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3H/RE5
AVDD
AVSS
OC4/RD3
VSS
VDD
SCK1/RF6
PGC/EMUC/U1RX/SDI1/SDA/RF2
PGD/EMUD/U1TX/SDO1/SCK/RF3
PWM3L/RE4
VSS VDD
U2RX/RF4
U2TX/RF5
FLTA/INT0/RE8
40-Pin PDIP
dsPIC30F3011
Note: Pinout subject to change. See specific device data sheet for the most current design information.
Note: Pinout subject to change. See specific device data sheet for the most current design information.
dsPIC30F
DS70082G-page 6 Preliminary 2004 Microchip Technology Inc.
Pin Diagrams (Continued)
44-Pin TQFP
Note: Pinout subject to change. See specific device data sheet for the most current design information.
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
PGD/EMUD/U1TX/SDO1/SCL/RF3
SCK1/RF6
IC1/INT1/RD8
OC3/RD2
VDD
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
V
SS
OC4/RD3
EMUD/OC2/IC2/INT2/RD1
FLTA/INT0/RE8
NC
AN4/QEA/IC7/CN6/RB4
AN5/QEB/IC8/CN7/RB5
AN6/OCFA/RB6
AN7/RB7
AN8/RB8
NC
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RC15
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
EMUC3/AN1/VREF-/CN3/RB1
EMUD3/AN0/VREF+/CN2/RB0
MCLR
NC
AVDD
AVSS
PWM1L/RE0
PWM1H/RE1
NC
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
VDD
VSS
RF0
RF1
U2RX/CN17/RF4
U2TX/CN18/RF5
PGC/EMUC/U1RX/SDI1/SDA/RF2
dsPIC30F3011
2004 Microchip Technology Inc. Preliminary DS70082G-page 7
dsPIC30F
Pin Diagrams (Continued)
44-Pin QFN
Note: Pinout subject to change. See specific device data sheet for the most current design information.
44
43
42
41
40
39
38
37
36
35
12
13
14
15
16
17
19
20
21
3
30
29
28
27
26
25
24
23
4
5
7
8
9
10
11
1
2 32
31
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
VDD
VDD
RF0
RF1
U2RX/CN17/RF4
U2TX/CN18/RF5
PGC/EMUC/U1RX/SDI1/SDA/RF2
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
EMUC3/AN1/VREF-/CN3/RB1
EMUD3/AN0/VREF+/CN2/RB0
MCLR
AVDD
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
AN4/QEA/IC7/CN6/RB4
AN5/QEB/IC8/CN7/RB5
AN6/OCFA/RB6
AN7/RB7
AN8/RB8
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RC15
PGD/EMUD/U1TX/SDO1/SCL/RF3
SCK1/RF6
EMUC2/OC1/IC1/INT1/RD0
OC3/RD2
VDD
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
OC4/RD3
EMUD2/OC2/IC2/INT2/RD1
FLTA/INT0/RE8
6
22
33
34
VSS
AVSS
VDD
VSS
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
VSS
NC
dsPIC30F3011
18
dsPIC30F
DS70082G-page 8 Preliminary 2004 Microchip Technology Inc.
Pin Diagrams (Continued)
44-Pin TQFP
Note: Pinout subject to change. See specific device data sheet for the most current design information.
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
PGD/EMUD/U1TX/SDO1/SCL/RF3
SCK1/RF6
EMUC2/OC1/IC1/INT1/RD0
OC3/RD2
VDD
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
NC
VSS
OC4/RD3
EMUD2/OC2/IC2/INT2/RD1
FLTA/INT0/RE8
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
EMUC3/AN1/VREF-/CN3/RB1
EMUD3/AN0/VREF+/CN2/RB0
MCLR
NC
AVDD
AVSS
PWM1L/RE0
PWM1H/RE1
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
VDD
VSS
CRX1/RF0
CTX1/RF1
U2RX/CN17/RF4
U2TX/CN18/RF5
PGC/EMUC/U1RX/SDI1/SDA/RF2
AN4/QEA/IC7/CN6/RB4
AN5/QEB/IC8/CN7/RB5
AN6/OCFA/RB6
AN7/RB7
AN8/RB8
NC
VDD
VSS
OSC1/CLKIN
OSC2/CLKO/RC15
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
dsPIC30F4011
PWM2L/RE2
NC
2004 Microchip Technology Inc. Preliminary DS70082G-page 9
dsPIC30F
Pin Diagrams (Continued)
44-Pin QFN
Note: Pinout subject to change. See specific device data sheet for the most current design information.
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
VDD
VDD
CRX1/RF0
CTX1/RF1
U2RX/CN17/RF4
U2TX/CN18/RF5
PGC/EMUC/U1RX/SDI1/SDA/RF2
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
EMUC3/AN1/VREF-/CN3/RB1
EMUD3/AN0/VREF+/CN2/RB0
MCLR
AVDD
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
AN4/QEA/IC7/CN6/RB4
AN5/QEB/IC8/CN7/RB5
AN6/OCFA/RB6
AN7/RB7
AN8/RB8
VDD
VSS
OSC1/CLKIN
OSC2/CLKO/RC15
PGD/EMUD/U1TX/SDO1/SCL/RF3
SCK1/RF6
EMUC2/OC1/IC1/INT1/RD0
OC3/RD2
VDD
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
OC4/RD3
EMUD2/OC2/IC2/INT2/RD1
FLTA/INT0/RE8
VSS
AVSS
VDD
VSS
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
VSS
NC
44
43
42
41
40
39
38
37
36
35
12
13
14
15
16
17
19
20
21
3
30
29
28
27
26
25
24
23
4
5
7
8
9
10
11
1
2 32
31
6
22
33
34
dsPIC30F4011
18
dsPIC30F
DS70082G-page 10 Preliminary 2004 Microchip Technology Inc.
Pin Diagrams (Continued)
64-Pin TQFP
Note: Pinout subject to change. See specific device data sheet for the most current design information.
1
2
3
4
5
6
7
8
9
10
11
12
13 36
35
34
33
32
31
30
29
28
27
26
64
63
62
61
60
59
58
57
56
14
15
16
17
18
19
20
21
22
23
24
25
EMUC1/SOSCO/T1CK/CN0/RC14
EMUD1/SOSCI/T4CK/CN1/RC13
EMUC2/OC1/RD0
INT4/RD11
IC2/FLTB/INT2/RD9
IC1/FLTA/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN
VDD
SCL/RG2
EMUC3/SCK1/INT0/RF6
U1RX/SDI1/RF2
EMUD3/U1TX/SDO1/RF3
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
VSS
VDD
AN3/INDX/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
AN1/VREF-/CN3/RB1
AN0/VREF+/CN2/RB0
CN16/UPDN/RD7
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
VSS
PWM1L/RE0
CTX1/RF1
PWM1H/RE1
EMUD2/OC2/RD1
OC3/RD2
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
AVDD
AVSS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VSS
VDD
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
CN18/RF5
CN17/RF4
SDA/RG3
43
42
41
40
39
38
37
44
48
47
46
50
49
51
54
53
52
55
45
SS2/CN11/RG9
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
INT3/RD10
VDD
CRX1/RF0
OC4/RD3
CN15/RD6
CN14/RD5
CN13/RD4
dsPIC30F5015
2004 Microchip Technology Inc. Preliminary DS70082G-page 11
dsPIC30F
Pin Diagrams (Continued)
72
74
73
71
70
69
68
67
66
65
64
63
62
61
20
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
50
49
48
47
46
45
44
21
41
40
39
38
37
36
35
34
23
24
25
26
27
28
29
30
31
32
33
dsPIC30F6010
17
18
19
75
1
57
56
55
54
53
52
51
60
59
58
43
42
76
78
77
79
22
80
IC5/RD12
OC4/RD3
OC3/RD2
EMUD2/OC2/RD1
PWM2L/RE2
PWM1H/RE1
PWM1L/RE0
C2RX/RG0
C2TX/RG1
C1TX/RF1
C1RX/RF0
PWM3L/RE4
PWM2H/RE3
OC8/CN16/UPDN/RD7
OC6/CN14/RD5
EMUC2/OC1/RD0
IC4/RD11
IC2/RD9
IC1/RD8
INT4/RA15
IC3/RD10
INT3/RA14
VSS
OSC1/CLKI
VDD
SCL/RG2
U1RX/RF2
U1TX/RF3
EMUC1/SOSCO/T1CK/CN0/RC14
EMUD1/SOSCI/CN1/RC13
VREF+/RA10
VREF-/RA9
AVDD
AVSS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VDD
U2RX/CN17/RF4
IC8/CN21/RD15
U2TX/CN18/RF5
AN6/OCFA/RB6
AN7/RB7
PWM4H/RE7
T2CK/RC1
T4CK/RC3
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC/EMUC/AN1/CN3/RB1
PGD/EMUD/AN0/CN2/RB0
VSS
VDD
PWM3H/RE5
PWM4L/RE6
FLTB/INT2/RE9
FLTA/INT1/RE8
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
VDD
VSS
OC5/CN13/RD4
IC6/CN19/RD13
SDA/RG3
SDI1/RF7
EMUD3/SDO1/RF8
AN5/QEB/CN7/RB5
VSS
OSC2/CLKO/RC15
OC7/CN15/RD6
EMUC3/SCK1/INT0/RF6
IC7/CN20/RD14
80-Pin TQFP
Note: Pinout subject to change. See specific device data sheet for the most current design information.
dsPIC30F
DS70082G-page 12 Preliminary 2004 Microchip Technology Inc.
Table of Contents
1.0 Device Overview .................................................................................................................................................................... 13
2.0 CPU Architecture Overview.................................................................................................................................................... 19
3.0 Memory Organization ............................................................................................................................................................. 31
4.0 Address Generator Units........................................................................................................................................................ 43
5.0 Interrupts ................................................................................................................................................................................ 51
6.0 Flash Program Memory.......................................................................................................................................................... 57
7.0 Data EEPROM Memory ......................................................................................................................................................... 63
8.0 I/O Ports ................................................................................................................................................................................. 67
9.0 Timer1 Module ....................................................................................................................................................................... 73
10.0 Timer2/3 Module .................................................................................................................................................................... 77
11.0 Timer4/5 Module ................................................................................................................................................................... 83
12.0 Input Capture Module............................................................................................................................................................. 87
13.0 Output Compare Module ........................................................................................................................................................ 91
14.0 Quadrature Encoder Interface (QEI) Module ......................................................................................................................... 95
15.0 Motor Control PWM Module ................................................................................................................................................. 101
16.0 SPI™ Module ....................................................................................................................................................................... 111
17.0 I2C Module ........................................................................................................................................................................... 115
18.0 Universal Asynchronous Receiver Transmitter (UART) Module .......................................................................................... 123
19.0 CAN Module ......................................................................................................................................................................... 131
20.0 10-bit High Speed Analog-to-Digital Converter (A/D) Module .............................................................................................. 143
21.0 System Integration ............................................................................................................................................................... 151
22.0 Instruction Set Summary ...................................................................................................................................................... 165
23.0 Development Support........................................................................................................................................................... 173
24.0 Electrical Characteristics ...................................................................................................................................................... 179
25.0 Packaging Information.......................................................................................................................................................... 221
On-Line Support................................................................................................................................................................................. 239
Systems Information and Upgrade Hot Line ...................................................................................................................................... 239
Reader Response .............................................................................................................................................................................. 240
Product Identification System............................................................................................................................................................. 241
TO OUR VALUED CUSTOMERS
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2004 Microchip Technology Inc. Preliminary DS70082G-page 13
dsPIC30F
1.0 DEVICE OVERVIEW
This document contains device family specific informa-
tion for the dsPIC30F family of Digital Signal Controller
(DSC) devices. The dsPIC30F devices contain exten-
sive Digital Signal Processor (DSP) functionality within a
high performance 16-bit microcontroller (MCU)
architecture.
Figure 1-1 shows a sample device block diagram.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the dsPIC30F Family Reference
Manual (DS70046). For more information on the device
instruction set and programming, refer to the dsPIC30F
Programmer’s Reference Manual (DS70030).
Note: The device(s) depicted in this block dia-
gram are representative of the correspond-
ing device family. Other devices of the
same family may vary in terms of number
of pins and multiplexing of pin functions.
Typically, smaller devices in the family con-
tain a subset of the peripherals present in
the device(s) shown in this diagram.
dsPIC30F
DS70082G-page 14 Preliminary 2004 Microchip Technology Inc.
FIGURE 1-1: dsPIC30F6010 BLOCK DIAGRAM
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
Power-up
Timer
Oscillator
Start-up Timer
POR/BOR
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKI
MCLR
VDD, VSS
AN4/QEA/CN6/RB4
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
Low Voltage
Detect
UART1,
SPI1, Motor Control
PWM
INT4/RA15
INT3/RA14
VREF+/RA10
VREF-/RA9
CAN2
Timing
Generation
CAN1,
AN5/QEB/CN7/RB5
16
PCH PCL
16
Program Counter
ALU<16>
16
Address Latch
Program Memory
(144 Kbytes)
Data Latch
24
24
24
24
X Data Bus
IR
I2C
QEI
AN6/OCFA/RB6
AN7/RB7
PCU
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
10-bit ADC
Timers
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
FLTA/INT1/RE8
FLTB/INT2/RE9
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
SS2/CN11/RG9
U2TX/CN18/RF5
EMUC3/SCK1/INT0/RF6
SDI1/RF7
EMUD3/SDO1/RF8
Input
Capture
Module
Output
Compare
Module
EMUC1/SOSCO/T1CK/CN0/RC14
EMUD1/SOSCI/CN1/RC13
T4CK/RC3
T2CK/RC1
PORTB
C1RX/RF0
C1TX/RF1
U1RX/RF2
U1TX/RF3
C2RX/RG0
C2TX/RG1
SCL/RG2
SDA/RG3
PORTG PORTF
PORTD
16
16 16
16 x 16
W Reg Array
Divide
Unit
Engine
DSP
Decode
ROM Latch
16
Y Data Bus
Effective Address
X RAGU
X WAGU
Y AGU
PGD/EMUD/AN0/CN2/RB0
PGC/EMUC/AN1/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/INDX/CN5/RB3
OSC2/CLKO/RC15
U2RX/CN17/RF4
AVDD, AVSS
UART2
SPI2
16
16
16
16
16
PORTA
PORTC
PORTE
16
16
16
16
8
Interrupt
Controller
PSV & Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data LatchData Latch
Y Data
(4 Kbytes)
RAM
X Data
(4 Kbytes)
RAM
Address
Latch
Address
Latch
Control Signals
to Various Blocks
EMUC2/OC1/RD0
EMUD2/OC2/RD1
OC3/RD2
OC4/RD3
OC5/CN13/RD4
OC6/CN14/RD5
OC7/CN15/RD6
OC8/CN16/UPDN/RD7
IC1/RD8
IC2/RD9
IC3/RD10
IC4/RD11
IC5/RD12
IC6/CN19/RD13
IC7/CN20/RD14
IC8/CN21/RD15
16
Data EEPROM
(4 Kbytes)
2004 Microchip Technology Inc. Preliminary DS70082G-page 15
dsPIC30F
Table 1-1 provides a brief description of device I/O
pinouts and the functions that may be multiplexed to a
port pin. Multiple functions may exist on one port pin.
When multiplexing occurs, the peripheral module’s
functional requirements may force an override of the
data direction of the port pin.
TABLE 1-1: PINOUT I/O DESCRIPTIONS
Pin Name Pin
Type
Buffer
Type Description
AN0-AN15 I Analog Analog input channels.
AN0 and AN1 are also used for device programming data and clock inputs,
respectively.
AVDD P P Positive supply for analog module.
AVSS P P Ground reference for analog module.
CLKI
CLKO
I
O
ST/CMOS
—
External clock source input. Always associated with OSC1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always
associated with OSC2 pin function.
CN0-CN23 I ST Input change notification inputs.
Can be software programmed for internal weak pull-ups on all inputs.
COFS
CSCK
CSDI
CSDO
I/O
I/O
I
O
ST
ST
ST
—
Data Converter Interface frame synchronization pin.
Data Converter Interface serial clock input/output pin.
Data Converter Interface serial data input pin.
Data Converter Interface serial data output pin.
C1RX
C1TX
C2RX
C2TX
I
O
I
O
ST
—
ST
—
CAN1 bus receive pin.
CAN1 bus transmit pin.
CAN2 bus receive pin.
CAN2 bus transmit pin.
EMUD
EMUC
EMUD1
EMUC1
EMUD2
EMUC2
EMUD3
EMUC3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ICD Primary Communication Channel data input/output pin.
ICD Primary Communication Channel clock input/output pin.
ICD Secondary Communication Channel data input/output pin.
ICD Secondary Communication Channel clock input/output pin.
ICD Tertiary Communication Channel data input/output pin.
ICD Tertiary Communication Channel clock input/output pin.
ICD Quaternary Communication Channel data input/output pin.
ICD Quaternary Communication Channel clock input/output pin.
IC1-IC8 I ST Capture inputs 1 through 8.
INDX
QEA
QEB
UPDN
I
I
I
O
ST
ST
ST
CMOS
Quadrature Encoder Index Pulse input.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Position Up/Down Counter Direction State.
INT0
INT1
INT2
INT3
INT4
I
I
I
I
I
ST
ST
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
External interrupt 3.
External interrupt 4.
LVDIN I Analog Low Voltage Detect Reference Voltage input pin.
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Trigger input with CMOS levels O = Output
I = Input P = Power
dsPIC30F
DS70082G-page 16 Preliminary 2004 Microchip Technology Inc.
FLTA
FLTB
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM4L
PWM4H
I
I
O
O
O
O
O
O
O
O
ST
ST
—
—
—
—
—
—
—
—
PWM Fault A input.
PWM Fault B input.
PWM 1 Low output.
PWM 1 High output.
PWM 2 Low output.
PWM 2 High output.
PWM 3 Low output.
PWM 3 High output.
PWM 4 Low output.
PWM 4 High output.
MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an active
low Reset to the device.
OCFA
OCFB
OC1-OC8
I
I
O
ST
ST
—
Compare Fault A input (for Compare channels 1, 2, 3 and 4).
Compare Fault B input (for Compare channels 5, 6, 7 and 8).
Compare outputs 1 through 8.
OSC1
OSC2
I
I/O
ST/CMOS
—
Oscillator crystal input. ST buffer when configured in RC mode; CMOS other-
wise.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
PGD
PGC
I/O
I
ST
ST
In-Circuit Serial Programming data input/output pin.
In-Circuit Serial Programming clock input pin.
RA9-RA10
RA14-RA15
I/O
I/O
ST
ST
PORTA is a bi-directional I/O port.
RB0-RB15 I/O ST PORTB is a bi-directional I/O port.
RC1
RC3
RC13-RC15
I/O
I/O
I/O
ST
ST
ST
PORTC is a bi-directional I/O port.
RD0-RD15 I/O ST PORTD is a bi-directional I/O port.
RE0-RE9 I/O ST PORTE is a bi-directional I/O port.
RF0-RF8 I/O ST PORTF is a bi-directional I/O port.
RG0-RG3
RG6-RG9
I/O
I/O
ST
ST
PORTG is a bi-directional I/O port.
SCK1
SDI1
SDO1
SS1
SCK2
SDI2
SDO2
SS2
I/O
I
O
I
I/O
I
O
I
ST
ST
—
ST
ST
ST
—
ST
Synchronous serial clock input/output for SPI1.
SPI1 Data In.
SPI1 Data Out.
SPI1 Slave Synchronization.
Synchronous serial clock input/output for SPI2.
SPI2 Data In.
SPI2 Data Out.
SPI2 Slave Synchronization.
SCL
SDA
I/O
I/O
ST
ST
Synchronous serial clock input/output for I2C.
Synchronous serial data input/output for I2C.
SOSCO
SOSCI
O
I
—
ST/CMOS
32 kHz low power oscillator crystal output.
32 kHz low power oscillator crystal input. ST buffer when configured in RC
mode; CMOS otherwise.
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin
Type
Buffer
Type Description
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Trigger input with CMOS levels O = Output
I = Input P = Power
2004 Microchip Technology Inc. Preliminary DS70082G-page 17
dsPIC30F
T1CK
T2CK
T3CK
T4CK
T5CK
I
I
I
I
I
ST
ST
ST
ST
ST
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
U1RX
U1TX
U1ARX
U1ATX
U2RX
U2TX
I
O
I
O
I
O
ST
—
ST
—
ST
—
UART1 Receive.
UART1 Transmit.
UART1 Alternate Receive.
UART1 Alternate Transmit.
UART2 Receive.
UART2 Transmit.
VDD P — Positive supply for logic and I/O pins.
VSS P — Ground reference for logic and I/O pins.
VREF+ I Analog Analog Voltage Reference (High) input.
VREF- I Analog Analog Voltage Reference (Low) input.
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin
Type
Buffer
Type Description
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Trigger input with CMOS levels O = Output
I = Input P = Power
dsPIC30F
DS70082G-page 18 Preliminary 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Preliminary DS70082G-page 19
dsPIC30F
2.0 CPU ARCHITECTURE OVERVIEW
2.1 Core Overview
The core has a 24-bit instruction word. The Program
Counter (PC) is 23 bits wide with the Least Significant
(LS) bit always clear (see Section 3.1), and the Most
Significant (MS) bit is ignored during normal program
execution, except for certain specialized instructions.
Thus, the PC can address up to 4M instruction words
of user program space. An instruction pre-fetch mech-
anism is used to help maintain throughput. Program
loop constructs, free from loop count management
overhead, are supported using the DO and REPEAT
instructions, both of which are interruptible at any point.
The working register array consists of 16x16-bit regis-
ters, each of which can act as data, address or offset
registers. One working register (W15) operates as a
software stack pointer for interrupts and calls.
The data space is 64 Kbytes (32K words) and is split
into two blocks, referred to as X and Y data memory.
Each block has its own independent Address Genera-
tion Unit (AGU). Most instructions operate solely
through the X memory AGU, which provides the
appearance of a single unified data space. The
Multiply-Accumulate (MAC) class of dual source DSP
instructions operate through both the X and Y AGUs,
splitting the data address space into two parts (see
Section 3.2). The X and Y data space boundary is
device specific and cannot be altered by the user. Each
data word consists of 2 bytes, and most instructions
can address data either as words or bytes.
There are two methods of accessing data stored in
program memory:
• The upper 32 Kbytes of data space memory can
be mapped into the lower half (user space) of pro-
gram space at any 16K program word boundary,
defined by the 8-bit Program Space Visibility Page
(PSVPAG) register. This lets any instruction
access program space as if it were data space,
with a limitation that the access requires an addi-
tional cycle. Moreover, only the lower 16 bits of
each instruction word can be accessed using this
method.
• Linear indirect access of 32K word pages within
program space is also possible using any working
register, via table read and write instructions.
Table read and write instructions can be used to
access all 24 bits of an instruction word.
Overhead-free circular buffers (modulo addressing) are
supported in both X and Y address spaces. This is pri-
marily intended to remove the loop overhead for DSP
algorithms.
The X AGU also supports bit-reversed addressing on
destination effective addresses, to greatly simplify input
or output data reordering for radix-2 FFT algorithms.
Refer to Section 4.0 for details on modulo and
bit-reversed addressing.
The core supports Inherent (no operand), Relative, Lit-
eral, Memory Direct, Register Direct, Register Indirect,
Register Offset and Literal Offset Addressing modes.
Instructions are associated with predefined Addressing
modes, depending upon their functional requirements.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working reg-
ister (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, 3-operand instructions are supported, allowing
C = A+B operations to be executed in a single cycle.
A DSP engine has been included to significantly
enhance the core arithmetic capability and throughput.
It features a high speed 17-bit by 17-bit multiplier, a
40-bit ALU, two 40-bit saturating accumulators and a
40-bit bi-directional barrel shifter. Data in the accumu-
lator or any working register can be shifted up to 15 bits
right or 16 bits left in a single cycle. The DSP instruc-
tions operate seamlessly with all other instructions and
have been designed for optimal real-time performance.
The MAC class of instructions can concurrently fetch
two data operands from memory, while multiplying two
W registers. To enable this concurrent fetching of data
operands, the data space has been split for these
instructions and linear for all others. This has been
achieved in a transparent and flexible manner, by ded-
icating certain working registers to each address space
for the MAC class of instructions.
The core does not support a multi-stage instruction
pipeline. However, a single stage instruction pre-fetch
mechanism is used, which accesses and partially
decodes instructions a cycle ahead of execution, in
order to maximize available execution time. Most
instructions execute in a single cycle, with certain
exceptions as outlined in Section 2.3.
The core features a vectored exception processing
structure for traps and interrupts, with 62 independent
vectors. The exceptions consist of up to 8 traps (of
which 4 are reserved) and 54 interrupts. Each interrupt
is prioritized based on a user assigned priority between
1 and 7 (1 being the lowest priority and 7 being the
highest) in conjunction with a predetermined ‘natural
order’. Traps have fixed priorities, ranging from 8 to 15.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the dsPIC30F Family Reference
Manual (DS70046). For more information on the device
instruction set and programming, refer to the dsPIC30F
Programmer’s Reference Manual (DS70030).
dsPIC30F
DS70082G-page 20 Preliminary 2004 Microchip Technology Inc.
2.2 Programmer’s Model
The programmer’s model is shown in Figure 2-1 and
consists of 16x16-bit working registers (W0 through
W15), 2x40-bit accumulators (AccA and AccB),
STATUS register (SR), Data Table Page register
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART,
DOEND, DCOUNT and RCOUNT), and Program
Counter (PC). The working registers can act as data,
address or offset registers. All registers are memory
mapped. W0 acts as the W register for file register
addressing.
Some of these registers have a shadow register asso-
ciated with each of them, as shown in Figure 2-1. The
shadow register is used as a temporary holding register
and can transfer its contents to or from its host register
upon the occurrence of an event. None of the shadow
registers are accessible directly. The following rules
apply for transfer of registers into and out of shadows.
•PUSH.S and POP.S
W0, W1, W2, W3, SR (DC, N, OV, Z and C bits
only) are transferred.
•DO instruction
DOSTART, DOEND, DCOUNT shadows are
pushed on loop start, and popped on loop end.
When a byte operation is performed on a working reg-
ister, only the Least Significant Byte of the target regis-
ter is affected. However, a benefit of memory mapped
working registers is that both the Least and Most Sig-
nificant Bytes can be manipulated through byte wide
data memory space accesses.
2.2.1 SOFTWARE STACK POINTER/
FRAME POINTER
The dsPIC® devices contain a software stack. W15 is
the dedicated software stack pointer (SP), and will be
automatically modified by exception processing and
subroutine calls and returns. However, W15 can be ref-
erenced by any instruction in the same manner as all
other W registers. This simplifies the reading, writing
and manipulation of the stack pointer (e.g., creating
stack frames).
W15 is initialized to 0x0800 during a Reset. The user
may reprogram the SP during initialization to any
location within data space.
W14 has been dedicated as a stack frame pointer as
defined by the LNK and ULNK instructions. However,
W14 can be referenced by any instruction in the same
manner as all other W registers.
2.2.2 STATUS REGISTER
The dsPIC core has a 16-bit status register (SR), the
LS Byte of which is referred to as the SR Low Byte
(SRL) and the MS Byte as the SR High Byte (SRH).
See Figure 2-1 for SR layout.
SRL contains all the MCU ALU operation status flags
(including the Z bit), as well as the CPU Interrupt Prior-
ity Level status bits, IPL<2:0>, and the REPEAT active
status bit, RA. During exception processing, SRL is
concatenated with the MS Byte of the PC to form a
complete word value which is then stacked.
The upper byte of the STATUS register contains the
DSP Adder/Subtractor status bits, the DO Loop Active
bit (DA) and the Digit Carry (DC) status bit.
Most SR bits are read/write. Exceptions are:
1. The DA bit: DA is read and clear only, because
accidentally setting it could cause erroneous
operation.
2. The RA bit: RA is a read only bit, because acci-
dentally setting it could cause erroneous opera-
tion. RA is only set on entry into a repeat loop,
and cannot be directly cleared by software.
3. The OV, OA, OB and OAB bits: These bits are
read only and can only be set by the DSP engine
overflow logic.
4. The SA, SB and SAB bits: These are read and
clear only and can only be set by the DSP
engine saturation logic. Once set, these flags
remain set until cleared by the user, irrespective
of the results from any subsequent DSP
operations.
2.2.2.1 Z Status Bit
Instructions that use a carry/borrow input (ADDC,
CPB, SUBB and SUBBR) will only be able to clear Z
(for a non-zero result) and can never set it. A multi-
precision sequence of instructions, starting with an
instruction with no carry/borrow input, will thus auto-
matically logically AND the successive results of the
zero test. All results must be zero for the Z flag to
remain set by the end of the sequence.
All other instructions can set as well as clear the Z bit.
2.2.3 PROGRAM COUNTER
The Program Counter is 23 bits wide. Bit 0 is always
clear. Therefore, the PC can address up to 4M
instruction words.
Note: In order to protect against misaligned
stack accesses, W15<0> is always clear.
Note 1: Clearing the SAB bit will also clear both
the SA and SB bits.
2: When the memory mapped status regis-
ter (SR) is the destination address for an
operation which affects any of the SR bits,
data writes are disabled to all bits.
2004 Microchip Technology Inc. Preliminary DS70082G-page 21
dsPIC30F
FIGURE 2-1: PROGRAMMER’S MODEL
TABPAG
PC22 PC0
7 0
D0D15
Program Counter
Data Table Page Address
Status Register
Working Registers
DSP Operand
Registers
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
DSP Address
Registers
AD39 AD0AD31
DSP
Accumulators
AccA
AccB
PSVPAG
7 0
Program Space Visibility Page Address
Z
0
OA OB SA SB
RCOUNT
15 0
REPEAT Loop Counter
DCOUNT
15 0
DO Loop Counter
DOSTART
22 0
DO Loop Start Address
IPL2 IPL1
SPLIM Stack Pointer Limit Register
AD15
SRL
PUSH.S Shadow
DO Shadow
OAB SAB
15 0
Core Configuration Register
Legend
CORCON
DA DC RA N
TBLPAG
PSVPAG
IPL0 OV
W0/WREG
SRH
DO Loop End Address
DOEND
22
C
dsPIC30F
DS70082G-page 22 Preliminary 2004 Microchip Technology Inc.
2.3 Instruction Flow
There are 8 types of instruction flows:
1. Normal one-word, one-cycle instructions: these
instructions take one effective cycle to execute,
as shown in Figure 2-2.
FIGURE 2-2: INSTRUCTION PIPELINE FLOW: 1-WORD, 1-CYCLE
2. One-word, two-cycle (or three-cycle) instruc-
tions that are flow control instructions: these
instructions include the relative branches, rela-
tive call, skips and returns. When an instruction
changes the PC (other than to increment it), the
pipeline fetch is discarded. This causes the
instruction to take two effective cycles to exe-
cute as shown in Figure 2-3. Some instructions
that change program flow require 3 cycles, such
as the RETURN, RETFIE and RETLW instruc-
tions, and instructions that skip over 2-word
instructions.
FIGURE 2-3: INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOV.b #0x55,W0 Fetch 1 Execute 1
2. MOV.b #0x35,W1 Fetch 2 Execute 2
3. ADD.b W0,W1,W2 Fetch 3 Execute 3
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOV #0x55,W0 Fetch 1 Execute 1
2. BTSC W1,#3 Fetch 2 Execute 2
Skip Taken
3. ADD W0,W1,W2 Fetch 3 Flush
4. BRA SUB_1 Fetch 4 Execute 4
5. SUB W0,W1,W3 Fetch 5 Flush
6. Instruction @ address SUB_1 Fetch SUB_1
2004 Microchip Technology Inc. Preliminary DS70082G-page 23
dsPIC30F
3. One-word, two-cycle instructions that are not
flow control instructions: the only instructions of
this type are the MOV.D (load and store double
word) instructions, as shown in Figure 2-4.
FIGURE 2-4: INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE MOV.D OPERATIONS
4. Table read/write instructions. These instructions
will suspend the fetching to insert a read or write
cycle to the program memory. The instruction
fetched, while executing the table operation, is
saved for 1 cycle and executed in the cycle
immediately after the table operation, as shown
in Figure 2-5.
FIGURE 2-5: INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE TABLE OPERATIONS
5. Two-word instructions for CALL and GOTO. In
these instructions, the fetch after the instruction
provides the remainder of the jump or call desti-
nation address. These instructions require 2
cycles to execute, 1 cycle to fetch the 2 instruc-
tion words (enabled by a high speed path on the
second fetch), and 1 cycle to flush the pipeline,
as shown in Figure 2-6.
FIGURE 2-6: INSTRUCTION PIPELINE FLOW: 2-WORD, 2-CYCLE GOTO, CALL
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOV W0,0x1234 Fetch 1 Execute 1
2. MOV.D [W0++],W1 Fetch 2 Execute 2
R/W Cycle 1
3. MOV W1,0x00AA Fetch 3 Execute 2
R/W Cycle2
3a.Stall Stall Execute 3
4. MOV 0x0CC, W0 Fetch 4 Execute 4
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOV #0x1234,W0 Fetch 1 Execute 1
2. TBLRDL [W0++],W1 Fetch 2 Execute 2
3. MOV #0x00AA,W1 Fetch 3 Execute 2
Read Cycle
3a.Table Operation Bus Read Execute 3
4. MOV #0x0CC,W0 Fetch 4 Execute 4
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOV #0x1234,W0 Fetch 1 Execute 1
2. GOTO LABEL Fetch 2L Update PC
2a.Second Word Fetch 2H NOP
3. Instruction @ address LABEL Fetch
LABEL
Execute
LABEL
4. BSET W1, #BIT3 Fetch 4 Execute 4
dsPIC30F
DS70082G-page 24 Preliminary 2004 Microchip Technology Inc.
6. Two-word instructions for DO. In these instruc-
tions, the fetch after the instruction contains an
address offset. This address offset is added to
the first instruction address to generate the last
loop instruction address. Therefore, these
instructions require 2 cycles, as shown in
Figure 2-7.
FIGURE 2-7: INSTRUCTION PIPELINE FLOW: 2-WORD, 2-CYCLE DO, DOW
7. Instructions that are subjected to a stall due to a
data dependency between the X RAGU and X
WAGU. An additional cycle is inserted to resolve
the resource conflict, as shown in Figure 2-8.
Instruction stalls caused by data dependencies
are further discussed in Section 4.0.
FIGURE 2-8: INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE WITH INSTRUCTION STALL
8. Interrupt recognition execution. Refer to
Section 5.0 for details on interrupts.
TCY0TCY1TCY2TCY3TCY4
1. PUSH DOEND Fetch 1 Execute 1
2. DO LABEL,#COUNT Fetch 2L NOP
2a.Second Word Fetch 2H Execute 2
3. 1st Instruction of Loop Fetch 3 Execute 3
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOV.b W0,[W1] Fetch 1 Execute 1
2. MOV.b [W1],PORTB Fetch 2 NOP
2a.Stall (NOP) Stall Execute 2
3. MOV.b W0,PORTB Fetch 3 Execute 3
2004 Microchip Technology Inc. Preliminary DS70082G-page 25
dsPIC30F
2.4 Divide Support
The dsPIC devices feature a 16/16-bit signed fractional
divide operation, as well as 32/16-bit and 16/16-bit
signed and unsigned integer divide operations, in the
form of single instruction iterative divides. The following
instructions and data sizes are supported:
1. DIVF – 16/16 signed fractional divide
2. DIV.sd – 32/16 signed divide
3. DIV.ud – 32/16 unsigned divide
4. DIV.sw – 16/16 signed divide
5. DIV.uw – 16/16 unsigned divide
The 16/16 divides are similar to the 32/16 (same number
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
The quotient for all divide instructions is stored in W0,
and the remainder in W1. DIV and DIVF can specify any
W register for both the 16-bit dividend and divisor. All
other divides can specify any W register for the 16-bit
divisor, but the 32-bit dividend must be in an aligned W
register pair, such as W1:W0, W3:W2, etc.
The non-restoring divide algorithm requires one cycle
for an initial dividend shift (for integer divides only), one
cycle per divisor bit, and a remainder/quotient correc-
tion cycle. The correction cycle is the last cycle of the
iteration loop, but must be performed (even if the
remainder is not required) because it may also adjust
the quotient. A consequence of this is that DIVF will
also produce a valid remainder (though it is of little use
in fractional arithmetic).
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g. a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide instruction does not automatically
set up the RCOUNT value, and it must, therefore, be
explicitly and correctly specified in the REPEAT instruc-
tion, as shown in Table 2-1 (REPEAT will execute the
target instruction {operand value+1} times). The
REPEAT loop count must be set up for 18 iterations of
the DIV/DIVF instruction. Thus, a complete divide
operation requires 19 cycles.
TABLE 2-1: DIVIDE INSTRUCTIONS
Note: The Divide flow is interruptible. However,
the user needs to save the context as
appropriate.
Instruction Function
DIVF Signed fractional divide: Wm/Wn → W0; Rem → W1
DIV.sd Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1
DIV.sw (or DIV.s) Signed divide: Wm/Wn → W0; Rem → W1
DIV.ud Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1
DIV.uw (or DIV.u) Unsigned divide: Wm/Wn → W0; Rem → W1
dsPIC30F
DS70082G-page 26 Preliminary 2004 Microchip Technology Inc.
2.5 DSP Engine
Concurrent operation of the DSP engine with MCU
instruction flow is not possible, though both the MCU
ALU and DSP engine resources may be used concur-
rently by the same instruction (e.g., ED and EDAC
instructions).
The DSP engine consists of a high speed 17-bit x
17-bit multiplier, a barrel shifter, and a 40-bit adder/
Subtractor (with two target accumulators, round and
saturation logic).
Data input to the DSP engine is derived from one of the
following:
1. Directly from the W array (registers W4, W5, W6
or W7) via the X and Y data buses for the MAC
class of instructions (MAC, MSC, MPY, MPY.N,
ED, EDAC, CLR and MOVSAC).
2. From the X bus for all other DSP instructions.
3. From the X bus for all MCU instructions which
use the barrel shifter.
Data output from the DSP engine is written to one of the
following:
1. The target accumulator, as defined by the DSP
instruction being executed.
2. The X bus for MAC, MSC, CLR and MOVSAC
accumulator writes, where the EA is derived
from W13 only. (MPY, MPY.N, ED and EDAC do
not offer an accumulator write option.)
3. The X bus for all MCU instructions which use the
barrel shifter.
The DSP engine also has the capability to perform inher-
ent accumulator-to-accumulator operations, which
require no additional data. These instructions are ADD,
SUB and NEG.
The DSP engine has various options selected through
various bits in the CPU Core Configuration Register
(CORCON), as listed below:
1. Fractional or integer DSP multiply (IF).
2. Signed or unsigned DSP multiply (US).
3. Conventional or convergent rounding (RND).
4. Automatic saturation on/off for AccA (SATA).
5. Automatic saturation on/off for AccB (SATB).
6. Automatic saturation on/off for writes to data
memory (SATDW).
7. Accumulator Saturation mode selection
(ACCSAT).
A block diagram of the DSP engine is shown in
Figure 2-9.
Note: For CORCON layout, see Table 4-3.