32207 MS PC 20060719-S00002 No.A0692-1/8
http://onsemi.com
Semiconductor Components Industries, LLC, 2013
August, 2013
LV5609LP
Overview
The LV5609LP is vertical clock driver for CCD.
Functions
• Ternary output ×2ch
• Binary output ×2ch
• SHT output ×1ch
• Output ON resistance : 30Ω typ
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = VM = 0V
Parameter Symbol Conditions Ratings Unit
VDD max 6V
VH max 20 V
VL max -10 V
Maximum supply voltage
VH-VL max 24 V
Allowable power dissipation Pd max with specified substrate * 0.8 W
Operating temperature Topr -20 to +80 °C
Storage temperature Tstg -40 to +125 °C
* : Specified substrate : 40×50×0.8mm3, glass epoxy four-layer (2S2P) board
Allowable Operating Ratings at Ta = 25°C, VSS = VM = 0V
Ratings
Parameter Symbol Conditions min typ max Unit
VDD 2.0 3.3 5.5 V
VH 15 17 V
VL -8.5 -7.5 -4 V
Supply voltage
VH-VL 23.5 V
CMOS input High voltage VINH 0.8VDD V
DD V
CMOS input Low voltage VINL -0.1 0.4 V
Bi-CMOS LSI
Vertical Clock Driver for CCD
Orderin
g
numbe
r
: ENA0692
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
C onditions is not implied. Extended exposure to stresses above the Recommended Operating C onditions may affect device reliability.
LV5609LP
No.A0692-2/8
Electrical Characteristics at Ta = 25°C, VDD = 3.3V, VSS = 0V, VH = 15V, VL = -7.5V, VM = 0V,
Unless otherwise specified
Ratings
Parameter Symbol Conditions min typ max
Unit
IDD V
DD pin 1 μA
IH VH pin 10 μA
Stati c current drain
IL VL pin 1 μA
IDD V
DD pin See *1 and *2. 1 mA
IH VH pin See *1 and *2. 2.4 4.5 mA
Dynamic current drain
IL VL pin See *1 and *2. 3 5 mA
RL IO = +10mA 20 30 Ω
RM IO = ±10mA 30 45 Ω
RH IO = -10mA 30 40 Ω
Output ON resistance
RSHT IO = -10mA 30 40 Ω
TPLM No load 200 ns
TPMH No load 200 ns
TPLH No load 200 ns
TPML No load 200 ns
TPHM No load 200 ns
Propagation delay time
TPHL No load 200 ns
VL → VM V1, V3 See *1. 800 ns TTLM
VL → VM V2, V4 See *1. 800 ns
TTMH VM → VL V1, V3 See *1. 800 ns
Rise time
TTLH VL → VH SHT See *1. 200 ns
VM → VL V1, V3 See *1. 800 ns TTML
VM → VL V2, V4 See *1. 800 ns
TTHM VH → VM V1, V3 See *1. 800 ns
Fall time
TTHL VH → VL SHT See *1. 200 ns
*1 : Refer to the CCD equivalent load shown below.
*2 : Refer to the timing waveform on Page 7.
V1
(Ternary)
V2
(Binary)
V4
(Ternary)
V3
(Binary)
SHT
2000pF 2000pF
1000pF
3000pF 3000pF
1000pF
2000pF 2000pF
1600pF
LV5609LP
No.A0692-3/8
Package Dimensions
unit : mm (typ)
3322
SIDE VIEW
SIDE VIEW
BOTTOM VIEW
TOP VIEW
3.5
0.25
0.83 3.5
0.4
(0.035)
0.5 (0.5)
(0.125)
(C0.116)
(0.13)
16
24
19
1813
12
7
SANYO : VCT24(3.5X3.5)X01
0
0.8
0.36
0.07
0.4
0.2
0.15
0.6
1.0
– 20 806020 40010
0
Ambient temperature, Ta – °C
Allowable power dissipation, Pd max – W
Pd max – Ta
Independent IC
Specified circuit board : 40×50×0.8mm
3
, glass epoxy
four-layer (2S2P) board
With specified substrate
LV5609LP
No.A0692-4/8
Pin Assignment
Pin Function
Pin No. Name Mode
1 VL Lo power for output (-7.5V system)
2 SHT Level shift output (binary VH, VL)
3 V4 Level shift output (binary VM, VL)
4 V3 Level shift output (ternary VH, VM, VL)
5 V2 Level shift output (binary VM, VL)
6 V1 Level shift output (ternary VH, VM, VL)
7 VM GND for output
8 NC
9 VH Hi power supply for output (15V system)
10 NC
11 NC
12 XV1 V1 transfer pulse input
13 XSG1 V1 read pulse input
14 XV2 V2 transfer pulse input
15 XV3 V3 transfer pulse input
16 XSG3 V3 read pulse input
17 XV4 V4 transfer pulse input
18 XSHT SHT pulse input
19 NC
20 VDD Power supply for input buffer (3.3V system)
21 VSS GND for input buffer
22 NC
23 NC
24 NC
1
2
3
4
5
6
7 8 9 10 11 12
18
17
16
15
14
13
24 23 22 21 20 19
VL
SHT
V4
V3
V2
V1
VM
NC
VH
NC
NC
XV1
XSG1
XV2
XV3
XSG3
XV4
XSHT
NC
VDD
VSS
NC
NC
NC
Top view
LV5609LP
No.A0692-5/8
Block Diagram
Logical Function Table
Input Output
XV1
XV3 XSG1
XSG3 XV2
XV4 XSHT V1
V3 V2
V4 SHT
L L X X VH X X
L H X X VM X X
H L X X VL X X
H H X X VL X X
X X L X X VM X
X X H X X VL X
X X X L X X VH
X X X H X X VL
9
6
5
7
4
3
2
1
20
12
13
14
15
16
17
18
21
30
30
30
30
Input Buffer
VDD
XV1
XSG1
XV2
XV3
XSG3
XV4
XSHT
VSS
VH
V1
V2
VM
V3
V4
SHT
VL
0.1μF
1μF
1μF
Level Shift
& Output Buffer
30
LV5609LP
No.A0692-6/8
Timing Chart
XSG1
XSG3
XV1 to XV4
VDD
VSS
VDD
VSS
50% 50%
50%
TPMH
TTLM
VH 90% TTML
V1
V3
10%
90%
TPLM
VM
VL
10% TPML
10%
90%
TPLM
VM
VL
TPML
TTLM
V2
V4
TTML
XSHT
VDD
VSS
50% 50%
10%
90%
TPLH
VH
VL
TPHL
TTLH
SHT
TTHL
TTMH
TPHM
TTHM
LV5609LP
No.A0692-7/8
63.5μs
2μs127μs
2.5μs
16.7ms
2.5μs
63.5μs
2μs
XV3
XV1
XV2
XV4
XSG1
XSG3
XSHT
XV1
XV2
XV3
XV4
0μs0.7μs1.4μs2.1μs2.8μs3.5μs4.2μs4.9μs
CCD Equivalent Load Measurement Timing Waveform
Enlarged View of overlapped portion
LV5609LP
PS No.A0692-8/8
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