STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89468
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
C
SHEET 10
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
16/ This specification indicates the guaranteed maximum frequency at which a state machine with internal only feedback can
operate. If register output states must also control external points, this frequency can still be observed as long as this
frequency is less than 1/tCO1.
17/ This frequency indicates the maximum frequency at which the device may operate in data path mode (dedicated input pin
to output pin). This assumes data input signals are applied to dedicated input pins and no expander logic is used. If any
of the data inputs are I/O pins, tS2 is the appropriate tS for calculation.
18/ This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or
buried register can be cycled by a clock signal applied to the dedicated clock input pin.
19/ This parameter indicates the minimum time after a synchronous register clock input that the previous register output data
is maintained on the output pin.
20/ This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register
output signal to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are
used in logic of combinatorial output or the asynchronous clock input. The clock signal is applied to the dedicated clock
input pin and all feedback is within a single LAB.
21/ This specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock
to LAB logic array input. This delay plus the asynchronous register setup time, tAS1, is the minimum internal period for an
internal asynchronously clocked state machine configuration. This delay is for feedback within the same LAB, assumes no
expander logic in the clock path and assumes that the clock input signal is applied to a dedicated input pin.
22/ This parameter indicates the guaranteed maximum frequency at which an asynchronously clocked state machine
configuration with external feedback can operate. It is assumed that all data inputs, clock inputs, and feedback signals are
applied to dedicated inputs and that no expander logic is employed in the clock signal path or data path.
23/ This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be
cycled in asynchronously clocked mode by a clock signal applied to an external dedicated input pin.
24/ This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path
mode. This specification is determined by the least of 1/(tAWH + tAWL), 1/(tAS1 + tAH) or 1/(tACO1). It assumes data and clock
input signals are applied to dedicated input pins and no expander logic is used.
25/ This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with
internal only feedback can operate. This parameter is determined by the lesser of (1/(tACF + tAS)) or (1/(tAWH + tAWL)). If
register output states must also control external points, this frequency can still be observed as long as this frequency is
less than 1/tACO1.
This specification assumes no expander logic is utilized, all data inputs and clock inputs are applied to dedicated inputs,
and all state feedback is within a single LAB.
26/ This parameter indicates the minimum time that the previous register output data is maintained on the output after an
asynchronous register clock input applied to an external dedicated input pin.
3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN
listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD
PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device.
3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in
compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a "Q" or "QML" certification
mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used.
3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an
approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to
listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-
38535, appendix A and the requirements herein.
3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided
with each lot of microcircuits delivered to this drawing.
3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing.