FIGURE 3. Example Application in Multimedia Phone Using Stereo Loudspeaker ...................................................... 4
FIGURE 4. Example Application in a Multimedia Phone Using a Dedicated RF Module for Voice Modern Functions ............. 5
FIGURE 5. Example Application in a Portable Media Player with a Differential Stereo Line Input .................................... 6
FIGURE 6. Timing for I2S Master ................................................................................................................ 18
FIGURE 7. Timing for I2S Slave .................................................................................................................. 18
FIGURE 8. I2C Signals: Data Validity ............................................................................................................ 26
FIGURE 9. I2C Start and Stop Conditions ...................................................................................................... 26
FIGURE 10. I2C Chip Address .................................................................................................................... 26
FIGURE 11. Example I2C Write Cycle .......................................................................................................... 27
FIGURE 12. Example I2C Read Cycle .......................................................................................................... 28
FIGURE 13. I2C Timing Diagram ................................................................................................................. 28
FIGURE 14. Internal Clock Network ............................................................................................................. 36
FIGURE 15. PLL1 Loop ........................................................................................................................... 37
FIGURE 16. PLL2 Loop ............................................................................................................................ 37
FIGURE 17. EMI/RFI Filter for the Class D Amplifier ......................................................................................... 44
FIGURE 18. Digital Mixer .......................................................................................................................... 52
FIGURE 19. I2S Serial Data Format (24 bit example) ........................................................................................ 56
FIGURE 20. Left Justified Data Format (24 bit example) .................................................................................... 56
FIGURE 21. Right Justified Data Format (24 bit example) .................................................................................. 56
FIGURE 22. PCM Serial Data Format (16 bit example) ...................................................................................... 56
FIGURE 23. ADC DSP Effects Chain ........................................................................................................... 62
FIGURE 24. DAC DSP Effects Chain ........................................................................................................... 62
FIGURE 25. ALC Example ........................................................................................................................ 64
FIGURE 26. Demo Board Schematic ............................................................................................................ 98
FIGURE 27. Top Silkscreen Layer ............................................................................................................... 99
FIGURE 28. Top Layer ............................................................................................................................. 99
FIGURE 29. Inner Layer 1 ....................................................................................................................... 100
FIGURE 30. Inner Layer 2 ....................................................................................................................... 100
FIGURE 31. Bottom Silkscreen Layer ......................................................................................................... 101
FIGURE 32. Bottom Layer ...................................................................................................................... 101
FIGURE 33. Recommended Power Connection ............................................................................................ 102
FIGURE 34. Schematic for MEMs Microphones ............................................................................................. 103
List of Tables
TABLE 1. Device Register Map .................................................................................................................. 29
TABLE 2. PMC_SETUP (0x00h) ................................................................................................................. 33
TABLE 3. PMC_SETUP (0x01h) ................................................................................................................. 34
TABLE 4. PMC_SETUP (0x02h) (Default data value is 0x50h) ............................................................................. 34
TABLE 5. DAC Clock Requirements ............................................................................................................. 35
TABLE 6. ADC Clock Requirements ............................................................................................................. 35
TABLE 7. PLL Settings for Common System Clock Frequencies .......................................................................... 38
TABLE 8. PLL_CLOCK_SOURCE (0x03h) .................................................................................................... 39
TABLE 9. PLL1_M (0x04h) ........................................................................................................................ 39
TABLE 10. PLL1_N (0x05h) ...................................................................................................................... 39
TABLE 11. PLL1_N_MOD (0x06h) .............................................................................................................. 40
TABLE 12. PLL1_P1 (0x07h) ..................................................................................................................... 40
TABLE 13. PLL1_P2 (0x08h) ..................................................................................................................... 40
TABLE 14. PLL2_M (0x09h) ...................................................................................................................... 41
TABLE 15. PLL2_N (0x0Ah) ...................................................................................................................... 41
TABLE 16. PLL2_N_MOD (0x0Bh) .............................................................................................................. 41
TABLE 17. PLL2_P (0x0Ch) ...................................................................................................................... 42
TABLE 18. CLASS_D_OUTPUT (0x10h) ....................................................................................................... 43
TABLE 19. LEFT HEADPHONE_OUTPUT (0x11h) .......................................................................................... 44
TABLE 20. RIGHT HEADPHONE_OUTPUT (0x12h) ........................................................................................ 44
TABLE 21. AUX_OUTPUT (0x13h) .............................................................................................................. 45
TABLE 22. OUTPUT_OPTIONS (0x14h) ....................................................................................................... 45
TABLE 23. ADC_INPUT (0x15h) ................................................................................................................. 45
TABLE 24. MIC_L_INPUT (0x16h) .............................................................................................................. 46
TABLE 25. MIC_R_INPUT (0x17h) .............................................................................................................. 46
TABLE 26. AUX_L_INPUT (0x18h) .............................................................................................................. 47
TABLE 27. AUX_R_INPUT (0x19h) ............................................................................................................. 48
TABLE 28. ADC Basic (0x20h) ................................................................................................................... 49
TABLE 29. ADC_CLK_DIV (0x21h) ............................................................................................................. 50
TABLE 30. ADC TRIM (0x22h) ................................................................................................................... 50
TABLE 31. DAC Basic (0x30h) ................................................................................................................... 51
TABLE 32. DAC_CLK_DIV (0x31h) ............................................................................................................. 51
TABLE 33. Input Levels 1 (0x40h) ............................................................................................................... 53
TABLE 34. Input Levels 2 (0x41h) ............................................................................................................... 53
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