June 29, 2012 High Performance Audio Codec Sub-System with a Ground-Referenced Stereo Headphone Amplifier & an Ultra Low EMI Class D Loudspeaker Amplifier with Dual I2S/PCM Digital Audio Interfaces 1.0 General Description The LM49350 is a high performance audio subsystem that supports both analog and digital audio functions. The LM49350 includes a high quality stereo DAC, a high quality stereo ADC, a stereo headphone amplifier that supports ground referenced output cap-less operation, a dual mode earpiece speaker amplifier, and a low EMI Class D loudspeaker amplifier. It is designed for demanding applications in mobile phones and other portable devices. The LM49350 features dual bi-directional I2S or PCM audio interfaces for full range audio and an I2C compatible interface for control. The stereo DAC path features an SNR of 96dB with 24-bit 48 kHz input. The headphone amplifier delivers 69mWRMS (typ) to a 32 single-ended stereo load with less than 1% distortion (THD+N) when A_VDD = 3.3V. The earpiece speaker amplifier delivers 58mWRMS (typ) to a 32 bridged-tied load with less than 1% distortion (THD+N) when A_VDD = 3.3V. The loudspeaker amplifier delivers up to 495mW into an 8 load with less than 1% distortion when LS_VDD = 3.3V and up to 1.2W when LS_VDD = 5.0V. The LM49350 employs advanced techniques to reduce power consumption, to reduce controller overhead, to speed development time, and to eliminate click and pop. Boomer audio power amplifiers were designed specifically to provide high quality output power with a minimal amount of external components. It is therefore ideally suited for mobile phone and other low voltage applications where minimal power consumption, PCB area and cost are primary requirements. Smart Phones Mobile Phones and VOIP Phones Portable GPS Navigator and Portable Gaming Devices Portable DVD/CD/AAC/MP3/MP4 Players Digital Cameras/Camcorders 3.0 Key Specifications PHP at A_VDD = 3.3V, Stereo 32, 1% THD 69mW/ch (typ) PLS at LS_VDD = 5V, 8, 1% THD 1.2W (typ) PLS at LS_VDD = 4.2V, 8, 1% THD 825mW (typ) PLS at LS_VDD = 3.3V, 8, 1% THD 495mW (typ) PEP at A_VDD = 3.3V, 32 BTL, 1% THD 58mW (typ) 96dB (typ) 94dB (typ) 2.3A (typ) 97dB (typ) 4.0 Features 2.0 Applications SNR (Stereo DAC at 48kHz) SNR (Stereo ADC at 48kHz) Shutdown Current PSRR at 217 Hz, A_VDD = 3.3V, (HP from AUX) High performance 96dB SNR stereo DAC High performance 94dB SNR stereo ADC Up to 192kHz stereo audio playback Up to 48kHz stereo recording Dual bidirectional I2S or PCM compatible audio interfaces Read/write I2C compatible control interface Flexible digital mixer with sample rate conversion Dual sigma-delta PLLs for operation from any clock at any sample rate Digital 3D stereo enhancement Dual 5 band parametric equalizers Cascadable DSP effects that allow 10 band parametric equalization ALC/Compressor/Limiter on both DAC and ADC paths Ultra low EMI, Class D loudspeaker amplifier with spread spectrum control Ground referenced output cap-less headphone amplifier operation Earpiece speaker amplifier with reduced power consumption mode for mono differential line out applications Stereo auxiliary inputs or mono differential input Differential stereo microphone inputs with single-ended option Automatic level control for digital audio inputs, stereo microphone inputs, and stereo auxiliary inputs Flexible audio routing from input to output 16 Step volume control for microphones with 2dB steps 32 Step volume control for auxiliary inputs in 1.5dB steps Micro-power shutdown mode Available in the 3.5 x 3.5 mm 36 bump micro SMD package Supply Voltage Range D_VDD = 1.7V to 2.0V LS_VDD and A_VDD = 2.7V to 5.5V I/O_VDD = 1.6V to 4.5V Boomer(R) is a registered trademark of National Semiconductor Corporation. (c) 2012 Texas Instruments Incorporated 201941 SNAS359D www.ti.com LM49350 High Performance Audio Codec Sub-System with a Ground-Referenced Stereo Headphone Amplifier & an Ultra Low EMI Class D Loudspeaker Amplifier with Dual I2S/PCM Digital Audio Interfaces LM49350 LM49350 5.0 LM49350 Overview 20194111 FIGURE 1. LM49350 Block Diagram www.ti.com 2 LM49350 6.0 Typical Application 20194102 FIGURE 2. Example Application in Multimedia Phone with a Dedicated Earpiece and Mono Loudspeaker 3 www.ti.com LM49350 20194103 FIGURE 3. Example Application in Multimedia Phone Using Stereo Loudspeaker www.ti.com 4 LM49350 20194104 FIGURE 4. Example Application in a Multimedia Phone Using a Dedicated RF Module for Voice Modern Functions 5 www.ti.com LM49350 20194105 FIGURE 5. Example Application in a Portable Media Player with a Differential Stereo Line Input www.ti.com 6 1.0 General Description ......................................................................................................................... 1 2.0 Applications .................................................................................................................................... 1 3.0 Key Specifications ........................................................................................................................... 1 4.0 Features ........................................................................................................................................ 1 5.0 LM49350 Overview .......................................................................................................................... 2 6.0 Typical Application ........................................................................................................................... 3 7.0 Connection Diagrams ..................................................................................................................... 10 7.1 PIN TYPE DEFINITIONS ........................................................................................................ 11 8.0 Absolute Maximum Ratings ............................................................................................................ 12 9.0 Operating Ratings ......................................................................................................................... 12 10.0 Electrical Characteristics: A_VDD = LS_VDD = 3.3V; D_VDD = I/O_VDD = 1.8V ..................................... 12 11.0 Timing Characteristics: DVDD = I/OVDD = 1.8V ................................................................................. 16 12.0 Timing Characteristics: DVDD = I/OVDD = 1.8V ................................................................................ 17 13.0 Typical Performance Characteristics .............................................................................................. 19 14.0 System Control ............................................................................................................................ 26 14.1 I2C SIGNALS ....................................................................................................................... 26 14.2 I2C DATA VALIDITY ............................................................................................................. 26 14.3 I2C START AND STOP CONDITIONS ..................................................................................... 26 14.4 TRANSFERRING DATA ........................................................................................................ 26 14.5 I2C TIMING PARAMETERS .................................................................................................. 28 15.0 Device Register Map .................................................................................................................... 29 16.0 Basic PMC Setup Register ............................................................................................................ 33 17.0 PMC Clocks Register ................................................................................................................... 34 18.0 PMC Clock Divide Register ........................................................................................................... 34 19.0 LM49350 Clock Network .............................................................................................................. 35 20.0 PLL Setup Registers .................................................................................................................... 37 21.0 Analog Mixer Control Registers ..................................................................................................... 43 21.1 CLASS D LOUDSPEAKER AMPLIFIER .................................................................................. 43 21.2 SPREAD SPECTRUM MODULATION .................................................................................... 43 21.3 CLASS D POWER DISSIPATION AND EFFICIENCY ............................................................... 43 21.3.1 EMI/RFI Filtering ........................................................................................................ 43 21.4 HEADPHONE AMPLIFIER FUNCTION ................................................................................... 44 21.5 CHARGE PUMP CAPACITOR SELECTION ............................................................................ 44 21.6 CHARGE PUMP FLYING CAPACITOR (C6) ............................................................................ 44 21.7 CHARGE PUMP FLYING CAPACITOR (C5) ............................................................................ 44 21.8 AUXILIARY OUTPUT AMPLIFIER .......................................................................................... 45 22.0 ADC Control Registers ................................................................................................................. 49 23.0 DAC Control Registers ................................................................................................................. 51 24.0 Digital Mixer Control Registers ...................................................................................................... 52 24.1 DIGITAL MIXER ................................................................................................................... 52 25.0 Audio Port Control Registers ......................................................................................................... 56 26.0 Digital Effects Engine ................................................................................................................... 62 26.1 DIGITAL SIGNAL PROCESSOR (DSP) ................................................................................... 62 26.2 ALC OVERVIEW .................................................................................................................. 64 27.0 DAC Effects Registers .................................................................................................................. 80 28.0 GPIO Registers ........................................................................................................................... 96 FIGURE 26. Demo Board Schematic ..................................................................................................... 98 29.0 Demonstration Board Layout ......................................................................................................... 99 30.0 Application Note for LM49350 ...................................................................................................... 102 30.1 POWER CONNECTIONS .................................................................................................... 102 30.2 MICROPHONE BIAS CONFIGURATIONS ............................................................................. 103 30.2.1 Schematic Considerations for MEMs Microphones ........................................................ 103 30.2.2 Schematic Considerations for ECM Microphones .......................................................... 103 30.3 PCB LAYOUT CONSIDERATIONS ....................................................................................... 104 30.3.1 Microphone Inputs .................................................................................................... 104 30.3.2 Class D Loudspeaker ............................................................................................... 104 30.3.3 Capacitors ............................................................................................................... 104 31.0 Revision History ........................................................................................................................ 105 32.0 Physical Dimensions .................................................................................................................. 106 List of Figures FIGURE 1. LM49350 Block Diagram ............................................................................................................. 2 FIGURE 2. Example Application in Multimedia Phone with a Dedicated Earpiece and Mono Loudspeaker ......................... 3 7 www.ti.com LM49350 Table of Contents LM49350 FIGURE 3. Example Application in Multimedia Phone Using Stereo Loudspeaker ...................................................... 4 FIGURE 4. Example Application in a Multimedia Phone Using a Dedicated RF Module for Voice Modern Functions ............. 5 FIGURE 5. Example Application in a Portable Media Player with a Differential Stereo Line Input .................................... 6 FIGURE 6. Timing for I2S Master ................................................................................................................ 18 FIGURE 7. Timing for I2S Slave .................................................................................................................. 18 FIGURE 8. I2C Signals: Data Validity ............................................................................................................ 26 FIGURE 9. I2C Start and Stop Conditions ...................................................................................................... 26 FIGURE 10. I2C Chip Address .................................................................................................................... 26 FIGURE 11. Example I2C Write Cycle .......................................................................................................... 27 FIGURE 12. Example I2C Read Cycle .......................................................................................................... 28 FIGURE 13. I2C Timing Diagram ................................................................................................................. 28 FIGURE 14. Internal Clock Network ............................................................................................................. 36 FIGURE 15. PLL1 Loop ........................................................................................................................... 37 FIGURE 16. PLL2 Loop ............................................................................................................................ 37 FIGURE 17. EMI/RFI Filter for the Class D Amplifier ......................................................................................... 44 FIGURE 18. Digital Mixer .......................................................................................................................... 52 FIGURE 19. I2S Serial Data Format (24 bit example) ........................................................................................ 56 FIGURE 20. Left Justified Data Format (24 bit example) .................................................................................... 56 FIGURE 21. Right Justified Data Format (24 bit example) .................................................................................. 56 FIGURE 22. PCM Serial Data Format (16 bit example) ...................................................................................... 56 FIGURE 23. ADC DSP Effects Chain ........................................................................................................... 62 FIGURE 24. DAC DSP Effects Chain ........................................................................................................... 62 FIGURE 25. ALC Example ........................................................................................................................ 64 FIGURE 26. Demo Board Schematic ............................................................................................................ 98 FIGURE 27. Top Silkscreen Layer ............................................................................................................... 99 FIGURE 28. Top Layer ............................................................................................................................. 99 FIGURE 29. Inner Layer 1 ....................................................................................................................... 100 FIGURE 30. Inner Layer 2 ....................................................................................................................... 100 FIGURE 31. Bottom Silkscreen Layer ......................................................................................................... 101 FIGURE 32. Bottom Layer ...................................................................................................................... 101 FIGURE 33. Recommended Power Connection ............................................................................................ 102 FIGURE 34. Schematic for MEMs Microphones ............................................................................................. 103 List of Tables TABLE 1. Device Register Map .................................................................................................................. TABLE 2. PMC_SETUP (0x00h) ................................................................................................................. TABLE 3. PMC_SETUP (0x01h) ................................................................................................................. TABLE 4. PMC_SETUP (0x02h) (Default data value is 0x50h) ............................................................................. TABLE 5. DAC Clock Requirements ............................................................................................................. TABLE 6. ADC Clock Requirements ............................................................................................................. TABLE 7. PLL Settings for Common System Clock Frequencies .......................................................................... TABLE 8. PLL_CLOCK_SOURCE (0x03h) .................................................................................................... TABLE 9. PLL1_M (0x04h) ........................................................................................................................ TABLE 10. PLL1_N (0x05h) ...................................................................................................................... TABLE 11. PLL1_N_MOD (0x06h) .............................................................................................................. TABLE 12. PLL1_P1 (0x07h) ..................................................................................................................... TABLE 13. PLL1_P2 (0x08h) ..................................................................................................................... TABLE 14. PLL2_M (0x09h) ...................................................................................................................... TABLE 15. PLL2_N (0x0Ah) ...................................................................................................................... TABLE 16. PLL2_N_MOD (0x0Bh) .............................................................................................................. TABLE 17. PLL2_P (0x0Ch) ...................................................................................................................... TABLE 18. CLASS_D_OUTPUT (0x10h) ....................................................................................................... TABLE 19. LEFT HEADPHONE_OUTPUT (0x11h) .......................................................................................... TABLE 20. RIGHT HEADPHONE_OUTPUT (0x12h) ........................................................................................ TABLE 21. AUX_OUTPUT (0x13h) .............................................................................................................. TABLE 22. OUTPUT_OPTIONS (0x14h) ....................................................................................................... TABLE 23. ADC_INPUT (0x15h) ................................................................................................................. TABLE 24. MIC_L_INPUT (0x16h) .............................................................................................................. TABLE 25. MIC_R_INPUT (0x17h) .............................................................................................................. TABLE 26. AUX_L_INPUT (0x18h) .............................................................................................................. TABLE 27. AUX_R_INPUT (0x19h) ............................................................................................................. TABLE 28. ADC Basic (0x20h) ................................................................................................................... TABLE 29. ADC_CLK_DIV (0x21h) ............................................................................................................. TABLE 30. ADC TRIM (0x22h) ................................................................................................................... TABLE 31. DAC Basic (0x30h) ................................................................................................................... TABLE 32. DAC_CLK_DIV (0x31h) ............................................................................................................. TABLE 33. Input Levels 1 (0x40h) ............................................................................................................... TABLE 34. Input Levels 2 (0x41h) ............................................................................................................... www.ti.com 8 29 33 34 34 35 35 38 39 39 39 40 40 40 41 41 41 42 43 44 44 45 45 45 46 46 47 48 49 50 50 51 51 53 53 9 54 54 55 55 57 57 58 58 59 60 61 62 62 63 65 65 66 67 68 69 69 69 70 71 72 73 74 75 76 77 78 79 80 80 81 82 83 84 84 84 85 86 87 88 89 90 91 92 93 94 95 95 96 97 97 97 97 97 97 97 97 www.ti.com LM49350 TABLE 35. Audio Port 1 Input (0x42h) .......................................................................................................... TABLE 36. Audio Port 2 Input (0x43h) .......................................................................................................... TABLE 37. DAC Input Select (0x44h) ........................................................................................................... TABLE 38. Decimator Input Select (0x45h) .................................................................................................... TABLE 39. BASIC_SETUP (0x50h/0x60h) ..................................................................................................... TABLE 40. CLK_GEN_1 (0x51h/0x61h) ........................................................................................................ TABLE 41. CLK_GEN_1 (0x52h/62h) ........................................................................................................... TABLE 42. CLK_GEN_1 (0x53h/63h) ........................................................................................................... TABLE 43. DATA_WIDTHS (0x54h/64h) ....................................................................................................... TABLE 44. RX_MODE (0x55h/65h) ............................................................................................................. TABLE 45. TX_MODE (0x56h/x66h) ............................................................................................................ TABLE 46. ADC EFFECTS (0x70h) ............................................................................................................. TABLE 47. DAC EFFECTS (0x71h) ............................................................................................................. TABLE 48. HPF MODE (0x80h) .................................................................................................................. TABLE 49. ADC_ALC_1 (0x81h) ................................................................................................................. TABLE 50. ADC_ALC_2 (0x82h) ................................................................................................................. TABLE 51. ADC_ALC_3 (0x83h) ................................................................................................................. TABLE 52. ADC_ALC_4 (0x84h) ................................................................................................................. TABLE 53. ADC_ALC_5 (0x85h) ................................................................................................................. TABLE 54. ADC_ALC_6 (0x86h) ................................................................................................................. TABLE 55. ADC_ALC_7 (0x87h) ................................................................................................................. TABLE 56. ADC_ALC_8 (0x88h) ................................................................................................................. TABLE 57. ADC_L_LEVEL (0x89h) (Default data value is 0x33h) ......................................................................... TABLE 58. ADC_R_LEVEL (0x8Ah) (Default data value is 0x33h) ........................................................................ TABLE 59. EQ_BAND_1 (0x8Bh) ................................................................................................................ TABLE 60. EQ_BAND_2 (0x8Ch) ................................................................................................................ TABLE 61. EQ_BAND_3 (0x8Dh) ................................................................................................................ TABLE 62. EQ_BAND_4 (0x8Eh) ................................................................................................................ TABLE 63. EQ_BAND_5 (0x8Fh) ................................................................................................................ TABLE 64. SOFTCLIP1 (0x90h) ................................................................................................................. TABLE 65. SOFTCLIP2 (0x91h) ................................................................................................................. TABLE 66. SOFTCLIP3 (0x92h) ................................................................................................................. TABLE 67. DAC_ALC_1 (0xA0h) ................................................................................................................ TABLE 68. DAC_ALC_2 (0xA1h) ................................................................................................................ TABLE 69. DAC_ALC_3 (0xA2h) ................................................................................................................ TABLE 70. DAC_ALC_4 (0xA3h) ................................................................................................................ TABLE 71. DAC_ALC_5 (0xA4h) ................................................................................................................ TABLE 72. DAC_ALC_6 (0xA5h) ................................................................................................................ TABLE 73. DAC_ALC_7 (0xA6h) ................................................................................................................ TABLE 74. DAC_ALC_8 (0xA7h) ................................................................................................................ TABLE 75. DAC_L_LEVEL (0xA8h) (Default data value is 0x33h) ......................................................................... TABLE 76. DAC_R_LEVEL (0xA9h) (Default data value is 0x33h) ........................................................................ TABLE 77. DAC_3D (0xAAh) ..................................................................................................................... TABLE 78. EQ_BAND_1 (0xABh) ............................................................................................................... TABLE 79. EQ_BAND_2 (0xACh) ............................................................................................................... TABLE 80. EQ_BAND_3 (0xADh) ............................................................................................................... TABLE 81. EQ_BAND_4 (0xAEh) ............................................................................................................... TABLE 82. EQ_BAND_5 (0xAFh) ................................................................................................................ TABLE 83. SOFTCLIP1 (0xB0h) ................................................................................................................. TABLE 84. SOFTCLIP2 (0xB1h) ................................................................................................................. TABLE 85. SOFTCLIP3 (0xB2h) ................................................................................................................. TABLE 86. GPIO (0xE0h) ......................................................................................................................... TABLE 87. DEBUG1 (0xF0h) ..................................................................................................................... TABLE 88. Spread Spectrum (0xF1h) ........................................................................................................... TABLE 89. ADC Compensation Filter C0 LSBs (0xF8h) ..................................................................................... TABLE 90. ADC Compensation Filter C0 MSBs (0xF9h) .................................................................................... TABLE 91. ADC Compensation Filter C1 LSBs (0xFAh) ..................................................................................... TABLE 92. ADC Compensation Filter C1 MSBs (0xFBh) .................................................................................... TABLE 93. ADC Compensation Filter C2 LSBs (0xFCh) .................................................................................... TABLE 94. ADC Compensation Filter C2 MSBs (0xFDh) .................................................................................... TABLE 95. AUX_LINEOUT (0xFE) .............................................................................................................. LM49350 7.0 Connection Diagrams 36 Bump micro SMD 36 Bump micro SMD Marking 201941q7 Top View XY -- Date Code TT -- Die Traceability G -- Boomer J8 -- LM49350RL 20194101 Top View (Bump Side Down) Order Number LM49350RL See NS Package Number RLA36TTA Ordering Information Order Number Package Package DWG # Transport Media MSL Level Green Status LM49350RL 36 Bump micro SMDxt RLA36TTA 250 units on tape and reel 1 RoHS and no Sb/Br LM49350RLX 36 Bump micro SMDxt RLA36TTA 3000 units on tape and reel 1 RoHS and no Sb/Br www.ti.com 10 LM49350 Pin Descriptions Pin Pin Name Type Direction A1 HPR Analog Output Description A2 A_VDD Supply Input Headphone and mixer power supply input A3 AGND Supply Input Headphone and mixer ground A4 VREF_FLT Analog Input/Output Filter point for the microphone power supply and internal references A5 GPIO Digital Input/Output General purpose input or output A6 SDA Digital Input/Output I2C interface data line B1 HPL Analog Output Headphone left output B2 AUX_R Analog Input Right analog input B3 AUX_L Analog Input Left analog input B4 PORT2_SYNC Digital Input/Output B5 PORT2_SDI Digital Input Audio Port 2 serial data input B6 SCL Digital Input I2C interface clock line C1 HP_VSS Analog Output Negative power supply pin for the headphone amplifier C2 AUX_OUT+ Analog Output Auxiliary positive output C3 AUX_OUT- Analog Output Auxiliary negative output C4 PORT2_SDO Digital Output Audio port 2 serial data out C5 PORT2_CLK Digital Input/Output C6 MCLK Digital Input D1 CP- Analog Input/Output Charge pump flying capacitor negative input D2 CP+ Analog Input/Output Charge pump flying capacitor positive input D3 MIC_BIAS Analog Output D4 PORT1_SYNC Digital Input/Output D5 PORT1_SDO Digital Output D6 DGND Supply Input Digital ground E1 LSGND Supply Input Loudspeaker ground Headphone right output Audio Port 2 SYNC Signal (can be master or slave) Audio port 2 clock signal (can be master or slave) Input clock from 0.5MHz to 50 MHz Microphone ultra clean supply (2.2V) Audio Port 1 sync signal (can be master or slave) Audio Port 1 serial data output E2 LS_VDD Supply Input Loudspeaker power supply input E3 RIGHT_MIC- Analog Input Right microphone negative input E4 LEFT_MIC- Analog Output E5 PORT1_SDI Digital Input Audio Port 1 serial data input E6 D_VDD Supply Input Digital power supply input F1 LS + Analog Output Loudspeaker positive output F2 LS - Analog Output Loudspeaker negative output F3 RIGHT_MIC + Analog Input Right microphone positive input F4 LEFT_MIC + Analog Input Left microphone positive input F5 PORT1_CLK Digital Input/Output F6 I/O_VDD Supply Input Left microphone negative input Audio Port 1 clock signal (can be master or slave) Digital interface power supply input 7.1 PIN TYPE DEFINITIONS Analog Input -- A pin that is used by the analog and is never driven by the device. Supplies are part of this classification. Analog Output -- A pin that is driven by the device and should not be driven by external sources. Analog Input/Output -- A pin that is typically used for filtering a DC signal within the device. Pas- Digital Input -- Digital Output -- Digital Input/Output -- 11 sive components can be connected to these pins. A pin that is used by the digital but is never driven by the device. A pin that is driven by the device and should not be driven by another device to avoid contention. A pin that is either open drain (SDA) or a bidirectional CMOS in/out. In the latter case the direction is selected by a control register within the LM49350. www.ti.com LM49350 Junction Temperature Thermal Resistance JA - RLA36 (soldered down to PCB with 2in2 1oz. copper plane) Soldering Information See Applications Note AN-1112. 8.0 Absolute Maximum Ratings (Note 1, Note 2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Analog Supply Voltage (A_VDD and LS_VDD) Digital Supply Voltage D_VDD I/O Supply Voltage I/O_VDD Storage Temperature Power Dissipation (Note 3) ESD Ratings Human Body Model (Note 4) Machine Model (Note 5) 6.0V 150C 60C/W 9.0 Operating Ratings 2.2V Temperature Range Supply Voltage A_VDD and LS_VDD (Note 8) D_VDD I/O_VDD 5.5V -65C to +150C Internally Limited -40C to +85C 2.7V to 5.5V 1.7V to 2.0V 1.6V to 4.5V 2000V 200V 10.0 Electrical Characteristics: A_VDD = LS_VDD = 3.3V; D_VDD = I/O_VDD = 1.8V (Note 1, Note 2) The following specifications apply for RL(LS) = 8, RL(HP) = 32, f = 1kHz, unless otherwise specified. Limits apply for TA = 25C. LM49350 Symbol Parameter Conditions Typical (Note 6) Limit (Note 7) Units (Limits) DC CHARACTERISTICS (Digital current combines D_VDD and I/O_VDD. Analog current combines A_VDD and LS_VDD) DISD Digital Shutdown Current Shutdown Mode, fMCLK = 13MHz, PLL Off DIST Digital Standby Current Digital Active Current (MP3 Mode) 2 15 A (max) fMCLK = 12.288MHz, PMC On only 0.25 1 mA (max) fMCLK = 11.2896MHz, fS = 44.1kHz, Stereo DAC On, OSRDAC = 128, PLL Off, HP On 0.9 2 mA (max) Digital Active Current (FM Mode) fMCLK = 13MHz Analog Audio modes 0.2 0.5 mA (max) Digital Active Current (FM Record Mode) fMCLK = 12.288MHz, fS = 48kHz, Stereo ADC On, OSRADC = 128, PLL Off, Stereo Analog Inputs On 1.5 2 mA (max) Digital Active Current (CODEC Mode)- fMCLK = 11.2896MHz, fS = 44.1kHz, Mono ADC On, Stereo DAC On, OSR = 128, PLL Off, MIC On 2.7 3.8 mA (max) AISD Analog Shutdown Current Shutdown Mode 0.3 5 A (max) AIST Analog Standby Quiescent Current Reference Voltages On only DIDD 0.85 1.5 mA (max) fMCLK = 11.2896MHz, fS = 44.1kHz, Analog Supply Current (MP3 Mode) Stereo DAC On, OSRDAC = 128, PLL Off, HP On 7.8 10 mA (max) Analog Supply Current (FM Mode) Stereo Analog Inputs On, HP On 5.3 7 mA (max) Analog Supply Current (FM Record Mode) fMCLK = 12.288MHz, fS = 48kHz, Stereo ADC On, OSRADC = 128, PLL Off, Stereo Analog Inputs On 9.8 12 mA (max) Analog Supply Current (CODEC Mode) fMCLK = 11.2896MHz, fS = 44.1kHz, Mono ADC On, Stereo DAC On, OSR = 128, PLL Off, MIC On 13 15 mA (max) PLLIDD PLL Total Active Current fMCLK = 13MHz, fPLLOUT = 12MHz, PLL On only 2.9 5.5 mA (max) HPIDD Headphone Quiescent Current Stereo HP On only 3.5 mA LSIDD Loudspeaker Quiescent Current LS On only 2.9 mA AIDD www.ti.com 12 Parameter Conditions Typical (Note 6) Limit (Note 7) Units (Limits) MICIDD Microphone Quiescent Current mono MIC + MIC Bias On 0.5 mA ADCIDD ADC Total Active Current fS = 48kHz, Stereo 9 mA DACIDD DAC Total Active Current fS = 48kHz, Stereo 5.5 mA AUXINIDD Auxiliary Input Amplifier Quiescent Current Stereo Auxiliary Inputs enabled 0.7 mA AUXOUTIDD Auxiliary Output Amplifier Quiescent AUX_LINE_OUT enabled Current Earpiece mode enabled 0.5 mA 1.0 mA 83 % 0.07 % LOUDSPEAKER AMPLIFIER LSEFF Loudspeaker Efficiency THD+N Total Harmonic Distortion + Noise PO = 400mW, RL = 8 PO = 400mW, f = 1kHz, RL = 8, Mono Input Signal RL = 8, f = 1kHz, THD+N = 1%, Mono Input Signal PO Output Power LS_VDD = 3.3V LS_VDD = 4.2V LS_VDD = 5V 495 825 1.2 400 mW (min) mW W RL = 4, f = 1kHz, THD+N = 1%, Mono Input Signal LS_VDD = 3.3V LS_VDD = 4.2V LS_VDD = 5V 800 1.4 2 73 55 dB (min) 85 dB (min) PSRR Power Supply Rejection Ration VRIPPLE = 200mVP-P fRIPPLE = 217Hz Mono Input Terminated VREF = 1.0F SNR Signal-to-Noise Ratio Reference = VOUT (1% THD+N ) Gain = 0dB, A-weighted Mono Input Terminated 95 eOS Output Noise Gain = 0dB, A-weighted, Mono Input Terminated 35 VOS Offset Voltage Gain = 0dB, form Mono Input 10 TWU Turn-On Time PMC Clock = 300kHz 28 mW W W V 50 mV (max) ms HEADPHONE AMPLIFIERS PO = 7.5mW, f = 1kHz, THD+N Total Harmonic Distortion + Noise PO Headphone Output Power Power Supply Rejection Ratio PSRR SNR Signal-to-Noise Ratio RL = 32 Stereo Analog Input Signal 0.025 0.1 % (max) RL = 32, f = 1kHz, THD+N = 1%, Stereo Analog Input Signal 69 60 mW (min) VRIPPLE = 200mVP-P, fRIPPLE = 217Hz Stereo Analog Inputs Terminated, VREF = 1.0F, Mono Differential Input Mode 97 75 dB (min) Reference = VOUT (1% THD+N ) Gain = 0dB, A-weighted Stereo Inputs Terminated 106 98 dB (min) Reference = VOUT (0dBFS ) Gain = 0dB, A-weighted, I2S Input = Digital Zero 96 90 dB (min) 13 www.ti.com LM49350 LM49350 Symbol LM49350 LM49350 Symbol eOS Parameter Output Noise Conditions Typical (Note 6) Limit (Note 7) Units (Limits) Gain = 0dB, A-weighted, Stereo Inputs Terminated 8 V Gain = 0dB, A-weighted, I2S Input = Digital Zero 16 V 71 dB 0.03 dB PO = 60mW, f = 1kHz, XTALK Crosstalk ACH-CH Channel-to-Channel Gain Matching VOS TWU Output Offset Voltage Turn-On Time RL = 32 Stereo Analog Input Signal AUX Gain = 0dB From Differential Mono Input 0.5 6 mV (max) DAC Gain = 0dB, From DAC Input fMCLK = 12.288MHz, PLL off 1 6 mV (max) PMC Clock = 300kHz 28 ms AUX_LINE_OUT RL = 5k, VOUT = 1VRMS 0.004 % Earpiece mode, f = 1kHz RL = 32 BTL, POUT = 20mW 0.08 % Earpiece mode, f = 1kHz RL = 32 BTL, THD+N = 1% 58 AUXILIARY OUTPUTS THD+N POUT Total Harmonic Distortion + Noise Output Power 45 mW (min) VRIPPLE = 200mVP-P, fRIPPLE = 217Hz PSRR Power Supply Rejection Ratio Mono Input terminated, CREF = 1F AUX_LINE_OUT 100 dB VRIPPLE = 200mVP-P, fRIPPLE = 217Hz Mono Input terminated, CREF = 1F Earpiece mode 94 62 dB (min) SNR Signal-to-Noise Ratio Gain = 0dB, VREF = VOUT (1%THD+N) A-weighted, Mono Input Terminated 100 dB OUT Output Noise Gain = 0dB, VREF = VOUT (1%THD+N) A-weighted, Mono Input Terminated 13 V Gain = 0dB, From Mono Input AUX_LINE_OUT 7 mV Gain = 0dB, From Mono Input Earpiece mode 3 Turn-On Time PMC Clock = 300kHz 28 ms ADC Total Harmonic Distortion + Noise Differential Line Input VIN = 200mVRMS, f = 1kHz Gain = 0dB 0.03 % HPF On, fS = 48kHz Lower -3dB Point 300 Hz VOS TWU Output Offset Voltage 15 mV (max) STEREO ADC THD+NADC PBADC ADC Passband RADC ADC Ripple 0.41*fS kHz ADC Compensated 0.1 dB Reference = VOUT (0dBFS ) Gain = 6dB, A-weighted From MIC, fS = 8kHz 90 dB Reference = VOUT (0dBFS ) Gain = 0dB, A-weighted From Stereo Input, fS = 48kHz 94 dB HPF On, Upper -3dB Point SNRADC www.ti.com ADC Signal-to-Noise Ratio 14 ADCLEVEL Parameter Conditions ADC Full Scale Input Level Typical (Note 6) Limit (Note 7) Units (Limits) 1 VRMS 0.05 % 1 VRMS STEREO DAC I2S Input VIN = 500mFFSRMS, f = 1kHz Gain = 0dB THD+NDAC DAC Total Harmonic Distortion + Noise DACLEVEL DAC Full Scale Output Level RDAC DAC Ripple PBDAC DAC Passband Upper -3dB Point SNRDAC DAC Signal-to-Noise Ratio Microphone Bias Voltage 0.1 dB 0.45*fS kHz fS = 48kHz, A-weighted 96 dB MIC input selected 2.2 V Minimum Gain -46.5 dB Maximum Gain 12 dB Minimum Gain -76.5 dB Maximum Gain 18 dB Minimum Gain -76.5 dB Maximum Gain 18 dB Minimum Gain 6 dB Maximum Gain 36 dB MIC BIAS VBIAS VOLUME CONTROL VCRAUX Stereo Input Volume Control Range VCRDAC DAC Volume Control Range VCRADC ADC Volume Control Range VCRMIC MIC Volume Control Range SSAUX AUX Volume Control Stepsize 1.5 dB SSDAC DAC Volume Control Stepsize 1.5 dB SSADC DAC Volume Control Stepsize 1.5 dB SSMIC MIC Volume Control Stepsize 2 SVAUX AUX Volume Setting Variation 1 dB (max) SVMIC MIC Volume Setting Variation 1 dB (max) dB ANALOG INPUTS AUXR_RIN Right Auxiliary Input Impedance AUXR Gain = 12dB 17.5 k AUXR Gain = 0dB 38 k AUXR Gain = -46.5dB 64 k AUXL Gain = 12dB 17.5 k AUXL Gain = 0dB 38 k AUXL_RIN Right Auxiliary Input Impedance AUXL Gain = -46.5dB 64 k MICR_RIN Right Microphone Input Impedance All MIC gain settings 50 k MICL_RIN Left Microphone Input Impedance All MIC gain settings 50 k Note 1: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, JA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / JA or the number given in Absolute Maximum Ratings, whichever is lower. Note 4: Human body model, applicable std. JESD22-A114C. Note 5: Machine model, applicable std. JESD22-A115-A. Note 6: Typical values represent most likely parametric norms at TA = +25C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 7: Datasheet min/max specification limits are guaranteed by test or statistical analysis. Note 8: LS_VDD need to be the highest voltage than A_VDD, D_VDD, and I/O_VDD. For proper power supply sequence, LS_VDD need to be applied first. 15 www.ti.com LM49350 LM49350 Symbol LM49350 11.0 Timing Characteristics: DVDD = I/OVDD = 1.8V (Note 1, Note 2) The following specifications apply for RL(SP) = 8, RL(HP) = 32, f = 1kHz, unless otherwise specified. Limits apply for TA = 25C. LM49350 Symbol Parameter Conditions Typical (Note 6) Limit (Note 7) Units (Limits) PLL fIN PLL Input Frequency Range Minimum MCLK Frequency 0.5 MHz (min) Maximum MCLK Frequency 50 MHz (max) 3 ns (max) 3 ns (max) DIGITAL AUDIO INTERFACE TIMING tBCLKR BCK rise time tBCLKCF BCK fall time tBCLKDS BCK duty cycle tDL WS Propagation Delay from BCK falling edge 10 ns (max) tDST DATA Setup Time to BCK Rising Edge 10 ns (min) tDHT DATA Hold Time from BCK Rising Edge 10 ns (min) SCL Frequency 400 kHz (max) 1 Hold Time (repeated START Condition) 0.6 s (min) 2 Clock Low Time 1.3 s (min) 3 Clock High Time 600 ns (min) 4 Setup Time for a Repeated START Condition 600 ns (min) Output 300 900 ns (min) ns (max) Input 0 900 ns (min) ns (max) 50 % CONTROL INTERFACE TIMING 5 6 Data Hold Time Data Setup Time 100 ns (min) ns (min) ns (max) 7 Rise Time of SDA and SCL 20+0.1CB 300 8 Fall Time SDA and SCL 15+0.1CB 300 ns (min) ns (max) 9 Setup Time for STOP Condition 600 ns (min) 10 Bus Free Time Between a STOP and START Condition 1.3 s (min) CB Bus Capacitance 10 200 pF (min) pF(max) www.ti.com 16 (Note 1, Note 2) The following specifications apply for RL(SP) = 8, RL(HP) = 32, f = 1kHz, unless otherwise specified. Limits apply for TA = 25C. LM49350 Symbol Parameter Conditions Typical (Note 6) Limit (Note 7) Units (Limit) PLL fIN PLL Input Frequency Range Minimum MCLK Frequency 0.5 MHz (min) Maximum MCLK Frequency 50 MHz (max) I2S MASTER TIMING I2S_CLKPER I2S_CLK Period I2S Master 81.38 ns tCLK_L I2S_CLK Low Time I2S Master 37 ns tCLK_H I2S_CLK High Time I2S Master 37 ns tWS_DLY WS Propagation Delay from I2S_CLK falling edge I2S Master 21 ns tSDO_DLY SDO Propagation Delay from I2S_CLK falling edge I2S Master 21 ns tDST SDI Setup Time to I2S_CLK Rising Edge I2S Master 20 ns tDHT SDI Hold Time to I2S_CLK Rising Edge I2S Master 20 ns I2S SLAVE TIMING I2S_CLKPER I2S_CLK Period I2S Slave tCLK_L I2S_CLK Low Time I2S tCLK_H I2S_CLK High Time tSDO_DLY SDO Propagation Delay from I2S_CLK falling edge I2S Slave tDST SDI Setup Time to I2S_CLK Rising Edge I2S Slave 20 ns (min) tDHT SDI Hold Time to I2S_CLK Rising Edge I2S Slave 20 ns (min) tWS_ST WS Setup Time to I2S_CLK Rising Edge I2S Slave 20 ns (min) tWS_HT WS Hold Time to I2S_CLK Rising Edge I2S Slave 20 ns (min) 17 81.38 ns (min) Slave 37 ns (min) I2S Slave 37 ns (min) 21 ns www.ti.com LM49350 12.0 Timing Characteristics: DVDD = I/OVDD = 1.8V LM49350 20194113 w = write (SDA = "0") r = read (SDA = "1") ack = acknowledge (SDA pulled down by slave) rs = repeated start FIGURE 6. Timing for I2S Master 20194121 w = write (SDA = "0") r = read (SDA = "1") ack = acknowledge (SDA pulled down by slave) rs = repeated start FIGURE 7. Timing for I2S Slave www.ti.com 18 LM49350 13.0 Typical Performance Characteristics DAC Frequency Response fS = 48kHz, OSR = 128 DAC Frequency Response fS = 8kHz, OSR = 128 20194140 20194139 Stereo Audio ADC Frequency Response fS = 48kHz, OSR = 128, CIN = 1F, MIC gain = 6dB Stereo Audio ADC Frequency Response fS = 8kHz, OSR = 128, CIN = 1F, MIC gain = 6dB 20194142 20194141 Stereo Audio ADC HPF Frequency Response fS = 48kHz, OSR = 128, CIN = 1F, MIC gain = 6dB (Top-No HPF, Upper-HPF_Mode = '101', Lower-HPF_Mode = '110)' Bottom-HPF_Mode = '111' Mono Voice ADC Frequency Response fS = 48kHz, OSR = 128, CIN = 1F, MIC gain = 6dB 20194144 20194143 19 www.ti.com LM49350 Mono Voice ADC Frequency Response fS = 8kHz, OSR = 128, CIN = 1F, MIC gain = 6dB Mono Voice ADC HPF Frequency Response fS = 48kHz, OSR = 128, CIN = 1F, MIC gain = 6dB (Top-No HPF) (From Left to Right: HPF_Mode = '000', '001', '010', '011', '100') 20194145 20194146 Mono Voice ADC HPF Frequency Response fS = 8kHz, OSR = 128, CIN = 1F, MIC gain = 6dB (Top-No HPF) (From Left to Right: HPF_Mode = '000', '001', '010', '011', '100') ADC Output THD+N vs Frequency Differential Line Input, Aux Gain = 0dB VIN = 200mVRMS, fS = 48kHz 20194155 20194147 ADC Output THD+N vs Frequency Differential MIC Input, MIC Gain = 6dB VIN = 100mVRMS, fS = 48kHz ADC Output THD+N vs VIN Differential Line Input, Aux Gain = 0dB VIN = 1kHz, fS = 48kHz 20194156 20194148 www.ti.com 20 LM49350 ADC Output THD+N vs VIN Differential MIC Input, MIC Gain = 6dB VIN = 1kHz, fS = 48kHz Loudspeaker THD+N vs Frequency Differential Aux Input, Aux Gain = 0dB VDD = 3.3V, POUT = 400mW, RL = 8 20194159 20194149 Loudspeaker THD+N vs Frequency Differential Aux Input, Aux Gain = 0dB VDD = 5V, POUT = 400mW, RL = 8 Loudspeaker THD+N vs Frequency Differential Aux Input, Aux Gain = 0dB LS_VDD = 3.3V, POUT = 500mW, RL = 4 20194161 20194181 Loudspeaker THD+N vs Output Power Differential Aux Input, Aux Gain = 0dB VDD = 3.3V, VIN = 1kHz, RL = 8 Loudspeaker THD+N vs Output Power Differential Aux Input, Aux Gain = 0dB VDD = 4.2V, VIN = 1kHz, RL = 8 20194165 20194166 21 www.ti.com LM49350 Loudspeaker THD+N vs Output Power Differential Aux Input, Aux Gain = 0dB VDD = 5V, VIN = 1kHz, RL = 8 Loudspeaker THD+N vs Output Power Differential Aux Input, Aux Gain = 0dB LS_VDD = 3.3V, RL = 4, f = 1kHz 20194167 20194182 Loudspeaker THD+N vs Output Power Differential Aux Input, Aux Gain = 0dB LS_VDD = 4.2V, RL = 4, f = 1kHz Loudspeaker THD+N vs Output Power Differential Aux Input, Aux Gain = 0dB LS_VDD = 5V, RL = 4, f = 1kHz 20194183 20194184 Loudspeaker PSRR vs Frequency LS_VDD = 3.3V, Aux Gain = 0dB Differential Aux Input to Ground VRIPPLE = 200mVPP Loudspeaker PSRR vs Frequency LS_VDD = 4.2V, Aux Gain = 0dB Differential Aux Input to Ground VRIPPLE = 200mVPP 20194151 www.ti.com 20194152 22 LM49350 Loudspeaker PSRR vs Frequency LS_VDD = 5V, Aux Gain = 0dB Differential Aux Input to Ground VRIPPLE = 200mVPP Headphone THD+N vs Frequency Stereo Aux Input, Aux Gain = 0dB VDD = 3.3V, POUT = 7.5mW, RL = 32 20194157 20194153 Headphone THD+N vs Frequency Stereo Aux Input, Aux Gain = 0dB VDD = 5V, POUT = 7.5mW, RL = 32 Headphone THD+N vs Frequency Differential Aux Input, Aux Gain = 0dB A_VDD = 3.3V, POUT = 7.5mW, RL = 16 20194158 20194179 Headphone THD+N vs Output Power Stereo Aux Input, Aux Gain = 0dB VDD = 3.3V, VIN = 1kHz, RL = 32 Headphone THD+N vs Output Power Stereo Aux Input, Aux Gain = 0dB VDD = 5V, VIN = 1kHz, RL = 32 20194173 20194174 23 www.ti.com LM49350 Headphone THD+N vs Output Power A_VDD = 3.3V, Stereo Aux Input, Aux Gain = 0dB RL = 16, f = 1kHz Headphone PSRR vs Frequency Differential Aux Input to Ground, Aux Gain = 0dB VRIPPLE = 200mVPP 20194175 20194180 Headphone Crosstalk vs Frequency Stereo Aux Inputs, Aux Gain = 0dB, RL = 32 Earpiece THD+N vs Frequency Differential Aux Input, Aux Gain = 0dB A_VDD = 3.3V, POUT = 20mW, RL = 32 20194169 20194176 Earpiece THD+N vs Output Power Differential Aux Input, Aux Gain = 0dB A_VDD45 = 3.3V, RL = 32, f = 1kHz Earpiece PSRR vs Frequency Differential Aux Input to Ground, Aux Gain = 0dB VRIPPLE = 200mVPP 20194177 www.ti.com 20194178 24 LM49350 AUXOUT THD+N vs Frequency Differential Aux Input, Aux Gain = 0dB VDD = 5V, VOUT = 1VRMS, RL = 5k AUXOUT THD+N vs Output Voltage Differential Aux Input, Aux Gain = 0dB VIN = 1kHz, RL = 5k 20194162 20194168 AUXOUT PSRR vs Frequency Differential Aux Input to Ground, Aux Gain = 0dB VRIPPLE = 200mVPP 20194154 25 www.ti.com LM49350 these signals need a pull-up resistor according to I2C specification. The I2C slave address for LM49350 is 00110102. 14.0 System Control Method 1. I2C Compatible Interface 14.2 I2C DATA VALIDITY The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when SCL is LOW. 14.1 I2C SIGNALS In I2C mode the LM49350 pin SCL is used for the I2C clock SCL and the pin SDA is used for the I2C data signal SDA. Both 20194123 FIGURE 8. I2C Signals: Data Validity START and STOP bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data transmission, I2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise. 14.3 I2C START AND STOP CONDITIONS START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates 20194124 FIGURE 9. I2C Start and Stop Conditions After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eight bit which is a data direction bit (R/W). The LM49350 address is 00110102. For the eighth bit, a "0" indicates a WRITE and a "1" indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register. 14.4 TRANSFERRING DATA Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been received. 20194125 FIGURE 10. I2C Chip Address www.ti.com 26 LM49350 Register changes take effect at the SCL rising edge during the last ACK from slave. 20194126 w = write (SDA = "0") r = read (SDA = "1") ack = acknowledge (SDA pulled down by slave) rs = repeated start FIGURE 11. Example I2C Write Cycle 27 www.ti.com LM49350 When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle waveform. 20194127 FIGURE 12. Example I2C Read Cycle 20194128 FIGURE 13. I2C Timing Diagram 14.5 I2C TIMING PARAMETERS Symbol Limit Parameter 1 Hold Time (repeated) START Condition 2 3 Min Max Units 0.6 s Clock Low Time 1.3 s Clock High Time 600 ns 4 Setup Time for a Repeated START Condition 600 ns 5 Data Hold Time (Output direction, delay generated by LM49350) 300 900 ns 5 Data Hold Time (Input direction, delay generated by the Master) 0 900 ns 6 Data Setup Time 7 Rise Time of SDA and SCL 20+0.1Cb 300 ns 8 Fall Time of SDA and SCL 15+0.1Cb 300 ns 100 9 Set-up Time for STOP condition 600 10 Bus Free Time between a STOP and a START Condition 1.3 CB Capacitive Load for Each Bus Line 10 NOTE: Data guaranteed by design www.ti.com 28 ns ns s 200 pF LM49350 15.0 Device Register Map TABLE 1. Device Register Map Address Register 7 6 5 4 3 2 1 0 OSC ENB PLL2 ENB PLL1 ENB CHIP ENABLE BASIC SETUP 0x00h PMC SETUP 0x01h PMC CLOCKS 0x02h PMC CLK_DIV CHIP ACTIVE PORT2 CLK OVR PORT1 CLK OVR MCLK OVR PMC_CLK_SEL PMC_CLK_DIV(R) PLLs 0x03h PLL2_CLK_SEL 0x04h PLL1 M 0x05h PLL1 N 0x06h PLL1 N_MOD 0x07h PLL1 P1 PLL1 P1 [7:0] 0x08h PLL1 P2 PLL1 P2[7:0] 0x09h PLL2 M 0x0Ah PLL2 N 0x0Bh PLL2 N_MOD 0x0Ch PLL2 P PLL1_CLK_SEL PLL1 M PLL1 N PLL2 P2[8] PLL1 P1[8] PLL1 N_MOD PLL2 M PLL2 N PLL2 P[8] PLL2 N_MOD PLL2 P[7:0] ANALOG MIXER 0x10h CLASSD 0x11h HEAD PHONESL AUXL_LS AUXR_LS MICL_LS MICR_LS DACL_LS AUXL_HPL AUXR_HPL MICL_HPL MICR_HPL DACL_HPL 0x12h HEAD PHONESR AUXL_HPR AUXR_ HPR 0x13h AUX_OUT AUXL_AX AUXR_AX MICL_AX 0x14h OUTPUT OPTIONS CP_ FORCE 0x15h ADC AUXL_ ADCR AUXR_ ADCL 0x16h MICL_LVL MUTE SE/DIFF MIC_L_LEVEL 0x17h MICR_LVL MUTE SE/DIFF MIC_R_LEVEL 0x18h AUXL_LVL FROM LINEL 0x19h AUXR_LVL DIFF_MOD FROM E LINER DACR_LS DACR_HPL DACL_ HPR DACR_ HPR MICR_AX DACL_AX DACR_AX AUX-6dB LS-6dB HP-6dB EPMODE MICL_ ADCR MICR_ ADCL DACL_ ADCR DACR_ ADCL MICL_HPR MICR_HPR AUX_L_LEVEL AUX_R_LEVEL ADC 0x20h ADC BASIC DSPONLY 0x21h ADC CLOCK 0x22h ADC_DSP ADC_CLK_SEL MUTE_R MUTE_L ADC_OSR MONO ADC_CLK_DIV (T) ADC_TRIM DAC 0x30h DAC_BASI C 0x31h DAC_CLO CK 0x32h DAC_DSP DSPONLY DAC_CLK_SEL MUTE_R MUTE_L DAC_OSR DAC_CLK_DIV (S) DAC_TRIM 29 www.ti.com LM49350 Address Register 7 6 5 4 3 2 1 0 0x40h IPLVL1 PORT2_RX_R_LVL PORT2_RX_L_LVL PORT1_RX_R_LVL PORT1_RX_L_LVL 0x41h IPLVL2 INTERP_L_LVL INTERP_R_LVL ADC_R_LVL ADC_L_LVL 0x42h OPPORT1 MONO SWAP R_SEL L_SEL 0x43h OPPORT2 MONO SWAP R_SEL 0x44h OPDAC ADCR PORT2R 0x45h OPDECI DIGITAL MIXER SWAP PORT1R MXRCLK_SEL L_SEL ADCL PORT2L R_SEL PORT1L L_SEL AUDIO PORT 1 STEREO_S STEREO_ YNC_ SYNC_ MODE PHASE 0x50h BASIC CLK_PH SYNC_MS 0x51h CLK_GEN1 0x52h CLK_GEN2 0x53h SYNC_ GEN 0x54h DATA_ WIDTH 0x55h RX_MODE A/ULAW COMPAND MSB_POSITION RX_MODE 0x56h TX_MODE A/ULAW COMPAND MSB_POSITION TX_MODE CLK_SEL CLK_MS TX_ENB RX_ENB STEREO HALF_CYCLE_DIVDER SYNTH_D ENOM SYNTH_NOM SYNC_WIDTH(MONO MODE) SYNC_RATE TX_WIDTH RX_WIDTH TX_EXTRA_BITS AUDIO PORT 2 STEREO_S STEREO_ YNC_ SYNC_ MODE PHASE 0x60h BASIC CLK_PH SYNC_MS 0x61h CLK_GEN1 0x62h CLK_GEN2 0x63h SYNC_ GEN 0x64h DATA_ WIDTH 0x65h RX_MODE A/ULAW COMPAND MSB_POSITION RX_MODE 0x66h TX_MODE A/ULAW COMPAND MSB_POSITION TX_MODE CLK_SEL CLK_MS TX_ENB RX_ENB STEREO HALF_CYCLE_DIVDER SYNTH_ DENOM SYNTH_NOM SYNC_WIDTH(MONO MODE) SYNC_RATE TX_WIDTH RX_WIDTH TX_EXTRA_BITS EFFECTS ENGINE 0x70h ADC FX ADC SCLP ENB ADC EQ ENB ADC PK ENB ADC ALC ENB ADC HPF_ENB 0x71h DAC FX DAC SCLP ENB DAC 3D ENB DAC EQ ENB DAC PK ENB DAC ALC ENB 0x80h HPF 0x81h ADC ALC 1 0x82h ADC ALC 2 0x83h ADC ALC 3 ALC_TARGET_LEVEL 0x84h ADC ALC 4 ATTACK_RATE 0x85h ADC ALC 5 0x86h ADC ALC 6 ADC EFFECTS www.ti.com HPF MODE SOURCE OVR SOURCE SEL STEREO LINK NG_ENB PK_DECAY_RATE LIMITER SAMPLE_RATE NOISE_FLOOR DECAY_RATE/RELEASE_RATE HOLDTIME 30 Register 7 6 5 4 3 2 0x87h ADC ALC 7 MAX_LEVEL 0x88h ADC ALC 8 MIN_LEVEL 0x89h ADC L LEVEL ADC_L_LEVEL 0x8Ah ADC R LEVEL ADC_R_LEVEL 0x8Bh EQ BAND 1 0x8Ch EQ BAND 2 0x8Dh EQ BAND 3 0x8Eh EQ BAND 4 0x8Fh 1 0 LEVEL FREQ Q LEVEL FREQ Q LEVEL FREQ Q LEVEL FREQ EQ BAND 5 LEVEL FREQ 0x90h SOFTCLIP 1 SOFT KNEE 0x91h SOFTCLIP 2 RATIO 0x92h SOFTCLIP 3 LEVEL THRESHOLD ADC EFFECT MONITORS 0x98h LVLMONL ADC LEFT LEVEL MONITOR 0x99h LVLMONR ADC RIGHT LEVEL MONITOR 0x9Ah FXCLIP SCLP_R CLIP SCLP_L CLIP 0x9Bh ALCMONL SCLP_R DISTORT SCLP_L DISTORT ADC LEFT ALC MONITOR 0x9Ch ALCMONR SCLP_L DISTORT SCLP_R DISTORT ADC RIGHT ALC MONITOR 0xA0h DAC ALC 1 STEREO LINK 0xA1h DAC ALC 2 NG_ENB 0xA2h DAC ALC 3 AGC_TARGET_LEVEL 0xA3h DAC ALC 4 ATTACK_RATE 0xA4h DAC ALC 5 0xA5h DAC ALC 6 0xA6h DAC ALC 7 MAX_LEVEL 0xA7h DAC ALC 8 MIN_LEVEL 0xA8h DAC L LEVEL DAC_L_LEVEL 0xA9h DAC R LEVEL DAC_R_LEVEL 0xAAh DAC_3D EQ_R CLIP EQ_L CLIP GAIN_R CLIP ADC_R CLIP GAIN_L CLIP ADC_L CLIP DAC EFFECTS PK_DECAY_RATE LIMITER SAMPLE_RATE NOISE_FLOOR DECAY_RATE/RELEASE_RATE HOLDTIME ATTEN FILTER_TYPE 31 EFFECT_LEVEL EFFECT_ MODE www.ti.com LM49350 Address LM49350 Address Register 7 6 5 4 3 2 1 0 0xABh EQ BAND 1 LEVEL FREQ 0xACh EQ BAND 2 Q LEVEL FREQ 0xADh EQ BAND 3 Q LEVEL FREQ 0xAEh EQ BAND 4 Q LEVEL FREQ 0xAFh EQ BAND 5 LEVEL FREQ 0xB0h SOFTCLIP 1 SOFT KNEE 0xB1h SOFTCLIP 2 RATIO 0xB2h SOFTCLIP 3 LEVEL 0xB8h LVLMONL DAC LEFT LEVEL MONITOR 0xB9h LVLMONR DAC RIGHT LEVEL MONITOR 0xBAh FXCLIP SCLP_R CLIP SCLP_L CLIP 0xBBh ALCMONL SCLP_R DISTORT SCLP_L DISTORT DAC LEFT ALC MONITOR 0xBCh ALCMONR SCLP_L DISTORT SCLP_R DISTORT DAC RIGHT ALC MONITOR 0xE0h GPIO TEMP SHORT THRESHOLD DAC EFFECT MONITORS EQ_R CLIP EQ_L CLIP 3D_R CLIP 3D_L CLIP GAIN_R CLIP GAIN_L CLIP GPIO GPIO_RX GPIO_TX GPIO_MODE SPREAD SPECTRUM SS_ DISABLE 0xF1h SS 0xF8h ADC_C0_ LSB ADC_C0_LSB 0xF9h ADC_C0_ MSB ADC_C0_MSB 0xFAh ADC_C1_ LSB ADC_C1_LSB 0xFBh ADC_C1_ MSB ADC_C1_MSB 0xFCh ADC_C2_ LSB ADC_C2_LSB 0xFDh ADC_C2_ MSB ADC_C2_MSB 0xFEh AUX_LINE _OUT ADC COMPENSATION FILTER AUX_LINE _OUT RSVD Unless otherwise specified, the default values of the I2C registers is 0x00h. www.ti.com 32 RSVD RSVD LM49350 16.0 Basic PMC Setup Register This register is used to control the LM49350's Basic Power Management Setup: TABLE 2. PMC_SETUP (0x00h) Bits 0 Field Description CHIP_ENABLE When this bit is set the power management will enable the MCLK I/O or internal oscillator1. It will then use this clock to sequence the enabling of the analog references and bias points. When this bit is cleared the PMC will bring the analog down gently and disable the MCLK or oscillator. CHIP _ENABLE Chip Status 0 Turn Chip Off 1 Turn Chip On This enables the primary PLL 1 PLL1_ENB PLL1_ENABLE PLL1 Status 0 PLL1 Off 1 PLL1 On This enables the secondary PLL 2 PLL2_ENB PLL2_ENABLE PLL2 Status 0 PLL2 Off 1 PLL2 On This enables the internal 300kHz Oscillator. For analog only chip modes, the oscillator can be used instead of an external system clock to drive the chip's power management (PMC). 3 4 OSC_ENB MCLK_OVR OSC_ENABLE Oscillator Status 0 Oscillator Off 1 Oscillator On This forces the MCLK input to enable, regardless of requirement. If set, the audio ports and digital mixer can be activated even if the chip is in shutdown mode. This assumes that MCLK is selected as the clock source and that there is an active clock signal driving the MCLK pin. Setting this bit reduces power consumption, by allowing audio ports and digital mixer to operate while the analog sections of the chip is powered down. MCLK_OVR Comment 0 I/O control is automatic 1 MCLK input forced on. This forces the clock input of Audio Port 1 input to enable, regardless of other port settings. 5 PORT1_CLK_OVR PORT1_CLK_OVR Comment 0 I/O control is automatic 1 PORT_CLK input forced on This forces the clock input of Audio Port 2 input to enable, regardless of other port settings. 6 PORT2_CLK_OVR 7 CHIP_ACTIVE PORT2_CLK_OVR Comment 0 I/O control is automatic 1 PORT_CLK input forced on This bit is used to read back the enable status of the chip. 1. If the PMC is set to operate from one of the audio ports then it will wait for the port to be enabled or the relevant over ride bit to be set, forcing the port clock input to enable. 33 www.ti.com LM49350 17.0 PMC Clocks Register This register is used to control the LM49350's Basic Power Management Setup: TABLE 3. PMC_SETUP (0x01h) Bits Field 1:0 PMC_CLK_SEL Description This selects the source of the PMC input clock. PMC_CLK_SEL PMC Input Clock Source 00 MCLK (Default divide is 40) 01 Internal 300kHz Oscillator 10 DAC SOURCE CLOCK 11 ADC SOURCE CLOCK 18.0 PMC Clock Divide Register This register is used to control the LM49350's Power Management Circuits Clocks: TABLE 4. PMC_SETUP (0x02h) (Default data value is 0x50h) Bits Field 7:0 PMC_CLK_DIV Description This programs the half cycle divider that precedes the PMC. The PMC should run from a 300kHz clock. The default of this divider is 0x50h (divide by 40) to get a 300kHz PMC clock from a 12MHz or 12.288MHz MCLK. Program this divider with the division you want, multiplied by 2, and subtract 1. www.ti.com PMC_CLK_DIV Divide by 00000000 1 00000001 1 00000010 1.5 00000011 2 00000100 2.5 00000101 3 -- -- 11111101 126 11111110 127.5 11111111 128 34 Refer to Figure 14 The audio DAC and ADC operate at a clock frequency of 2*OSR*fS where OSR is the oversampling ratio and fS is the sampling frequency of the DAC or ADC. The DAC can operate at four different OSR settings (128, 125, 64, 32). The ADC can operate at three different OSR settings (128, 125, 64). For example, if the stereo DAC or ADC is set at OSR = 128, a 12.288MHz clock is required for 48kHz data. If a 12.288MHz clock is not available, then one of the LM49350's dual PLLs can be used to generate the desired clock frequency. Otherwise, if a 12.288MHz is available, then the PLL can be bypassed to reduce power consumption. The DAC clock divider (S divider) or ADC clock divider (T divider) can also be used to generate the correct clock. If an 18.432 MHz clock is available, the S or T divider could be set to 1.5 in order to generate a 12.288MHz clock from 18.432MHz without using a PLL. TABLE 5. DAC Clock Requirements DAC Sample Rate (kHz) Clock Required at A (OSR = 128) Clock Required at A (OSR= 125) Clock Required at A (OSR = 64) Clock Required at A (OSR = 32) 8 2.048 MHz 2 MHz 1.024 MHz 0.512 MHz 11.025 2.8224 MHz 2.75625 MHz 1.4112 MHz 0.7056 MHz 12 3.072 MHz 3 MHz 1.536 MHz 0.768 MHz 16 4.096 MHz 4 MHz 2.048 MHz 1.024 MHz 22.05 5.6448 MHz 5.5125 MHz 2.8224 MHz 1.4112 MHz 24 6.144 MHz 6 MHz 3.072 MHz 1.536 MHz 32 8.192 MHz 8 MHz 4.096 MHz 2.048MHz 44.1 11.2896 MHz 11.025 MHz 5.6448 MHz 2.8224 MHz 48 12.288 MHz 12 MHz 6.144 MHz 3.072 MHz 96 24.576 MHz 24 MHz 12.288 MHz 6.144 MHz 192 -- -- 24.576 MHz 12.288 MHz TABLE 6. ADC Clock Requirements ADC Sample Rate (kHz) Clock Required at B (OSR = 128) Clock Required at B (OSR= 125) Clock Required at B (OSR = 64) 8 2.048 MHz 2 MHz 1.024 MHz 11.025 2.8224 MHz 2.75625 MHz 1.4112 MHz 12 3.072 MHz 3 MHz 1.536 MHz 16 4.096 MHz 4 MHz 2.048 MHz 22.05 5.6448 MHz 5.5125 MHz 2.8224 MHz 24 6.144 MHz 6 MHz 3.072 MHz 32 8.192 MHz 8 MHz 4.096 MHz 44.1 11.2896 MHz 11.025 MHz 5.6448 MHz 48 12.288 MHz 12 MHz 6.144 MHz 35 www.ti.com LM49350 The DAC path clock (DAC_SOURCE_CLK) and ADC path clock (ADC_SOURCE_CLK) can be driven directly by the MCLK input, the PORT1_CLK input, the PORT2_CLK input, PLL1's output, or PLL2's output. For instances where a PLL must be used, the PLL input clock can come from three sources. The clock input to PLL1 or PLL2 can come from the MCLK input, the PORT1_CLK input, or the PORT2_CLK input. The LM49350's Power Management Circuit (PMC) requires a clock that is independent from the DAC or ADC. It is recommended to provide a 300kHz clock at Point C. The PMC clock divider (R divider) is available to generate the correct clock to the PMC block. The PMC clock path can be driven directly by the MCLK input, the internal 300kHz oscillator, the DAC_SOURCE_CLK, or the ADC_SOURCE_CLK. 19.0 LM49350 Clock Network LM49350 20194129 FIGURE 14. Internal Clock Network www.ti.com 36 LM49350 20.0 PLL Setup Registers 20194130 FIGURE 15. PLL1 Loop 20194131 FIGURE 16. PLL2 Loop The LM49350 contains two PLLs for flexible operation of its dual audio ports. PLL1 has a P1 and P2 output divider thereby allowing PLL1 to generate two distinct clock outputs. The equations for PLL1's generated output clocks are as follows: fOUT1 = (fIN . N1 / M1 . P1) fOUT2 = (fIN . N1 / M1 . P2) where: N1 = PLL1_N + PLL1_N_MOD M1 = (PLL1_M + 1) / 2 P1 = (PLL1_P1 + 1) / 2 P2 = (PLL1_P2 + 1) / 2 The equations for PLL2's generated output clock are as follows: fOUT3 = (fIN.N2 / M2.P) where: N2 = PLL2_N + PLL2_N_MOD M2 = (PLL2_M + 1) / 2 P = (PLL2_P + 1) / 2 The VCO frequency and comparison frequencies are as follows: fVCO = fOUT.P fCOMP = fIN/M Keep fVCO between 140MHz to 240MHz and keep fCOMP between 700kHz to 5MHz. 37 www.ti.com LM49350 TABLE 7. PLL Settings for Common System Clock Frequencies www.ti.com fIN (MHz) M N N_MOD P fOUT (MHz) 12 2.5 32 0 12.5 12288000 0 13 15.5 175 26 12 12287970 -30 14.4 12.5 128 0 12 12288000 0 16.2 13.5 128 0 12.5 12288000 0 16.8 3.5 32 0 12.5 12288000 0 19.2 12.5 96 0 12 12288000 0 19.68 20.5 160 0 12.5 12288000 0 19.8 16.5 128 0 12.5 12288000 0 27 22.5 128 0 12.5 12288000 0 0 Error (Hz) 12 12.5 147 0 12.5 11289600 12.288 10 147 0 16 11289600 0 13 9 144 19 18.5 11289603 +3 13.5 15.5 213 28 16.5 11289589 -11 14.4 12.5 147 0 15 11289600 0 16.2 22.5 196 0 12.5 11289600 0 16.8 12.5 126 0 15 11289600 0 19.2 20 147 0 12.5 11289600 0 19.68 20.5 147 0 12.5 11289600 0 19.8 27.5 196 0 12.5 11289600 0 27 37.5 196 0 12.5 12289600 0 11.2896 10.5 195 0 17.5 12000000 0 12.288 8 125 0 16 12000000 0 13 6.5 102 0 17 12000000 0 13.5 4.5 68 0 17 12000000 0 14.4 6 85 0 17 12000000 0 16.2 13.5 170 0 17 12000000 0 16.8 7 85 0 17 12000000 0 19.2 8 85 0 17 12000000 0 19.68 20.5 200 0 16 12000000 0 19.8 16.5 170 0 17 12000000 0 11.2896 8 125 0 16 11025000 0 12 10 147 0 16 11025000 0 12.288 8 114 27 16 11025000 0 13 6.5 96 15 17.5 11025000 0 13.5 10 147 0 18 11025000 0 14.4 4 49 0 16 11025000 0 16.2 4 49 0 18 11025000 0 16.8 16 189 0 18 11025000 0 19.2 16 147 0 16 11025000 0 19.68 16 189 0 18 11025000 0 19.8 16 147 0 16.5 11025000 0 38 LM49350 TABLE 8. PLL_CLOCK_SOURCE (0x03h) Bits Field 1:0 PLL1_CLK_SEL Description This selects the source of the input clock to PLL1 PLL1_CLK_SEL PLL1 Input Clock Source 00 MCLK 01 PORT1_CLK 10 PORT2_CLK 11 RESERVED TABLE 9. PLL1_M (0x04h) Bits Field 6:0 PLL1_M Description This programs the PLL1 M divider to divide from 1 to 64. PLL1_M PLL1 Input Divider Vaue 000000 1 000001 1 000010 1.5 000011 2 000100 2.5 000101 3 -- -- 1111101 63 1111110 63.5 1111111 64 TABLE 10. PLL1_N (0x05h) Bits Field 7:0 PLL1_N Description This programs the PLL1 N divider to divide from 1 to 250. PLL1_N Feedback Divider Value 00000000 to 00001010 10 00001011 11 00001100 12 00001101 13 00001110 14 00001111 15 -- -- 11111000 248 11111001 249 11111010 to 11111111 250 39 www.ti.com LM49350 TABLE 11. PLL1_N_MOD (0x06h) Bits Field 4:0 PLL1_N_MOD Description This programs the sigma-delta modulator in PLL1 PLL1_N_MOD Fractional Part of N 00000 0 00001 1/32 00010 2/32 00011 3/32 00100 4/32 00101 5/32 -- -- 11101 20/32 11110 30/32 11111 31/32 5 PLL1_P1[8] This sets the MSB of the 1st P Divider on PLL1 which is part of a standard half-cycle divider control. 6 PLL1_P2[8] This sets the MSB of the 2nd P Divider on PLL1 which is part of a standard half-cycle divider control. TABLE 12. PLL1_P1 (0x07h) Bits Field Description 7:0 PLL1_P1[7:0] This programs the 8 LSBs of the PLL1's P1 Divider. These LSBs combine with PLL1_P1[8] which allows the P1 divider to divide by up to 256 PLL1_P1 P1 Divider Value 000000000 1 000000001 1 000000010 1.5 000000011 2 000000100 2.5 000000101 3 -- -- 111111101 255 111111110 255.5 111111111 256 TABLE 13. PLL1_P2 (0x08h) Bits Field Description 7:0 PLL1_P2[7:0] This programs 8 LSBs of PLL1's P2 Divider. These LSBs combine with PLL1_P2[8] which allows the P2 divider to divide by up to 256 www.ti.com PLL1_P2 P2 Divider Value 000000000 1 000000001 1 000000010 1.5 000000011 2 000000100 2.5 000000101 3 -- -- 111111101 255 111111110 255.5 111111111 256 40 LM49350 TABLE 14. PLL2_M (0x09h) Bits Field 6:0 PLL2_M Description This programs the PLL2 M divider to divide from 1 to 64. PLL2_M PLL2 Input Divider Value 0000000 1 0000001 1 0000010 1.5 0000011 2 0000100 2.5 0000101 3 -- -- 1111101 63 0000010 63.5 1111111 64 TABLE 15. PLL2_N (0x0Ah) Bits Field 7:0 PLL2_N Description This programs PLL2's N divider to divide from 10 to 250. PLL2_N Comment 00000000 to 00001010 10 00001011 11 00001100 12 00001101 13 00001110 14 00001111 15 -- -- 11111000 248 11111001 249 11111010 to 11111111 250 TABLE 16. PLL2_N_MOD (0x0Bh) Bits Field 4:0 PLL2_N_MOD 5 PLL2_P[8] Description This programs the sigma-delta modulator in PLL2 PLL2_N_MOD Fractional Part of N 00000 0 00001 1/32 00010 2/32 00011 3/32 00100 4/32 00101 5/32 -- -- 11101 29/32 11110 30/32 11111 31/32 This is the MSB of the P Divider on PLL2. 41 www.ti.com LM49350 TABLE 17. PLL2_P (0x0Ch) Bits Field 7:0 PLL2_P[7:0] www.ti.com Description This programs the 8 LSBs of PLL2's P Divider. These LSBs combine with PLL2_P[8] which allows the P divider to divide by up to 256 PLL2_P P Divides by 000000000 1 000000001 1 000000010 1.5 000000011 2 000000100 2.5 000000101 3 -- -- 111111101 255 111111110 255.5 111111111 256 42 LM49350 21.0 Analog Mixer Control Registers This register is used to control the LM49350's Analog Mixer: TABLE 18. CLASS_D_OUTPUT (0x10h) Bits Field Description 0 DACR_LS The right DAC output is added to the loudspeaker output. 1 DACL_LS The left DAC output is added to the loudspeaker output. 2 MICR_LS The right MIC input is added to the loudspeaker output. Setting this bit enables MIC BIAS. 3 MICL_LS The left MIC input is added to the loudspeaker output. Setting this bit enables MIC BIAS. 4 AUXR_LS The right AUX input is added to the loudspeaker output. 5 AUXL_LS The left AUX input is added to the loudspeaker output. signal. Sub-sonic (DC) and super-sonic components (>22kHz) are not useful. The difference between the power flowing from the power supply and the audio band power being transduced is dissipated in the LM49350 and in the transducer load. The amount of power dissipation in the LM49350's class D amplifier is very low. This is because the ON resistance of the switches used to form the output waveforms is typically less than 0.25. This leaves only the transducer load as a potential "sink" for the small excess of input power over audio band output power. The LM49350 dissipates only a fraction of the excess power requiring no additional PCB area or copper plane to act as a heat sink. 21.1 CLASS D LOUDSPEAKER AMPLIFIER The LM49350 features a filterless modulation scheme. The differential outputs of the device switch at 300kHz from VDD to GND. When there is no input signal applied, the two outputs (LS+ and LS-) switch with a 50% duty cycle, with both outputs in phase. Because the outputs of the LM49350 are differential, the two signals cancel each other. This results in no net voltage across the speaker, thus there is no load current during an idle state, conserving power. With an input signal applied, the duty cycle (pulse width) of the LM49350 outputs changes. For increasing output voltages, the duty cycle of LS+ increases, while the duty cycle of LS- decreases. For decreasing output voltages, the converse occurs, the duty cycle of LS- increases while the duty cycle of LS+ decreases. The difference between the two pulse widths yields the differential output voltage. 21.3.1 EMI/RFI Filtering If system level PCB layout constraints require the LM49350's Class D output bumps to be placed far away from the speaker or the Class D output traces to be routed near EMI/RFI sensitive components, an external EMI/RFI filter should be used. A series ferrite bead placed close to the Class D output bumps along with a shunt capacitor to ground placed close to the ferrite bead will reduce the EMI/RFI emissions of the Class D amplifier's switching outputs. The ferrite bead must be rated with a current rating high enough to properly drive the loudspeaker. The ferrite bead that is rated for 1A or greater is recommended. The DC resistance of the ferrite bead is another important specification that must be taken into consideration. A low DC resistance will minimize any power losses dissipated by the EMI/RFI filter thereby preserving the power efficiency advantages of the Class D amplifier. Selecting a ferrite bead with high DC resistance will decrease output power delivered to speaker and reduce the Class D amplifier's efficiency. The shunt capacitor needs to have low ESR. A 10pF ceramic capacitor with a X7R dielectric is recommended as a starting point. Care needs to be taken to ensure that the value of the shunt capacitor does not exceed 47pF when using a low resistance ferrite bead in order to prevent permanent damage to the low side FETs of the Class D output stage. 21.2 SPREAD SPECTRUM MODULATION The LM49350 features a fitlerless spread spectrum modulation scheme that eliminates the need for output filters, ferrite beads or chokes. The switching frequency varies by 30% about a 300kHz center frequency, reducing the wideband spectral content, improving EMI emissions radiated by the speaker and associated cables and traces. Where a fixed frequency class D exhibits large amounts of spectral energy at multiples of the switching frequency, the spread spectrum architecture of the LM49350 spreads that energy over a larger bandwidth. The cycle-to-cycle variation of the switching period does not affect the audio reproduction or efficiency. 21.3 CLASS D POWER DISSIPATION AND EFFICIENCY In general terms, efficiency is considered to be the ratio of useful work output divided by the total energy required to produce it with the difference being the power dissipated, typically, in the IC. The key here is "useful" work. For audio systems, the energy delivered in the audible bands is considered useful including the distortion products of the input 43 www.ti.com LM49350 20194110 FIGURE 17. EMI/RFI Filter for the Class D Amplifier TABLE 19. LEFT HEADPHONE_OUTPUT (0x11h) Bits Field 0 DACR_HPL The right DAC output is added to the left headphone output. Description 1 DACL_HPL The left DAC output is added to the left headphone output. 2 MICR_HPL The right MIC input is added to the left headphone output. Setting this bit enables MIC BIAS. 3 MICL_HPL The left MIC input is added to the left headphone output. Setting this bit enables MIC BIAS. 4 AUXR_HPL The right AUX input is added to the left headphone output. 5 AUXL_HPL The left AUX input is added to the left headphone output. TABLE 20. RIGHT HEADPHONE_OUTPUT (0x12h) Bits Field 0 DACR_HPR The right DAC output is added to the right headphone output. Description 1 DACL_HPR The left DAC output is added to the right headphone output. 2 MICR_HPR The right MIC input is added to the right headphone output. Setting this bit enables the MIC BIAS output. 3 MICL_HPR The left MIC input is added to the right headphone output. Setting this bit enables the MIC BIAS output. 4 AUXR_HPR The right AUX input is added to the right headphone output. 5 AUXL_HPR The left AUX input is added to the right headphone output. 21.4 HEADPHONE AMPLIFIER FUNCTION The LM49350 headphone amplifier features National's ground referenced architecture that eliminates the large DCblocking capacitors required at the outputs of traditional headphone amplifiers. A low-noise inverting charge pump creates a negative supply (HP_VSS) from the positive supply voltage (LS_VDD). The headphone amplifiers operate from these bipolar supplies, with the amplifier outputs biased about GND, instead of a nominal DC voltage (typically VDD/2), like traditional amplifiers. Because there is no DC component to the headphone output signals, the large DC-blocking capacitors (typically 220F) are not necessary, conserving board space and system cost, while improving frequency response. 21.6 CHARGE PUMP FLYING CAPACITOR (C6) The flying capacitor (C6) affects the load regulation and output impedance of the charge pump. A C6 value that is too low results in a loss of current drive, leading to a loss of amplifier headroom. A higher valued C6 improves load regulation and lowers charge pump output impedance to an extent. Above 2.2F, the RDS(ON) of the charge pump switches and the ESR of C6 and C5 dominate the output impedance. A lower value capacitor can be used in systems with low maximum output power requirements. Please refer to the demonstration board schematic shown in Figure 26. 21.7 CHARGE PUMP FLYING CAPACITOR (C5) The value and ESR of the hold capacitor (C5) directly affects the ripple on CPVSS. Increasing the value of C5 reduces output ripple. Decreasing the ESR of C5 reduces both output ripple and charge pump output impedance. A lower value capacitor can be used in systems with low maximum output 21.5 CHARGE PUMP CAPACITOR SELECTION Use low ESR ceramic capacitors (less than 100m) for optimum performance. www.ti.com 44 LM49350 power requirements. Please refer to the demonstration board schematic shown in Figure 26. TABLE 21. AUX_OUTPUT (0x13h) Bits Field Description 0 DACR_AUX The right DAC output is added to the AUX output. 1 DACL_AUX The left DAC output is added to the AUX output. 2 MICR_AUX The right MIC input is added to the AUX output. Setting this bit enables the MIC BIAS output. 3 MICL_AUX The left MIC input is added to the AUX output. Setting this bit enables the MIC BIAS output. 4 AUXR_AUX The right AUX input is added to the AUX output. 5 AUXL_AUX The left AUX input is added to the AUX output. amplifier which then isolates it from any ground noise, thereby improving signal to noise ratio (SNR) and power supply rejection ratio (PSRR). The AUXOUT amplifier has two modes of operation. The primary mode of operation is high current drive mode (Earpiece Mode) where the AUXOUT amplifier can be used to differentially drive a mono earpiece speaker. The secondary mode of operation is low current drive mode where the AUXOUT amplifier operates in a power saving mode (AUX_LINE_OUT Mode) to provide a differential output that is used as a mono differential line level input to a standalone mono differential input class D amplifier (LM4675) for stereo loudspeaker applications. 21.8 AUXILIARY OUTPUT AMPLIFIER The LM49350's auxiliary output (AUXOUT) amplifier provides differential drive capability to loads that are connected across its outputs. This results in output signals at the AUX_OUT+ and AUX_OUT- pins that are 180 degrees out of phase with respect to each other. This effectively doubles the maximum possible output swing for a specific supply voltage when compared to single-ended output configurations. The differential output configuration also allows the load to be isolated from ground since both the AUX_OUT+ and AUX_OUT- pins are biased at the same DC potential. This eliminates the need for any large and expensive DC blocking capacitors at the AUXOUT amplifier outputs. The load can then be directly connected to the positive and negative outputs of the AUXOUT TABLE 22. OUTPUT_OPTIONS (0x14h) Bits Field 0 EPMODE Description 1 HP_NEG_6dB If set, both HPL and HPR are attenuated by 6dB. This is useful when adding stereo signals that need more headroom due to being highly correlated. 2 LS_NEG_6dB If set the class D output is attenuated by 6dB. This is useful when adding stereo signals that need more headroom due to being highly correlated. 3 AUX_NEG_6dB If set the AUX output is attenuated by 6dB. This is useful when adding stereo signals that need more headroom due to being highly correlated. 4 CP_FORCE If set, a -LS_VDD rail will be created on HP_VSS, even if the HP output stage is not required. If set the HPR output is driven with the negative input of the HPL output stage. TABLE 23. ADC_INPUT (0x15h) Bits Field 0 DACR_ADCR The right DAC output is added to the ADC right input. Description 1 DACL_ADCL The left DAC output is added to the ADC left input. 2 MICR_ADCR The right MIC input is added to the ADC right input. Setting this bit enables MIC BIAS. 3 MICL_ADCL The left MIC input is added to the ADC left input. Setting this bit enables MIC BIAS. 4 AUXR_ADCR The right AUX input is added to the ADC right input. 5 AUXL_ADCL The left AUX input is added to the ADC left input. 45 www.ti.com LM49350 TABLE 24. MIC_L_INPUT (0x16h) Bits Field 3:0 MIC_L_LEVEL Description This sets the gain of the left microphone preamp. MIC_L_LEVEL Gain 0000 6dB 0001 8dB 0010 10dB 0011 12dB 0100 14dB 0101 16dB 0110 18dB 0111 20dB 1000 22dB 1001 24dB 1010 26dB 1011 28dB 1100 30dB 1101 32dB 1110 34dB 1111 36dB 4 SE_DIFF If set, the MIC_L negative input is ignored. 5 MUTE If set, the left microphone preamp is muted. TABLE 25. MIC_R_INPUT (0x17h) Bits Field 3:0 MIC_R_LEVEL 4 SE_DIFF 5 MUTE www.ti.com Description This sets the gain of the right microphone preamp. MIC_R_LEVEL Gain 0000 6dB 0001 8dB 0010 10dB 0011 12dB 0100 14dB 0101 16dB 0110 18dB 0111 20dB 1000 22dB 1001 24dB 1010 26dB 1011 28dB 1100 30dB 1101 32dB 1110 34dB 1111 36dB If set, the MIC_R negative input is ignored. If set, the right microphone preamp is muted. 46 LM49350 TABLE 26. AUX_L_INPUT (0x18h) Bits 5:0 6 Field Description AUX_L_LEVEL This programs the left AUX input level. All gain changes are performed at zero crossings. AUX_L_LEVEL Level AUX_L_LEVEL Level 000000 -46.5dB 100000 1.5dB 000001 -45dB 100001 3dB 000010 -43.5dB 100010 4.5dB 000011 -42dB 100011 6dB 000100 -40.5dB 100100 7.5dB 000101 -39dB 100101 9dB 000110 -37.5dB 100110 10.5dB 000111 -36dB 100111 12dB 001000 -34.5dB 101000 12dB 001001 -33dB 101001 12dB 001010 -31.5dB 101010 12dB 001011 -30dB 101011 12dB 001100 -28.5dB 101100 12dB 001101 -27dB 101101 12dB 001110 -25.5dB 101110 12dB 001111 -24dB 101111 12dB 010000 -22.5dB 110000 12dB 010001 -21dB 110001 12dB 010010 -19.5dB 110010 12dB 010011 -18dB 110011 12dB 010100 -16.5dB 110100 12dB 010101 -15dB 110101 12dB 010110 -13.5dB 110110 12dB 010111 -12dB 110111 12dB 011000 -10.5dB 111000 12dB 011000 -9dB 111001 12dB 011001 -7.5dB 111010 12dB 011010 -6dB 111011 12dB 011100 -4.5dB 111100 12dB 011101 -3dB 111101 12dB 011110 -1.5dB 111110 12dB 011111 0dB 111111 12dB FROM_LINE_L If set, the LEFT_MIC/LINE differential input is routed to the AUX_L input amplifier for line level volume control. This bit overrides the DIFF_MODE (bit 7 of 0x19h) setting. 47 www.ti.com LM49350 TABLE 27. AUX_R_INPUT (0x19h) Bits 5:0 6 7 www.ti.com Field Description AUX_R_LEVEL This programs the right AUX input level. All gain changes are performed at zero crossings. AUX_R_LEVEL Level AUX_R_LEVEL Level 000000 -46.5dB 100000 1.5dB 000001 -45dB 100001 3dB 000010 -43.5dB 100010 4.5dB 000011 -42dB 100011 6dB 000100 -40.5dB 100100 7.5dB 000101 -39dB 100101 9dB 000110 -37.5dB 100110 10.5dB 000111 -36dB 100111 12dB 001000 -34.5dB 101000 12dB 001001 -33dB 101001 12dB 001010 -31.5dB 101010 12dB 001011 -30dB 101011 12dB 001100 -28.5dB 101100 12dB 001101 -27dB 101101 12dB 001110 -25.5dB 101110 12dB 001111 -24dB 101111 12dB 010000 -22.5dB 110000 12dB 010001 -21dB 110001 12dB 010010 -19.5dB 110010 12dB 010011 -18dB 110011 12dB 010100 -16.5dB 110100 12dB 010101 -15dB 110101 12dB 010110 -13.5dB 110110 12dB 010111 -12dB 110111 12dB 011000 -10.5dB 111000 12dB 011000 -9dB 111001 12dB 011001 -7.5dB 111010 12dB 011010 -6dB 111011 12dB 011100 -4.5dB 111100 12dB 011101 -3dB 111101 12dB 011110 -1.5dB 111110 12dB 011111 0dB 111111 12dB FROM_LINE_R If set, the RIGHT_MIC/LINE differential input is routed to the AUX_R input amplifier for line level volume control. This bit overrides the DIFF_MODE (bit 7) setting. DIFF_MODE If set, the stereo single-ended inputs AUX_L and AUX_R convert to a mono differential input pair MONO_IN + and MONO_IN-. (MONO_IN+) - (MONO_IN-) is routed to the AUX_L input amplifier. (MONO_IN-) - (MONO_IN+) is routed to the AUX_R input amplifier. (unless overriden by the respective FROM_LINE bits). 48 LM49350 22.0 ADC Control Registers This register is used to control the LM49350's ADC: TABLE 28. ADC Basic (0x20h) Bits Field 0 MONO Description This sets mono or stereo operation of the ADC. MONO 1 OSR ADC Operation 0 Stereo Audio 1 Mono Voice (Right ADC channel disabled, Left ADC channel active) This sets the oversampling ratio of the ADC. OSR Stereo Audio ADC Oversampling Ratio Mono Voice ADC Oversampling Ratio 0 128 125 1 64 128 2 MUTE_L If set, a digital mute is applied to the Left (or mono) ADC output. 3 MUTE_R If set, a digital mute is applied to the Right ADC output. 6.4 ADC_CLK_SEL This selects the source of the ADC clock domain, ADC_SOURCE_CLK. ADC_CLK_SEL 7 ADC_DSP_ONLY Source 000 MCLK 001 PORT1_RX_CLK 010 PORT2_RX_CLK 011 PLL1_OUTPUT2 100 PLL2_OUTPUT If set the ADC's analog circuitry is disabled to reduce power consumption, however, ADC DSP functionality is maintained. This can be used to perform asyncronous resampling between audio rates of a common family. Setting this bit is also useful whenever applying Automatic Level Control (ALC) to an analog only audio path. 49 www.ti.com LM49350 TABLE 29. ADC_CLK_DIV (0x21h) Bits Field 7:0 ADC_CLK_DIV Description This programs the half cycle divider that preceeds the ADC. The input of this divider should be around 12MHz. The default of this divider is 0x00. Program this divider with the division you want, multiplied by 2, and subtract 1. ADC_CLK_DIV Divides by 00000000 1 00000001 1 00000010 1.5 00000011 2 -- -- 11111101 127 11111110 127.5 11111111 128 TABLE 30. ADC TRIM (0x22h) Bits Field 7:0 ADC_TRIM Description If set, the ADC is compensated with recommended compensation filter coefficients. The recommended ADC compensation filter coefficients are programmed as follows: Register 0xF8h set to 0x00h Register 0xF9h set to 0x01h Register 0xFAh set to 0x96h Register 0xFBh set to 0xFBh Register 0xFCh set to 0x30h Register 0xFDh set to 0x62h www.ti.com 50 LM49350 23.0 DAC Control Registers This register is used to control the LM49350's DAC: TABLE 31. DAC Basic (0x30h) Bits Field 1:0 MODE Description This programs the over sampling ratio of the stereo DAC. MODE DAC Oversampling Ratio 00 125 01 128 10 64 11 32 2 MUTE_L This digitally mutes the Left DAC output. 3 MUTE_R This digitally mutes the Right DAC output. 6:4 DAC_CLK_SEL 7 DSP_ONLY This selects the source of the DAC clock domain, DAC_SOURCE_CLK. DAC_CLK_SEL Source 000 MCLK 001 PORT1_RX_CLK 010 PORT2_RX_CLK 011 PLL1_OUTPUT1 100 PLL2_OUTPUT If set, the DAC's analog circuitry is disabled to reduce power consumption, however DAC DSP functionality is maintained. This can be used to perform asyncronous resampling between audio rates of a common family. TABLE 32. DAC_CLK_DIV (0x31h) Bits Field 7:0 DAC_CLK_DIV Description This programs the half cycle divider that precedes the DAC. The input of this divider should be around 12MHz. The default of this divider is 0x00. Program this divider with the division you want, multiplied by 2, and subtract 1. DAC_CLK_DIV Divides by 00000000 1 00000001 1 00000010 1.5 00000011 2 -- -- 11111101 127 11111110 127.5 11111111 128 51 www.ti.com LM49350 output to the ADC decimator input which allows the DAC and ADC DSP blocks to be cascaded without having to enable the analog of the DAC and ADC inorder to save power. Another key feature of the digital mixer is sample rate conversion (SRC) between audio ports. This allows simultaneous operation of the dual audio ports even if each port is operating at a different sample rate. The LM49350 can be used as an audio port bridge with SRC capability. The digital mixer allows either straight pass through between audio ports or, if desired, DSP effects can be added to the digital audio signal during audio port bridge operation. The digital mixer automatically handles stereo I2S to mono PCM conversion between audio ports and vice versa. 24.0 Digital Mixer Control Registers 24.1 DIGITAL MIXER The LM49350's digital mixer allows for flexible routing of digital audio signals between both audio ports, DAC, and ADC. This mixer handles which digital data path (Port1 RX data, Port2 RX data, or ADC output) is routed to the DAC input. The digital mixer also selects the appropriate digital data path [Port1 RX data, Port2 RX data, ADC output, or DAC DSP (Interpolator)] output that is used for data transmission on Audio Port 1 and 2. Audio inputs to the digital mixer can be attenuated down to -18dB to avoid clipping conditions. The digital mixer also allows direct routing from the DAC interpolator 20194137 FIGURE 18. Digital Mixer The LM49350 includes two separate and independent DSP blocks, one for the DAC and the other for the ADC. The digital mixer also allows both DSP blocks to be cascaded together in either order so that the DSP effects from both blocks can www.ti.com be combined into the same signal path. For example, the 5 band parametric EQ of each DSP block can be combined together to form a 10 band parametric EQ for added flexibility. 52 LM49350 This register is used to control the LM49350's digital mixer: TABLE 33. Input Levels 1 (0x40h) Bits Field 1:0 PORT1_RX_L _LVL 3:2 5:4 7:6 PORT1_RX_R _LVL PORT2_RX_L _LVL PORT2_RX_R _LVL Description This programs the input level of the data arriving from the left receive channel of Audio Port 1. PORT1_RX_L_LVL Level 00 0dB 01 -6dB 10 -12dB 11 -18dB This programs the input level of the data arriving from the right receive channel of Audio Port 1. PORT1_RX_R_LVL Level 00 0dB 01 -6dB 10 -12dB 11 -18dB This programs the input level of the data arriving from the left receive channel of Audio Port 2. PORT2_RX_L_LVL Level 00 0dB 01 -6dB 10 -12dB 11 -18dB This programs the input level of the data arriving from the right receive channel of Audio Port 2. PORT2_RX_R_LVL Level 00 0dB 01 -6dB 10 -12dB 11 -18dB TABLE 34. Input Levels 2 (0x41h) Bits Field 1:0 ADC_L_LVL Description This programs the input level of the data arriving from the left ADC channel. ADC_L_LVL 3:2 5:4 ADC_R_LVL INTERP_L_LVL Level 00 0dB 01 -6dB 10 -12dB 11 -18dB This programs the input level of the data arriving from the right ADC channel. ADC_R_LVL Level 00 0dB 01 -6dB 10 -12dB 11 -18dB This programs the input level of the data arriving from the left DAC's interpolator output. INTERP_L_LVL Level 00 0dB 01 -6dB 10 -12dB 11 -18dB 53 www.ti.com LM49350 Bits Field 7:6 INTERP_R_LVL Description This programs the input level of the data arriving from the right DAC's interpolator output. INTERP_R_LVL Level 00 0dB 01 -6dB 10 -12dB 11 -18dB TABLE 35. Audio Port 1 Input (0x42h) Bits Field 1:0 L_SEL Description This selects which input is fed to the Left TX Channel of Audio Port 1. L_SEL 3:2 R_SEL Selected Input 00 None 01 ADC_L 10 PORT2_RX_L 11 DAC_INTERP_L This selects which input is fed to the Right TX Channel of Audio Port 1. R_SEL Selected Input 00 None 01 ADC_R 10 PORT2_RX_R 11 DAC_INTERP_R 4 SWAP If set, this swaps the Left and Right outputs to Audio Port 1. The swap bit can be used to control which microphone is being used for audio port transmit. For example, if LEFT_MIC is used as a primary handset microphone and RIGHT_MIC is used a headset microphone, the SWAP bit allows the audio port to select one of the microphones at a time for audio port transmit via the ADC. 5 MONO If set, the right channel is ignored and the left channel becomes (left+right)/2. TABLE 36. Audio Port 2 Input (0x43h) Bits Field 1:0 L_SEL 3:2 R_SEL Description This selects which input is fed to Audio Port 2's Left TX Channel. L_SEL Selected Input 00 None 01 ADC_L 10 PORT1_RX_L 11 DAC_INTERP_L This selects which input is fed to Audio Port 2's Right TX Channel. R_SEL Selected Input 00 None 01 ADC_R 10 PORT1_RX_R 11 DAC_INTERP_R 4 SWAP If set, this swaps the Left and Right outputs to Audio Port 2. The swap bit can be used to control which microphone is being used for audio port transmit. For example, if LEFT_MIC is used as a primary handset microphone and RIGHT_MIC is used a headset microphone, the SWAP bit allows the audio port to select one of the microphones at a time for audio port transmit via the ADC. 5 MONO If set, the right channel is ignored and the left channel becomes (left+right)/2. www.ti.com 54 LM49350 TABLE 37. DAC Input Select (0x44h) Bits Field Description 0 PORT1_L This adds Audio Port 1's left RX channel to the DAC's left input. 1 PORT2_L This adds Audio Port 2's left RX channel to the DAC's left input. 2 ADC_L 3 PORT1_R This adds Audio Port 1's right RX channel to the DAC's right input. 4 PORT2_R This adds Audio Port 2's right RX channel to the DAC's right input. 5 ADC_R This adds the ADC's right output to the DAC's right input. 6 SWAP If set, this swaps the Left and Right inputs to the DAC. This adds the ADC's left output to the DAC's left input TABLE 38. Decimator Input Select (0x45h) Bits Field 1:0 L_SEL Description This selects which input is fed to the left ADC's decimator input. L_SEL 3:2 R_SEL Selected Input 00 None 01 PORT1_RX_L 10 PORT2_RX_L 11 DAC_INTERP_L This selects which input is fed to the right ADC's decimator input. R_SEL 5:4 MXR_CLK_SEL Selected Input 00 None 01 PORT1_RX_R 10 PORT2_RX_R 11 DAC_INTERP_R This selects sets the source of the Digital Mixer Clock. The 'Auto' setting will automatically select the source with the highest clock frequency. Whenever the DAC interpolator (DAC_OSR_L or DAC_OSR_R) is selected then MXR_CLK_SEL should be set to '10'. MXR_CLK_SEL Selected Input 00 Auto 01 MCLK 10 DAC 11 ADC 55 www.ti.com LM49350 25.0 Audio Port Control Registers 20194171 FIGURE 19. I2S Serial Data Format (24 bit example) 20194172 FIGURE 20. Left Justified Data Format (24 bit example) 20194170 FIGURE 21. Right Justified Data Format (24 bit example) 20194134 FIGURE 22. PCM Serial Data Format (16 bit example) www.ti.com 56 TABLE 39. BASIC_SETUP (0x50h/0x60h) Bits Field 0 STEREO Description 1 RX_ENABLE If set the input is enabled (enables the SDI port and input shift register and any clock generation required). 2 TX_ENABLE If set the output is enabled (enables the SDO port and output shift register and any clock generation required). 3 CLOCK_MS If set the audio port will transmit the clock when either the RX or TX is enabled. 4 SYNC_MS If set, the audio port will receive and transmit stereo data. If set the audio port will transmit the sync signal when either the RX or TX is enabled. This sets how data is clocked by the Audio Port. 5 CLOCK_PHASE CLOCK_PHASE Audio Data Mode 0 I2S (TX on falling edge, RX on rising edge) 1 PCM (TX on rising edge, RX on falling edge) If set, this reverses the left and right channel data of the Audio Port. 6 STEREO_SYNC_PHASE STEREO_SYNC_PHASE Audio Port Data Orientation 0 Left channel data goes to left channel output. Right channel data goes to right channel output. 1 Right channel data goes to left channel output. Left channel data goes to right channel output. If this bit is set the SYNC is inverted before the receiver and transmitter. 7 SYNC_INVERT SYNC_INVERT Sync Orientation 0 SYNC Low = Left, SYNC High = Right 1 SYNC Low = Right, SYNC High = Left TABLE 40. CLK_GEN_1 (0x51h/0x61h) Bits 5:0 6 Field Description HALF_CYCLE_CLK_ This programs the half-cycle divider that generates the master clocks in the audio port. The input DIV of this divider should be around 12MHz. The default of this divider is 0x00, i.e. bypassed. Program this divider with the division you want, multiplied by 2, and subtract 1. CLOCK_SEL HALF_CYCLE_CLK_DIV Divides By 000000 BYPASS 000001 1 000010 1.5 000011 2 -- -- 111101 31 111110 31.5 11111 32 This selects the clock source of the master mode Audio Port Clock generator's half-cycle divider. 0 = DAC_SOURCE_CLK 1 = ADC_SOURCE_CLK 57 www.ti.com LM49350 The following registers are used to control the LM49350's audio ports. Audio Port 1 and Audio Port 2 are identical. Port 1 is programmed through the (0x5Xh) registers. Port 2 is programmed through the (0x6Xh) registers. LM49350 TABLE 41. CLK_GEN_1 (0x52h/62h) Bits Field 2:0 SYNTH_NUM 3 SYNTH_DENOM Description Along with SYNTH_DENOM, this sets the clock divider that generates the Port 1 or Port 2 clock in master mode. SYNTH_NUM Numerator 000 SYNTH_DENOM (1/1) 001 100/SYNTH_DENOM 010 96/SYNTH_DENOM 011 80/SYNTH_DENOM 100 72/SYNTH_DENOM 101 64/SYNTH_DENOM 110 48/SYNTH_DENOM 111 0/SYNTH_DENOM Along with SYNTH_NUM, this sets the clock divider that generates the Port 1 or Port 2 clock in master mode. SYNTH_DENOM Denominator 0 128 1 125 TABLE 42. CLK_GEN_1 (0x53h/63h) Bits Field Description 2:0 SYNC_RATE This sets the number of clock cycles before the sync pattern repeats. This depends if the audio port data is mono or stereo. In MONO mode: SYNC_RATE Number of Clock Cycles 000 8 001 12 010 16 011 18 100 20 101 24 110 25 111 32 In STEREO mode: www.ti.com SYNC_RATE Number of Clock Cycles 000 16 001 24 010 32 011 36 100 40 101 48 110 50 111 64 58 Field 5:3 SYNC_WIDTH LM49350 Bits Description In MONO mode, this programs the width (in number of bits) of the SYNC signal. SYNC_WIDTH Width of SYNC (in bits) 000 1 001 2 010 4 011 7 100 8 101 11 110 15 111 16 TABLE 43. DATA_WIDTHS (0x54h/64h) Bits Field 2:0 RX_WIDTH 5:3 7:6 TX_WIDTH TX_EXTRA_BITS Description This programs the expected bits per word of the serial data input SDI. RX_WIDTH Bits 000 24 001 20 010 18 011 16 100 14 101 13 110 12 111 8 This programs the bits per word of the serial data output SDO. TX_WIDTH Description 000 24 001 20 010 18 011 16 100 14 101 13 110 12 111 8 This programs the TX data output padding. TX_EXTRA_BITS Description 00 0 01 1 10 High-Z 11 High-Z 59 www.ti.com LM49350 TABLE 44. RX_MODE (0x55h/65h) Bits Field 0 RX_MODE 5:1 MSB_POSITION Description This sets the RX data input justification with respect to the SYNC signal. RX_MODE Description 0 MSB Justified 1 LSB Justified This specifies the bit location of the MSB from the start of the frame (MSB Justified) or from the end of the frame (LSB Justified). MSB_POSITION Description 00000 0(Left Justified/PCM Long) 00001 1(I2S/PCM Short) 00010 2 00011 3 00100 4 00101 5 00110 6 00111 7 01000 8 01001 9 01010 10 01011 11 01100 12 01101 13 01110 14 01111 15 10000 16 10001 17 10010 18 10011 19 10100 20 10101 21 10110 22 10111 23 11000 24 11001 25 11010 26 11011 27 11100 28 11101 29 11110 30 11111 31 6 COMPAND If set, audio data will be companded. 7 Law/A-Law This sets the audio companding mode. Law/A-Law www.ti.com Compand Mode 0 Law 1 A-Law 60 LM49350 TABLE 45. TX_MODE (0x56h/x66h) Bits Field 0 TX_MODE 5:1 MSB_POSITION Description This sets the TX data output justification with respect to the SYNC signal. TX_MODE Description 0 MSB Justified 1 LSB Justified This specifies the bit location of the MSB from the start of the frame (MSB Justified) or from the end of the frame (LSB Justified). MSB_POSITION Description 00000 0(Left Justified/PCM Long) 00001 1(I2S/PCM Short) 00010 2 00011 3 00100 4 00101 5 00110 6 00111 7 01000 8 01001 9 01010 10 01011 11 01100 12 01101 13 01110 14 01111 15 10000 16 10001 17 10010 18 10011 19 10100 20 10101 21 10110 22 10111 23 11000 24 11001 25 11010 26 11011 27 11100 28 11101 29 11110 30 11111 31 6 COMPAND If set, audio data will be companded. 7 Law/A-Law This sets the audio companding mode. Law/A-Law Compand Mode 0 Law 1 A-Law 61 www.ti.com LM49350 quality digital audio effects engine. The data paths on each DSP engine are 24 bits wide for ultimate flexibility. Both DSP engines feature digital volume control, automatic level control (ALC), digital soft clip compression, and a 5-band parametric EQ. The ADC DSP engine adds a dedicated high-pass filter to reduce wind noise or pop noise during uplink. The DAC DSP engine adds a digital 3D algorithm that allows for stereo widening of the original audio signal. The effects chain of each DSP engine is shown by the diagrams below. 26.0 Digital Effects Engine 26.1 DIGITAL SIGNAL PROCESSOR (DSP) The LM49350 is designed to handle the entire audio signal conditioning and processing within the audio system, thereby freeing up the workload of any other applications processor contained within the system. The LM49350 features two independent DSPs, one for the DAC and the other for the ADC. Each DSP is fully featured and performs as a professional 20194135 FIGURE 23. ADC DSP Effects Chain 20194136 FIGURE 24. DAC DSP Effects Chain The ADC and DAC DSP engines can be cascaded together in any order via the digital mixer to combine different audio effects to the same signal path. For example, a signal can be processed with high-pass filtering from the ADC effects engine with 3D stereo widening from the DAC effects engine. The 5-band parametric EQs from each DSP engine can be combined to form a single 10-band parametric EQ or a single 5-band parametric EQ with 30dB (instead of 15dB) gain control for each band. TABLE 46. ADC EFFECTS (0x70h) Bits Field Description 0 ADC_HPF_ENB This enables the ADC's High Pass Filter. 1 ADC_ALC_ENB This enables the ADC's Auto Level Control. 2 ADC_PK_ENB This enables the ADC's Peak Detector. 3 ADC_EQ_ENB This enables the ADC's 5-band Parametric EQ. 4 ADC_SCLP_ENB This enables the ADC's Soft Clip Feature. TABLE 47. DAC EFFECTS (0x71h) Bits Field 0 DAC_ALC_ENB 1 DAC_PK_ENB This enables the DAC's Peak Detector. 2 DAC_EQ_ENB This enables the DAC's 5-band Parametric EQ. 3 DAC_3D_ENB This enables the DAC's Stereo Widening Circuit. 4 ADC_SCLP_ENB www.ti.com Description This enables the DAC's Auto Level Control. This enables the DAC's Soft Clip Feature. 62 LM49350 TABLE 48. HPF MODE (0x80h) Bits Field 2:0 HPF_MODE Description This configures the ADC's High Pass Filter. To calculate the -3dB cutoff frequency, multiply the coefficient by the sample rate (Hz): fC = XN.fS(Hz) HPF_MODE Coefficient Filter Characteristics fC = 220Hz for: 000 X0 = 0.0275 8kHz Voice 001 X1 = 0.01833 12kHz Voice 010 X2 = 0.01375 16kHz Voice 011 X3 = 0.009166 24kHz Voice 100 X4 = 0.006875 32kHz Voice fC = 100Hz for: 101 X5 = 0.003125 32kHz Audio 110 X6 = 0.0020833 48kHz Audio 111 X7 = 0.0015625 fC =150Hz for: 63 96kHz Audio www.ti.com LM49350 detector in order to avoid noise pumping. So it is important to set NOISE_FLOOR to correlate with the signal to noise ratio of the corresponding audio path. In some instances (ie. Conference calls), it may be desirable to mute audio input signals that consist solely of background noise from the audio output. This is accomplished by enabling the ALC's noise gate (NG_ENB). When the noise gate is enabled, signals lower than the noise floor level will be muted from the audio output. If the audio input signal is below the target level, the ALC will increase the gain of the corresponding volume control until the signal reaches the target level. The rate at which the ALC performs gain increases is known as decay rate (DECAY RATE). But before each ALC gain increase the ALC must wait a predetermined amount of time (HOLD TIME). If the audio input signal is above the target level, the ALC will decrease the gain of the corresponding volume control until the signal reaches the target level. The rate at which the ALC performs attenuation is known as attack rate (ATTACK RATE). The ALC's peak detector tracks increases in audio input signal amplitude instantaneously, but tracks decreases in audio input signal amplitude at programmable rate (PEAK DECAY TIME). ATTACK RATE, DECAY RATE, HOLD TIME, and PEAK DECAY TIME are fully adjustable which allows flexible operation of the ALC circuit. The ALC's timers are based on the sample rate of the DAC or ADC, so the closest corresponding sample rate must be programmed into the ALC SAMPLE RATE setting (for DAC ALC) or the ALC MODE setting (for ADC ALC). 26.2 ALC OVERVIEW The Automatic Level Control (ALC) system can be used to regulate the audio output level to a user defined target level. The ALC feature is especially useful whenever the level of the audio input is unknown, unpredictable, or has a large dynamic range. The main purpose of the ALC is to optimize the dynamic range of the audio input to audio output path. There are two separate and independent ALC circuits in the LM49350. One of the ALC circuits is located within the DAC DSP effects block. The other ALC circuit is integrated into the ADC DSP effects block. The DAC ALC controls the DAC digital gain. The ADC ALC controls the auxiliary input amplifier gain or microphone preamplifier gain. The dual ALCs can be used to regulate the level of the analog (Stereo Auxiliary, mono differential, Stereo MIC/LINE) and digital (Port1 Data In, Port2 Data In) audio inputs. The ALC regulated output can be routed to any of the LM49350's amplifier outputs for playback. The ALC regulated output can also be routed to Audio Port1 or Audio Port2 for digital data transmission via I2S or PCM. Only audio inputs that are considered signals (rather than noise) are sent to the ALC's peak detector block. The peak detector compares the level of the audio input versus the ALC target level (TARGET_LEVEL). Signals lower than the target level will be amplified and signals higher than the target level will be attenuated. Any audio input that is lower than the level specified by the noise floor level (NOISE_FLOOR) will be considered as noise and will be gated from the ALC's peak 20194138 FIGURE 25. ALC Example www.ti.com 64 LM49350 TABLE 49. ADC_ALC_1 (0x81h) Bits Field 2:0 SAMPLE_RATE Description This programs the timers on the ALC with the closest sample rate of the ADC. SAMPLE_RATE ADC Fs 000 8kHz 001 12kHz 010 16kHz 011 24kHz 100 32kHz 101 48kHz 110 96kHz 111 192kHz 3 LIMITER If set, the circuit will never apply gain to the signal, no matter how small, but it will attenuate the signal as soon as it reaches target and release it at the decay rate, once signal level reduces below target. The I2C gain setting (at the time the LIMITER is enabled) is the maximum gain that the ALC will apply. Care should be taken when choosing the optimum I2C gain setting whenever enabling the Limiter. 4 STEREO LINK If set, the ALC circuit uses the stereo average of the input signals to control the gain of the stereo output. This maintains stereo imaging. If this bit is cleared, then both channels operate as dual mono. 5 SOURCE_SEL If SOURCE_OVR is set then this manually overrides the selection of the input amplifier that is used to alter the gain for ALC operation. 0 = Both ALCs control AUX gain 1 = Both ALCs control MIC gain 6 SOURCE_OVR If set, the output of the ALC is not set automatically but is controlled by the SOURCE_SEL bit. If cleared each ALC controls the input gain of the amplifier (AUX or MIC) that is set to that ADC channel (or MIC if both are selected). TABLE 50. ADC_ALC_2 (0x82h) Bits Field Description 3:0 NOISE_FLOOR This sets the anticipated noise floor. Signals lower than the noise floor specified will be gated from the ALC to avoid noise pumping. 4 NG_ENB NOISE_FLOOR Noise Floor (dB) 0000 -39 0001 -42 0010 -45 0011 -48 0100 -51 0101 -54 0110 -57 0111 -60 1000 -63 1001 -66 1010 -69 1011 -72 1100 -75 1101 -78 1110 -81 1111 -84 This enables the Noise Gate. 65 www.ti.com LM49350 TABLE 51. ADC_ALC_3 (0x83h) Bits Field Description 4:0 TARGET_LEVEL This sets the desired target output level. Signals lower than this will be amplified and signals larger than this will be attenuated. www.ti.com TARGET_LEVEL Target Level (dB) 00000 -1.5 00001 -3 00010 -4.5 00011 -6 00100 -7.5 00101 -9 00110 -10.5 00111 -12 01000 -13.5 01001 -15 01010 -16.5 01011 -18 01100 -19.5 01101 -21 01110 -22.5 01111 -24 10000 -25.5 10001 -27 10010 -28.5 10011 -30 10100 -31.5 10101 -33 10110 -34.5 10111 -36 11000 -37.5 11001 -39 11010 -40.5 11011 -42 11100 -43.5 11101 -45 11110 -46.5 11111 -48 66 LM49350 TABLE 52. ADC_ALC_4 (0x84h) Bits Field 4:0 ATTACK_RATE Description This sets the rate at which the ALC will reduce gain if it detects the input signal is large. ATTACK_RATE Time between gain steps (s) 00000 21 00001 42 00010 83 00011 167 00100 250 00101 333 00110 417 00111 542 01000 729 01001 958 01010 1250 01011 1604 01100 1896 01101 2208 01110 2792 01111 3708 10000 4792 10001 5688 10010 6563 10011 8396 10100 11000 10101 14167 10110 17083 10111 20000 11000 25000 11001 32000 11010 45000 11011 60000 11100 75000 11101 87500 11110 100000 11111 114583 67 www.ti.com LM49350 TABLE 53. ADC_ALC_5 (0x85h) Bits Field 4:0 DECAY_RATE 7:5 www.ti.com PK_DECAY_RATE Description This sets the rate at which the ALC will increase gain if it detects the input signal is too small. DECAY_RATE Time between gain steps (s) 00000 104 00001 125 00010 167 00011 250 00100 292 00101 396 00110 500 00111 708 01000 896 01001 1250 01010 1396 01011 2000 01100 2708 01101 3500 01110 4750 01111 6250 10000 8000 10001 11000 10010 14000 10011 18500 10100 25000 10101 32000 10110 42000 10111 55000 11000 72500 11001 100000 11010 125000 11011 160000 11100 225000 11101 300000 11110 375000 11111 500000 (0.5s) PK_DECAY_RATE Max Time to track decay 000 1.3ms 001 2.6ms 010 5.3ms 011 10.6ms 100 21.3ms 101 42.6.3ms 110 85.5ms 111 2.73 secs 68 LM49350 TABLE 54. ADC_ALC_6 (0x86h) Bits Field 4:0 HOLD_TIME Description This sets how long the ALC circuit waits before increasing the gain. HOLD_TIME Time (ms) 00000 1 00001 1.25 00010 1.6 00011 2 00100 2.5 00101 3.2 00110 4 00111 5 01000 6.25 01001 8 01010 10 01011 12.5 01100 16 01101 20 01110 25 01111 32 10000 40 10001 50 10010 64 10011 80 10100 100 10101 125 10110 160 10111 200 11000 250 11001 320 11010 400 11011 500 11100 640 11101 800 11110 1000 11111 1250 TABLE 55. ADC_ALC_7 (0x87h) Bits Field Description 5:0 MAX_LEVEL This sets the maximum allowed gain of the volume control to the output amplifier. If the volume control is less than 6 bits the relevant LSBs are used as the limit and the MSBs are ignored. TABLE 56. ADC_ALC_8 (0x88h) Bits Field Description 5:0 MIN_LEVEL This sets the minimum allowed gain of the volume control to the output amplifier. If the volume control is less than 6 bits the relevant LSBs are used as the limit and the MSBs are ignored. 69 www.ti.com LM49350 TABLE 57. ADC_L_LEVEL (0x89h) (Default data value is 0x33h) www.ti.com Bits Field 5:0 ADC_L_LEVEL Description This sets the post ADC digital gain of the left channel. ADC_L_LEVEL Level ADC_L_LEVEL Level 000000 -76.5dB 100000 -28.5dB 000001 -75dB 100001 -27dB 000010 -73.5dB 100010 -25.5dB 000011 -72dB 100011 -24dB 000100 -70.5dB 100100 -22.5dB 000101 -69dB 100101 -21dB 000110 -67.5dB 100110 -20.5dB 000111 -66dB 100111 -18dB 001000 -64.5dB 101000 -16.5dB 001001 -63dB 101001 -15dB 001010 -61.5dB 101010 -13.5dB 001011 -60dB 101011 -12dB 001100 -58.5dB 101100 -10.5dB 001101 -57dB 101101 -9dB 001110 -55.5dB 101110 -7.5dB 001111 -54dB 101111 -6dB 010000 -52.5dB 110000 -4.5dB 010001 -51dB 110001 -3dB 010010 -49.5dB 110010 -1.5dB 010011 -48dB 110011 0dB 010100 -46.5dB 110100 1.5dB 010101 -45dB 110101 3dB 010110 -43.5dB 110110 4.5dB 010111 -42dB 110111 6dB 011000 -40.5dB 111000 7.5dB 011001 -39dB 111001 9dB 011010 -37.5dB 111010 10.5dB 011011 -36dB 111011 12dB 011100 -34.5dB 111100 13.5dB 011101 -33dB 111101 15dB 011110 -31.5dB 111110 16.5dB 011111 -30dB 111111 18dB 70 LM49350 TABLE 58. ADC_R_LEVEL (0x8Ah) (Default data value is 0x33h) Bits Field 5:0 ADC_R_LEVEL Description This sets the post ADC digital gain of the right channel. ADC_R_LEVEL Level ADC_R_LEVEL Level 000000 -76.5dB 100000 -28.5dB 000001 -75dB 100001 -27dB 000010 -73.5dB 100010 -25.5dB 000011 -72dB 100011 -24dB 000100 -70.5dB 100100 -22.5dB 000101 -69dB 100101 -21dB 000110 -67.5dB 100110 -20.5dB 000111 -66dB 100111 -18dB 001000 -64.5dB 101000 -16.5dB 001001 -63dB 101001 -15dB 001010 -61.5dB 101010 -13.5dB 001011 -60dB 101011 -12dB 001100 -58.5dB 101100 -10.5dB 001101 -57dB 101101 -9dB 001110 -55.5dB 101110 -7.5dB 001111 -54dB 101111 -6dB 010000 -52.5dB 110000 -4.5dB 010001 -51dB 110001 -3dB 010010 -49.5dB 110010 -1.5dB 010011 -48dB 110011 0dB 010100 -46.5dB 110100 1.5dB 010101 -45dB 110101 3dB 010110 -43.5dB 110110 4.5dB 010111 -42dB 110111 6dB 011000 -40.5dB 111000 7.5dB 011001 -39dB 111001 9dB 011010 -37.5dB 111010 10.5dB 011011 -36dB 111011 12dB 011100 -34.5dB 111100 13.5dB 011101 -33dB 111101 15dB 011110 -31.5dB 111110 16.5dB 011111 -30dB 111111 18dB 71 www.ti.com LM49350 TABLE 59. EQ_BAND_1 (0x8Bh) Bits Field 1:0 FREQ 6:2 www.ti.com LEVEL Description This sets the Sub-bass shelving filter's cut-off frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. FREQ Frequency (Hz) 00 60 01 80 10 100 11 120 This sets the gain at fc. LEVEL Effect 00000 Off (0dB) 00001 -15dB 00010 -14dB 00011 -13dB 00100 -12dB 00101 -11dB 00110 -10dB 00111 -9dB 01000 -8dB 01001 -7dB 01010 -6dB 01011 -5dB 01100 -4dB 01101 -3dB 01110 -2dB 01111 -1dB 10000 0dB 10001 1dB 10010 2dB 10011 3dB 10100 4dB 10101 5dB 10110 6dB 10111 7dB 11000 8dB 11001 9dB 11010 10dB 11011 11dB 11100 12dB 11101 13dB 11110 14dB 11111 15dB 72 LM49350 TABLE 60. EQ_BAND_2 (0x8Ch) Bits Field Description 1:0 FREQ This sets the Bass peak filter's center frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. 6:2 7 LEVEL Q FREQ Frequency (Hz) 00 150 01 200 10 250 11 300 This sets the gain at fc. LEVEL Effect 00000 Off (0dB) 00001 -15dB 00010 -14dB 00011 -13dB 00100 -12dB 00101 -11dB 00110 -10dB 00111 -9dB 01000 -8dB 01001 -7dB 01010 -6dB 01011 -5dB 01100 -4dB 01101 -3dB 01110 -2dB 01111 -1dB 10000 0dB 10001 1dB 10010 2dB 10011 3dB 10100 4dB 10101 5dB 10110 6dB 10111 7dB 11000 8dB 11001 9dB 11010 10dB 11011 11dB 11100 12dB 11101 13dB 11110 14dB 11111 15dB Programs the width of the peak filter. Q Bandwidth 0 2/3 Octave 1 4/3 Octave 73 www.ti.com LM49350 TABLE 61. EQ_BAND_3 (0x8Dh) Bits Field Description 1:0 FREQ This sets the Mid peak filter's center frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. 6:2 7 www.ti.com LEVEL Q FREQ Frequency (Hz) 00 600 01 800 10 1k 11 1.2k This sets the gain at fC. LEVEL Effect 00000 Off (0dB) 00001 -15dB 00010 -14dB 00011 -13dB 00100 -12dB 00101 -11dB 00110 -10dB 00111 -9dB 01000 -8dB 01001 -7dB 01010 -6dB 01011 -5dB 01100 -4dB 01101 -3dB 01110 -2dB 01111 -1dB 10000 0dB 10001 1dB 10010 2dB 10011 3dB 10100 4dB 10101 5dB 10110 6dB 10111 7dB 11000 8dB 11001 9dB 11010 10dB 11011 11dB 11100 12dB 11101 13dB 11110 14dB 11111 15dB This programs the width of the peak filter. Q Bandwidth 0 2/3 Octave 1 4/3 Octave 74 Bits Field Description 1:0 FREQ This sets the Treble peak filter's center frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. FREQ 6:2 7 LEVEL Q Frequency (Hz) 00 2k 01 2.7k 10 3.4k 11 4.1k This sets the gain at fC. LEVEL Effect 00000 Off (0dB) 00001 -15dB 00010 -14dB 00011 -13dB 00100 -12dB 00101 -11dB 00110 -10dB 00111 -9dB 01000 -8dB 01001 -7dB 01010 -6dB 01011 -5dB 01100 -4dB 01101 -3dB 01110 -2dB 01111 -1dB 10000 0dB 10001 1dB 10010 2dB 10011 3dB 10100 4dB 10101 5dB 10110 6dB 10111 7dB 11000 8dB 11001 9dB 11010 10dB 11011 11dB 11100 12dB 11101 13dB 11110 14dB 11111 15dB This programs the width of the peak filter. Q Bandwidth 0 2/3 Octave 1 4/3 Octave 75 www.ti.com LM49350 TABLE 62. EQ_BAND_4 (0x8Eh) LM49350 TABLE 63. EQ_BAND_5 (0x8Fh) Bits Field 1:0 FREQ 6:2 www.ti.com LEVEL Description This sets the presence shelving filter's cut-off frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. FREQ Frequency (Hz) 00 7k 01 9k 10 11k 11 20k This sets the gain at fC. LEVEL Effect 00000 Off (0dB) 00001 -15dB 00010 -14dB 00011 -13dB 00100 -12dB 00101 -11dB 00110 -10dB 00111 -9dB 01000 -8dB 01001 -7dB 01010 -6dB 01011 -5dB 01100 -4dB 01101 -3dB 01110 -2dB 01111 -1dB 10000 0dB 10001 1dB 10010 2dB 10011 3dB 10100 4dB 10101 5dB 10110 6dB 10111 7dB 11000 8dB 11001 9dB 11010 10dB 11011 11dB 11100 12dB 11101 13dB 11110 14dB 11111 15dB 76 LM49350 TABLE 64. SOFTCLIP1 (0x90h) Bits Field 3:0 THRESHOLD 4 SOFT_KNEE Description This sets the threshold level of the audio compressor. Audio signals above the threshold will be compressed. THRESHOLD Threshold Level (dB) 0000 -36dB 0001 -30dB 0010 -24dB 0011 -20dB 0100 -18dB 0101 -17dB 0110 -16dB 0111 -15dB 1000 -14dB 1001 -12dB 1010 -10dB 1011 -8dB 1100 -6dB 1101 -4dB 1110 -2.5dB 1111 -1dB If set, the audio compressor will automatically apply higher compression ratios to audio signals higher than the threshold level. As the audio signal approaches levels higher than the threshold, SOFT_KNEE will increase the compression RATIO. The highest compression that the SOFT_KNEE algorithm will apply is the compression that is set by RATIO. 77 www.ti.com LM49350 TABLE 65. SOFTCLIP2 (0x91h) www.ti.com Bits Field Description 4:0 RATIO This sets the ratio at which the audio is compressed to when it passes beyond the threshold. In SOFT_KNEE mode this is the final level of compression. RATIO Ratio 00000 1:1 (Bypass) 00001 1:1.2 00010 1:1.4 00011 1:1.7 00100 1:2.0 00101 1:2.4 00110 1:2.8 00111 1:3.4 01000 1:4.0 01001 1:4.7 01010 1:5.7 01011 1:6.7 01100 1:8.0 01101 1:9.5 01110 1:11.3 01111 1:13.5 10000 1:16.0 10001 1:19.0 10010 1:22.8 10011 1:27.0 10100 1:32.0 10101 1:37.9 10110 1:45.5 10111 1:53.9 11000 1:64.0 11001 1:75.0 11010 1:91.0 11011 1:108 11100 1:128 11101 1:152 11110 1:182 11111 1:215 78 LM49350 TABLE 66. SOFTCLIP3 (0x92h) Bits Field 4:0 LEVEL Description This sets the post compressor gain level. LEVEL Level (dB) 00000 -22.5dB 00001 -21dB 00010 -19.5dB 00011 -18dB 00100 -16.5dB 00101 -15dB 00110 -13.5dB 00111 -12dB 01000 -10.5dB 01001 -9dB 01010 -7.5dB 01011 -6dB 01100 -4.5dB 01101 -3dB 01110 -1.5dB 01111 0dB 10000 1.5dB 10001 3dB 10010 4.5dB 10011 6dB 10100 7.5dB 10101 9dB 10110 10.5dB 10111 12dB 11000 13.5dB 11001 15dB 11010 16.5dB 11011 18dB 11100 19.5dB 11101 21dB 11110 22.5dB 11111 24dB 79 www.ti.com LM49350 27.0 DAC Effects Registers TABLE 67. DAC_ALC_1 (0xA0h) Bits 2:0 Field Description SAMPLE_ RATE This programs the timers on the ALC with the closest DAC sample rate. SAMPLE_ RATE DAC Fs 000 8kHz 001 12kHz 010 16kHz 011 24kHz 100 32kHz 101 48kHz 110 96kHz 111 192kHz 3 LIMITER If set, the circuit will never apply gain to the signal, no matter how small, but it will attenuate the signal as soon as it reaches target and release it at the decay rate, once signal level reduces below target. The I2C gain setting (at the time the LIMITER is enabled) is the maximum gain that the ALC will apply. Care should be taken when choosing the optimum I2C gain setting whenever enabling the Limiter. 4 STEREO LINK If set, the ALC circuit uses the stereo average of the input signals to control the gain of the stereo output. This maintains stereo imaging. If this bit is cleared, then both channels operate as dual mono. TABLE 68. DAC_ALC_2 (0xA1h) Bits Field Description 3:0 NOISE_FLOOR This sets the anticipated noise floor. Signals lower than the specified noise floor will be gated from the ALC to avoid noise pumping. 4 www.ti.com NG_ENB NOISE_FLOOR Noise Floor (dB) 0000 -39 0001 -42 0010 -45 0011 -48 0100 -51 0101 -54 0110 -57 0111 -60 1000 -63 1001 -66 1010 -69 1011 -72 1100 -75 1101 -78 1110 -81 1111 -84 This enables the Noise Gate 80 LM49350 TABLE 69. DAC_ALC_3 (0xA2h) Bits 4:0 Field Description TARGET_LEVEL This sets the desired output level. Signals lower than this will be amplified and signals larger than this will be attenuated. TARGET_LEVEL Target Level (dB) 00000 -1.5 00001 -3 00010 -4.5 00011 -6 00100 -7.5 00101 -9 00110 -10.5 00111 -12 01000 -13.5 01001 -15 01010 -16.5 01011 -18 01100 -19.5 01101 -21 01110 -22.5 01111 -24 10000 -25.5 10001 -27 10010 -28.5 10011 -30 10100 -31.5 10101 -33 10110 -34.5 10111 -36 11000 -37.5 11001 -39 11010 -40.5 11011 -42 11100 -43.5 11101 -45 11110 -46.5 11111 -48 81 www.ti.com LM49350 TABLE 70. DAC_ALC_4 (0xA3h) www.ti.com Bits Field 4:0 ATTACK_RATE Description This sets the rate at which the ALC will reduce gain if it detects the input signal is too large. ATTACK_RATE Time between gain steps(us) 00000 21 00001 42 00010 83 00011 167 00100 250 00101 333 00110 417 00111 542 01000 729 01001 958 01010 1250 01011 1604 01100 1896 01101 2208 01110 2792 01111 3708 10000 4792 10001 5688 10010 6563 10011 8396 10100 11000 10101 14167 10110 17083 10111 20000 11000 25000 11001 32000 11010 45000 11011 60000 11100 75000 11101 87500 11110 100000 11111 114583 82 LM49350 TABLE 71. DAC_ALC_5 (0xA4h) Bits Field Description 4:0 DECAY_RATE This sets the rate at which the ALC will increase gain if it detects the input signal is too small. 7:5 PK_DECAY_RATE DECAY_RATE Time between gain steps (us) 00000 104 00001 125 00010 167 00011 250 00100 292 00101 396 00110 500 00111 708 01000 896 01001 1250 01010 1396 01011 2000 01100 2708 01101 3500 01110 4750 01111 6250 10000 8000 10001 11000 10010 14000 10011 18500 10100 25000 10101 32000 10110 42000 10111 55000 11000 72500 11001 100000 11010 125000 11011 160000 11100 225000 11101 300000 11110 375000 11111 500000 (0.5s) This sets how precise the ALC will track amplitude reductions of the audio input. The shorter the length of time for PK_DECAY_RATE, the more responsive the ALC will be when applying gain increases whenever the audio falls below target level. PK_DECAY_RATE Time 000 1.3ms 001 2.6ms 010 5.3ms 011 10.6ms 100 21.3ms 101 42.6ms 110 85.5ms 111 2.73secs 83 www.ti.com LM49350 TABLE 72. DAC_ALC_6 (0xA5h) Bits Field 4:0 HOLD_TIME Description This sets how long the ALC circuit waits before increasing the gain. HOLDTIME Time (ms) 00000 1 00001 1.25 00010 1.6 00011 2 00100 2.5 00101 3.2 00110 4 00111 5 01000 6.25 01001 8 01010 10 01011 12.5 01100 16 01101 20 01110 25 01111 32 10000 40 10001 50 10010 64 10011 80 10100 100 10101 125 10110 160 10111 200 11000 250 11001 320 11010 400 11011 500 11100 640 11101 800 11110 1000 11111 1250 TABLE 73. DAC_ALC_7 (0xA6h) Bits Field 5:0 MAX_LEVEL Description This sets the maximum allowed gain to the digital level control when the ALC is used. TABLE 74. DAC_ALC_8 (0xA7h) www.ti.com Bits Field 5:0 MIN_LEVEL Description This sets the minimum allowed gain to the digital level control when the ALC is used. 84 LM49350 TABLE 75. DAC_L_LEVEL (0xA8h) (Default data value is 0x33h) Bits Field 5:0 DAC_L_LEVEL Description This sets the pre DAC digital gain. DAC_L_LEVEL Level DAC_L_LEVEL Level 000000 -76.5dB 100000 -28.5dB 000001 -75dB 100001 -27dB 000010 -73.5dB 100010 -25.5dB 000011 -72dB 100011 -24dB 000100 -70.5dB 100100 -22.5dB 000101 -69dB 100101 -21dB 000110 -67.5dB 100110 -20.5dB 000111 -66dB 100111 -18dB 001000 -64.5dB 101000 -16.5dB 001001 -63dB 101001 -15dB 001010 -61.5dB 101010 -13.5dB 001011 -60dB 101011 -12dB 001100 -58.5dB 101100 -10.5dB 001101 -57dB 101101 -9dB 001110 -55.5dB 101110 -7.5dB 001111 -54dB 101111 -6dB 010000 -52.5dB 110000 -4.5dB 010001 -51dB 110001 -3dB 010010 -49.5dB 110010 -1.5dB 010011 -48dB 110011 0dB 010100 -46.5dB 110100 1.5dB 010101 -45dB 110101 3dB 010110 -43.5dB 110110 4.5dB 010111 -42dB 110111 6dB 011000 -40.5dB 111000 7.5dB 011001 -39dB 111001 9dB 011010 -37.5dB 111010 10.5dB 011011 -36dB 111011 12dB 011100 -34.5dB 111100 13.5dB 011101 -33dB 111101 15dB 011110 -31.5dB 111110 16.5dB 011111 -30dB 111111 18dB 85 www.ti.com LM49350 TABLE 76. DAC_R_LEVEL (0xA9h) (Default data value is 0x33h) www.ti.com Bits Field 5:0 DAC_R_LEVEL Description This sets the pre DAC digital gain. DAC_R_LEVEL Level DAC_R_LEVEL Level 000000 -76.5dB 100000 -28.5dB 000001 -75dB 100001 -27dB 000010 -73.5dB 100010 -25.5dB 000011 -72dB 100011 -24dB 000100 -70.5dB 100100 -22.5dB 000101 -69dB 100101 -21dB 000110 -67.5dB 100110 -20.5dB 000111 -66dB 100111 -18dB 001000 -64.5dB 101000 -16.5dB 001001 -63dB 101001 -15dB 001010 -61.5dB 101010 -13.5dB 001011 -60dB 101011 -12dB 001100 -58.5dB 101100 -10.5dB 001101 -57dB 101101 -9dB 001110 -55.5dB 101110 -7.5dB 001111 -54dB 101111 -6dB 010000 -52.5dB 110000 -4.5dB 010001 -51dB 110001 -3dB 010010 -49.5dB 110010 -1.5dB 010011 -48dB 110011 0dB 010100 -46.5dB 110100 1.5dB 010101 -45dB 110101 3dB 010110 -43.5dB 110110 4.5dB 010111 -42dB 110111 6dB 011000 -40.5dB 111000 7.5dB 011001 -39dB 111001 9dB 011010 -37.5dB 111010 10.5dB 011011 -36dB 111011 12dB 011100 -34.5dB 111100 13.5dB 011101 -33dB 111101 15dB 011110 -31.5dB 111110 16.5dB 011111 -30dB 111111 18dB 86 LM49350 TABLE 77. DAC_3D (0xAAh) Bits 0 Field Description EFFECT_MODE This sets the digital 3D stereo enhancement mode. EFFECT_MODE 2:1 6:3 7 Type 0 Loudspeaker 1 Headphone EFFECT_LEVEL This sets the applied level of 3D effect. FILTER_TYPE ATTENUATE EFFECT_LEVEL Level 00 25% 01 37.50% 10 50% 11 75% This sets the 3D effect filter response. FILTER_TYPE Response 0000 200Hz HPF 0001 300Hz HPF 0010 600Hz HPF 0011 900Hz HPF 0100 200Hz-500Hz BPF 0101 200Hz-1kHz BPF 0110 200Hz-1.6kHz BPF 0111 200Hz-2.5kHz BPF 1000 300Hz-1kHz BPF 1001 300Hz-1.6kHz BPF 1010 300Hz-2.5kHz BPF 1011 600Hz-1kHz BPF 1100 600Hz-1.6kHz BPF 1101 600Hz-2.5kHz BPF 1110 900Hz-1.6kHz BPF 1111 900Hz-2.5kHz BPF If set, the inputs are reduced by 6dB before 3D effects are applied in order to avoid clipping. 87 www.ti.com LM49350 TABLE 78. EQ_BAND_1 (0xABh) Bits Field Description 1:0 FREQ This sets the Sub-bass shelving filter's cut-off frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. 6:2 www.ti.com LEVEL FREQ Frequency (Hz) 00 60 01 80 10 100 11 120 This sets the gain at fC. LEVEL Effect 00000 Off (0dB) 00001 -15dB 00010 -14dB 00011 -13dB 00100 -12dB 00101 -11dB 00110 -10dB 00111 -9dB 01000 -8dB 01001 -7dB 01010 -6dB 01011 -5dB 01100 -4dB 01101 -3dB 01110 -2dB 01111 -1dB 10000 0dB 10001 1dB 10010 2dB 10011 3dB 10100 4dB 10101 5dB 10110 6dB 10111 7dB 11000 8dB 11001 9dB 11010 10dB 11011 11dB 11100 12dB 11101 13dB 11110 14dB 11111 15dB 88 LM49350 TABLE 79. EQ_BAND_2 (0xACh) Bits Field Description 1:0 FREQ This sets the Bass peak filter's center frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. 6:2 7 LEVEL Q FREQ Frequency (Hz) 00 150 01 200 10 250 11 300 This sets the gain at fC. LEVEL Effect 00000 Off (0dB) 00001 -15dB 00010 -14dB 00011 -13dB 00100 -12dB 00101 -11dB 00110 -10dB 00111 -9dB 01000 -8dB 01001 -7dB 01010 -6dB 01011 -5dB 01100 -4dB 01101 -3dB 01110 -2dB 01111 -1dB 10000 0dB 10001 1dB 10010 2dB 10011 3dB 10100 4dB 10101 5dB 10110 6dB 10111 7dB 11000 8dB 11001 9dB 11010 10dB 11011 11dB 11100 12dB 11101 13dB 11110 14dB 11111 15dB This programs the width of the peak filter. Q Bandwidth 0 2/3 Octave 1 4/3 Octave 89 www.ti.com LM49350 TABLE 80. EQ_BAND_3 (0xADh) Bits Field 1:0 FREQ 6:2 7 www.ti.com LEVEL Q Description This sets the Mid peak filter's center frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. FREQ Frequency (Hz) 00 600 01 800 10 1k 11 1.2k This sets the gain at fC. LEVEL Effect 00000 Off (0dB) 00001 -15dB 00010 -14dB 00011 -13dB 00100 -12dB 00101 -11dB 00110 -10dB 00111 -9dB 01000 -8dB 01001 -7dB 01010 -6dB 01011 -5dB 01100 -4dB 01101 -3dB 01110 -2dB 01111 -1dB 10000 0dB 10001 1dB 10010 2dB 10011 3dB 10100 4dB 10101 5dB 10110 6dB 10111 7dB 11000 8dB 11001 9dB 11010 10dB 11011 11dB 11100 12dB 11101 13dB 11110 14dB 11111 15dB This programs the width of the peak filter. Q Bandwidth 0 2/3 Octave 1 4/3 Octave 90 LM49350 TABLE 81. EQ_BAND_4 (0xAEh) Bits Field Description 1:0 FREQ This sets the Treble peak filter's center frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. FREQ 6:2 7 LEVEL Q Frequency (Hz) 00 2k 01 2.7k 10 3.4k 11 4.1k This sets the gain at fC. LEVEL Effect 00000 Off (0dB) 00001 -15dB 00010 -14dB 00011 -13dB 00100 -12dB 00101 -11dB 00110 -10dB 00111 -9dB 01000 -8dB 01001 -7dB 01010 -6dB 01011 -5dB 01100 -4dB 01101 -3dB 01110 -2dB 01111 -1dB 10000 0dB 10001 1dB 10010 2dB 10011 3dB 10100 4dB 10101 5dB 10110 6dB 10111 7dB 11000 8dB 11001 9dB 11010 10dB 11011 11dB 11100 12dB 11101 13dB 11110 14dB 11111 15dB This programs the width of the peak filter. Q Bandwidth 0 2/3 Octave 1 4/3 Octave 91 www.ti.com LM49350 TABLE 82. EQ_BAND_5 (0xAFh) Bits Field Description 1:0 FREQ This sets the presence shelving filter's cut-off frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. 6:2 www.ti.com LEVEL FREQ Frequency (Hz) 00 7k 01 9k 10 11k 11 20k This sets the gain at fC. LEVEL Effect 00000 Off (0dB) 00001 -15dB 00010 -14dB 00011 -13dB 00100 -12dB 00101 -11dB 00110 -10dB 00111 -9dB 01000 -8dB 01001 -7dB 01010 -6dB 01011 -5dB 01100 -4dB 01101 -3dB 01110 -2dB 01111 -1dB 10000 0dB 10001 1dB 10010 2dB 10011 3dB 10100 4dB 10101 5dB 10110 6dB 10111 7dB 11000 8dB 11001 9dB 11010 10dB 11011 11dB 11100 12dB 11101 13dB 11110 14dB 11111 15dB 92 LM49350 TABLE 83. SOFTCLIP1 (0xB0h) Bits Field Description 3:0 TRESHOLD This sets the threshold level of the audio compressor. Audio signals above the threshold will be compressed. 4 SOFT_KNEE THRESHOLD Threshold Level (dB) 0000 -36dB 0001 -30dB 0010 -24dB 0011 -20dB 0100 -18dB 0101 -17dB 0110 -16dB 0111 -15dB 1000 -14dB 1001 -12dB 1010 -10dB 1011 -8dB 1100 -6dB 1101 -4dB 1110 -2.5dB 1111 -1dB If set, the audio compressor will automatically apply higher compression ratios to audio signals higher than the threshold level. As the audio signal approaches levels higher than the threshold, SOFT_KNEE will increase the compression RATIO. The highest compression that the SOFT_KNEE algorithm will apply is the compression that is set by RATIO. 93 www.ti.com LM49350 TABLE 84. SOFTCLIP2 (0xB1h) www.ti.com Bits Field Description 4:0 RATIO This sets the ratio at which the audio is compressed to when it passes beyond the threshold. In soft clip mode this is the final level of compression. RATIO Ratio 00000 1:1 (Bypass) 00001 1:1.2 00010 1:1.4 00011 1:1.7 00100 1:2.0 00101 1:2.4 00110 1:2.8 00111 1:3.4 01000 1:4.0 01001 1:4.7 01010 1:5.7 01011 1:6.7 01100 1:8.0 01101 1:9.5 01110 1:11.3 01111 1:13.5 10000 1:16.0 10001 1:19.0 10010 1:22.8 10011 1:27.0 10100 1:32.0 10101 1:37.9 10110 1:45.5 10111 1:53.9 11000 1:64 11001 1:75.9 11010 1:91.0 11011 1:108 11100 1:128 11101 1:152 11110 1:182 11111 1:215 94 LM49350 TABLE 85. SOFTCLIP3 (0xB2h) Table 40: Bits Field 4:0 LEVEL Description This sets the post compressor gain level. LEVEL Level (dB) 00000 -22.5dB 00001 -21dB 00010 -19.5dB 00011 -18dB 00100 -16.5dB 00101 -15dB 00110 -13.5dB 00111 -12dB 01000 -10.5dB 01001 -9dB 01010 -7.5dB 01011 -6dB 01100 -4.5dB 01101 -3dB 01110 -1.5dB 01111 0dB 10000 1.5dB 10001 3dB 10010 4.5dB 10011 6dB 10100 7.5dB 10101 9dB 10110 10.5dB 10111 12dB 11000 13.5dB 11001 15dB 11010 16.5dB 11011 18dB 11100 19.5dB 11101 21dB 11110 22.5dB 11111 24dB 95 www.ti.com LM49350 28.0 GPIO Registers TABLE 86. GPIO (0xE0h) Bits Field 3:0 GPIO_MODE Description This sets the mode of the GPIO pin. GPIO_MODE GPIO Function 0000 OFF (input disabled) 0001 GPIO_RX 0010 GPIO_TX 0011 HP_ENB (out) 0100 HP_ENB (out) 0101 LS_ENB (out) 0110 LS_ENB (out) 0111 SHORT_CCT or THERMAL (out) 1000 SHORT_CCT or THERMAL or CLIP (out) 1001 CLIP (out) 1010 ADC_NG_ACTIVE (out) 1011 ADC_NG_ACTIVE (out) 1100 MIC_MUTE (in) 1101 MIC_MUTE (in) 1110 CHIP_ENB (in) 1111 CHIP_ENB (in) 4 GPIO_TX If set, the GPIO pin will transmit a logic high whenever GPIO_MODE is set to '0010'. 5 GPIO_RX This bit reports what logic level is present on the GPIO pin. 6 SHORT_CCT 7 THERMAL_EVENT If set, the GPIO records that a short circuit event has occurred on the class D outputs. If set records that a temperature event has occurred on the die. Clear on Write (1). TABLE 87. DEBUG1 (0xF0h) Bits Field 1:0 DAC_DITHER _LVL 3:2 www.ti.com DAC_DITHER _MODE 4 Not Used 5 SOFT_RESET 7:6 RSVD Description This sets the amount of DAC dither. Lower levels of the dither may improve the noise floor of the DAC. DAC_DITHER _LVL Level 00 Very Small 01 Small 10 Medium (Default) 11 Large This sets the DAC dither mode. DAC_DITHER _MODE Mode 00 AUTOMATIC 01 ON 10 OFF If set, the LM49350 enters RESET mode. To bring the LM49350 back out of RESET mode, then set this bit back to zero. Reserved 96 LM49350 TABLE 88. Spread Spectrum (0xF1h) Bits Field Description 1:0 RSVD 2 SS_DISABLE Reserved If this bit is set, Spread Spectrum mode will be disabled from the Class D amplifier. TABLE 89. ADC Compensation Filter C0 LSBs (0xF8h) Bits Field 7:0 ADC_CO_LSB Description Bits 7:0 of C0[15:0] TABLE 90. ADC Compensation Filter C0 MSBs (0xF9h) Bits Field 7:0 ADC_CO_MSB Description Bits 15:0 of C0[15:0] TABLE 91. ADC Compensation Filter C1 LSBs (0xFAh) Bits Field 7:0 ADC_C1_LSB Description Bits 7:0 of C1[15:0] TABLE 92. ADC Compensation Filter C1 MSBs (0xFBh) Bits Field 7:0 ADC_C1_MSB Description Bits 15:0 of C1[15:0] TABLE 93. ADC Compensation Filter C2 LSBs (0xFCh) Bits Field 7:0 ADC_C2_LSB Description Bits 7:0 of C2[15:0] TABLE 94. ADC Compensation Filter C2 MSBs (0xFDh) Bits Field 7:0 ADC_C2_MSB Description Bits 15:0 of C2[15:0] TABLE 95. AUX_LINEOUT (0xFE) Bits Field 4:0 RSVD 5 AUX_LINE_OUT Description Reserved If set, the earpiece amplifier operates in a low current drive mode for line out applications in order to reduce power consumption. 97 www.ti.com www.ti.com 98 FIGURE 26. Demo Board Schematic Schematic Diagram 20194119 LM49350 LM49350 29.0 Demonstration Board Layout 20194106 FIGURE 27. Top Silkscreen Layer 20194115 FIGURE 28. Top Layer 99 www.ti.com LM49350 20194116 FIGURE 29. Inner Layer 1 20194117 FIGURE 30. Inner Layer 2 www.ti.com 100 LM49350 20194120 FIGURE 31. Bottom Silkscreen Layer 20194118 FIGURE 32. Bottom Layer 101 www.ti.com LM49350 30.0 Application Note for LM49350 30.1 POWER CONNECTIONS Recommended target application circuit must provide same voltage level for A_VDD and LSVDD to get performance on Electrical Specifications on LM49350 datasheet. 20194185 FIGURE 33. Recommended Power Connection www.ti.com 102 30.2.1 Schematic Considerations for MEMs Microphones The internal microphone bias of the LM49350 is provided through a two stage amplifier. Adding a capacitor larger than 100pF directly to this pin can cause instability. In many cases, 20194186 FIGURE 34. Schematic for MEMs Microphones many cases, an RC filter is required to provide a more stable microphone bias (see Figure 34). In this case, a 10 resistor (RB ) in series with CB is recommended. 30.2.2 Schematic Considerations for ECM Microphones When using ECM microphones, refer to the configurations shown in Figure 33 or Figure 34 to bias the microphones. In 20194187 FIGURE 33: Schematic Option for ECM Microphones 20194132 FIGURE 34: Schematic Option for ECM Microphones 103 www.ti.com LM49350 when using MEMs microphones, a larger bypass capacitor is required on the MIC_BIAS pin. To avoid oscillations and to keep the device stable, it is recommended to add a resistor (RB) greater than 10 in series with the capacitor (CB). Another option is to bias the MEMs microphone from the 1.8V supply used for D_VDD/IO_VDD. 30.2 MICROPHONE BIAS CONFIGURATIONS LM49350 output (LS-, LS+) traces should be as wide as possible. It is also essential to keep these same traces as short and well shielded as possible to decrease the amount of EMI radiation. 30.3 PCB LAYOUT CONSIDERATIONS 30.3.1 Microphone Inputs When routing the differential microphone inputs the electrical length of the two traces should be well matched. The differential input pair can be routed in parallel on the same plane or the traces can overlap on two adjacent planes. It is important to surround these traces with a ground plane or trace to isolate the microphone inputs from the noise coupling from the class D amplifier. 30.3.3 Capacitors All supply bypass capacitors (for A_VDD, D_VDD. I/O VDD, and LS_VDD), and charge pump capacitors should be as close to the device as possible. Careful consideration should be taken with the ground connection of the analog supply (A_VDD) bypass cap, for proper performance it should be referenced to a low noise ground plane. The charge pump capacitors and traces connecting the capacitor to the device should be kept away from the input and output traces to avoid noise coupling issues. 30.3.2 Class D Loudspeaker To minimize trace resistance and therefore maintain the highest possible output power, the power (LS_VDD) and class D www.ti.com 104 LM49350 31.0 Revision History Rev Date 1.0 09/03/08 Description Initial released. 1.01 09/04/08 Text edits. 1.02 09/22/08 Text edits. 1.03 10/24/08 Text edits. 1.04 12/15/08 Text edits and replaced the top silkscreen layer. 1.05 05/27/09 Added the EMI/RFI section and the corresponding graphic. 1.06 05/29/09 Text edits. 1.07 04/09/10 Text edits. 1.08 04/15/10 Text edits. 1.09 09/17/10 Added the Application section required for Leadcore (chipset partner). 1.10 03/23/11 Input minor text edits. 1.11 04/05/11 Added sections 29.2 and 29.3 including their corresponding graphics, then generated a CONFIDENTIAL version for LEADCORE. 1.12 04/12/11 Edited Figure 32 and input text edits. 1.13 04/13/11 Input text edits. 1.14 08/24/11 Added table: RX_MODE (0x55h/65h). 1.15 03/16/12 Added the one more Timing Char table (DVDD = I/OVDD = 1.8V with the 2 diagrams (Timing I2S Master and Timing for I2S Slave). 1.16 06/29/12 Edited Figures 2, 3, 4, and 5 (Typical Application circuit diagrams). 105 www.ti.com LM49350 32.0 Physical Dimensions inches (millimeters) unless otherwise noted micro SMD-36 Package Order Number LM49350RL NS Package Number RLA36TTA X1 = 3.459.03mm, X2 = 3.459.03mm, X3 = 0.65.075mm www.ti.com 106 LM49350 Notes 107 www.ti.com LM49350 High Performance Audio Codec Sub-System with a Ground-Referenced Stereo Headphone Amplifier & an Ultra Low EMI Class D Loudspeaker Amplifier with Dual I2S/PCM Digital Audio Interfaces Notes www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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