Copyright © 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-
ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al-
tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap-
plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera
Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in-
formation and before placing orders for products or services.
ii Altera Corporation
Preliminary
Altera Corporation iii
Preliminary
Contents
Chapter Revision Dates ........................................................................... xi
About this Handbook ............................................................................. xiii
How to Find Information ..................................................................................................................... xiii
How to Contact Altera .......................................................................................................................... xiii
Typographic Conventions .................................................................................................................... xiv
Section I. Cyclone FPGA Family Data Sheet
Revision History .................................................................................................................................... 2–1
Chapter 1. Introduction
Introduction ............................................................................................................................................ 1–1
Features ................................................................................................................................................... 1–1
Document Revision History ................................................................................................................. 1–3
Chapter 2. Cyclone Architecture
Functional Description .......................................................................................................................... 2–1
Logic Array Blocks ................................................................................................................................ 2–3
LAB Interconnects ............................................................................................................................ 2–3
LAB Control Signals ......................................................................................................................... 2–4
Logic Elements ....................................................................................................................................... 2–5
LUT Chain and Register Chain ...................................................................................................... 2–7
addnsub Signal ................................................................................................................................. 2–7
LE Operating Modes ........................................................................................................................ 2–7
MultiTrack Interconnect ..................................................................................................................... 2–12
Embedded Memory ............................................................................................................................. 2–18
Memory Modes ............................................................................................................................... 2–18
Parity Bit Support ........................................................................................................................... 2–20
Shift Register Support .................................................................................................................... 2–20
Memory Configuration Sizes ........................................................................................................ 2–21
Byte Enables .................................................................................................................................... 2–23
Control Signals and M4K Interface .............................................................................................. 2–23
Independent Clock Mode .............................................................................................................. 2–25
Input/Output Clock Mode ........................................................................................................... 2–25
Read/Write Clock Mode ............................................................................................................... 2–28
Single-Port Mode ............................................................................................................................ 2–29
Global Clock Network and Phase-Locked Loops ........................................................................... 2–29
Global Clock Network ................................................................................................................... 2–29
iv Altera Corporation
Preliminary
Cyclone Device Handbook, Volume 1
Dual-Purpose Clock Pins .............................................................................................................. 2–31
Combined Resources ..................................................................................................................... 2–31
PLLs .................................................................................................................................................. 2–32
Clock Multiplication and Division .............................................................................................. 2–35
External Clock Inputs .................................................................................................................... 2–36
External Clock Outputs ................................................................................................................. 2–36
Clock Feedback ............................................................................................................................... 2–37
Phase Shifting ................................................................................................................................. 2–37
Lock Detect Signal .......................................................................................................................... 2–37
Programmable Duty Cycle ........................................................................................................... 2–38
Control Signals ................................................................................................................................ 2–38
I/O Structure ........................................................................................................................................ 2–39
External RAM Interfacing ............................................................................................................. 2–46
DDR SDRAM and FCRAM ........................................................................................................... 2–46
Programmable Drive Strength .....................................................................................................2–49
Open-Drain Output ........................................................................................................................ 2–50
Slew-Rate Control .......................................................................................................................... 2–51
Bus Hold .......................................................................................................................................... 2–51
Programmable Pull-Up Resistor .................................................................................................. 2–51
Advanced I/O Standard Support ................................................................................................ 2–52
LVDS I/O Pins ................................................................................................................................ 2–54
MultiVolt I/O Interface ................................................................................................................. 2–54
Power Sequencing and Hot Socketing ............................................................................................. 2–55
Referenced Documents ....................................................................................................................... 2–56
Document Revision History ............................................................................................................... 2–56
Chapter 3. Configuration and Testing
IEEE Std. 1149.1 (JTAG) Boundary Scan Support ............................................................................. 3–1
SignalTap II Embedded Logic Analyzer ............................................................................................ 3–5
Configuration ......................................................................................................................................... 3–5
Operating Modes .............................................................................................................................. 3–6
Configuration Schemes ................................................................................................................... 3–6
Referenced Documents ......................................................................................................................... 3–7
Document Revision History ................................................................................................................. 3–7
Chapter 4. DC and Switching Characteristics
Operating Conditions ........................................................................................................................... 4–1
Power Consumption ............................................................................................................................. 4–8
Timing Model ......................................................................................................................................... 4–9
Preliminary and Final Timing ........................................................................................................ 4–9
Performance .................................................................................................................................... 4–10
Internal Timing Parameters .......................................................................................................... 4–11
External Timing Parameters ......................................................................................................... 4–15
External I/O Delay Parameters .................................................................................................... 4–21
Maximum Input and Output Clock Rates .................................................................................. 4–27
PLL Timing ...................................................................................................................................... 4–29
Referenced Document ......................................................................................................................... 4–31
Altera Corporation v
Preliminary
Contents
Document Revision History ............................................................................................................... 4–31
Chapter 5. Reference and Ordering Information
Software .................................................................................................................................................. 5–1
Device Pin-Outs ..................................................................................................................................... 5–1
Ordering Information ........................................................................................................................... 5–1
Referenced Documents ......................................................................................................................... 5–2
Document Revision History ................................................................................................................. 5–2
Section II. Clock Management
Revision History .................................................................................................................................... 5–1
Chapter 6. Using PLLs in Cyclone Devices
Introduction ............................................................................................................................................ 6–1
Hardware Overview ........................................................................................................................ 6–1
Software Overview .......................................................................................................................... 6–4
Pins and Clock Network Connections .......................................................................................... 6–6
Hardware Features ................................................................................................................................ 6–8
Clock Multiplication and Division ................................................................................................ 6–8
Phase Shifting ................................................................................................................................... 6–9
Programmable Duty Cycle ........................................................................................................... 6–10
External Clock Output ................................................................................................................... 6–11
Control Signals ................................................................................................................................ 6–12
Clock Feedback Modes ....................................................................................................................... 6–13
Normal Mode .................................................................................................................................. 6–14
Zero Delay Buffer Mode ................................................................................................................ 6–15
No Compensation .......................................................................................................................... 6–15
Pins ......................................................................................................................................................... 6–16
Board Layout ........................................................................................................................................ 6–17
VCCA and GNDA .......................................................................................................................... 6–17
Jitter Considerations ...................................................................................................................... 6–19
Specifications ........................................................................................................................................ 6–20
Software Support ................................................................................................................................. 6–20
Quartus II altpll Megafunction ..................................................................................................... 6–20
altpll Input Ports ............................................................................................................................. 6–22
altpll Output Ports ......................................................................................................................... 6–23
MegaWizard Customization ......................................................................................................... 6–23
MegaWizard Page Description .....................................................................................................6–25
Compilation Report ....................................................................................................................... 6–31
Timing Analysis .............................................................................................................................. 6–33
Simulation ....................................................................................................................................... 6–37
Global Clock Network ........................................................................................................................ 6–38
Dedicated Clock Input Pins .......................................................................................................... 6–40
Dual-Purpose Clock I/O Pins ...................................................................................................... 6–40
Combined Sources .......................................................................................................................... 6–41
vi Altera Corporation
Preliminary
Cyclone Device Handbook, Volume 1
Conclusion ............................................................................................................................................ 6–43
Referenced Documents ....................................................................................................................... 6–44
Document Revision History ............................................................................................................... 6–44
Section III. Memory
Revision History .................................................................................................................................... 7–1
Chapter 7. On-Chip Memory Implementations Using Cyclone Memory Blocks
Introduction ............................................................................................................................................ 7–1
M4K Memory Features ......................................................................................................................... 7–1
Parity Bit Support ............................................................................................................................. 7–2
Byte-Enable Support ........................................................................................................................ 7–3
Power-up Conditions and Memory Initialization ....................................................................... 7–4
Using M4K Memory .............................................................................................................................. 7–4
Implementing Single-Port Mode .................................................................................................... 7–5
Implementing Simple Dual-Port Mode ......................................................................................... 7–6
Implementing True Dual-Port Mode ............................................................................................ 7–8
Implementing Shift-Register Mode ............................................................................................. 7–11
Implementing ROM Mode ............................................................................................................ 7–12
Implementing FIFO Buffers .......................................................................................................... 7–12
Clock Modes ......................................................................................................................................... 7–13
Independent Clock Mode .............................................................................................................. 7–13
Input/Output Clock Mode ........................................................................................................... 7–15
Read/Write Clock Mode ............................................................................................................... 7–17
Single-Port Mode ............................................................................................................................ 7–18
Synchronous and Pseudo-Asynchronous Modes ........................................................................... 7–19
Read-during-Write Operation at the Same Address ...................................................................... 7–20
Same-Port Read-during-Write Mode .......................................................................................... 7–20
Mixed-Port Read-during-Write Mode ........................................................................................ 7–21
Conclusion ............................................................................................................................................ 7–22
Referenced Documents ....................................................................................................................... 7–23
Document Revision History ............................................................................................................... 7–23
Section IV. I/O Standards
Revision History .................................................................................................................................... 8–1
Chapter 8. Using Selectable I/O Standards in Cyclone Devices
Introduction ............................................................................................................................................ 8–1
Supported I/O Standards ..................................................................................................................... 8–2
3.3-V LVTTL (EIA/JEDEC Standard JESD8-B) ............................................................................ 8–3
3.3-V LVCMOS (EIA/JEDEC Standard JESD8-B) ....................................................................... 8–3
2.5-V LVTTL Normal and Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD8-5) ..... 8–3
2.5-V LVCMOS Normal and Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD8-5) . 8–4
Altera Corporation vii
Preliminary
Contents
1.8-V LVTTL Normal and Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD8-7) ..... 8–4
1.8-V LVCMOS Normal and Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD8-7) . 8–4
1.5-V LVCMOS Normal and Wide Voltage Ranges (EIA/JEDEC Standard JESD8-11) ........ 8–5
3.3-V (PCI Special Interest Group (SIG) PCI Local Bus Specification Revision 2.2) ............... 8–5
SSTL-3 Class I and II (EIA/JEDEC Standard JESD8-8) ............................................................... 8–7
SSTL-2 Class I and II (EIA/JEDEC Standard JESD8-9A) ........................................................... 8–7
LVDS (ANSI/TIA/EIA Standard ANSI/TIA/EIA-644) ............................................................ 8–8
Differential SSTL-2 - EIA/JEDEC Standard JESD8-9A ............................................................... 8–9
Cyclone I/O Banks ................................................................................................................................ 8–9
Programmable Current Drive Strength ............................................................................................ 8–12
Hot Socketing ....................................................................................................................................... 8–13
I/O Termination .................................................................................................................................. 8–13
Voltage-Referenced I/O Standard Termination ........................................................................ 8–14
Differential I/O Standard Termination ...................................................................................... 8–14
Pad Placement and DC Guidelines ................................................................................................... 8–14
Differential Pad Placement Guidelines ....................................................................................... 8–14
VREF Pad Placement Guidelines ................................................................................................... 8–15
DC Guidelines ................................................................................................................................. 8–18
Quartus II Software Support .............................................................................................................. 8–18
Settings ............................................................................................................................................. 8–18
Conclusion ............................................................................................................................................ 8–22
More Information ................................................................................................................................ 8–22
References ............................................................................................................................................. 8–22
Referenced Documents ....................................................................................................................... 8–23
Document Revision History ............................................................................................................... 8–23
Chapter 9. High-Speed Differential Signaling in Cyclone Devices
Introduction ............................................................................................................................................ 9–1
Cyclone High-Speed I/O Banks .......................................................................................................... 9–2
Cyclone High-Speed I/O Interface ..................................................................................................... 9–3
Clock Domains .................................................................................................................................. 9–3
LVDS Receiver and Transmitter .......................................................................................................... 9–4
RSDS I/O Standard Support in Cyclone Devices ............................................................................. 9–7
Designing with RSDS ....................................................................................................................... 9–9
RSDS Software Support ................................................................................................................. 9–10
High-Speed I/O Timing in Cyclone Devices .................................................................................. 9–11
LVDS Receiver and Transmitter Termination ................................................................................. 9–15
Implementing Cyclone LVDS and RSDS I/O Pins in the Quartus II Software .......................... 9–16
Design Guidelines ............................................................................................................................... 9–18
Differential Pad Placement Guidelines ....................................................................................... 9–18
Board Design Considerations ....................................................................................................... 9–18
Conclusion ............................................................................................................................................ 9–19
Referenced Documents ....................................................................................................................... 9–19
Document Revision History ............................................................................................................... 9–20
viii Altera Corporation
Preliminary
Cyclone Device Handbook, Volume 1
Section V. Design Considerations
Revision History .................................................................................................................................. 10–1
Chapter 10. Implementing Double Data Rate I/O Signaling in Cyclone Devices
Introduction .......................................................................................................................................... 10–1
Double Data Rate Input ...................................................................................................................... 10–1
Double Data Rate Output ................................................................................................................... 10–2
Bidirectional Double Data Rate ......................................................................................................... 10–3
DDR Memory Support ........................................................................................................................ 10–4
Conclusion ............................................................................................................................................ 10–4
Referenced Documents ....................................................................................................................... 10–4
Document Revision History ............................................................................................................... 10–5
Chapter 11. Using Cyclone Devices in Multiple-Voltage Systems
Introduction .......................................................................................................................................... 11–1
I/O Standards ...................................................................................................................................... 11–1
MultiVolt I/O Operation .................................................................................................................... 11–2
5.0-V Device Compatibility ................................................................................................................ 11–3
Hot-Socketing ....................................................................................................................................... 11–6
Devices Can Be Driven before Power-Up ................................................................................... 11–6
I/O Pins Remain Tri-Stated during Power-Up .......................................................................... 11–6
Signal Pins Do Not Drive the VCCIO or VCCINT Power Supplies .............................................. 11–6
Power-Up Sequence ............................................................................................................................ 11–7
Power-On Reset ................................................................................................................................... 11–7
Conclusion ............................................................................................................................................ 11–8
Document Revision History ............................................................................................................... 11–8
Chapter 12. Designing with 1.5-V Devices
Introduction .......................................................................................................................................... 12–1
Power Sequencing and Hot Socketing ............................................................................................. 12–1
Using MultiVolt I/O Pins ................................................................................................................... 12–2
Voltage Regulators .............................................................................................................................. 12–3
Linear Voltage Regulators ............................................................................................................. 12–4
Switching Voltage Regulators ...................................................................................................... 12–6
Maximum Output Current ........................................................................................................... 12–8
Selecting Voltage Regulators ........................................................................................................ 12–8
Voltage Divider Network ............................................................................................................ 12–10
1.5-V Regulator Circuits .............................................................................................................. 12–10
1.5-V Regulator Application Examples .......................................................................................... 12–19
Synchronous Switching Regulator Example ............................................................................ 12–20
Board Layout ...................................................................................................................................... 12–21
Split-Plane Method ....................................................................................................................... 12–23
Conclusion .......................................................................................................................................... 12–24
References ........................................................................................................................................... 12–24
Referenced Documents ..................................................................................................................... 12–25
Document Revision History ............................................................................................................. 12–25
Altera Corporation ix
Preliminary
Contents
Section VI. Configuration
Revision History .................................................................................................................................. 13–1
Chapter 13. Configuring Cyclone FPGAs
Introduction .......................................................................................................................................... 13–1
Device Configuration Overview ....................................................................................................... 13–1
Data Compression ............................................................................................................................... 13–3
Configuration Schemes ....................................................................................................................... 13–8
Active Serial Configuration (Serial Configuration Devices) .................................................... 13–8
Passive Serial Configuration ....................................................................................................... 13–18
JTAG-Based Configuration ......................................................................................................... 13–31
Combining Configuration Schemes ................................................................................................ 13–45
Active Serial and JTAG ................................................................................................................ 13–45
Device Configuration Pins ............................................................................................................... 13–46
Referenced Documents ..................................................................................................................... 13–50
Document Revision History ............................................................................................................. 13–51
Chapter 14. Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and
EPCS128) Data Sheet
Introduction .......................................................................................................................................... 14–1
Functional Description ........................................................................................................................ 14–2
Accessing Memory in Serial Configuration Devices ................................................................. 14–7
Active Serial FPGA Configuration .................................................................................................... 14–8
Serial Configuration Device Memory Access ................................................................................ 14–12
Memory Array Organization ...................................................................................................... 14–12
Operation Codes ........................................................................................................................... 14–20
Power and Operation ........................................................................................................................ 14–33
Power Mode .................................................................................................................................. 14–33
Power-On Reset ............................................................................................................................ 14–34
Error Detection ............................................................................................................................. 14–34
Timing Information ........................................................................................................................... 14–35
Programming and Configuration File Support ............................................................................. 14–38
Operating Conditions ....................................................................................................................... 14–39
Pin Information .................................................................................................................................. 14–41
Package ................................................................................................................................................ 14–43
Ordering Code ................................................................................................................................... 14–44
Referenced Documents ..................................................................................................................... 14–44
Document Revision History ............................................................................................................. 14–44
Section VII. Cyclone Device Package Information
Revision History .................................................................................................................................. 15–1
Chapter 15. Package Information for Cyclone Devices
Introduction .......................................................................................................................................... 15–1
x Altera Corporation
Preliminary
Cyclone Device Handbook, Volume 1
Device and Package Cross Reference ............................................................................................... 15–1
Thermal Resistance .............................................................................................................................. 15–2
Package Outlines ................................................................................................................................. 15–2
Document Revision History ............................................................................................................... 15–3
Altera Corporation xi
Chapter Revision Dates
The chapters in this book, Cyclone Device Handbook, Volume 1, were revised on the following dates.
Where chapters or groups of chapters are available separately, part numbers are listed.
Chapter 1. Introduction
Revised: May 2008
Part number: C51001-1.5
Chapter 2. Cyclone Architecture
Revised: May 2008
Part number: C51002-1.6
Chapter 3. Configuration and Testing
Revised: May 2008
Part number: C51003-1.4
Chapter 4. DC and Switching Characteristics
Revised: May 2008
Part number: C51004-1.7
Chapter 5. Reference and Ordering Information
Revised: May 2008
Part number: C51005-1.4
Chapter 6. Using PLLs in Cyclone Devices
Revised: May 2008
Part number: C51006-1.5
Chapter 7. On-Chip Memory Implementations Using Cyclone Memory Blocks
Revised: May 2008
Part number: C51007-1.4
Chapter 8. Using Selectable I/O Standards in Cyclone Devices
Revised: May 2008
Part number: C51008-1.6
Chapter 9. High-Speed Differential Signaling in Cyclone Devices
Revised: May 2008
Part number: C51009-1.6
xii Altera Corporation
Cyclone Device Handbook, Volume 1
Chapter 10. Implementing Double Data Rate I/O Signaling in Cyclone Devices
Revised: May 2008
Part number: C51010-1.2
Chapter 11. Using Cyclone Devices in Multiple-Voltage Systems
Revised: May 2008
Part number: C51011-1.2
Chapter 12. Designing with 1.5-V Devices
Revised: May 2008
Part number: C51012-1.4
Chapter 13. Configuring Cyclone FPGAs
Revised: May 2008
Part number: C51013-1.8
Chapter 14. Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data
Sheet
Revised: May 2008
Part number: C51014-3.1
Chapter 15. Package Information for Cyclone Devices
Revised: May 2008
Part number: C52006-1.3
Altera Corporation xiii
Preliminary
About this Handbook
This handbook provides comprehensive information about the Altera®
Cyclone® family of devices.
How to Find
Information
You can find more information in the following ways:
■The Adobe Acrobat Find feature, which searches the text of a PDF
document. Click the binoculars toolbar icon to open the Find dialog
box.
■Acrobat bookmarks, which serve as an additional table of contents in
PDF documents.
■Thumbnail icons, which provide miniature previews of each page,
provide a link to the pages.
■Numerous links, shown in green text, which allow you to jump to
related information.
How to Contact
Altera
For the most up-to-date information about Altera products, refer to the
following table.
Contact (1) Contact Method Address
Technical support Website www.altera.com/support
Technical training Website www.altera.com/training
Email custrain@altera.com
Product literature Website www.altera.com/literature
Altera literature services Email literature@altera.com
Non-technical support (General)
(Software Licensing)
Email nacomp@altera.com
Email authorization@altera.com
Note to table:
(1) You can also contact your local Altera sales office or sales representative.
xiv Altera Corporation
Preliminary
Cyclone Device Handbook, Volume 1
Typographic
Conventions
This document uses the typographic conventions shown below.
Visual Cue Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold
type. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial Capital
Letters
Document titles are shown in italic type with initial capital letters. Example: AN
75: High-Speed Board Design.
Italic type Internal timing parameters and variables are shown in italic type.
Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.
Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title” References to sections within a document and titles of on-line help topics are
shown in quotation marks. Example: “Typographic Conventions.”
Courier type Signal and port names are shown in lowercase Courier type. Examples: data1,
tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in
Courier.
1., 2., 3., and
a., b., c., etc.
Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■●• Bullets are used in a list of items when the sequence of the items is not important.
v The checkmark indicates a procedure that consists of one step only.
1 The hand points to information that requires special attention.
r The angled arrow indicates you should press the Enter key.
f The feet direct you to more information on a particular topic.
Altera Corporation Section I–1
Preliminary
Section I. Cyclone FPGA
Family Data Sheet
This section provides designers with the data sheet specifications for
Cyclone® devices. The chapters contain feature definitions of the internal
architecture, configuration and JTAG boundary-scan testing information,
DC operating conditions, AC timing parameters, a reference to power
consumption, and ordering information for Cyclone devices.
This section contains the following chapters:
■Chapter 1. Introduction
■Chapter 2. Cyclone Architecture
■Chapter 3. Configuration and Testing
■Chapter 4. DC and Switching Characteristics
■Chapter 5. Reference and Ordering Information
Revision History Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the complete handbook.
Section I–2 Altera Corporation
Preliminary
Revision History Cyclone Device Handbook, Volume 1
Altera Corporation 1–1
May 2008 Preliminary
1. Introduction
Introduction The Cyclone® field programmable gate array family is based on a 1.5-V,
0.13-μm, all-layer copper SRAM process, with densities up to
20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like
phase-locked loops (PLLs) for clocking and a dedicated double data rate
(DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)
memory requirements, Cyclone devices are a cost-effective solution for
data-path applications. Cyclone devices support various I/O standards,
including LVDS at data rates up to 640 megabits per second (Mbps), and
66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),
for interfacing with and supporting ASSP and ASIC devices. Altera also
offers new low-cost serial configuration devices to configure Cyclone
devices.
Features The Cyclone device family offers the following features:
■2,910 to 20,060 LEs, see Table 1–1
■Up to 294,912 RAM bits (36,864 bytes)
■Supports configuration through low-cost serial configuration device
■Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
■Support for 66- and 33-MHz, 64- and 32-bit PCI standard
■High-speed (640 Mbps) LVDS I/O support
■Low-speed (311 Mbps) LVDS I/O support
■311-Mbps RSDS I/O support
■Up to two PLLs per device provide clock multiplication and phase
shifting
■Up to eight global clock lines with six clock resources available per
logic array block (LAB) row
■Support for external memory, including DDR SDRAM (133 MHz),
FCRAM, and single data rate (SDR) SDRAM
■Support for multiple intellectual property (IP) cores, including
Altera® MegaCore® functions and Altera Megafunctions Partners
Program (AMPPSM) megafunctions.
Table 1–1. Cyclone Device Features (Part 1 of 2)
Feature EP1C3 EP1C4 EP1C6 EP1C12 EP1C20
LEs 2,910 4,000 5,980 12,060 20,060
M4K RAM blocks (128 ×36bits)1317205264
C51001-1.5
1–2 Altera Corporation
Preliminary May 2008
Cyclone Device Handbook, Volume 1
Cyclone devices are available in quad flat pack (QFP) and space-saving
FineLine® BGA packages (see Tables 1–2 through 1–3).
Vertical migration means you can migrate a design from one device to
another that has the same dedicated pins, JTAG pins, and power pins, and
are subsets or supersets for a given package across device densities. The
largest density in any package has the highest number of power pins; you
must use the layout for the largest planned density in a package to
provide the necessary power pins for migration.
For I/O pin migration across densities, cross-reference the available I/O
pins using the device pin-outs for all planned densities of a given package
type to identify which I/O pins can be migrated. The Quartus®II
software can automatically cross-reference and place all pins for you
when given a device migration list. If one device has power or ground
pins, but these same pins are user I/O on a different device that is in the
migration path,the Quartus II software ensures the pins are not used as
user I/O in the Quartus II software. Ensure that these pins are connected
Total RAM bits 59,904 78,336 92,160 239,616 294,912
PLLs 12222
Maximum user I/O pins (1) 104 301 185 249 301
Note to Table 1–1:
(1) This parameter includes global clock pins.
Table 1–1. Cyclone Device Features (Part 2 of 2)
Feature EP1C3 EP1C4 EP1C6 EP1C12 EP1C20
Table 1–2. Cyclone Package Options and I/O Pin Counts
Device 100-Pin TQFP
(1)
144-Pin TQFP
(1), (2)
240-Pin PQFP
(1)
256-Pin
FineLine BGA
324-Pin
FineLine BGA
400-Pin
FineLine BGA
EP1C3 65 104 — — — —
EP1C4————249301
EP1C6 — 98 185 185 — —
EP1C12 — — 173 185 249 —
EP1C20————233301
Notes to Table 1– 2 :
(1) TQFP: thin quad flat pack.
PQFP: plastic quad flat pack.
(2) Cyclone devices support vertical migration within the same package (i.e., designers can migrate between the
EP1C3 device in the 144-pin TQFP package and the EP1C6 device in the same package).
Altera Corporation 1–3
May 2008 Preliminary
Document Revision History
to the appropriate plane on the board. The Quartus II software reserves
I/O pins as power pins as necessary for layout with the larger densities
in the same package having more power pins.
Document
Revision History
Table 1–4 shows the revision history for this document.
Table 1–3. Cyclone QFP and FineLine BGA Package Sizes
Dimension 100-Pin
TQFP
144-Pin
TQFP
240-Pin
PQFP
256-Pin
FineLine
BGA
324-Pin
FineLine
BGA
400-Pin
FineLine
BGA
Pitch (mm) 0.5 0.5 0.5 1.0 1.0 1.0
Area (mm2)256 484 1,024 289 361 441
Length ×width
(mm ×mm)
16×16 22×22 34.6×34.6 17×17 19×19 21×21
Table 1–4. Document Revision History
Date and
Document
Version
Changes Made Summary of Changes
May 2008
v1.5
Minor textual and style changes. —
January 2007
v1.4
Added document revision history. —
August 2005
v1.3
Minor updates. —
October 2003
v1.2
Added 64-bit PCI support information. —
September
2003 v1.1
●Updated LVDS data rates to 640 Mbps from 311 Mbps.
●Updated RSDS feature information.
—
May 2003 v1.0 Added document to Cyclone Device Handbook. —
1–4 Altera Corporation
Preliminary May 2008
Cyclone Device Handbook, Volume 1
Altera Corporation 2–1
May 2008 Preliminary
2. Cyclone Architecture
Functional
Description
Cyclone® devices contain a two-dimensional row- and column-based
architecture to implement custom logic. Column and row interconnects
of varying speeds provide signal interconnects between LABs and
embedded memory blocks.
The logic array consists of LABs, with 10 LEs in each LAB. An LE is a
small unit of logic providing efficient implementation of user logic
functions. LABs are grouped into rows and columns across the device.
Cyclone devices range between 2,910 to 20,060 LEs.
M4K RAM blocks are true dual-port memory blocks with 4K bits of
memory plus parity (4,608 bits). These blocks provide dedicated true
dual-port, simple dual-port, or single-port memory up to 36-bits wide at
up to 250 MHz. These blocks are grouped into columns across the device
in between certain LABs. Cyclone devices offer between 60 to 288 Kbits of
embedded RAM.
Each Cyclone device I/O pin is fed by an I/O element (IOE) located at the
ends of LAB rows and columns around the periphery of the device. I/O
pins support various single-ended and differential I/O standards, such as
the 66- and 33-MHz, 64- and 32-bit PCI standard and the LVDS I/O
standard at up to 640 Mbps. Each IOE contains a bidirectional I/O buffer
and three registers for registering input, output, and output-enable
signals. Dual-purpose DQS, DQ, and DM pins along with delay chains
(used to phase-align DDR signals) provide interface support with
external memory devices such as DDR SDRAM, and FCRAM devices at
up to 133 MHz (266 Mbps).
Cyclone devices provide a global clock network and up to two PLLs. The
global clock network consists of eight global clock lines that drive
throughout the entire device. The global clock network can provide
clocks for all resources within the device, such as IOEs, LEs, and memory
blocks. The global clock lines can also be used for control signals. Cyclone
PLLs provide general-purpose clocking with clock multiplication and
phase shifting as well as external outputs for high-speed differential I/O
support.
Figure 2–1 shows a diagram of the Cyclone EP1C12 device.
C51002-1.6
2–2 Altera Corporation
Preliminary May 2008
Cyclone Device Handbook, Volume 1
Figure 2–1. Cyclone EP1C12 Device Block Diagram
The number of M4K RAM blocks, PLLs, rows, and columns vary per
device. Table 2–1 lists the resources available in each Cyclone device.
Logic Array
PLL
IOEs
M4K Blocks
EP1C12 Device
Table 2–1. Cyclone Device Resources
Device
M4K RAM
PLLs LAB Columns LAB Rows
Columns Blocks
EP1C3 1 13 1 24 13
EP1C4 1 17 2 26 17
EP1C6 1 20 2 32 20
EP1C12 2 52 2 48 26
EP1C20 2 64 2 64 32
Altera Corporation 2–3
May 2008 Preliminary
Logic Array Blocks
Logic Array
Blocks
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local
interconnect, look-up table (LUT) chain, and register chain connection
lines. The local interconnect transfers signals between LEs in the same
LAB. LUT chain connections transfer the output of one LE's LUT to the
adjacent LE for fast sequential LUT connections within the same LAB.
Register chain connections transfer the output of one LE's register to the
adjacent LE's register within a LAB. The Quartus®II Compiler places
associated logic within a LAB or adjacent LABs, allowing the use of local,
LUT chain, and register chain connections for performance and area
efficiency. Figure 2–2 details the Cyclone LAB.
Figure 2–2. Cyclone LAB Structure
LAB Interconnects
The LAB local interconnect can drive LEs within the same LAB. The LAB
local interconnect is driven by column and row interconnects and LE
outputs within the same LAB. Neighboring LABs, PLLs, and M4K RAM
blocks from the left and right can also drive a LAB's local interconnect
through the direct link connection. The direct link connection feature
minimizes the use of row and column interconnects, providing higher
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Row Interconnect
Column Interconnect
Local InterconnectLAB
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
2–4 Altera Corporation
Preliminary May 2008
Cyclone Device Handbook, Volume 1
performance and flexibility. Each LE can drive 30 other LEs through fast
local and direct link interconnects. Figure 2–3 shows the direct link
connection.
Figure 2–3. Direct Link Connection
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its LEs.
The control signals include two clocks, two clock enables, two
asynchronous clears, synchronous clear, asynchronous preset/load,
synchronous load, and add/subtract control signals. This gives a
maximum of 10 control signals at a time. Although synchronous load and
clear signals are generally used when implementing counters, they can
also be used with other functions.
Each LAB can use two clocks and two clock enable signals. Each LAB's
clock and clock enable signals are linked. For example, any LE in a
particular LAB using the labclk1 signal will also use labclkena1. If
the LAB uses both the rising and falling edges of a clock, it also uses both
LAB-wide clock signals. Deasserting the clock enable signal will turn off
the LAB-wide clock.
Each LAB can use two asynchronous clear signals and an asynchronous
load/preset signal. The asynchronous load acts as a preset when the
asynchronous load data input is tied high.
LAB
Direct link
interconnect
to right
Direct link interconnect from
right LAB, M4K memory
block, PLL, or IOE output
Direct link interconnect from
left LAB, M4K memory
block, PLL, or IOE output
Local
Interconnect
Direct link
interconnect
to left
Altera Corporation 2–5
May 2008 Preliminary
Logic Elements
With the LAB-wide addnsub control signal, a single LE can implement a
one-bit adder and subtractor. This saves LE resources and improves
performance for logic functions such as DSP correlators and signed
multipliers that alternate between addition and subtraction depending
on data.
The LAB row clocks [5..0] and LAB local interconnect generate the
LAB-wide control signals. The MultiTrackTM interconnect's inherent low
skew allows clock and control signal distribution in addition to data.
Figure 2–4 shows the LAB control signal generation circuit.
Figure 2–4. LAB-Wide Control Signals
Logic Elements The smallest unit of logic in the Cyclone architecture, the LE, is compact
and provides advanced features with efficient logic utilization. Each LE
contains a four-input LUT, which is a function generator that can
implement any function of four variables. In addition, each LE contains a
programmable register and carry chain with carry select capability. A
single LE also supports dynamic single bit addition or subtraction mode
selectable by a LAB-wide control signal. Each LE drives all types of
interconnects: local, row, column, LUT chain, register chain, and direct
link interconnects. See Figure 2–5.
labclkena1
labclk2labclk1
labclkena2
asyncload
or labpre
syncload
Dedicated
LAB Row
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect labclr1
labclr2
synclr
addnsub
6
2–6 Altera Corporation
Preliminary May 2008
Cyclone Device Handbook, Volume 1
Figure 2–5. Cyclone LE
Each LE's programmable register can be configured for D, T, JK, or SR
operation. Each register has data, true asynchronous load data, clock,
clock enable, clear, and asynchronous load/preset inputs. Global signals,
general-purpose I/O pins, or any internal logic can drive the register's
clock and clear control signals. Either general-purpose I/O pins or
internal logic can drive the clock enable, preset, asynchronous load, and
asynchronous data. The asynchronous load data input comes from the
data3 input of the LE. For combinatorial functions, the LUT output
bypasses the register and drives directly to the LE outputs.
Each LE has three outputs that drive the local, row, and column routing
resources. The LUT or register output can drive these three outputs
independently. Two LE outputs drive column or row and direct link
routing connections and one drives local interconnect resources. This
allows the LUT to drive one output while the register drives another
output. This feature, called register packing, improves device utilization
because the device can use the register and the LUT for unrelated
labclk1
labclk2
labclr2
labpre/aload
Carry-In1
Carry-In0
LAB Carry-In
Clock &
Clock Enable
Select
LAB Carry-Out
Carry-Out1
Carry-Out0
Look-Up
Tab l e
(LUT)
Carry
Chain
Row, column,
and direct link
routing
Row, column,
and direct link
routing
Programmable
Register
PRN/ALD
CLRN
DQ
ENA
Register Bypass
Packed
Register Select
Chip-Wide
Reset
labclkena1
labclkena2
Synchronous
Load and
Clear Logic
LAB-wide
Synchronous
Load LAB-wide
Synchronous
Clear
Asynchronous
Clear/Preset/
Load Logic
data1
data2
data3
data4
LUT chain
routing to next LE
labclr1
Local Routing
Register chain
output
AD ATA
addnsub
Register
Feedback
Register chain
routing from
previous LE
Altera Corporation 2–7
May 2008 Preliminary
Logic Elements
functions. Another special packing mode allows the register output to
feed back into the LUT of the same LE so that the register is packed with
its own fan-out LUT. This provides another mechanism for improved
fitting. The LE can also drive out registered and unregistered versions of
the LUT output.
LUT Chain and Register Chain
In addition to the three general routing outputs, the LEs within a LAB
have LUT chain and register chain outputs. LUT chain connections allow
LUTs within the same LAB to cascade together for wide input functions.
Register chain outputs allow registers within the same LAB to cascade
together. The register chain output allows a LAB to use LUTs for a single
combinatorial function and the registers to be used for an unrelated shift
register implementation. These resources speed up connections between
LABs while saving local interconnect resources. “MultiTrack
Interconnect” on page 2–12 for more information on LUT chain and
register chain connections.
addnsub Signal
The LE's dynamic adder/subtractor feature saves logic resources by
using one set of LEs to implement both an adder and a subtractor. This
feature is controlled by the LAB-wide control signal addnsub. The
addnsub signal sets the LAB to perform either A + B or A − B. The LUT
computes addition; subtraction is computed by adding the two's
complement of the intended subtractor. The LAB-wide signal converts to
two's complement by inverting the B bits within the LAB and setting
carry-in = 1 to add one to the least significant bit (LSB). The LSB of an
adder/subtractor must be placed in the first LE of the LAB, where the
LAB-wide addnsub signal automatically sets the carry-in to 1. The
Quartus II Compiler automatically places and uses the adder/subtractor
feature when using adder/subtractor parameterized functions.
LE Operating Modes
The Cyclone LE can operate in one of the following modes:
■Normal mode
■Dynamic arithmetic mode
Each mode uses LE resources differently. In each mode, eight available
inputs to the LE⎯the four data inputs from the LAB local interconnect,
carry-in0 and carry-in1 from the previous LE, the LAB carry-in
from the previous carry-chain LAB, and the register chain connection⎯are
directed to different destinations to implement the desired logic function.
LAB-wide signals provide clock, asynchronous clear, asynchronous
2–8 Altera Corporation
Preliminary May 2008
Cyclone Device Handbook, Volume 1
preset/load, synchronous clear, synchronous load, and clock enable
control for the register. These LAB-wide signals are available in all LE
modes. The addnsub control signal is allowed in arithmetic mode.
The Quartus II software, in conjunction with parameterized functions
such as library of parameterized modules (LPM) functions, automatically
chooses the appropriate mode for common functions such as counters,
adders, subtractors, and arithmetic functions. If required, you can also
create special-purpose functions that specify which LE operating mode to
use for optimal performance.
Normal Mode
The normal mode is suitable for general logic applications and
combinatorial functions. In normal mode, four data inputs from the LAB
local interconnect are inputs to a four-input LUT (see Figure 2–6). The
Quartus II Compiler automatically selects the carry-in or the data3
signal as one of the inputs to the LUT. Each LE can use LUT chain
connections to drive its combinatorial output directly to the next LE in the
LAB. Asynchronous load data for the register comes from the data3
input of the LE. LEs in normal mode support packed registers.
Figure 2–6. LE in Normal Mode
Note to Figure 2–6:
(1) This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain.
data1
4-Input
LUT
data2
data3
cin (from cout
of previous LE)
data4
addnsub (LAB Wide)
clock (LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
aload
(LAB Wide)
ALD/PRE
CLRN
D
Q
ENA
ADATA
sclear
(LAB Wide)
sload
(LAB Wide)
Register chain
connection
LUT chain
connection
Register
chain output
Row, column, and
direct link routing
Row, column, and
direct link routing
Local routing
Register Feedback
(1)
Altera Corporation 2–9
May 2008 Preliminary
Logic Elements
Dynamic Arithmetic Mode
The dynamic arithmetic mode is ideal for implementing adders, counters,
accumulators, wide parity functions, and comparators. An LE in dynamic
arithmetic mode uses four 2-input LUTs configurable as a dynamic
adder/subtractor. The first two 2-input LUTs compute two summations
based on a possible carry-in of 1 or 0; the other two LUTs generate carry
outputs for the two chains of the carry select circuitry. As shown in
Figure 2–7, the LAB carry-in signal selects either the carry-in0 or
carry-in1 chain. The selected chain's logic level in turn determines
which parallel sum is generated as a combinatorial or registered output.
For example, when implementing an adder, the sum output is the
selection of two possible calculated sums:
data1 + data2 + carry-in0
or
data1 + data2 + carry-in1
The other two LUTs use the data1 and data2 signals to generate two
possible carry-out signals⎯one for a carry of 1 and the other for a carry of
0. The carry-in0 signal acts as the carry select for the carry-out0
output and carry-in1 acts as the carry select for the carry-out1
output. LEs in arithmetic mode can drive out registered and unregistered
versions of the LUT output.
The dynamic arithmetic mode also offers clock enable, counter enable,
synchronous up/down control, synchronous clear, synchronous load,
and dynamic adder/subtractor options. The LAB local interconnect data
inputs generate the counter enable and synchronous up/down control
signals. The synchronous clear and synchronous load options are
LAB-wide signals that affect all registers in the LAB. The Quartus II
software automatically places any registers that are not used by the
counter into other LABs. The addnsub LAB-wide signal controls
whether the LE acts as an adder or subtractor.
2–10 Altera Corporation
Preliminary May 2008
Cyclone Device Handbook, Volume 1
Figure 2–7. LE in Dynamic Arithmetic Mode
Note to Figure 2–7:
(1) The addnsub signal is tied to the carry input for the first LE of a carry chain only.
Carry-Select Chain
The carry-select chain provides a very fast carry-select function between
LEs in dynamic arithmetic mode. The carry-select chain uses the
redundant carry calculation to increase the speed of carry functions. The
LE is configured to calculate outputs for a possible carry-in of 0 and
carry-in of 1 in parallel. The carry-in0 and carry-in1 signals from a
lower-order bit feed forward into the higher-order bit via the parallel
carry chain and feed into both the LUT and the next portion of the carry
chain. Carry-select chains can begin in any LE within a LAB.
The speed advantage of the carry-select chain is in the parallel
pre-computation of carry chains. Since the LAB carry-in selects the
precomputed carry chain, not every LE is in the critical path. Only the
propagation delays between LAB carry-in generation (LE 5 and LE 10) are
now part of the critical path. This feature allows the Cyclone architecture
to implement high-speed counters, adders, multipliers, parity functions,
and comparators of arbitrary width.
data1 LUT
data2
data3
addnsub
(LAB Wide)
clock (LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
ALD/PRE
CLRN
D
Q
ENA
ADATA
Register chain
connection
LUT
LUT
LUT
Carry-Out1Carry-Out0
LAB Carry-In
Carry-In0
Carry-In1
(1)
sclear
(LAB Wide)
sload
(LAB Wide)
LUT chain
connection
Register
chain output
Row, column, and
direct link routing
Row, column, and
direct link routing
Local routing
aload
(LAB Wide)
Register Feedback