CS4412-CNZ - Cirrus Logic, Inc.

http://www.cirrus.com

Advance Product Information This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

30 W Quad Half-Bridge Digital Amplifier Power Stage

Features

Configurable Outputs (10% THD+N)

– 2 x 15 W into 8 Ω, Full-Bridge

– 1 x 30 W into 4 Ω, Parallel Full-Bridge

– 4 x 7 W into 4 Ω, Half-Bridge

– 2 x 7 W into 4 Ω, Half-Bridge + 1 x 15 W

into 8 Ω, Full-Bridge

Space-Efficient Thermally-Enhanced QFN

– No External Heat Sink Required

> 100 dB Dynamic Range - System Level

0.1% THD+N @ 1 W - System Level

Built-In Protection with Error Reporting

– Over-current

– Thermal Warning and Overload

– Under-voltage

+9 V to +18 V High Voltage Supply

PWM Popguard® for Quiet Startup

High Efficiency (85%)

Low RDS(ON)

Low Quiescent Current

Low Power Standby Mode

Common Applications

Integrated Digital Televisions

Portable Docking Stations

Mini/Micro Shelf Systems

Powered Desktop Speakers

General Description

The CS441 2 is a hig h-efficie ncy pow er stage for di gital

Class-D amplifiers designed to input PWM signa ls from

a modulator such as the CS4525. The power stage out-

puts can be configured as four half-bridge channels, two

half-bridge channels and one full-bridge channel, two

full-bridge channels, or one parallel full-bridge channel.

The CS4412 integrates on-chip over-current, under-

voltage, over-temperature protection and error report-

ing as well as a thermal warning indicator. The low

RDS(ON) outputs can source up to 2.4 A peak current,

delivering 85% efficiency. This efficiency provides for a

small device package and lower power supplies.

The CS4412 is available in a 48-pin QFN package in

Commercial grade (-40 to +70° C). The CRD4412 cu s-

tomer reference design is also available. Please refer to

“Ordering Information” on page 22 for complete order-

ing information.

VP Amplifier

Out 1

Amplifier

Out 2

PGND

Amplifier

Out 3

Amplifier

Out 4

Gate

Drive

Gate

Drive

Gate

Drive

Gate

Drive

2.5 V to 5 V 9 V to 18 V

In 1 Non-Overlap

Time Insertion

Non-Overlap

Time Insertion

Non-Overlap

Time Insertion

Non-Overlap

Time Insertion

Protection &

Error Reporting

In 2

In 3

In 4

Current &

Thermal Data

Control Logic

Hardware

Configuration

Reset

Mode

Configuration

SEPTEMBER '06

DS749A1

CS4412

2DS749A1
CS4412
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 2
2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 4
RECOMMENDED OPERATING CONDITIONS .................................................................................... 4
ABSOLUTE MAXIMUM RATINGS  ........................................................................................................ 4
PWM POWER OUTPUT CHARACTERISTICS ..................................................................................... 5
DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6
DIGITAL INTERFACE SPECIFICATIONS ............................................................................................. 6
DIGITAL I/O PIN CHARACTERISTICS  ................................................................................................. 7
3. TYPICAL CONNECTION DIAGRAMS   ................................................................................................. 8
4. APPLICATIONS  ................................................................................................................................... 12
4.1 Overview ........................................................................................................................................ 12
4.2 Reset and Power-Up .. .... ... ... ... .... ................ ... ... ... .... ... ... ... .... ... ... ... ... .... ... ................ ... ... ................ 12
4.2.1 PWM Popguard Transient Control  . .... ... ... ................ .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 12
4.2.2 Recommended Power-Up Sequence .................................................................................... 12
4.2.3  Recommended Power-Down Sequence .............................. ................ .... ... ... ... ... .... ... ... ... ... 13
4.3 Output Mode Configuration ............................................................................................................ 13
4.4 Output Filters  ................................................................................................................................. 14
4.4.1 Half-Bridge Output Filter ........................................................................................................ 14
4.4.2 Full-Bridge Output Filter (Stereo or Parallel) ......................................................................... 15
4.5 Device Protection and Error Reporting  .......................................................................................... 16
4.5.1 Over-current Protection ......................... ... ................ .... ... ... ... ... .... ... ................ ... ... .... ... ......... 16
4.5.2 Thermal Warning, Thermal Error, and Under-Volt age Error  ................................................. 16
5. POWER SUPPLY, GROUNDING, AND PCB LAYOUT ....................................................................... 17
5.1 Power Supply and Grounding ........................................................................................................ 17
5.1.1 Integrated VD Regulator ........................................................................................................ 17
5.2 QFN Thermal Pad .......................................................................................................................... 17
6. PARAMETER DEFINITIONS ................................................................................................................ 18
7. PACKAGE DIMENSIONS  .................................................................................................................... 19
8. THERMAL CHARACTERISTICS  ......................................................................................................... 20
8.1 Thermal Flag .................................................................................................................................. 20
9. ORDERING INFORMATION  ................................................................................................................ 21
10. REVISION HISTORY .......................................................................................................................... 21
LIST OF FIGURES
Figure 1.Stereo Full-Bridge Typical Connection Diagram ........................................................................... 8
Figure 2.2.1 Channel Typical Configuration Diagram  ................................................................................. 9
Figure 3.4-Channel Half-Bridge Typical Connec tion Diagram ............... ... ... .... ... ... ... .... ... ... ... ................... 10
Figure 4.Mono Parallel Full-Bridge Typic al Connection Diagram  .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 11
Figure 5.Output Filter - Half-Bridge ........................................................................................................... 14
Figure 6.Output Filter - Full-Bridge ............................................................................................................ 15
LIST OF TABLES
Table 1. I/O Power Rails ............................................................................................................................. 7
Table 2. Output Mode Configuration Options ............................................................................................ 13
Table 3. Low-Pass Filter Components - Half-Bridge ................................................................................. 14
Table 4. DC-Blocking Capacitors Values - Half-Bridge ............................................................................. 15
Table 5. Low-Pass Filter Components - Full-Bridge  ................................................................................. 15
Table 6. Over-current Error Conditions ..................................................................................................... 16
Table 7. Thermal and Under-Voltage Error Conditions ............................................................................. 16
Table 8. VD Supply Level Indication ......................................................................................................... 17

DS749A1 3

CS4412

1. PIN DESCRIPTION

Pin Name Pin # Pin Description

CNFG0

CNFG1

CNFG2

Out Configuratio n Select (Input) - Used to set the PWM output configuration mode. See “Output

Mode Configuration” on page 14.

IN1

IN2

IN3

IN4

PWM Input (Input) - Inputs from a PWM modulator.

RST1/2

RST3/4 8

46 Reset Input (Input) - Reset inpu ts for channel s 1/2 and 3/4 respectively. Active low.

LVD 9VD Voltage Level Indicator (Input) - Identifies the voltage level attached to VD. When applying

5.0 V to VD, LVD must be connected to VD. When applying 2.5 V or 3.3 V to VD, LVD must be

GND.

VD_REG 11 Core Digital Power (Output) - Filter connection for the internally generated power supply for the

low voltage digital circuitry.

VD 12 Digita l Power (Input) - Low voltage power supply for internal logic.

VA_REG 13 Core Analog Power (Output) - Filter connection for internally generated power supply for the low

voltage analog circuitry

1413

15 16 17 18 19 20

424344

464748

Top-Down View

48-Pin QFN Package

37383940

21 22 23 24

GND

RST34

RAMP

ERROC34

ERROC12

TWR

GND

CNFG0

CNFG1

CNFG2

IN1

IN2

RST12

OUT1

PGND

OUT2

OUT3

LVD

VD_REG

PGND

OUT4

OCREF

PGND

RAMP_CAP

ERRUVTE

IN3

IN4

GND

VA_REG

CS4412

4DS749A1

CS4412

OCREF 21 Over-current Reference (Input) - Sets over-current trip level. Connect pin through a resistor to

GND. See “Device Protection and Error Reporting” on page 17. This pins should no t be left float-

ing.

RAMP_CAP 24 Output Ramp Capacitor (Input) - Sets the output ramp time for half-bridge configured outputs.

GND

10,14

15,16

17,18

19,20

47,48

Ground (Input) - Ground for the internal logic and I/O. These pins should be connected to the

common system ground.

VP 25,30

31,36 High Voltage Output Power (Input) - High voltage power supply for the individual output power

half-bridge devices.

PGND

22,23

27,28

33,34

37,38

39,40

Power Ground (Input) - Ground for the individual output power half-brid ge devices. These pins

should be connected to the common system ground.

OUT4

OUT3

OUT2

OUT1

PWM Output (Output) - Amplified PWM power half-bridge outputs.

TWR 41 Thermal Warning Output (Output) - Thermal warning output. Open drain, active low. See

“Device Protection and Error Reporting” on page 17.

ERRUVTE 42 Thermal and Under-voltage Error Output (Output) - Error flag for thermal shutdown and under-

voltage. Open drain, active low. See “Device Protection and Error Reporting” on page 17

ERROC1/2

ERROC3/4 43

44 Over-current Error Output (Output) - Over-current error flag for the associated outputs. Open

drain, active low. See “Device Protection and Erro r Reporting” on page 17.

RAMP 45 Ramp-up/down Sele ct (Input) - Set high to enable ramping. When set low, ramping is disabl ed.

See “PWM Popguard Transient Control” on page 13.

Pin Name Pin # Pin Description

DS749A1 5

CS4412

2. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

GND=PGND=0 V, all voltages with respect to ground.

ABSOLUTE MAXIMUM RATINGS

GND = PGND = 0 V; all voltages with respect to ground. (Note 1)

Notes: 1. Operation beyond these limits may result in permanent damage to the device.

2. Normal operation is not guaranteed at these extremes.

3. Any pin except supplies. Transient currents of up to ±100 mA on the PWM input pins will not cause

SCR latch-up.

4. The maximum over/under voltage is limited by the input current.

Parameters Symbol Min Nom Max Units

DC Power Supply

Digital and Analog Core VD 2.375 2.5 2.625 V

VD 3.135 3.3 3.465 V

VD 4.75 5.0 5.25 V

Power Stage VP 8.1 19.8 V

Temperature

Ambient Temperature Commercial TA-40 - +70 °C

Junction Temperature TJ-+150°C

Parameters Symbol Min Max Units

DC Power Supply

Power St age Outputs Switching and Under Load

Power Stage No Output Switching

Digital and Analog Core (Note 2)

-0.3

19.8

23.0

6.0

Inputs (Note 2)

Input Current (Note 3)I

in -±10mA

Digital Input Voltage (Note 4)V

IND -0.3 VD + 0.4 V

Temperature (Note 2)

Ambient Operating Temper ature - Power Applied Commercial TA-40 +85 °C

Storage Temperature Tstg -65 +150 °C

6DS749A1

CS4412

PWM POWER OUTPUT CHARACTERISTICS

Test Conditions (unless otherwise specified): GND = PGND = 0 V; All voltages with respect to groun d; T A = 25° C;

VD = 3.3 V; VP = 18 V; RL = 8 Ω for full-bridge, RL = 4 Ω for half-bridge and parallel full-bridge; PWM Switch Rate

= 384 kHz; 10 Hz to 20 kHz Measurement Bandwidth; Input source is CS4525 PWM_SIG outputs; Performance

measurements taken with a full scale 997 Hz sine wave and AES17 filter.

Parameters Symbol Conditions Min Typ Max Units

Power Output per Channel Stereo Full-Bridge

Half-Bridge

Parallel Full-Bridge

THD+N < 10%

THD+N < 1%

THD+N < 10%

THD+N < 1%

THD+N < 10%

THD+N < 1%

5.5

23.5

Total Harmonic Distortion + Noise

Stereo Full-Bridge

Half-Bridge

Parallel Full-Bridge

THD+N

PO = 1 W

PO = 0 dBFS = 11.3 W

PO = 1 W

PO = 0 dBFS = 5.0 W

PO = 1 W

PO = 0 dBFS = 22.6 W

0.1

0.3

0.1

0.3

0.1

0.3

Dynamic Range Stereo Full-Bridge

Half-Bridge

Parallel Full-Bridge

DYR

PO = -60 dBFS, A-We ighted

PO = -60 dBFS, Unweighted

PO = -60 dBFS, A-We ighted

PO = -60 dBFS, Unweighted

PO = -60 dBFS, A-We ighted

PO = -60 dBFS, Unweighted

102

MOSFET On Resistance RDS(ON) Id= 0.5 A, TJ=50°C - 518 615 mΩ

Efficiency h PO = 2 x 11.3 W, RL = 8 Ω-85-%

Minimum Output Pulse Width PWmin No Load - 50 - ns

Rise Time of OUTx trResistive Load - 20 - ns

Fall Time of OUTx tfResistive Load - 20 - ns

PWM Output Over-Current Error Trip Point ICE OCREF = 16.2 kΩ2.4 - - A

Junction Thermal Warning Trip Poin t TTW - 120 - °C

Junction Thermal Error Trip Point TTE - 140 - °C

VP Under-Voltage Error Trip Point VUV 4.5 - - V

Ramp-Up Time - Half-Bridge Configuration TRU Capacitor = 1000 µF - 0.8 - s

Ramp-Down T ime- Half-Bridge Configuration TRD Capacitor = 1000 µF - 50 - s

DS749A1 7

CS4412

DC ELECTRICAL CHARACTERISTICS

GND = PGND = 0 V; All voltages with respect to ground; PWM switch rate = 384 kHz; Unless otherwise specified.

Notes: 5. Normal operation is defined as RSTx/y = H I.

6. All outputs idle.

7. Power-Down Mode is defined as RSTx/y = LOW with all input lines held static.

8. Power supply current increases with increasing PWM switching rates.

DIGITAL INTERFACE SPECIFICATIONS

GND = PGND = 0 V; All voltages with respect to ground; Unless otherwise specified.

Parameters Min Typ Max Units

Normal Operation (Notes 5, 8)

Power Supply Current VD = 3.3 V - 20 - mA

Power Dissipation VD = 3.3 V - 66 - mW

50 % Duty Cycle VP Idle Current (Note 6) VP = 18 V - 20 - mA

Power-Down Mode (Note 7)

Power Supply Current VD = 3 .3 V - 4.3 - mA

Power Supply Current VP = 18 V - 100 - μA

VD_REG Characteristics

Nominal Voltage

DC current source 2.25

-2.5

-2.75

VA_REG Characteristics

Nominal Voltage

DC current source 2.25

-2.5

-2.75

Parameters Symbol Min Max Units

High-Level Input Voltage VIH 0.7*VD_REG VD V

Low-Level Input Voltage VIL - 0.20*VD_REG V

High-Level Output Voltage Io=2 mA VOH 0.90*VD - V

Input Leakage Current Iin -±10μA

Input Capacitance - 8 pF

8DS749A1

CS4412

DIGITAL I/O PIN CHARACTERISTICS

The logic level for each input is set by its corresponding powe r supply and should not exceed the maximum ratings.

Power

Supply Pin

Number Pin Name I/O Driver Receiver

VD 1 CNFG0 Input - 2.5 V-5.0 V

2 CNFG1 Input - 2.5 V-5.0 V

3 CNFG2 Input - 2.5 V-5.0 V

4IN1Input - 2.5V-5.0V

5IN2Input - 2.5V-5.0V

6IN3Input - 2.5V-5.0V

7IN4 Input - 2.5 V-5.0 V

8RST12Input - 2.5 V-5.0 V

9 LVD Input - 2.5 V-5.0 V

41 TWR Output 2.5 V-5.0 V, Open Drain -

42 ERRUVTE Output 2.5 V-5.0 V, Ope n Drain -

43 ERROC12 Output 2.5 V-5.0 V, Open Drain -

44 ERROC34 Output 2.5 V-5.0 V, Open Drain -

45 RAMP Input - 2.5 V-5.0 V

46 RST34 Input/ - 2.5 V-5.0 V

VP 35 OUT1 Output 9 V-18 V Power MOSFET -

32 OUT2 Output 9 V-18 V Power MOSFET -

29 OUT3 Output 9 V-18 V Power MOSFET -

26 OUT4 Output 9 V-18 V Power MOSFET -

Table 1. I/O Power Rails

DS749A1 9

CS4412

3. TYPICAL CONNECTION DIAGRAMS

+9 V to +18 V

313025

470 µF 0. 1 µF 0. 1 µF 0.1 µF 0.1 µF0.1 µF10 µF

+ 3.3 V or +5.0 V

22 28 34 37 38 39 4033

PGND

IN1

GND

VD_REG

0. 1 µF10 µF

IN4

IN2

IN3

RAMP_CAP

VA_REG

0. 1 µF10 µF

OCREF

16.2 k Ω

GND

PGND

GND

PWM1+

PWM2+

PWM3+

PWM4+ Output

Filter

OUT1

Output

Filter

OUT2

OUT3

OUT4

Output

Filter

Output

Filter

RAMP

Hardware

Control

Settings

CNFG2

CNFG1

CNFG0

LVD

System

Control

Logic

ERROC12

ERROC34

ERRUVTE

TWR

RST12

RST34

22 kΩ

Figure 1. Stereo Full-Bridge Typical Connection Diagram

CS4412

10 DS749A1

CS4412

+9 V to +18 V

313025

470 µF 0.1 µF 0. 1 µ F 0.1 µF 0. 1 µ F0.1 µF10 µF

+ 3 .3 V or +5.0 V

22 28 34 37 38 39 4033

PGND

IN1

GND

VD_REG

0. 1 µF10 µF

IN4

IN2

IN3

RAMP_CAP

VA_REG

0.1 µF10 µF

OCREF

16. 2 k Ω

GND

PGND

GND

PWM1+

PWM2+

PWM3+

PWM4+

Output

Filter

OUT3

Output

Filter

OUT4

Output

Filter

OUT1

Output

Filter

OUT2

470 µF 470 µF

System

Control

Logic

ERROC12

ERROC34

ERRUVTE

TWR

RST12

RST34

22 kΩ

22 k Ω

RAMP

Hardware

Control

Settings

CNFG2

CNFG1

CNFG0

LVD

Figure 2. 2.1 Channel Typ ica l Confi gura tio n Dia gra m

CS4412

DS749A1 11

CS4412

+9 V to +18 V

313025

0. 1 µ F 0. 1 µF 0.1 µF 0. 1 µF0.1 µF10 µ F

+3.3 V o r +5.0 V

22 28 34 37 38 39 4033

PGND

IN1

GND

VD_REG

0. 1 µ F10 µF

IN4

IN2

IN3

RAMP_CAP

VA_REG

0.1 µF10 µF

OCREF

16.2 kΩ

GND

PGND

GND

PWM1+

PWM2+

PWM3+

PWM4+

Output

Filter

OUT1

Output

Filter

OUT2

390 pF

470 µF 470 µF

Output

Filter

OUT3

Output

Filter

OUT4

470 µF 470 µF

RAMP

Hardware

Control

Settings

CNFG2

CNFG1

CNFG0

LVD

System

Control

Logic

ERROC12

ERROC34

ERRUVTE

TWR

RST12

RST34

22 kΩ

Figure 3. 4-Channel Half-Bridge Typical Connection Diagram

CS4412

12 DS749A1

CS4412

+9 V to +18 V

313025

470 µF 0. 1 µF 0. 1 µ F 0.1 µF 0.1 µF0.1 µF10 µF

+ 3 .3 V or +5.0 V

22 28 34 37 38 39 4033

PGND

IN1

GND

VD_REG

0. 1 µF10 µ F

IN4

IN2

IN3

RAMP_CAP

VA_REG

0.1 µF10 µF

OCREF

16.2 kΩ

GND

PGND

GND

PWM1+

PWM2+

PWM3+

PWM4+

OUT1

OUT2

OUT3

OUT4

Output

Filter

Output

Filter

System

Control

Logic

ERROC12

ERROC34

ERRUVTE

TWR

RST12

RST34

22 kΩ

RAMP

Hardware

Control

Settings

CNFG2

CNFG1

CNFG0

LVD

Figure 4. Mono Parallel Full-Bridge Typical Connection Diagram

CS4412

DS749A1 13

CS4412

4. APPLICATIONS

4.1 Overview

The CS4412 is a high-efficiency power stage for digital Class-D amplifiers designed to be configured as four

half-bridge chan nels, two half-bridge channels a nd one full-bridg e channel, two full-bridge channels, or on e

parallel full-bridge channel.

The CS4412 integrates on-chip over-current, under-voltage, over-temperature protection and error report-

ing as well as a thermal warning indicator. The low RDS(ON) outputs can source up to 2.4 A peak current,

delivering 85% efficiency. This efficiency provides for smaller device package, no external heat sink require-

ments, and smaller power supplies.

4.2 Reset and Power-Up

Reliable power-up can be a ccomplished by keeping the device in reset until the po wer supplies, clocks, and

configuration pins are stable. It is also recommended that the RSTx/y pin be activated if the voltage supplies

drop below the recommended operating condition to prevent power-glitch- related issues.

When RSTx/y is low, the corresponding channels of the CS4412 enter a low-power mode and all of the

channels’ internal states are reset and the outputs are set to HI-Z. When RSTx/y is high, the de sired mod e

settings will be loaded and the outputs will begin normal operation.

4.2.1 PWM Popguard Transient Control

The CS4412 uses Popguar d technology to minim ize the effects o f output tr ansie nts during powe r-up and

power-down for half-bridge configurations. This technique reduces the audio transients commonly pro-

duced by half-bridge, single-supply amplifiers when implemented with external DC-blocking capacitors

connected in series with the audio outputs.

When the device is configured for ramping (RAMP set high) and RSTx/y is set high, the OUTx/y outputs

will ramp-up to the bias point (VP/2). This gradual voltage ramping allows time for the external DC-block-

ing capacitor to charge to the quiescent voltage, minimizing the power-up transient. The OUTx/y outputs

will not begin normal operation until the ramp has reached the bias point. The INx/y inputs must begin

switching before the ramp cycle begins.

When the device is configured for ramping (RAMP set high) and RSTx/y is set low, the OUTx/y outputs

will begin to slowly ramp down from the bias point to PGND, allowing the DC-blocking ca pacitor to dis-

charge.

The ramp fe ature should on ly be used in quad ha lf-bridg e configuration. It is not necessary to complete a

ramp-up/down sequence before ramping up/down a gain.

4.2.2 Recommended Power-Up Sequence

1. Turn on the system power.

2. Hold RSTx/y low until the power supply and system clocks are stable. In this state, all associated

outputs are HI-Z.

3. Start the PWM modulator output.

4. Once the PWM modulator output is valid, release RSTx/y high. If the CS4412 is configured for

ramping, the outputs will ramp to the bias point and then begin switching normally. If the CS4412 is

not configured for ramping, the outputs will immediately begin switching normally.

14 DS749A1

CS4412

4.2.3 Recommended Power-Down Sequence

1. Mute the logic-level PWM inputs present on IN1 - IN4 by applying 50 % duty-cycle inputs.

2. Set RSTx/y low. If the CS4412 is configured for ramping, the outputs will ramp down to PGND and

then become HI-Z. If the CS4412 is not configured for ramping, the outputs will immediately become

HI-Z.

3. Power down the remainder of the system.

4. Turn off the system power.

4.3 Output Mode Configuration

The CS4412 can be configure d for several modes of operation. Table 2 shows the setting of the CNFG[2:0]

inputs and the correspond ing mode of operation. These pins should remain static during op eration (RSTx/y

set high).

CNFG2 CNFG1 CNFG0 Output Config. Description

0 0 0 Stereo Full-Bridge

Tied Loads IN1 must be inverted from IN2 for full-bridge operation.

IN3 must be inverted from IN4 for full-bridge operation.

0 0 1 Stereo Half-Bridge

and Mono Full-

Bridge Tied Loads

IN1 must be provided for half-bridge operation.

IN2 must be provided for half-bridge operation.

IN3 must be inverted from IN4 for full-bridge operation.

0 1 0 Mono Parallel Full-

Bridge Tied Load IN1 and IN3 must be inverted from IN2 and IN4 for parallel full-

bridge operation.

0 1 1 Quad Half-Bridge

Tied Loads IN1 must be provided for half-bri dge operation.

IN2 must be provided for half-bridge operation.

IN3 must be provided for half-bridge operation.

IN4 must be provided for half-bridge operation.

1 0 0 Stereo Full-Bridge

Tied Loads

With Inversion

IN1 must be provided for full-bridge operation.

Wire IN2 to IN1. IN2 is internally inverted for full-bridge operation.

IN3 must be provided for full-bridge operation.

Wire IN4 to IN3. IN4 is internally inverted for full-bridge operation.

1 0 1 Stereo Half-Bridge

& Mono Full-Bridge

Tied Loads

With Inversion

IN1 must be provided for half-bridge operation.

IN2 must be provided for half-bridge operation.

IN3 must be provided for full-bridge operation.

Wire IN4 to IN3. IN4 is internally inverted for full-bridge operation.

1 1 0 Mono Parallel Full-

Bridge Tied Load

With Inversion

IN1 must be provided for parallel full-bridge operation.

Wire IN4, IN3, and IN2 to IN1.

IN2 and IN4 are internally inverted for parallel full-bridge operation.

1 1 1 Quad Half-Bridge

Tied Loads IN1 must be provided for half-bri dge operation.

IN2 must be provided for half-bridge operation.

IN3 must be provided for half-bridge operation.

IN4 must be provided for half-bridge operation.

Table 2. Output Mode Configuration Options

DS749A1 15

CS4412

4.4 Output Filters

The filter placed after the PWM outputs can greatly affect the output performance. The filter not only reduces

radiated EMI (snubber filter), but also filters high frequency content from the switching output before going

to the speaker (low-pass LC filter).

4.4.1 Half-Bridge Output Filter

Figure 5 shows the output filter for a half-bridge configuration. The transient-voltage suppression circuit

(snubber circui t) is co mpr ise d of a resistor ( 20 Ω, ¼W) and ca pacitors (220 pF) and should be placed as

close as possible to the corresponding PWM output pin to greatly reduce radiated EMI.

The inductor, L1, a nd capacitor, C1, comp rise the low-pass filter. Alo ng with th e nominal load impe dance

of the speaker, these values set the cutoff frequency of the filter. Table 3 shows the compo nent values for

L1 and C1 based on nominal speaker (load) impedance for a corner frequency (-3 dB point) of approxi-

mately 35 kHz.

C2 is the DC-blocking capacitor. Table 4 shows the compone nt values for C2 base d on corner fr equency

(-3 dB point) and a nominal speaker (load) impedances of 4 Ω, 6Ω, and 8Ω. This capacitor should also

be chosen to have a ripple current rating above the amount of current that will passed through it.

Load L1 C1

4Ω22 µH 1.0 µF

6Ω33 µH 0.68 µF

8Ω47 µH 0.47 µF

Table 3. Low-Pass Filter Components - Half-Bridge

PWM

Output

220 pF C1

20 Ω

L1 C2

*Diode is Zetex

ZHCS400 or

equivalent

Figure 5. Output Filter - Half-Bridge

16 DS749A1

CS4412

4.4.2 Full-Bridge Output Filter (Stereo or Parallel)

Figure 6 shows the output filter for a full-bridge configuration. The transient-voltage suppression circuit

(snubber circuit) is comprised of a resistor (20 Ω) and capacitor (330 pF) and should be placed as close

as possible to the corr esponding PWM outp ut pins to greatly reduce radiated EMI. Th e inductors, L1, and

capacitor, C1, com prise the lo w-pass filte r. Along wit h the n ominal load imp edance of the spea ker, these

values set the cutoff frequency of the filter. Table 5 shows the component values based on nominal speak-

er (load) impedance for a corner frequency (-3 dB point) of approximately 35 kHz.

Load Corner Frequency C2

4Ω40 Hz 1000 µF

58 Hz 680 µF

120 Hz 330 µF

6Ω39 Hz 680 µF

68 Hz 390 µF

120 Hz 220 µF

8Ω42 Hz 470 µF

60 Hz 330 µF

110 Hz 180 µF

Table 4. DC-Blocking Capacitors Values - Half-Bridge

Load L1 C1

4Ω10 µH 1.0 µF

6Ω15 µH 0.47 µF

8Ω22 µH 0.47 µF

Table 5. Low-Pass Filter Components - Full-Bridge

330 pF

20 Ω

*Diode is Zetex

ZHCS400 or

equivalent

+ PWM

Output

- PWM

Output

Figure 6. Output Filter - Full-Bridge

DS749A1 17

CS4412

4.5 Device Protection and Error Reporting

The CS4412 has built-in protection circuitry for over-current, under-voltage, and thermal warning/overload

conditions. Th e leve ls of th e ov er -c ur re nt err or , th er mal error, and VP under-voltage trip points are listed

in the PWM Power Output Char acteristics table on page 6. Automatic shut-down will occur whenever any

of these pres et thre sh o lds ar e cr ossed.

Each error and warning pin implements an active-low open-drain driver and requires an external pull-up

for proper operation.

4.5.1 Over-current Protection

Over-current errors are reported on the ERROCx/y pins. For example, an over-current error on OUT1 is

reported by the ERROC1/2 pin. The power output of the cha nnel which is reporting the over -curr ent con-

dition will be set to high-impedance until the error condition has been removed and the RSTx/y signal for

that channel has been toggled from low to high.

4.5.2 Thermal Warning, Thermal Error, and Under-Voltage Error

Table 7 shows the behavior of the TWR an d ERRUVTE pins. When the junction temperature exceeds the

junction thermal warning trip point, the TWR pin will be set low. If the junc tion temperature continues to

increase beyond the junction thermal error trip point, the ERRUVTE pin will be set low. If the voltage on

VP falls below the VP under-voltage error trip point, ERRUVTE will be set low.

When the thermal error or VP under-voltage trip point is crossed, all power outputs will be set to high-

impedance until the error condition has been removed and the RSTx/y signals have been toggled from

low to high.

ERROCx/y Re ported Condition

0 Over-current error on channel x or channel y.

1 Operating current of channel x and y within allowable limits.

Table 6. Over-current Error Conditions

TWR ERRUVTE Reported Condition

0 0 Thermal warning and thermal error and/or under-voltage error.

0 1 Thermal warning only.

1 0 Under-voltage error.

1 1 Junction temperature and VP voltage within normal limits.

Table 7. Ther mal and Under- Voltage Error Conditions

18 DS749A1
CS4412
5. POWER SUPPLY, GROUNDING, AND PCB LAYOUT
5.1 Power Supply and Grounding
The CS4412 requires careful attention to power supply and grounding arrangements if its potential perfor-
mance is to be realized. 
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. It is necessary to decouple the power supply b y placing capacitors  directly
between the power and g round of the CS44 12. Deco upling capacitors should be as close to the pins of the
CS4412 as possible. The lowest value ceramic capacitor should be closest to the p in and should be mou nt-
ed on the same side of the board as the CS4412 to minimize inductance effects. The CRD4412 reference
design demonstrates the optimum layout and power supply arrangements.
5.1.1 Integrated VD Regulator
The CS4412 includes two internal linear regulators, one from the VD supply voltage to provide a fixed
2.5 V supply to its intern al  digi tal b locks, a nd a nother fro m the VD supply voltag e to provide a fixed  2.5 V
supply to its  internal analog block s. The LVD pin must  be set to indicate the voltage present on the VD
pin as shown in Table 8 below.
The output of the di gital regulator is p resented on the VD_ REG pin and may be  used to provide a n exter-
nal device with up to 3mA of current at its nominal output voltage of  2.5 V. T he outpu t o f the an alog  re g-
ulator is pres ented on the  VA_REG pin and mu st only be connected to the bypass capacitors as shown
in the typical connection diagrams. 
If a nominal supply voltage of 2.5 V is used as the VD su pply (see th e Recommended Operating Condi-
tions table on page 5), the VD, VD_REG, and VA_REG pins must all be connected to the VD supply
source. In this configu ration, the  inter nal  regu lator s  ar e b ypassed  an d the e xterna l sup ply source i s  used
to directly drive the internal digital and analog sections.
5.2 QFN Thermal Pad
The CS4412 is available in a compact QFN package. The underside of th e QFN package  reveals a large
metal pad that serves as a thermal relief to provide for ma ximum he at dissipa tion. This pad  must mate with
an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of
thermal vias should be used to  co nnect this cop per  pad to one or more la rg er g round  pla nes on  other PCB
layers. The CRD4412 reference de sign demonstrates the optimum thermal pad and via configuration.
LVD Indicated VD Supply Level
Low 2.5 V or 3.3 V Nominal
High 5 V Nominal
Table 8. VD Supply Level Indication

DS749A1 19

CS4412

6. PARAMETER DEFINITIONS

Dynamic Range (DYR)

The ratio of the rms valu e of th e signa l to th e rms sum o f all ot her sp ectral c ompon ents ove r the specified

bandwidth, typically 20 Hz to 20 kHz. Dynamic Range is a signa l-to-noise ratio measurement over the spec-

ified band width made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer

the measurement to full-scale. This technique ensures that the distortion components are below the noise

level and do not effect the measurement. This measurement technique has been accepted by the Audio

Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Ex-

pressed in decib els .

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified

band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured

at -1 and -20 dBFS as suggested in AES17-1991 Annex A.

20 DS749A1

CS4412

7. PACKAGE DIMENSIONS

Notes: 1. Dimensioning and tolerance per ASME Y4.5M - 1994.

2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and

0.25 mm from the terminal tip.

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A----0.0354----0.901

A1 0.0000 -- 0.0020 0.00 -- 0.05 1

b 0.0118 0.0138 0.0157 0.30 0.35 0.40 1,2

D 0.3543 BSC 9.00 BSC 1

D2 0.2618 0.2677 0.2736 6.65 6.80 6.95 1

E 0.3543 BSC 9.00 BSC 1

E2 0.2618 0.2677 0.2736 6.65 6.80 6.95 1

e 0.0256 BSC 0.65 BSC 1

L 0.0177 0.0217 0.0276 0.45 0.55 0.70 1

JEDEC #: MO-220

Controlling Dimension is Millimeters.

Side View

Bottom View

Top View

Pin #1 ID

bePin #1 ID

48L QFN (9 × 9 MM BODY) PACKAGE DRAWING

DS749A1 21

CS4412

8. THERMAL CHARACTERISTICS

8.1 Thermal Flag

This device is designed to have the metal flag on the bottom of the device soldered directly to a metal plane

on the PCB. To enhance the thermal dissipation capabilities of the system, this metal plane should be cou-

pled with vias to a large metal plane on the backside (and inner ground layer , if applicable) of the PCB.

In either case, it is beneficial to use copper fill in any unused regions inside the PCB layout, especially those

immediately surrounding the CS4412. In addition to improving in electrical performance, this practice also

aids in heat dissipation.

The heat dissipation capability required of the metal plane for a given output power can be calculated as

follows:

θCA = [(TJ(MAX) - TA) / PD] - θJC

where,

θCA = Thermal resistance of the metal plane in °C/Watt

TJ(MAX) = Maximum rated operating junction temperature in °C, equal to 150 °C

TA = Ambient temperature in °C

PD = RMS power dissipation of the device, equal to 0.15*PRMS-IN or 0.176*PRMS-OUT (assuming 85% eff i-

ciency)

θJC = Junction-to-case therma l res ista n ce of the devic e in ° C/ Watt

Parameter Symbol Min Typ Max Units

Junction to Case Thermal Impedance θJC -1-°C/Watt

22 DS749A1

CS4412

9. ORDERING INFORMATION

10.REVISION HISTORY

Product Description Package Pb-Free Grade Temp Range Container Order#

CS4412

30 W Quad Half-

Bridge Digital

Amplifier Power

Stage

48-QFN Yes Commercial -40° to +70°C

Rail CS4412-CNZ

Tape and

Reel CS4412-CNZR

CRD4412 1x30W

Referenc e De si g n

Daughter Card - - - - - CRD4412

CRD4525 2x15W

Referenc e De si g n

Main Board - - - - - CRD4525

Release Changes

A1 Initial Release

Contacting Cirrus Logic Support

For all product questions and inquiries, contact a Cirrus Logic Sales Representative.

To find one nearest you, go to www.cirrus.com.

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