© 2000 Fairchild Semiconductor Corporation DS009472 www.fairchildsemi.com
April 1988
Revised September 2000
74F112 Dual JK Negative Edge-Triggered Flip-Flop
74F112
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The 74F 112 contain s tw o indep enden t, hi gh-sp eed JK f lip-
flops with Direct Set and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Trig-
gering occurs at a voltage level of the clock and is not
directly related to the transition time. The J and K inputs
can change when the clock is in eith er state witho ut affect-
ing the flip-fl op, provided tha t they are in the desired sta te
during the recommended setup and hold times relative to
the falling edge of the clock. A LOW signal on SD or CD
prevents clocking and forces Q or Q HIGH, respectively.
Sim ult a ne o us LO W sign als on SD and CD force both Q and
Q HIGH.
Asynchronous Inputs:
LOW input to SD sets Q to HIGH level
LOW input to CD sets Q to LOW level
Clear and Set are indepe nde nt of clock
Simultaneous LOW on CD and SD makes both Q
and Q HIGH
Ordering Code:
Devices also available in Tape and Reel. Speci fy by appending the s uffix let t er “X” to the o rdering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F112SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F112SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F112PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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74F112
Unit Loading/Fan Out
Truth Table
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
X = Immaterial
= HIGH-to-LOW C loc k Transit ion
Q0(Q0) = Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.
Logic Diagram
(One Half Shown)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names Description U.L. Input IIH/IIL
HIGH/LOW Output IOH/IOL
J1, J2, K1, K2Data Inputs 1.0/1.0 20 µA/−0.6 mA
CP1, CP2Clock Pulse Inputs (Active Falling Edge) 1.0/4.0 20 µA/−2.4 mA
CD1, CD2 Direct Cle ar Inputs (Active LOW) 1.0/5.0 20 µA/−3.0 mA
SD1, SD2 Direct Set Inputs (Active LOW) 1.0/5.0 20 µA/−3.0 mA
Q1, Q2, Q1, Q 2Outputs 50/33.3 −1 mA/20 mA
Inputs Outputs
SDCDCP JKQ Q
LHXXXHL
HLXXXLH
LLXXXHH
HH
hhQ
0Q0
HH
lhL H
HH
hl H L
HH
llQ
0Q0
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74F112
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Eith er v oltage lim it or c urrent limit is sufficie nt to protect inputs.
DC Electrical Characteristics
Storage Temperature −65°C to +150°C
Ambient Tem per atu re und er Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
VCC Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Cu rrent (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standa rd Outp ut −0.5V to VCC
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Ma x) twice the rat ed IOL (mA)
Free Air A mbient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units VCC Conditions
VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal
VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
VOH Output HIGH 10% VCC 2.5 V Min IOH = −1 mA
Voltage 5% VCC 2.7 IOH = −1 mA
VOL Output LOW 10% VCC 0.5 V Min IOL = 20 mA
Voltage
IIH Input HIGH 5.0 µAMaxV
IN = 2.7 V
Current
IBVI Input HIGH Current 7.0 µAMaxV
IN = 7.0 V
Breakdown Test
ICEX Output HIGH 50 µAMaxV
OUT = VCC
Leakage Current
VID Input Leakage 4.75 V 0.0 IID = 1.9 µA
Test All other pins grounded
IOD Output Leakage 3.75 µA0.0
VIOD = 150 mV
Circuit Current All other pins grounded
IIL Input LOW Current −0.6 VIN = 0.5V (Jn, Kn)
−2.4 mA Max VIN = 0.5V (CPn)
−3.0 VIN = 0.5V (CDn, SDn)
IOS Output Short-Circuit Current −60 −150 mA Max VOUT = 0V
ICCH Power Supply Current 12 19 mA Max VO = HIGH
ICCL Power Supply Current 12 19 mA Max VO = LOW
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74F112
AC Electrical Characteristics
AC Operating Requirements
Symbol Parameter
TA = +25°CT
A = 0°C to +70°C
Units
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
fMAX Maximum Clock Frequency 85 105 80 MHz
tPLH Propagation Delay 2.0 5.0 6.5 2.0 7.5 ns
tPHL CPn to Qn or Qn2.0 5.0 6.5 2.0 7.5
tPLH Propagation Delay 2.0 4.5 6.5 2.0 7.5 ns
tPHL CDn, SDn to Qn, Qn2.0 4.5 6.5 2.0 7.5
Symbol Parameter
TA = +25°CT
A = 0°C to +70°C
UnitsVCC = +5.0V VCC = +5.0V
Min Max Min Max
tS(H) Setup Time, HIGH or LOW 4.0 5.0
ns
tS(L) Jn or Kn to CPn3.0 3.5
tH(H) Hold Time, HIGH or LOW 0 0
tH(L) Jn or Kn to CPn00
tW(H) CP Pulse Width 4.5 5.0 ns
tW(L) HIGH or LOW 4.5 5.0
tW(L) Pulse Width, LOW 4.5 5.0 ns
CDn or SDn
tREC Recovery Time 4.0 5.0 ns
SDn, CDn to CP
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74F112
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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74F112
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Sma ll Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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74F112 Dual JK Negative Edge-Triggered Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume an y responsibility for u se of any circuitry descr ibed, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syst ems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instruct ions fo r use pr ovi de d in the l abe ling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A crit ical componen t in any com ponen t of a life s uppor t
device or system whose failure to perform can be rea-
sonabl y e xpec ted to cause th e fa i lure of the l ife s upport
device or system, or to affect its safety or effectiveness.
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