W29GL128CL1B - Winbond Electronics Corporation America

W29GL128C

Publication Release Date: July 28, 2010

Preliminary - Revision A

128M-BIT

3.0-VOLT PARALLEL FLASH MEMORY WITH

PAGE MODE

W29GL128C

Publication Release Date: July 28, 2010

i Preliminary - Revision A

Table of Contents

1 GENERAL DESCRIPTION ......................................................................................................... 1

2 FEATURES ................................................................................................................................. 1

3 PIN CONFIGURATIONS............................................................................................................. 2

4 BLOCK DIAGRAM ...................................................................................................................... 2

5 PIN DESCRIPTION..................................................................................................................... 2

6 ARRAY ARCHITECTURE........................................................................................................... 3

6.1 Sector Address Table ..................................................................................................... 3

7 FUNCTIONAL DESCRIPTION.................................................................................................... 4

7.1 Device Bus Operation..................................................................................................... 4

7.2 Instruction Definitions...................................................................................................... 5

7.2.1 Reading Array Data ..........................................................................................................5

7.2.2 Page Mode Read..............................................................................................................5

7.2.3 Device Reset Operation ...................................................................................................6

7.2.4 Standby Mode ..................................................................................................................6

7.2.5 Output Disable Mode........................................................................................................6

7.2.6 Write Operation ................................................................................................................6

7.2.7 Byte/Word Selection .........................................................................................................7

7.2.8 Automatic Programming of the Memory Array..................................................................7

7.2.9 Erasing the Memory Array................................................................................................8

7.2.10 Erase Suspend/Resume.................................................................................................9

7.2.11 Sector Erase Resume ....................................................................................................9

7.2.12 Program Suspend/Resume ..........................................................................................10

7.2.13 Program Resume .........................................................................................................10

7.2.14 Write Buffer Programming Operation ...........................................................................10

7.2.15 Buffer Write Abort .........................................................................................................11

7.2.16 Accelerated Programming Operation ...........................................................................11

7.2.17 Automatic Select Bus Operation...................................................................................11

7.2.18 Automatic Select Operations ........................................................................................12

7.2.19 Automatic Select Instruction Sequence ........................................................................12

7.2.20 Enhanced Variable IO (EVIO) Control ..........................................................................13

7.2.21 Hardware Data Protection Options ...............................................................................13

7.2.22 Inherent Data Protection...............................................................................................13

7.2.23 Power Supply Decoupling.............................................................................................13

7.3 Enhanced Sector Protect/Un-protect ............................................................................ 14

7.3.1 Lock Register..................................................................................................................15

7.3.2 Individual (Non-Volatile) Protection Mode ......................................................................16

7.4 Security Sector Flash Memory Region ......................................................................... 19

7.4.1 Factory Locked: Security Sector Programmed and Protected at factory ........................19

7.4.2 Customer Lockable: Security Sector Not Programmed or Protected..............................19

7.5 Instruction Definition Tables ......................................................................................... 20

7.6 Common Flash Memory Interface (CFI) Mode ............................................................. 24

7.6.1 Query Instruction and Common Flash memory Interface (CFI) Mode ............................24

W29GL128C

8 ELECTRICAL CHARACTERISTICS......................................................................................... 28

8.1 Absolute Maximum Stress Ratings............................................................................... 28

8.2 Operating Temperature and Voltage ............................................................................ 28

8.3 DC Characteristics ........................................................................................................ 29

8.4 Switching Test Circuits.................................................................................................. 30

8.4.1 Switching Test Waveform...............................................................................................30

8.5 AC Characteristics ........................................................................................................ 31

8.5.1 Instruction Write Operation .............................................................................................32

8.5.2 Read / Reset Operation..................................................................................................33

8.5.3 Erase/Program Operation...............................................................................................35

8.5.4 Write Operation Status ...................................................................................................44

8.5.5 WORD/BYTE CONFIGURATION (#BYTE) ....................................................................48

8.5.6 DEEP POWER DOWN MODE .......................................................................................50

8.5.7 WRITE BUFFER PROGRAM .........................................................................................50

8.6 Recommended Operating Conditions........................................................................... 51

8.6.1 At Device Power-up........................................................................................................51

8.7 Erase and Programming Performance ......................................................................... 52

8.8 Data Retention .............................................................................................................. 52

8.9 Latch-up Characteristics ............................................................................................... 52

8.10 Pin Capacitance............................................................................................................ 52

9 PACKAGE DIMENSIONS ......................................................................................................... 53

9.1 TSOP 56-pin 14x20mm ................................................................................................ 53

9.2 Fortified BGA 64-ball 11x13mm (LAA64) ..................................................................... 54

10 ORDERING INFORMATION..................................................................................................... 55

10.1 Ordering Part Number Definitions................................................................................. 55

10.2 Valid Part Numbers and Top Side Marking .................................................................. 56

11 HISTORY .................................................................................................................................. 57

Figure 3-1 ............................................................................... 2 FBGA-64 TOP VIEW FACE DOWN

Figure 3-2 56-PIN STANDARD TSOP (TOP VIEW)........................................................................ 2

Figure 4-1 Block Diagram................................................................................................................. 2

Figure 7-1 Enhanced Sector Protect/Un-protect IPB Program Algorithm...................................... 14

Figure 7-2 Lock Register Program Algorithm................................................................................. 15

Figure 7-3 IPB Program Algorithm ................................................................................................. 17

Figure 8-1 Maximum Negative Overshoot ..................................................................................... 28

Figure 8-2 Maximum Positive Overshoot ....................................................................................... 28

Figure 8-3 Switch Test Circuit ........................................................................................................ 30

Figure 8-4 Switching Test Waveform ............................................................................................. 30

Figure 8-5 Instruction Write Operation Waveform.......................................................................... 32

Figure 8-6 Read Timing Waveform ................................................................................................ 33

Figure 8-7 #RESET Timing Waveform........................................................................................... 34

Figure 8-8 Automatic Chip Erase Timing Waveform...................................................................... 35

Figure 8-9 Automatic Chip Erase Algorithm Flowchart .................................................................. 36

Figure 8-10 Automatic Sector Erase Timing Waveform................................................................... 37

Figure 8-11 Automatic Sector Erase Algorithm Flowchart ............................................................... 38

Figure 8-12 Erase Suspend/Resume Flowchart .............................................................................. 39

Figure 8-13 Automatic Program Timing Waveform.......................................................................... 40

Figure 8-14 Accelerated Program Timing Waveform....................................................................... 40

Figure 8-15 CE# Controlled Write Timing Waveform....................................................................... 41

Figure 8-16 Automatic Programming Algorithm Flowchart .............................................................. 42

W29GL128C

Publication Release Date: July 28, 2010

iii Preliminary - Revision A

Figure 8-17 Silicon ID Read Timing Waveform................................................................................ 43

Figure 8-18 Data# Polling Timing Waveform (During Automatic Algorithms).................................. 44

Figure 8-19 Status Polling for Word Programming/Erase................................................................ 45

Figure 8-20 Status Polling for Write Buffer Program Flowchart ....................................................... 46

Figure 8-21 Toggling Bit Timing Waveform (During Automatic Algorithms) .................................... 47

Figure 8-22 Toggle Bit Algorithm...................................................................................................... 48

Figure 8-23 #BYTE Timing Waveform For Read operations ........................................................... 49

Figure 8-24 Page Read Timing Waveform....................................................................................... 49

Figure 8-25 Deep Power Down mode Waveform ............................................................................ 50

Figure 8-26 Write Buffer Program Flowchart ................................................................................... 50

Figure 8-27 AC Timing at Device Power-Up .................................................................................... 51

Figure 9-1 TSOP 56-pin 14x20mm ................................................................................................ 53

Figure 9-2 BGA 64-ball 11x13mm.................................................................................................. 54

Figure 10-1 Ordering Part Numbering.............................................................................................. 55

Table 5-1 Pin Description................................................................................................................ 2

Table 6-1 Sector Address ............................................................................................................... 3

Table 7-1 Device Bus Operation..................................................................................................... 4

Table 7-2 Device Bus Operation (continue).................................................................................... 4

Table 7-3 Polling During Embedded Program Operation ............................................................... 7

Table 7-4 Polling During Embedded Sector Erase Operation ........................................................ 8

Table 7-5 Polling During Embedded Chip Erase Operation ........................................................... 9

Table 7-6 Polling During Embedded Erase Suspend ..................................................................... 9

Table 7-7 Polling During Embedded Program Suspend............................................................... 10

Table 7-8 Polling Buffer Write Abort Flag ..................................................................................... 11

Table 7-9 Auto Select for MFR/Device ID/Secure Silicon/Sector Protect Read .......................... 12

Table 7-10 Lock Register Bits......................................................................................................... 15

Table 7-11 Sector Protection Status Table ..................................................................................... 18

Table 7-12 Factory Locked: Security Sector................................................................................... 19

Table 7-13 ID Reads, Sector Verify, and Security Sector Entry/Exit .............................................. 20

Table 7-14 Program, Write Buffer, CFI, Erase and Suspend ......................................................... 21

Table 7-15 Deep Power Down ........................................................................................................ 21

Table 7-16 Lock Register and Global Non-Volatile......................................................................... 22

Table 7-17 IPB Functions............................................................................................................... 22

Table 7-18 Volatile DPB Functions ................................................................................................. 23

Table 7-19 CFI Mode: ID Data Values............................................................................................ 24

Table 7-20 CFI Mode: System Interface Data Values .................................................................... 25

Table 7-21 CFI Mode: Device Geometry Data Values.................................................................... 26

Table 7-22 CFI mode: Primary Vendor-Specific Extended Query Data Values ............................. 27

Table 8-1 Absolute Maximum Stress Ratings............................................................................... 28

Table 8-2 Operating Temperature and Voltage ............................................................................ 28

Table 8-3 DC Characteristics ........................................................................................................ 29

Table 8-4 Test Specification.......................................................................................................... 30

Table 8-5 AC Characteristics ........................................................................................................ 32

Table 8-6 AC Characteristics #RESET and RY/#BY .................................................................... 33

Table 8-7 AC Characteristics Word/Byte Configuration (#BYTE)................................................. 48

Table 8-8 AC Characteristics for Deep Power Down.................................................................... 50

Table 8-9 AC Characteristics at Device Power Up ....................................................................... 51

Table 8-10 AC Characteristics for Erase and Programming Performance..................................... 52

Table 8-11 Data Retention .............................................................................................................. 52

Table 8-12 Latch-up Characteristics ............................................................................................... 52

Table 8-13 Pin Capacitance............................................................................................................ 52

Table 10-1 Valid Part Numbers and Markings ................................................................................ 56

Table 11-1 Revision History ............................................................................................................ 57

W29GL128C

Publication Release Date: July 28, 2010

1 Preliminary - Revision A

1 GENERAL DESCRIPTION

The W29GL128C Parallel Flash memory provides a storage solution for embedded system

applications that require better performance, lower power consumption and higher density. The device

has a random access speed of 90ns and a fast page access speed of 25ns, as well as significantly

faster program and erase time than the products available on the market today. The W29GL128C also

offers special features such as Compatible Manufacturer ID that makes the device industry standard

compatible without the need to change firmware.

2 FEATURES

 64k-Word/128k-Byte uniform sector

architecture

– Total 128 uniform sectors

 32-Word/64-Byte write buffer

– Reduces total program time for multiple-

word updates

 8-Word/16-Byte page read buffer

 Secured Silicon Sector area

– Programmed and locked by the customer

or during production

– 128-word/256-byte sector for permanent,

safe identification using an 8-word/16-byte

random electronic serial number

 Enhanced Sector Protect using

Dynamic and Individual mechanisms

 Polling/Toggling methods are used to

detect the status of program and erase

operation

 Suspend and resume commands used

for program and erase operations

 More than 100,000 erase/program

cycles

 More than 20-year data retention

 Software and Hardware write protection

– Write-Protect all or a portion of memory

– Enable/Disable protection with #WP pin

– Top or bottom array protection

 Low power consumption

 Deep power down mode

 Wide temperature range

 Compatible manufacturer ID for drop-in

replacement

– No firmware change is required

 Faster Erase and Program time

– Erase is1.5x faster than industry standard

– Program is 2x faster than industry

standard

– Allows for improved production throughput

and faster field updates

 CFI (Common Flash Interface) support

 Single 3V Read/Program/Erase (2.7 -

3.6V)

 Enhanced Variable IO control

– All input levels (address, control, and DQ)

and output levels are determined by

voltage on the EVIO input. EVIO ranges

from 1.65 to VCC

 #WP/ACC Input

– Accelerates programming time (when VHH

is applied) for greater throughput during

system production

– Protects first or last sector regardless of

sector protection settings

 Hardware reset input (#reset) resets

device

 Ready/#Busy output (RY/#BY) detects

completion of program or erase cycle

 Packages

– 56-pin TSOP

– 64-ball Fortified BGA

W29GL128C

3 PIN CONFIGURATIONS

A0A1A2A4A3 #CE #OE VSS

NCNCNCNCNC EVIO NC NC

DQ0A5A6A17A7 DQ8 DQ9 DQ1

DQ2A20A18#WP/ACCRY/#BY DQ10 DQ11 DQ3

DQ5A19A21#RESET#WE DQ12 VCC DQ4

DQ7A11A10A8A9 DQ14 DQ13 DQ6

A16A15A14A12A13 #BYTE DQ15/A-1 VSS

VSSEVIONCA22NC NC NC NC

Figure 3-1 FBGA-64 TOP VIEW FACE

DOWN

A16

#BYTE

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

#OE

VSS

#CE

EVIO

A22

A15

A14

A13

A12

A11

A10

A19

A20

#WE

#RESET

A21

#WP/ACC

RY/#BY

A18

A17

Figure 3-2 56-PIN STANDARD TSOP

(TOP VIEW)

4 BLOCK DIAGRAM

CONTROL OUTPUT

BUFFER

#CE

#OE

#WE

RY/#BY

#BYTE

#RESET

#WP/ACC

DECODER MAIN ARRAY

DQ15/A-1

A22

DQ15/A-1

DQ0

VCC

EVIO

VSS

Figure 4-1 Block Diagram

5 PIN DESCRIPTION

SYMBOL PIN NAME

A0-A22 Address Inputs

DQ0-DQ14 Data Inputs/Outputs

Word

mode

DQ15 is Data

Input/Output

DQ15/A-1

Byte

mode

A-1 is Address Input

#CE Chip Enable

#OE Output Enable

#WE Write Enable

#WP/ACC Hardware Write Protect/

Acceleration Pin

#BYTE Byte Enable Input

#RESET Hardware Reset

RY/#BY Ready/Busy Status

VCC Power Supply

EVIO Enhanced Variable IO Supply

VSS Ground

NC No Connection

Table 5-1 Pin Description

W29GL128C

Publication Release Date: July 28, 2010

3 Preliminary - Revision A

6 ARRAY ARCHITECTURE

6.1 Sector Address Table

Sector Sector Address

A22-A16

Sector Size

(KByte/KWord)

Start / Finish

X16

Start / Finish

SA00 0000000 128/64 000000h 01FFFFh 000000h 00FFFFh

SA01 0000001 128/64 020000h 03FFFFh 010000h 01FFFFh

SA126 1111110 128/64 FC0000h FDFFFFh 7E0000h 7EFFFFh

SA127 1111111 128/64 FE0000h FFFFFFh 7F0000h 7FFFFFh

Table 6-1 Sector Address

Note: The address range [A22:A-1] in byte mode (#BYTE = VIL) or [A22:A0] in word mode (#BYTE = VIH)

W29GL128C

7 FUNCTIONAL DESCRIPTION

7.1 Device Bus Operation

#BYTE

VIL VIH

Mode Select #Reset #CE #WE #OE Address(4) Data I/O

DQ[7:0]

Data I/O DQ[15:8]

#WP/ACC

Device Reset L X X X X High-Z High-Z High-

Z L/H

Standby

Mode VCC±0.3V VCC±0.3V X X X High-Z High-Z High-

Z H

Output

Disable H L H H X High-Z High-Z

High-

Z L/H

Read Mode H L H L AIN DOUT DOUT L/H

Write H L L H AIN DIN DIN Note(1,2)

Accelerated

Program H L L H AIN DIN

DQ[14:8]=High-

DQ15=A-1 DIN VHH

Table 7-1 Device Bus Operation

Notes:

1. The first or last sector was protected if #WP/ACC=VIL.

2. When #WP/ACC = VIH, the protection conditions of the outmost sector depends on previous protection conditions.

Refer to the enhanced protect feature.

3. DQ[15:0] are input (DIN) or output (DOUT) pins according to the requests of instruction sequence, sector protection,

or data polling algorithm.

4. In Word Mode (Byte#=VIH), the addresses are A22 to A0. In Byte Mode (Byte#=VIL), the addresses are A22 to A-1

(DQ15),.

Control

Inputs DQ[15:8]

Description

#CE #WE #OE

A22

~12

A11

~10 A9 A8

~7 A6 A5

~2 A1 A0 DQ[7:0]

BYTE WORD

Read Silicon ID

Manufacturer Code L H L X X VHH X L X L L L EF X 00

Cycle 1 L H L X X VHH X L X L L H 7E X 22

Cycle 2 L H L X X VHH X L X H H L 21 X 22

Device ID

Cycle 3 L H L X X VHH X L X H H H 01 X 22

Sector Lock Status

Verification(1) L H L SA X VHH X L X L H L 01/00 X X

Secure Sector (H) (2) L H L X X VHH X L X L H H 99/19 X X

Secure Sector (L) (2) L H L X X VHH X L X L H H 89/09 X X

Table 7-2 Device Bus Operation (continue)

Notes:

1. Sector unprotected code:00h. Sector protected code:01h.

2. Factory locked code: #WP protects high address sector: 99h. #WP protects low address sector: 89h Factory unlocked

code: #WP protects high address sector: 19h. #WP protects low address sector: 09h

W29GL128C

Publication Release Date: July 28, 2010

5 Preliminary - Revision A

7.2 Instruction Definitions

The device operation can be initiated by writing specific address and data commands or sequences

into the instruction register. The device will be reset to reading array data when writing incorrect

address and data values or writing them in the improper sequence.

The addresses will be latched on the falling edge of #WE or #CE, whichever happens later; while the

data will be latched on the rising edge of #WE or #CE, whichever happens first. Please refer to timing

waveforms.

7.2.1 Reading Array Data

The default state after power up or a reset operation is the Read mode.

To execute a read operation, the chip is enabled by setting #CE and #OE active and #WE high. At the

same time, the required address or status register location is provided on the address lines. The

system reads the addressed location contents on the Data IO pins after the tCE and tOE timing

requirements have been met. Output data will not be accessible on the Data IO pins if either the

device or it’s outputs are not enabled by #CE or #OE being High, and the outputs will remain in a tri-

state condition.

When the device completes an embedded memory operation (i.e., Program, automatic Chip Erase or

Sector Erase) successfully, it will return to the Read mode and from any address in the memory array

the data can be read. However, If the embedded operation fails to complete, by verifying the status

execute a Reset operation causing the device to return to Read mode.

Some operating states require a reset operation to return to Read mode such as:

 Time-out condition during a program or erase failed condition, indicated by the status register

bit DQ5 going High during the operation. Failure during either of these states will prevent the

device from automatically returning to Read mode.

 During device Auto Select mode or CFI mode, a reset operation is required to terminate their

operation.

In the above two situations, the device will not return to the Read mode unless a reset operation is

executed (either hardware reset or software reset instruction) or the system will not be able to read

array data.

The device will enter Erase-Suspended Read mode if the device receives an Erase Suspend

instruction while in the Sector Erase state. The erase operation will pause (after a time delay not

exceeding 20µs) prior to entering Erase-Suspend Read mode. At this time data can be programmed

or read from any sector that is not being erased. Another way to verify device status is to read the

addresses inside the sectors being erased. This will only provide the contents of the status register.

Program operation during Erase-Suspend Read mode of valid sector(s) will automatically return to the

Erase-Suspend Read mode upon successful completion of the program operation.

An Erase Resume instruction must be executed to exit the Erase-Suspended Read mode, at which

time suspended erase operations will resume. Erase operation will resume where it left off and

continue until successful completion unless another Erase Suspend instruction is received.

7.2.2 Page Mode Read

The Page Mode Read has page sizes of 16 bytes or 8 words. The higher addresses A[22:3] accesses

the desired page. To access a particular word or byte in a page, it is selected by A[2:0] for word mode

and A[2:0,A-1] for byte mode. Page mode can be turned on by keeping “page-read address” constant

and changing the “intra-read page” addresses. The page access time is tAA or tCE, followed by tPA for

the page read time. When #CE toggles, access time is tAA or tCE.

W29GL128C

7.2.3 Device Reset Operation

Pulling the #RESET pin Low for a period equal to or greater than tRP will return the device to Read

mode. If the device is performing a program or erase operation, the reset operation will take at most a

period of tREADY1 before the device returns to Read mode. The RY/#BY pin will remain Low (Busy

Status) until the device returns to Read mode.

Note, the device draws larger current if the #RESET pin is held at voltages greater that GND+0.3V

and less than or equal to VIL. When the #RESET pin is held a GND±0.3V, the device only consumes

Reset (ICC5) current.

It is recommended to tie the system reset signal to the #RESET pin of the flash memory. This allows

the device to be reset with the system and puts it in a state where the system can immediately begin

reading boot code from it.

Executing the Reset instruction will reset the device back to the Read mode in the following situations:

 During an erase instruction sequence, before the full instruction set is completed.

 Sector erase time-out period

 Erase failed, while DQ5 is High.

 During program instruction sequence, before the full instruction set is completed, including the

erase-suspended program instruction.

 Program failed, while DQ5 is High as well as the erase-suspended program failure.

 Auto-select mode

 CFI mode

 The user must issue a reset instruction to reset the device back to the Read mode when the

device is in Auto-Select mode or CFI mode, or when there is a program or erase failure (DQ5

is High).

 When the device is performing a Programming (not program fail) or Erasing (Not erase fail)

function, the device will ignore reset commands.

7.2.4 Standby Mode

Standby mode is entered when both #RESET and #CE are driven to VCC ±300mV (inactive state). At

this time output pins are placed in the high impedance state regardless of the state of the #WE or #OE

pins and the device will draw minimal standby current (ICC4). If the device is deselected during erase

or program operation, the device will draw active current until the operation is completed.

7.2.5 Output Disable Mode

The #OE pin controls the state of the Data IO pins. If #OE is driven High (VIH), all Data IO pins will

remain at high impedance and if driven Low, the Data IO pins will drive data ( #OE has no affect on

the RY/BY# output pin).

7.2.6 Write Operation

To execute a write operation, Chip Enable (#CE) pin is driven Low and the Output Enable (#OE) is

pulled high to disable the Data IO pins to a high impedance state. The desired address and data

should be present on the appropriate pins. Addresses are latched on the falling edge of either #WE or

#CE and Data is latched on the rising edge or either #CE or #WE. To see an example, please refer to

timing diagrams in Figure 8-5 and Figure 8-15. If an invalid write instruction, not defined in this

datasheet is written to the device, it may put the device in an undefined state.

W29GL128C

Publication Release Date: July 28, 2010

7 Preliminary - Revision A

7.2.7 Byte/Word Selection

To choose between the Byte or Word mode, the #BYTE input pin is used to select how the data is

input/output on the Data IO pins and the organization of the array data. If the #BYTE pin is driven

High, Word mode will be selected and all 16 Data IO pins will be active. If the #BYTE is pulled Low,

Byte mode will be active and only Data IO DQ[7:0] will be active. The remaining Data IO pins

(DQ[14:8]) will be in a high impedance state and DQ15 becomes the A-1 address input pin.

7.2.8 Automatic Programming of the Memory Array

To program the memory array in Byte or Word mode, refer to the Instruction Definition Tables for

correct cycle defined instructions that include the 2 unlocking instruction cycles, the A0h program cycle

instruction and subsequent cycles containing the specified address location and the byte or word

desired data content, followed by the start of the embedded algorithm to automatically program the

array.

Once the program instruction sequence has been executed, the internal state machine commences

execution of the algorithms and timing necessary for programming and cell verification. Included in this

operation is generating suitable program pulses, checking cell threshold voltage (VT) margins, and if

any cells do not pass verification or have acceptable margins, repetitive program pulse sequence will

be cycled again. The internal process mechanisms will protect cells that do pass margin and

verification tests from being over-programmed by prohibiting further program pulses to passing cells

as failing cells continue to be run through the internal programming sequence until the pass.

This feature allows the user to only perform the auto-programming sequence once and the device

state machine takes care of the program and verification process.

Array bits during programming can only change a bit status of “1” (erase state) to a “0” (programmed

state). It is not possible to do the reverse with a programming operation. This can only be done by first

performing an erase operation. Keep in mind, the internal write verification only checks and detects

errors in cases where a “1” is not successfully programmed to “0”.

During the embedded programming algorithm process any commands written to the device will be

ignored, except hardware reset or a program suspend instruction. Hardware reset will terminate the

program operation after a period of time, not to exceed 10µs. If in the case a Program Suspend was

executed, the device will enter the program suspend read mode. When the embedded program

algorithm is completed or the program is terminated by a hardware reset, the device will return to

Read mode.

The user can check for completion by reading the following bits in the status register, once the

embedded program operation has started:

Status DQ7 DQ6 DQ5 DQ1 RY/#BY1

In progress DQ7# Toggling 0 0 0

Exceeded time

limit

DQ7# Toggling 1 N/A 0

Table 7-3 Polling During Embedded Program Operation

Note:

1. RY/#BY is an open drain output pin and should be connected to VCC through a high value pull-up resistor.

W29GL128C

7.2.9 Erasing the Memory Array

Sector Erase and Chip Erase are the two possible types of erase operations executed on the memory

array. Sector Erase operation erases one or more selected sectors and this can be simultaneous. Chip

Erase operation erases the entire memory array, except for any protected sectors.

7.2.9.1 Sector Erase

The sector erase operation returns all selected sectors in memory to the “1” state, effectively clearing

all data. This action requires six instruction cycles to commence the erase operation. The unlock

sequence is the first two cycles, followed by the configuration cycle, the fourth and fifth are

also ”unlock cycles”, and the Sector Erase instruction is the sixth cycle. An internal 50µs time-out

counter is started once the sector erase instruction sequence has been completed. During this time,

additional sector addresses and Sector Erase commands may be issued, thus allowing for multiple

sectors to be selected and erased simultaneously. Once the 50µs time-out counter has reached its

limit, no additional command instructions will be accepted and the embedded sector erase algorithm

will commence.

Note, that the 50µs time-out counter restarts after every sector erase instruction sequence. The device

will abort and return to Read mode, if any instruction other than Sector Erase or Erase Suspend is

attempted during the time-out period.

Once the embedded sector erase algorithm begins, all instructions except Erase Suspend or

Hardware Reset will be ignored. The hardware reset will abort the erase operation and return the

device to the Read mode.

The embedded sector erase algorithm status can be verified by the following:

Status DQ7 DQ6 DQ5 DQ31 DQ2 RY/#BY2

Time-out period 0 Toggling 0 0 Toggling 0

In progress 0 Toggling 0 1 Toggling 0

Exceeded time limit 0 Toggling 1 1 Toggling 0

Table 7-4 Polling During Embedded Sector Erase Operation

Note:

1. The DQ3 status bit is the 50µs time-out indicator. When DQ3=0, the 50µs time-out counter has not yet reached zero

and the new Sector Erase instruction maybe issued to specify the address of another sector to be erased. When

DQ3=1, the 50µs time-out counter has expired and the Sector Erase operation has already begun. Erase Suspend is

the only valid instruction that maybe issued once the embedded erase operation is underway.

2. RY/#BY is open drain output pin and should be connected to VCC through a high value pull-up resistor.

3. When an attempt is made to erase only protected sector(s), the erase operation will abort thus preventing any data

changes in the protected sector(s). DQ7 will output “0” and DQ6 will toggle briefly (100µs or less) before aborting and

returning the device to Read mode. If unprotected sectors are also specified, however, they will be erased normally

and the protected sector(s) will remain unchanged.

4. DQ2 is a localized indicator showing a specified sector is undergoing erase operation or not. DQ2 toggles when user

reads at the addresses where the sectors are actively being erased (in erase mode) or to be erased (in erase

suspend mode).

W29GL128C

Publication Release Date: July 28, 2010

9 Preliminary - Revision A

7.2.9.2 Chip Erase

The Chip Erase operation returns all memory locations containing a bit state of “0” to the “1” state,

effectively clearing all data. This action requires six instruction cycles to commence the erase

operation. The unlock sequence is the first two cycles, followed by the configuration cycle, the fourth

and fifth are also ”unlock cycles”, and the sixth cycle initiates the chip erase operation.

Once the chip erase algorithm begins, no other instruction will be accepted. However, if a hardware

reset is executed or the operating voltage is below acceptable levels, the chip erase operation will be

terminated and automatically returns to Read mode.

The embedded chip erase algorithm status can be verified by the following:

Status DQ7 DQ6 DQ5 DQ2 RY/#BY1

In progress 0 Toggling 0 Toggling 0

Exceeded time limit 0 Toggling 1 Toggling 0

Table 7-5 Polling During Embedded Chip Erase Operation

Note:

1. RY/#BY is open drain pin and should be connected to VCC through a high value pull-up resistor.

7.2.10 Erase Suspend/Resume

If there is a sector erase operation in progress, an Erase Suspend instruction is the only valid

instruction that may be issued. Once the Erase Suspend instruction is executed during the 50µs time-

out period following a Sector Erase instruction, the time-out period will terminate right away and the

device will enter Erase-Suspend Read mode. If an Erase Suspend instruction is executed after the

sector erase operation has started, the device will not enter Erase-Suspended Read mode until

approximately 20µs (5µs typical) time has elapsed. To determine the device has entered the Erase-

Suspend Read mode, use DQ6, DQ7 and RY/#BY status to verify the state of the device.

Once the device has entered Erase-Suspended Read mode, it is possible to read or program any

sector(s) except those being erased by the erase operation. Only the contents of the status register is

present when attempting to read a sector that has been scheduled to erase or be programmed when

in the suspend mode. A resume instruction must be executed and recommend checking DQ6 toggle

bit status, before issuing another erase instruction.

The status register bits can be verified to determine the current status of the device:

Status DQ7 DQ6 DQ5 DQ3 DQ2 DQ1RY/#BY

Erase suspend read in erase suspended sector 1 No toggle 0 N/A Toggle N/A 1

Erase suspend read in non-erase suspended sector Data Data DataData Data Data 1

Erase suspend program in non-erase suspended sector DQ7# Toggle 0 N/A N/A N/A 0

Table 7-6 Polling During Embedded Erase Suspend

Instruction sets such as read silicon ID, sector protect verify, program, CFI query and erase resume

can also be executed during Erase-Suspend mode, except sector and chip erase.

7.2.11 Sector Erase Resume

Only in the Erase-Suspended Read mode can the Sector Erase Resume instruction be a valid

command. Once erase resumes, another Erase Suspend instruction can be executed, but allow a

400µs interval between Erase Resume and the next Erase Suspend instruction.

W29GL128C

7.2.12 Program Suspend/Resume

Once a program operation is in progress, a Program Suspend is the only valid instruction that maybe

executed. Verifying if the device has entered the Program-Suspend Read mode after executing the

Program-Suspend instruction, can be done by checking the RY/#BY and DQ6. Programming should

halt within 15µs maximum (5µs typical).

Any sector(s) can be read except those being program suspended. Trying to read a sector being

program suspended is invalid. Before another program operation can be executed, a Resume

instruction must be performed and DQ6 toggling bit status has to be verified. Use the status register

bits shown in the following table to determine the current state of the device:

Status DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 RY/#RY

Program suspend read in program suspended sector 1

Program suspend read in non-program suspended sector Data Data Data Data Data Data 1

Table 7-7 Polling During Embedded Program Suspend

Instruction sets such as read silicon ID, sector protect verify, program, CFI query can also be executed

during Program/Erase-Suspend mode.

7.2.13 Program Resume

The program Resume instruction is valid only when the device is in Program-Suspended mode. Once

the program resumes, another Program Suspend instruction can be executed. Insure there is at least

a 5µs interval between Program Resume and the next Suspend instruction.

7.2.14 Write Buffer Programming Operation

Write Buffer Programming Operation, programs 64bytes or 32words in a two step programming

operation. To begin execution of the Write Buffer Programming, start with the first two unlock cycles,

the third cycle writes the programming Sector Address destination followed by the Write Buffer Load

Instruction (25h). The fourth cycle repeats the Sector Address, while the write data is the number of

intended word locations to be written minus one. (Example, if the number of word locations to be

written is 9, then the value would be 8h.) The 5th cycle is the first starting address/data set. This will be

the first pair to be programmed and consequentially, sets the “write-buffer-page” address. Repeat

Cycle 5 format for each additional address/data sets to be written to the buffer. Keep in mind all sets

must remain within the write buffer page address range. If not, operation will ABORT.

The “write-buffer-page” is selected by choosing address A[22:5].

The second step will be to program the contents of the write buffer page. This is done with one cycle,

containing the sector address that was used in step one and the “Write to Buffer Program Confirm”

instruction (29h).

Standard suspend/resume commands can be used during the operation of the write-buffer. Also, once

the write buffer programming operation is finished, it’ll return to the normal READ mode.

Write buffer programming can be conducted in any sequence. However the CFI functions, autoselect,

Secured Silicon sector are not functional when program operation is in progress. Multiple write buffer

programming operations on the same write buffer address range without intervention erase is

accessible. Any bit in a write buffer address range cannot be programmed from 0 back to 1.

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11 Preliminary - Revision A

7.2.15 Buffer Write Abort

Write Buffer Programming Sequence will ABORT, if the following condition takes place:

 The word count minus one loaded is bigger than the page buffer size (32) during, “Number of

Locations to Program.”

 Sector Address written is not the same as the one specified during the Write-Buffer-Load

instruction.

 If the Address/Data set is not inside the Write Buffer Page range which was set during cycle

5’s first initial write-buffer-page select address/data set.

 No “Program Confirm Instruction” after the assigned number of “data load” cycles.

After Write Buffer Abort, the status register will be DQ1=1, DQ7 = DATA# (last address loaded),

DQ6=toggle, DQ5=0. This status represents a Write Buffer Programming Operation was ABORTED. A

Write-to-Buffer-Abort Reset instruction sequence has to be written to reset the device back to the read

array mode.

DQ1 is the bit for Buffer Write Abort. When DQ1=1, the device will abort from buffer write operation

and go back to read status register shown in the following table:

Status DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 RY/#RY

Buffer Write Busy DQ7# Toggle 0 N/A N/A 0 0

Buffer Write Abort DQ7# Toggle 0 N/A N/A 1 0

Buffer Write Exceeded Time Limit DQ7# Toggle 1 N/A N/A 0 0

Table 7-8 Polling Buffer Write Abort Flag

7.2.16 Accelerated Programming Operation

The device will enter the Accelerated Programming mode by applying high voltage (VHH) to the

#WP/ACC pin. Accelerated Programming mode allows the system to skip the normal unlock

sequences instruction and program byte/word locations directly. The current drawn from the #WP/ACC

pin during accelerated programming is no more that IACC1. Important Note: Do not exceed 10

accelerated programs per sector.

7.2.17 Automatic Select Bus Operation

There are basically two methods to access Automatic Selection Operations; Automatic Select

Instructions through software commands and High Voltage applied to A9. See Automatic Select

Instruction Sequence later on in this section for details of equivalent instruction operations that do not

require the use of VHH. The following five bus operations require A9 to be raised to VHH.

7.2.17.1 Sector Lock Status Verification

To verify the protected state of any sector using bus operations, execute a Read Operation with VHH

applied to A9, the sector address present on address pins A[22:12], address pins A6, A3, A2, and A0

held Low, and address pins A1 held High. If DQ0 is Low, the sector is considered not protected, and if

DQ0 is High, the sector is considered to be protected.

7.2.17.2 Read Silicon Manufacturer ID Code

To verify the Silicon Manufacturer ID Code, execute a Read Operation with VHH applied to the A9 pin

and address pins A6, A3, A2, A1 and A0 are held Low. The Winbond Manufacturer ID code of EFh

should be shown on the data bits DQ[7:0].

W29GL128C

7.2.17.3 Read Silicon Device ID Code

To verify the Silicon Device ID Codes, execute a Read Operation with VHH applied to the A9 pin and

address pins A6, A3, A2, A1, and A0 have several bit combinations to return the Winbond Device ID

codes of 7Eh, 21h or 01h, which is shown on the data bits DQ[7:0]. See Table 7-2.

7.2.17.4 Read Indicator Bit DQ7 for Security Sector High and Low Address

To verify that the Security Sector has been factory locked, execute a Read Operation with VHH applied

to A9, address pins A6, A3, and A2 are held Low, and address pins A1 and A0 are held High. If the

Security Sector has been factory locked, the code 99h(Highest Address Sector) or 89h(Lowest

Address Sector) will be shown on the data bits DQ[7:0]. Otherwise, the factory unlocked code of

19h(H)/09(L) will be shown.

7.2.18 Automatic Select Operations

The Automatic Select instruction show in Table 7-13 can be executed if the device is in one of the

following modes; Read, Program Suspended, Erase-Suspended Read, or CFI. At which time the user

can issue (two unlock cycles followed by the Automatic Select instruction 90h) to enter Automatic

Select mode. Once in the Automatic Select mode, the user can query the Manufacturer ID, Device ID,

Security Sector locked status, or Sector protected status multiple times without executing the unlock

cycles and a Automatic Select instruction (90h) again.

Once in Automatic Select mode, executing a Reset instruction (F0h) will return the device back to the

valid mode from which it left when the Automatic Select mode was first executed.

Another way previously mentioned to enter Automatic Select mode is to use one of the bus operation

shown Table 7-2 in Device Bus Operation. Once the high voltage (VHH) is removed from the A9 pin,

the device will return back to the valid mode from which it left when the Automatic Select mode was

first executed.

7.2.19 Automatic Select Instruction Sequence

Accessing the manufacturer ID, device ID, and verifying whether or not secured silicon is locked and

whether or not a sector protected is the purpose of Automatic Select mode. There are four instruction

cycles that comprise the Automatic Select mode. The first two cycles are write unlock commands,

followed by the Automatic Select instruction (90h). The fourth cycle is a read cycle, and the user may

read at any address any number of times without entering another instruction sequence. To exit the

Automatic Select mode and back to read array, the Reset instruction is necessary. No other

instructions are allowed except the Reset Instruction once Automatic Select mode has been selected.

Refer to the following table for more detailed information.

Address Data (hex) Representation

Word X00 EF

Manufacturer ID Byte X00 EF

Word X01/0E/0F 227E/2221/2201

Device ID W29GL128C Byte X02/1C/1E 7E/21/01

99/19(H)

Word X03 89//09(L) Factory locked/unlocked

99/19(H)

Secure Silicon

Byte X06 89/09(L) Factory locked/unlocked

Word (Sector address) X02 00/01 Unprotected/protected

Sector Protect Verify Byte Sector address) X04 00/01 Unprotected/protected

Table 7-9 Auto Select for MFR/Device ID/Secure Silicon/Sector Protect Read

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Publication Release Date: July 28, 2010

13 Preliminary - Revision A

7.2.20 Enhanced Variable IO (EVIO) Control

The Enhanced Variable IO (EVIO) control allows the host system to set the voltage levels that the

device generates and tolerates on all inputs and outputs (address, control, and DQ signals). EVIO

range is 1.65 to VCC.

For example, a EVIO of 1.65-3.6 volts allows for I/O at the 1.8 or 3 volt levels, driving and receiving

signals to and from other 1.8 or 3 V devices on the same data bus.

7.2.21 Hardware Data Protection Options

Hardware Data Protection is the second of the two main sector protections offered by the W29GL128.

7.2.21.1 #WP/ACC Option

By setting the #WP/ACC pin to VIL, the highest or lowest sector (device specific) is protected from all

erase/program operations. If #WP/ACC is set High, the highest and Lowest sector revert back to the

previous protected/unprotected state.

Note: The max input load current can increase, if #WP/ACC pin is at VIH when the device is put into

standby mode.

7.2.21.2 VCC Write Protect

This device will not accept any write instructions when VCC is less that VWPT (VCC Write Protect

Threshold). This prevents data from inadvertently being altered during power-up, power-down, a

temporary power loss or to the low level of VCC. If VCC is lower that VWPT, the device automatically

resets itself and will ignore write cycles until VCC is greater than VWPT. Once VCC rises above VWPT,

insure that the proper signals are on the control pins to avoid unexpected program or erase operations.

7.2.21.3 Write Pulse “Glitch” Protection

Pulses less than 5ns are viewed as glitches for control signals #CE, #WE, and #OE and will not be

considered for valid write cycles.

7.2.21.4 Power-up Write Inhibit

The device ignores the first instruction on the rising edge of #WE, if upon powering up the device,

#WE and #CE are set at VIL and #OE is set at VIH.

7.2.21.5 Logical Inhibit

A write cycle is ignored when either #CE is at VIH, #WE is at VIH, or #OE is at VIL. A valid write cycle

requires both #CE and #WE are at VIL with #OE at VIH.

7.2.22 Inherent Data Protection

The device built-in mechanism will reset to Read mode during power up to avoid accidental erasure or

programming.

7.2.22.1 Instruction Completion

Invalid instruction sets will result in the memory returning to read mode. Only upon a successful

completion of a valid instruction set will the device begin its erase or program operation..

7.2.22.2 Power-up Sequence

The device is placed in Read mode, during power-up sequence.

7.2.23 Power Supply Decoupling

To reduce noise effects, a 0.1µF capacitor is recommended to be connected between VCC and GND.

W29GL128C

7.3 Enhanced Sector Protect/Un-protect

This device is set from the factory in the Individual Protection mode of the Enhanced Sector Protect

scheme. The user can disable or enable the programming or erasing operation to any individual sector

or whole chip. The figure below helps describe an overview of these methods.

The device defaults to the Individual mode and all sectors are unprotected when shipped from the

factory.

The following flow chart shows the detailed algorithm of Enhanced Sector Protect:

Start

Individual Protection

Mode

(Default)

Figure 7-1 Enhanced Sector Protect/Un-protect IPB Program Algorithm

Set IPB

Lock Bit IPB lock Bit locked

All IPB not changeable

Dynamic Write Protect bit

(DPB)

Sector Array Individual Protect bit

(IPB)

DPB=0 Sector Protect

DPB=1 Sector Unprotect

IPB Lock bit Unlocked

IPB is Changeable

DPB 0

DPB 1

DPB 2

DPB + n

SA 0

SA 1

SA 2

SA + n

IPB 0

IPB 1

IPB 2

IPB + n

IPB=0 Sector Protect

IPB=1 Sector Unprotect

IPB=0

IPB=1

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Publication Release Date: July 28, 2010

15 Preliminary - Revision A

7.3.1 Lock Register

User can choose Secured Silicon Sector Protection Bit for security sector protection method via setting

the Lock Register bit, DQ0. Lock Register is a 16-bit one time programmable register. Once

programmed DQ0, will be locked in that mode permanently.

Once the Instruction Set Entry instruction sequence for the Lock Register Bits is issued, all sectors

read and write functions are disabled until Lock Register Exit sequence has been executed.

The memory sectors and extended memory sector protection is configured using the Lock Register.

DQ[15:1] DQ0

Don’t Care Secured Silicon Sector Protection Bit

Table 7-10 Lock Register Bits

Start

Figure 7-2 Lock Register Program Algorithm

Write Data AAh, Address 555h

Write Data 55h, Address2AAh

Write Data 40h, Address 555h

Write Data A0h, Address don’t care

Write Program Data, Address don’t care

Data # Polling Algorithm

Fail

Reset instruction

Done

DQ5=1

Lock Register instruction set entry

Lock Register data program

YES

Pass

Exit lock Register instruction

W29GL128C

7.3.2 Individual (Non-Volatile) Protection Mode

7.3.2.1 Individual Protection Bits (IPB)

The Individual Protection Bit (IPB) is a nonvolatile bit, one bit per sector, with endurance equal to that

of the Flash memory array. Before erasing, IPB preprogramming and verification is managed by the

device, so no monitoring is necessary.

The Individual Protection Bits are set sector by sector by the IPB program instruction. Once a IPB is

set to “0”, the linked sector is protected, blocking any program and/or erase functions on that sector.

The IPB cannot be erased individually, but executing the “All IPB Erase” instruction will erase all IPB

simultaneously. Read and write functions are disabled when IPB programming is going on for all

sectors until this mode exits.

In case one of the protected sectors need to be unprotected, first, the IPB Lock Bit must be set to “1”

by performing one of the following: power-cycle the device or perform a hardware reset. Second, an

“All IPB Erase instruction needs to be performed. Third, Individual Protection Bits need to be set once

again to reflect the desired settings and finally, the IPB Lock Bit needs to be set once again which

locks the Individual Protection Bits and the device functions normally once again.

Executing an IPB Read instruction to the device is required to verify the programming state of the IPB

for any given sector. Refer to the IPB Program Algorithm flow chart below for details.

Note that

 While IPB Lock Bit is set, Program and/or erase instructions will not be executed and times

out without programming and/or erasing the IPB.

 For best protection results, it is recommended to execute the IPB Lock Bit Set instruction early

on in the boot code. Also, protect the boot code by holding WP#/ACC = VIL. Note that the IPB

and DPB bits perform the same when WP#/ACC = VHH, and when WP#/ACC =VIH.

 While in the IPB command mode, read within that sector will bring the IPB status back for that

sector. All Read must be executed by the read mode.

 Issuing the IPB Instruction Set Exit will reset the device to normal read mode enabling reads

and writes for the array.

7.3.2.2 Dynamic Protection Bits (DPB)

Dynamic Protection allows the software applications to easily protect sectors against unintentional

changes, although, the protection can be readily disabled when changes are needed.

All Dynamic Protection Bits (DPB) are individually linked to their associated sectors and these volatile

bits can be modified individually (set or cleared). The DPB provide protection schemes for only

unprotected sectors that have their associated IPB cleared. To change a DPB, the “DPB Instruction

Set Entry” must be executed first and then either the DPB Set (programmed to “0”) or DPB Clear

(erased to “1”) commands have to be executed. This places each sector in the protected or

unprotected state separately. To exit the DPB mode, execute the “DPB Instruction Set Exit” instruction.

Note that

 When the parts are first shipped, the IPB are cleared (erased to “1”) and upon power up or

reset, the DPB can be set or cleared.

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Publication Release Date: July 28, 2010

17 Preliminary - Revision A

Figure 7-3 IPB Program Algorithm

Program IPB

Read DQ[7:0] twice

DQ5=1?

DQ6=Toggle?

Program Fail Write Reset CMD

DQ6=Toggle?

Wait 500µs

Pass

IPB instruction set Exit

DQ0=

‘1’ (Erase) or

‘0’ (Program)

YES

IPB instruction set entry

Note:

1. IPB program/erase status polling flowchart: Check DQ6 toggle, when DQ6 stop toggle, the read status is 00h/01h

(ooh for program and 01h for erase, otherwise the status is “fail’ and “exit”.

7.3.2.3 Individual Protection Bit Lock Bit

The Individual Protection Bit Lock Bit (IPBLK) is a global lock bit to control all IPB states. It is a

singular volatile bit. If the IPBLK is set (“0”), all IPB are locked and all sectors are protected or

unprotected according to their individual IPB. When IPBLK=1 (cleared), all IPB are unlocked and

allowed to be set or cleared.

To clear the IPB Lock Bit, a hardware reset or a power-up cycle must be executed.

W29GL128C

Sector Protection Status

DPB IPBLK IPB

Sector Status

clear clear clear Unprotect, DPB and IPB are changeable

clear clear set Protect, DPB and IPB are changeable

clear set clear Unprotect, DPB is changeable

clear set set Protect, DPB is changeable

set clear clear Protect, DPB and IPB are changeable

set clear set Protect, DPB and IPB are changeable

set set clear Protect, DPB is changeable

set set set Protect, DPB is changeable

Table 7-11 Sector Protection Status Table

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Publication Release Date: July 28, 2010

19 Preliminary - Revision A

7.4 Security Sector Flash Memory Region

An extra memory space length of 128 words is used as the Security Sector Region which can be

factory locked or customer lockable. To enquire about the lock status of the device, the customer can

issue a Security Sector Protect Verify or Security Sector Factory Protect Verify using Automatic Select

Address 03h and DQ7.

The security sector region is unprotected when shipped from factory and the security silicon indicator

bit (DQ7) is set to "0" for a customer lockable device. The security sector region is protected when

shipped from factory and the security silicon sector indicator bit is set to "1" for a factory-locked device.

7.4.1 Factory Locked: Security Sector Programmed and Protected at factory

In a factory locked device, the Security Sector is permanently locked prior to factory shipment The

ESN occupies addresses 00000h to 0000Fh in byte mode or 00000h to 00007h in word mode since

the device has a 16-byte (8-word) ESN(Electronic Serial Number) in the security region.

Security Silicon

Sector Address

Range

Standard Factory

Locked

Express Flash

Factory Locked Customer Lockable

000000h-000007h ESN ESN or Determined by

Customer

000008h-00007Fh Inaccessible Determined by

Customer

Determined by

Customer

Table 7-12 Factory Locked: Security Sector

7.4.2 Customer Lockable: Security Sector Not Programmed or Protected

Important Notice; Once the security silicon sector is protected (Lock Register OTP DQ0 = “0”, Security

Sector indicator DQ7 bit=”0”), there is no way to unprotect the security silicon sector and the contents

of the memory region can no longer be programmed or erased.

Once the security silicon is locked and verified, an Exit Security Sector Region instruction must be

executed to get back to the Read Array mode. A power cycle, or a hardware reset will also return the

device to read array mode.

This region can act as extra memory space when this security feature is not utilized.

W29GL128C

7.5 Instruction Definition Tables

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle 4th Bus Cycle 5th Bus

Cycle

6th Bus Cycle

Instruction

ADD DATA ADD DATA ADD DATA ADD DATA ADD DATA ADD DATA

WORD Add Data

Read Mode

BYTE Add Data

WORD XXX F0

Reset Mode BYTE XXX F0

WORD 555 AA 2AA 55 555 90 X00 EF

Silicon ID

BYTE AAA AA 555 55 AAA 90 X00 EF

WORD 555 AA 2AA 55 555 90 X01 ID1 X0E ID2 X0F ID3

Device ID BYTE AAA AA 555 55 AAA 90 X02 ID1 X1C ID2 X1E ID3

WORD 555 AA 2AA 55 555 90 X03

99/19(H)

89/09(L)

Factory Protect

Verify BYTE AAA AA 555 55 AAA 90 X06

99/19(H)

89/09(L)

WORD 555 AA 2AA 55 555 90 (SA)X02 00/01

Automatic Select

Sector Protect

Verify BYTE AAA AA 555 55 AAA 90 (SA)X04 00/01

WORD 555 AA 2AA 55 555 88

Security Sector

Region BYTE AAA AA 555 55 AAA 88

WORD 555 AA 2AA 55 555 90 XXX 00

Exit Security Sector BYTE AAA AA 555 55 AAA 90 XXX 00

Table 7-13 ID Reads, Sector Verify, and Security Sector Entry/Exit

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21 Preliminary - Revision A

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus Cycle

Instruction

ADD DATA ADD DATA ADD DATA ADD DATA ADD DATA ADD DATA

WORD 555 AA 2AA 55 555 A0 Add Data

Program

BYTE AAA AA 555 55 AAA A0 Add Data

WORD 555 AA 2AA 55 SA 25 SA N-1 WA WD WBL WD

Write to Buffer Program BYTE AAA AA 555 55 SA 25 SA N-1 WA WD WBL WD

WORD 555 AA 2AA 55 555 F0

Write to Buffer Program

Abort Reset BYTE AAA AA 555 55 AAA F0

WORD SA 29

Write to Buffer Program

Confirm BYTE SA 29

WORD 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Chip Erase BYTE AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10

WORD 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30

Sector Erase BYTE AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30

WORD 55 98

CFI Read BYTE AA 98

WORD XXX B0

Program/Erase Suspend BYTE XXX B0

WORD XXX 30

Program/Erase Resume BYTE XXX 30

Table 7-14 Program, Write Buffer, CFI, Erase and Suspend

WA=WRITE ADDRESS, WD=WRITE DATA, SA=SECTOR ADDRESS, N-1=WORD COUNT, WBL=WRITEBUFFER LOCATION, ID1/ID2/ID3: REFER TO Table 7-2 FOR

DETAIL ID.

1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle

Instruction ADD DATA ADD DATA ADD DATA ADD DATA ADD DATA

WORD 555 AA 2AA 55 XXX B9

ENTER

BYTE AAA AA 555 55 XXX B9

WORD XXX AB

Deep Power

Down

EXIT BYTE XXX AB

Table 7-15 Deep Power Down

W29GL128C

1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle

Instruction ADD DATA ADD DATA ADD DATA ADD DATA ADD DATA

WORD 555 AA 2AA 55 555 40

Lock Register

Instruction Set

Entry BYTE AAA AA 555 55 AAA 40

WORD XXX A0 XXX DATA

Program BYTE XXX A0 XXX DATA

WORD XXX DATA

Read

BYTE XXX DATA

WORD XXX 90 XXX 00

Lock Register

Instruction Exit BYTE XXX 90 XXX 00

WORD 555 AA 2AA 55 555 C0

IPB Instruction Set

Entry BYTE AAA AA 555 55 AAA C0

WORD XXX A0 SA 00

IPB Program BYTE XXX A0 SA 00

WORD XXX 80 00 30

All IPB Erase BYTE XXX 80 00 30

WORD SA 00/01

Global Non-Volatile

IPB Status Read BYTE SA 00/01

Table 7-16 Lock Register and Global Non-Volatile

1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle

Instruction ADD DATA ADD DATA ADD DATA ADD DATA ADD DATA

WORD XXX 90 XXX 00

Global Non-

Volatile

IPB Instruction Set

Exit

BYTE XXX 90 XXX 00

WORD 555 AA 2AA 55 555 50

IPB Instruction Set

Entry BYTE AAA AA 555 55 AAA 50

WORD XXX A0 XXX 00

IPB Lock Set

BYTE XXX A0 XXX 00

WORD XXX 00/01

IPB Lock Status

Read BYTE XXX 00/01

WORD XXX 90 XXX 00

Global Volatile Freeze

IPB Lock Instruction

Set Exit BYTE XXX 90 XXX 00

Table 7-17 IPB Functions

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23 Preliminary - Revision A

1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle

Instruction ADD DATA ADD DATA ADD DATA ADD DATA ADD DATA

WORD 555 AA 2AA 55 555 E0

DPB Instruction Set

Entry BYTE AAA AA 555 55 AAA E0

WORD XXX A0 SA 00

DPB Set BYTE XXX A0 SA 00

WORD XXX A0 SA 01

DPB Clear BYTE XXX A0 SA 01

WORD SA 00/01

DPB Status READ BYTE SA 00/01

WORD XXX 90 XXX 00

Volatile

DPB Instruction Set

Exit BYTE XXX 90 XXX 00

Table 7-18 Volatile DPB Functions

Notes:

1. It is not recommended to use any other code that is not in the instruction definition table which can potentially enter

the hidden mode.

2. For the IPB Lock and DPB Status Read "00" represents lock (protect), "01" represents unlock (unprotect).

W29GL128C

7.6 Common Flash Memory Interface (CFI) Mode

7.6.1 Query Instruction and Common Flash memory Interface (CFI) Mode

Through Common Flash Interface(CFI) operations it is possible to access the operating characteristics,

structure and vendor specific information, such as identifying information, memory size, byte/word

configuration, operating voltages and timing information of this device. From the Read array mode

writing CFI Read instruction 98h to the address "55h"/"AAh" (Word/Byte, respectively), the device will

gain access to the CFI Query Mode. Once in the CFI mode data can be read using the addresses

given in Table 7-19 thru 7-22.

A reset instruction must be executed to exit CFI mode and the device will return to read array mode.

CFI mode: Identification Data Values (All Values in these tables are hexadecimal)

Description Address

(Word Mode) Data Address

(Byte Mode)

10h 0051h 20h

11h 0052h 22h

Query-unique ASII string “QRY”

12h 0059h 24h

13h 0002h 26h

Primary vendor instruction set and control interface ID code 14h 0000h 28h

15h 0040h 2Ah

Address for primary algorithm extended query table 16h 0000h 2Ch

17h 0000h 2Eh

Alternate vendor instruction set and control interface ID code 18h 0000h 30h

19h 0000h 32h

Address for alternate algorithm extended query table 1Ah 0000h 34h

Table 7-19 CFI Mode: ID Data Values

W29GL128C

Publication Release Date: July 28, 2010

25 Preliminary - Revision A

CFI mode: System Interface Data Values

Description Address

(Word Mode) Data Address

(Byte Mode)

VCC supply minimum program/erase voltage 1Bh 0027h 36h

VCC supply maximum program/erase voltage 1Ch 0036h 38h

VPP supply minimum program/erase voltage 1Dh 0000h 3Ah

VPP supply maximum program/erase voltage 1Eh 0000h 3Ch

Typical timeout per single word/byte write, 2n µs 1Fh 0003h 3Eh

Typical timeout for maximum-size buffer write, 2n µs (00h,

not support) 20h 0004h 40h

Typical timeout per individual block erase, 2n ms 21h 0009h 42h

Typical timeout for full chip erase, 2n ms (00h, not support) 22h 0010h 44h

Maximum timeout for word/byte write, 2n times typical 23h 0003h 46h

Maximum timeout for buffer write, 2n times typical 24h 0005h 48h

Maximum timeout per individual block erase, 2n times

typical 25h 0003h 4Ah

Maximum timeout for chip erase, 2n times typical (00h, not

support) 26h 0002h 4Ch

Table 7-20 CFI Mode: System Interface Data Values

W29GL128C

CFI mode: Device Geometry Data Values

Description Address

(Word Mode) Data Address

(Byte Mode)

Device size = 2n in number of bytes 27h 0018h 4Eh

28h 0002h 50h Flash device interface description (02=asynchronous

x8/x16) 29h 0000h 52h

2Ah 0006h 54h Maximum number of bytes in buffer write = 2n (00h, not

support) 2Bh 0000h 56h

Number of erase regions within device (01h:uniform,

02h:boot) 2Ch 0001h 58h

2Dh 007Fh 5Ah

2Eh 0000h 5Ch

2Fh 0000h 5Eh

Index for Erase Bank Area 1:

[2E,2D] = # of same-size sectors in region 1-1

[30, 2F] = sector size in multiples of 256K-bytes

30h 0002h 60h

31h 0000h 62h

32h 0000h 64h

33h 0000h 66h

Index for Erase Bank Area 2

34h 0000h 68h

35h 0000h 6Ah

36h 0000h 6Ch

37h 0000h 6Eh

Index for Erase Bank Area 3

38h 0000h 70h

39h 0000h 72h

3Ah 0000h 74h

3Bh 0000h 76h

Index for Erase Bank Area 4

3Ch 0000h 78h

Table 7-21 CFI Mode: Device Geometry Data Values

W29GL128C

Publication Release Date: July 28, 2010

27 Preliminary - Revision A

CFI mode: Primary Vendor-Specific Extended Query Data Values

Description Address

(Word Mode) Data Address

(Byte Mode)

40h 0050h 80h

41h 0052h 82h

Query - Primary extended table, unique ASCII string, PRI

42h 0049h 84h

Major version number, ASCII 43h 0031h 86h

Minor version number, ASCII 44h 0033h 88h

Unlock recognizes address (0= recognize, 1= don't recognize) 45h 000Ch 8Ah

Erase suspend (2= to both read and program) 46h 0002h 8Ch

Sector protect (N= # of sectors/group) 47h 0001h 8Eh

Temporary sector unprotect (1=supported) 48h 0000h 90h

Sector protect/Chip unprotect scheme 49h 0008h 92h

Simultaneous R/W operation (0=not supported) 4Ah 0000h 94h

Burst mode (0=not supported) 4Bh 0000h 96h

Page mode (0=not supported, 01 = 4 word page, 02 = 8 word

page) 4Ch 0002h 98h

Minimum ACC(acceleration) supply (0= not supported),

[D7:D4] for volt, [D3:D0] for 100mV 4Dh 0095h 9Ah

Maximum ACC(acceleration) supply (0= not supported),

[D7:D4] for volt, [D3:D0] for 100mV 4Eh 00A5h 9Ch

WP# Protection

04=Uniform sectors bottom WP# protect

05=Uniform sectors top WP# protect

4Fh 00xxh 9Eh

Program Suspend (0=not supported, 1=supported) 50h 0001h A0h

Table 7-22 CFI mode: Primary Vendor-Specific Extended Query Data Values

W29GL128C

8 ELECTRICAL CHARACTERISTICS(1)

8.1 Absolute Maximum Stress Ratings

Surrounding Temperature with Bias -65°C to +125°C

Storage Temperature -65°C to +150°C

VCC Voltage Range -0.5V to +4.0V

EVIO Voltage Range -0.5V to +4.0V

A9, #WP/ACC Voltage Range -0.5V to +4.0V

Other Pins Voltage Range -0.5V to VCC +0.5V

Output Short Circuit Current (less than one second) 200 mA

Table 8-1 Absolute Maximum Stress Ratings

8.2 Operating Temperature and Voltage

Industrial (I) Grade Surrounding Temperature (TA) -40°C to +85°C

Full VCC Range Supply Voltage +2.7V to 3.6V

Regulated VCC Range Supply Voltage +3.0V to 3.6V

EVIO Range Supply Voltage 1.65V to VCC

Table 8-2 Operating Temperature and Voltage

NOTE:

1. Specification for the W29GL128C is preliminary. See preliminary designation at the end of this document.

2. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the

device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended period may affect reliability.

3. Specifications contained within the following tables are subject to change.

4. During voltage transitions, all pins may overshoot VSS to -2.0V and VCC to +2.0V for periods up to 20ns, see below

Figure.

Vss

Vss -2.0V

20ns 20ns

20ns

Vcc +2.0V

Vcc

20ns

20ns20ns

Figure 8-1 Maximum Negative Overshoot Figure 8-2 Maximum Positive Overshoot

W29GL128C

Publication Release Date: July 28, 2010

29 Preliminary - Revision A

8.3 DC Characteristics

DESCRIPTION SYMBOL Conditions MIN TYP. MAX Unit

Others ±2.0 µA

Input Leak ILI WP#/ACC

±5.0 µA

A9 Leak ILIT A9=10.5V 35 µA

Output Leak ILO ±1.0 µA

#CE=VIL, #OE=VIH,

VCC=VCCmax;f=1MHz 6 20 mA

#CE=VIL, #OE=VIH,

VCC=VCCmax;f=5MHz 20 30 mA

Read Current ICC1

#CE=VIL, #OE=VIH,

VCC=VCCmax;f=10MHz 45 55 mA

#CE=VIL, #OE=VIH,

VCC=VCCmax;f=10MHz 7 15 mA

VCC Page Read Current ICC2 #CE=VIL, #OE=VIH,

VCC=VCCmax;f=33MHz 15 25 mA

EVIO Non-active Current IIO 0.2 10 mA

Write Current ICC3 #CE=VIL, #OE=VIH, VCC=VCCmax 20 30 mA

Standby Current ICC4 VCC=VCCmax, other pins disabled 10 20 µA

Reset Current ICC5 VCC=VCCmax, #RESET enabled,

other pins disabled 10 20 µA

Sleep Mode Current ICC6

VCC=VCCmax, VIH=VCC ±0.3,

VIL=VSS +(0.3v/-0.1v),

#WP/ACC=VIH

10 20 µA

VCC deep power down

current IDPD 1 5 µA

Accelerated Pgm

Current, WP#/ACC,

pin(Word/Byte)

IACC1

#CE=VIL, #OE=VIH

10 20 mA

Accelerated Pgm

Current, VCC pin,

(Word/Byte)

IACC2

#CE=VIL, #OE=VIH

20 30 mA

Input Low Voltage VIL -0.1 0.3xEVIO V

Input High Voltage VIH 0.7xEVIO EVIO+0.3 V

Very High Voltage for

Auto Select/

Accelerated Program

VHH

9.5 10.5

Output Low Voltage VOL IOL=100µA 0.45 V

Output High Voltage VOH IOH=-100µA 0.85xEVIO V

VCC Write Protect

Threshold VWPT 2.3 2.5 V

Table 8-3 DC Characteristics

Note:

1. Sleep mode enable the lower power when address remain stable for tAA+30ns

W29GL128C

8.4 Switching Test Circuits

Figure 8-3 Switch Test Circuit

DEVICE UNDER

TEST

CL 6.2KΩ

2.7KΩ

3.3V

DEVICE UNDER

TEST

CL 6.2KΩ

2.7KΩ

3.3V

Test Condition All Speeds Unit

Output Load 1TTL gate

Output Load Capacitance 30 pF

Rise/Fall Times 5 ns

Input Pulse levels 0.0 - EVIO V

Input timing measurement reference level (If EVIO<VCC, the reference level

is 0.5 EVIO) 0.5EVIO V

Output timing measurement reference levels 0.5EVIO V

Table 8-4 Test Specification

8.4.1 Switching Test Waveform

Test Points

INPUT

EVIO / 2

OUTPUT

EVIO / 2

EVIO

0.0V

Test Points

INPUT

EVIO / 2

OUTPUT

EVIO / 2

EVIO

0.0V

Figure 8-4 Switching Test Waveform

W29GL128C

Publication Release Date: July 28, 2010

31 Preliminary - Revision A

8.5 AC Characteristics

Symbol VCC=2.7V~3.6V

Description Min Max Units

EVIO=VCC 90 ns

Valid Data Output after Address EVIO=1.65V to VCC tAA 100 ns

EVIO=VCC 25 ns

Page Access Time EVIO=1.65V to VCC tPA 35 ns

EVIO=VCC 90 ns

Valid data output after #CE low EVIO=1.65V to VCC

tCE

100 ns

EVIO=VCC 25 ns

Valid data output after #OE low EVIO=1.65V to VCC

tOE

35 ns

EVIO=VCC 90 ns

Read Period Time EVIO=1.65V to VCC

tRC

100 ns

Data Output High Impedance after #OE high tDF 20 ns

Data Output High Impedance after #CE high tDF 20 ns

Output Hold Time from the earliest rising edge of address, #CE,

#OE tOH 0 ns

Write Period Time tWC 90 ns

Address Setup Time tAS 0 ns

Address Setup Time to #OE low during Toggle Bit Polling tASO 15 ns

Address Hold Time tAH 45 ns

Address Hold Time from #CE or #OE High during Toggle Bit

Polling tAHT 0 ns

Data Setup Time tDS 30 ns

Data Hold Time tDH 0 ns

VCC Setup Time tVCS 500 ns

Chip enable Setup Time tCS 0 ns

Chip enable Hold Time tCH 0 ns

Output enable Setup Time tOES 0 ns

Read 0 ns

Output enable Hold Time Toggle & Data#

Polling

tOEH

10 ns

#WE Setup Time tWS 0 ns

#WE Hold Time tWH 0 ns

#CE Pulse Width tCEPW 35 ns

#CE Pulse With High tCEPWH 30 ns

#WE Pulse Width tWP 35 ns

#WE Pulse Width High tWPH 30 ns

EVIO=VCC 90 ns

Program/Erase active time by RY/#BY EVIO=1.65V to VCC tBUSY 110 ns

Read Recover Time before Write (#OE High to #WE Low) tGHWL 0 ns

Read Recover Time before Write (#OE High to #WE Low) tGHEL 0 ns

32-Word Write Buffer Program Operation tWHWH1 192 µs

Effective Write Buffer Program

Operation Byte tWHWH1 3 14 µs

Effective Write Buffer Program

Operation Word tWHWH1 6 28 µs

Accelerated Effective Write Buffer

Operation Per Word tWHWH1 4.8 µs

Program Operation Byte tWHWH1 6 28 µs

W29GL128C

Program Operation Word tWHWH1 6 28 µs

ACC 32-Word Program Operation tWHWH1 154 µs

Sector Erase Operation tWHWH2 0.3 2 Sec

Sector Erase Timeout tSEA 50 µs

Release from Deep Power Down mode tRDP 100 200 µs

Table 8-5 AC Characteristics

8.5.1 Instruction Write Operation

DATA IN

VALID ADDRESS

OES

WPH

CWC

#CE

#WE

#OE

Addresses

Data

Figure 8-5 Instruction Write Operation Waveform

W29GL128C

Publication Release Date: July 28, 2010

33 Preliminary - Revision A

8.5.2 Read / Reset Operation

#CE

#WE

#OE

Addresses

Outputs

HIGH Z HIGH Z

ADD Valid

DATA Valid

OEH

Figure 8-6 Read Timing Waveform

8.5.2.1 AC Characteristics

Description Symbol Setup Speed Unit

#RESET Pulse Width (During Automatic Algorithm) tRP1 MIN 10 µs

#RESET Pulse Width (NOT During Automatic Algorithm) tRP2 MIN 500 ns

#RESET High Time Before Read tRH MIN 200 ns

RY/#BY Recovery Time (to #CE, #OE goes low) tRB1 MIN 0 ns

RY/#BY Recovery Time (to #WE goes low) tRB2 MIN 50 ns

#RESET Low (During Automatic Algorithm) to Read or Write tREADY1 MAX 20 µs

#RESET Low (Not During Automatic Algorithm) to Read or Write tREADY2 MAX 500 ns

Table 8-6 AC Characteristics #RESET and RY/#BY

W29GL128C

≈≈≈≈

#CE, #OE

#WE

RY/#BY

#RESET

Reset Timing during Automatic Algorithms

Reset Timing NOT during Automatic Algorithms

#CE, #OE

RY/#BY

#RESET

READY

Figure 8-7 #RESET Timing Waveform

W29GL128C

Publication Release Date: July 28, 2010

35 Preliminary - Revision A

8.5.3 Erase/Program Operation

≈≈≈≈

≈

WHWH

WPH

GHWL

BUSY

Read Status

Valid Address V. Add555h2AAh

55h 10h

Progress Complete

Last 2 Erase Command Cycles

#CE

#WE

#OE

Address

Data

RY/#BY

≈≈

Figure 8-8 Automatic Chip Erase Timing Waveform

W29GL128C

START

Write Data AAh Address 555h

Write Data 55h Address 2AAh

Write Data 80h Address 555h

Write Data AAh Address 555h

Write Data 55h Address 2AAh

Write Data 10h Address 555h

Data# Polling Algorithm or

Toggle Bit Algorithm

Data = FFh?

Auto Chip Erase Completed

Figure 8-9 Automatic Chip Erase Algorithm Flowchart

W29GL128C

Publication Release Date: July 28, 2010

37 Preliminary - Revision A

≈≈ ≈ ≈

#CE

#WE

#OE

Address

Data

RY/#BY

Read Status

WPH

WHWH

GHWL

SEA

BUSY

Valid Address V. ADD.

Progress Completed

2AAh

55h 30h 30h 30h

Last 2 Erase Command Cycle

Sector

ADD 0

Sector

ADD 1

Sector

ADD n

≈≈

Figure 8-10 Automatic Sector Erase Timing Waveform

≈

W29GL128C

START

Write Data AAh Address 555h

Write Data 55h Address 2AAh

Write Data 80h Address 555h

Write Data AAh Address 555h

Write Data 55h Address 2AAh

Write Data 30h Sector Address

Last

Sector to

Erase

Data# Polling Algorithm or Toggle Bit Algorithm

Data=FFh

Figure 8-11 Automatic Sector Erase Algorithm Flowchart

YES

Auto Sector Erase

Completed

W29GL128C

Publication Release Date: July 28, 2010

39 Preliminary - Revision A

START

Write Data B0h

Figure 8-12 Erase Suspend/Resume Flowchart

Toggle Bit

checking DQ6

not toggled

Read Array or

Program

Reading or

Programming

End

Write Data 30h

Continue Erase

Another

Erase

Suspend?

ERASE SUSPEND

YES

ERASE RESUME

W29GL128C

Figure 8-13 Automatic Program Timing Waveform

Figure 8-14 Accelerated Program Timing Waveform

#WP/ACC

IL or

(9.5V ~ 10.5V)

250ns

≈

250ns

IL or

#CE

#WE

#OE

ddress

Data

RY/#BY

555h Program Address Valid Address V. Add

A0h PData Status DOUT

Last 2 Program Command Cycles

WPH

GHWL

WHWH

BUSY

Last 2 Read Status Cycles

≈≈ ≈ ≈≈≈ ≈

W29GL128C

Publication Release Date: July 28, 2010

41 Preliminary - Revision A

≈≈≈≈

#WE

#CE

#OE

Address

Data

RY/#BY

555h PGM ADD Valid Address V.Add

A0h PD Status DOUT

CEPW

WHWH

CEPWH

GHWL

BUSY

≈

≈≈

Figure 8-15 CE# Controlled Write Timing Waveform

W29GL128C

START

Write Data AAh Address 555h

Write Data 55h Address 2AAh

Write Data A0h 555h

Write Program Data/Address

Data# Polling Algorithm

Toggle Bit Algorithm

Figure 8-16 Automatic Programming Algorithm Flowchart

Read Again Data:

Program Data?

Next Address

Last Word to be

Programmed

YES

Auto Program Completed

W29GL128C

Publication Release Date: July 28, 2010

43 Preliminary - Revision A

VCC

ADD

#CE

#WE

#OE

[15:0]

Manufacturer ID Device ID

Cycle 1

Device ID

Cycle 2

Device ID

Cycle 3

DATA OUT DATA OUT DATA OUT DATA OUT

Figure 8-17 Silicon ID Read Timing Waveform

W29GL128C

8.5.4 Write Operation Status

Figure 8-18 Data# Polling Timing Waveform (During Automatic Algorithms)

≈≈≈≈≈

≈≈

#CE

#WE

#OE

Address

DQ7

DQ[6-0]

RY/#BY

OEH

BUSY

VALID ADDRESS VALID ADDRESS

VALID DATA High Z

True

Complement

Status Data

≈

VALID DATA High Z

True

Complement

Status Data

W29GL128C

Publication Release Date: July 28, 2010

45 Preliminary - Revision A

Figure 8-19 Status Polling for Word Programming/Erase

Start

Read DQ[7:0] at Valid Address

(1)

DQ7=Data#?

DQ5=1?

Read DQ[7:0] at Valid Address

DQ7=Data#?

(2)

Notes:

1. For programming, valid address means program address. For erasing, valid address means erase sectors address.

2. DQ7 should be rechecked even DQ5="1" because DQ7 may change simultaneously with DQ5.

Fail

YES

Pass

W29GL128C

START

Read DQ[7:0] at Last

Write Address

(1)

DQ7=Data#?

DQ1=1?

Only for Write Buffer

Program

DQ5=1?

Read DQ[7:0] at Last

Write Address

(1)

DQ7=Data#?

(2)

Figure 8-20 Status Polling for Write Buffer Program Flowchart

Notes:

1. For programming, valid address means program address.

2. For erasing, valid address means erase sectors address.

3. DQ7 should be rechecked even DQ5="1" because DQ7 may change simultaneously with DQ5.

Fail Pass

YES

Write Buffer

Abort

W29GL128C

Publication Release Date: July 28, 2010

47 Preliminary - Revision A

OEH

VALID ADDRESS VALID ADDRESS

AHT

ASO

(First Read) (Second Read) (Stop Toggling)

VALID ADDRESS VALID ADDRESS

BUSY

#CE

#WE

#OE

Address

DQ6&2

RY/#BY

≈≈ ≈ ≈≈ ≈

VALID STATUS VALID STATUS VALID STATUS VALID STATUS

Figure 8-21 Toggling Bit Timing Waveform (During Automatic Algorithms)

≈

W29GL128C

START

Read DQ[7:0] Twice(1)

DQ6 Toggle?

DQ5=1?

Read DQ[7:0] Twice

DQ6 Toggle?

Figure 8-22 Toggle Bit Algorithm

Notes:

1. Read toggle bit twice to determine whether or not it is toggling.

2. Recheck toggle bit because it may stop toggling as DQ5 changes to "1".

8.5.5 WORD/BYTE CONFIGURATION (#BYTE)

Description Symbol Test Setup All Speed options Unit

#CE to #BYTE from L/H tELFL/tELFH MAX. 5 ns

#BYTE from L to Output Hiz tFLQZ Max. 30 ns

#BYTE from H to Output Active tFHQV Min. 90 ns

Table 8-7 AC Characteristics Word/Byte Configuration (#BYTE)

Program/Erase Fail

Write Reset CMD

YES

Program/Erase

Completed

W29GL128C

Publication Release Date: July 28, 2010

49 Preliminary - Revision A

Figure 8-23 #BYTE Timing Waveform For Read operations

Figure 8-24 Page Read Timing Waveform

DOUT

DQ[7:0]

DOUT

DQ[14:0]

VALID ADDRESS DOUT

DQ15

ELFH

#OE

#CE

DQ[14:0]

DQ15/A-1

#BYTE

FHQV

VALID ADDRESS

ADD 2

ADD 3

ADD

DATA 1 DATA 2 DATA 3

≈≈ ≈≈≈≈

ADD[22:3]

ADD[2:0], A-1

Word, Byte

DATA[15:0]

#CE/#OE

W29GL128C

8.5.6 DEEP POWER DOWN MODE

Description SYMBOL TYP. MAX

#WE High to release from Deep Power Down Mode tRDP 100µs 200µs

#WE High to Deep Power Down Mode tDP 10µs 20µs

Table 8-8 AC Characteristics for Deep Power Down

#CE

#WE

Address

Data

RDP

XXh (Don’t Care)XXh55h 2AAh

AAh 55h B9h B9h

Standby mode Deep Power Down mode Standby mode

Figure 8-25 Deep Power Down mode Waveform

8.5.7 WRITE BUFFER PROGRAM

Write CMD: DATA=29h, ADD=SA

Write CMD: DATA=AAh, ADD=555h

Figure 8-26 Write Buffer Program Flowchart

Write CMD: DATA=55h, ADD=2AAh

Polling Status

Write CMD: DATA=25h, ADD=SA

PASS?

Write CMD: DATA=PWC, ADD=SA

Write CMD: DATA=PGM DATA,

ADD=PGM ADD Return to Read mode

Want to Abort?

PWC=0?

Write Reset CMD

to return to Read mode

Write Abort Reset CMD

to return to Read mode

Write a different Sector Address

to cause Abort

FAIL?

Write Buffer Abort?

PWC=PWC-1

NO YES

YES

SA = Sector Address of the Page to be Programmed

PWC = Program Word Count

W29GL128C

Publication Release Date: July 28, 2010

51 Preliminary - Revision A

8.6 Recommended Operating Conditions

8.6.1 At Device Power-up

AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at

device power-up. If the timing in the figure is ignored, the device may not operate correctly.

VCS

Figure 8-27 AC Timing at Device Power-Up

Description SYMBOL MIN MAX UNIT

VCC Rise Time tVR 20 500,000 µs/V

Input Signal Rise Time tR 20 µs/V

Input Signal Fall Time tF 20 µs/V

VCC Setup Time tVCS 500 µs

Table 8-9 AC Characteristics at Device Power Up

Ror

High Z

Ror

VCC

#CE

#WE

#OE

ADDRESS

DATA

#WP/ACC

CC(min)

GND

VALID ADDRESS

Valid Data

Out

W29GL128C

8.7 Erase and Programming Performance

LIMITS

PARAMETER MIN TYP(1) MAX(2) UNITS

Chip Erase Time 38.4 256 Sec

Sector Erase Time 0.3 2 Sec

Chip Programming Time 48 224 Sec

Word Programming Time 6 28 µs

Total Write Buffer Time 192 µs

ACC Total Write Buffer Time 154 µs

Erase/Program Cycles 100,000 Cycles

Table 8-10 AC Characteristics for Erase and Programming Performance

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC. Programming specifications

assume checkboard data pattern.

2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and

including 100,000 program/erase cycles.

3. Erase/Program cycles comply with JEDEC JESD-47E & A117A standard.

4. Exclude 00h program before erase operation.

8.8 Data Retention

PARAMETER CONDITION MIN MAX UNIT

Data Retention 55°C 20 Years

Table 8-11 Data Retention

8.9 Latch-up Characteristics

PARAMETER MIN MAX

Input Voltage different with GND on #WP/ACC and A9 pins -1.0V 10.5V

Input Voltage difference with GND on all normal input pins -1.0V 1.5xVCC

VCC Current -100mA +100mA

All pins included except VCC. Test condition is VCC=3.0V, one pin per test.

Table 8-12 Latch-up Characteristics

8.10 Pin Capacitance

DESCRIPTION PARAMETER TEST SET TYP. MAX UNIT

Control Pin Capacitance CIN2 VIN=0 7.5 9 pF

Output Capacitance COUT VOUT=0 8.5 12 pF

Input Capacitance CIN VIN=0 6 7.5 pF

Table 8-13 Pin Capacitance

W29GL128C

Publication Release Date: July 28, 2010

53 Preliminary - Revision A

9 PACKAGE DIMENSIONS

9.1 TSOP 56-pin 14x20mm

PIN 1

IDENTIFIER

A2 R

0.80 REF

BOTTOM EJECTOR PIN

CAVITY # MARK

28 29

0.10

WITH PLATING

cc1

BASE

METAL

Dimension in MM Dimension Inch

Symbol MIN NOM MAX MIN NOM MAX

A - - 1.2 - - 0.047

A1 0.05 - 0.15 0.002 - 0.006

A2 0.95 1.00 1.05 0.037 0.039 0.041

b 0.17 0.22 0.27 0.007 0.009 0.011

b1 0.17 0.20 0.23 0.007 0.008 0.009

c 0.10 - 0.21 0.004 - 0.008

c1 0.10 0.13 0.16 0.004 0.005 0.006

D 20.00 BSC 0.787 BSC

D1 18.40 BSC 0.724 BSC

E 14.00 BSC 0.551 BSC

L 0.50 0.60 0.70 0.020 0.024 0.028

L1 0.25 BSC 0.010 BSC

0.5 BSC 0.020 BSC

R 0.08 - 0.35 0.003 - 0.008

θ 0° - 8° 0° - 8°

Figure 9-1 TSOP 56-pin 14x20mm

W29GL128C

9.2 Fortified BGA 64-ball 11x13mm (LAA64)

0.07

(2X)

TOP VIEW

PIN A1

CORNER

0.07 C

(2X)

PIN A1

CORNER

Øb

BOTTOM VIEW

HGFEDCBA

0.15 C0.15 C

0.25 C

AA2

A1 C

SIDE VIEW

64X Øb

Ø0.20

Ø0.10

DIMENSION (MM)

SYMBOL NOTE

MIN NOM MAX

A - - 1.40 PROFILE

A1 0.40 - BALL HEIGHT

A2 0.60 - BODY THICKNESS

D 13.00 BSC BODY SIZE

E 11.00 BSC BODY SIZE

D1 7.00 BSC MATRIX FOOTPRINT

E1 7.00 BSC MATRIX FOOTPRINT

n 64 BALL COUNT

Øb 0.5 0.6 0.7 BALL DIAMETER

eE 1.00 BSC BALL PITCH

eD 1.00 BSC BALL PITCH

SD/SE 0.50 BSC SOLDER BALL PLACEMENT

NONE DEPOPULATED SOLDER BALLS

Figure 9-2 BGA 64-ball 11x13mm

W29GL128C

Publication Release Date: July 28, 2010

55 Preliminary - Revision A

10 ORDERING INFORMATION

10.1 Ordering Part Number Definitions

29GL 128 C H 9 T

Winbond Standard Product

W: Winbond

Product Family

29GL: 3V

Density

032: 32Mb

064: 64Mb

128: 128Mb

256: 256Mb

Product Version

C: 90nm

Sector Type

H: EVIO=VCC=2.7~3.6V,Uniform sector, highest address sector protected

VIO=1.65V to VCC(2.7~3.6V),Uniform sector, highest address sector protected

L: EVIO=VCC=2.7~3.6V,Uniform sector, lowest address sector protected

VIO=1.65V to VCC(2.7~3.6V),Uniform sector, lowest address sector protected

Access Time

9: 90ns 1: 110ns

Packages

T: TSOP-56, Industrial (-40°C~+85°C) and Green (RoHS Compliant)

B: BGA-64, Industrial (-40°C~+85°C) and Green (RoHS Compliant)

Figure 10-1 Ordering Part Numbering

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Contact Winbond Sales for Secured Sector Lock Options.

W29GL128C

10.2 Valid Part Numbers and Top Side Marking

The following table provides the valid part numbers for the W29GL128C Parallel Flash Memory.

Please contact Winbond for specific availability by density and package type. Winbond Parallel

memories use a 12-digit Product Number for ordering.

PACKAGE TYPE DENSITY PRODUCT NUMBER TOP SIDE MARKING

TSOP-56 128Mb W29GL128CH9T W29GL128CH9T

TSOP-56 128Mb W29GL128CH1T W29GL128CH1T

TSOP-56 128Mb W29GL128CL9T W29GL128CL9T

TSOP-56 128Mb W29GL128CL1T W29GL128CL1T

BGA-64 128Mb W29GL128CH9B W29GL128CH9B

BGA-64 128Mb W29GL128CH1B W29GL128CH1B

BGA-64 128Mb W29GL128CL9B W29GL128CL9B

BGA-64 128Mb W29GL128CL1B W29GL128CL1B

Table 10-1 Valid Part Numbers and Markings

W29GL128C

Publication Release Date: July 28, 2010

57 Preliminary - Revision A

11 HISTORY

VERSION DATE PAGE DESCRIPTION

A 07-28-2010 - Preliminary Issue

Table 11-1 Revision History

Preliminary Designation

The “Preliminary” designation on a Winbond datasheet indicates that the product is not full

characterized. The specifications are subject to change and are not guaranteed. Winbond or an

authorized sales representative should be consulted for current information before using this product.

Trademarks

Winbond is a trademark of Winbond Electronics Corporation. All other marks are the property of their

respective owner.

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components in

systems or equipment intended for surgical implantation, atomic energy control instruments, airplane

or spaceship instruments, transportation instruments, traffic signal instruments, combustion control

instruments, or for other applications intended to support or sustain life. Further more, Winbond

products are not intended for applications wherein failure of Winbond products could result or lead to a

situation wherein personal injury, death or severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their own risk

and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.

Information in this document is provided solely in connection with Winbond products. Winbond

reserves the right to make changes, corrections, modifications or improvements to this document and

the products and services described herein at any time, without notice.