Preliminary AEC Q100 Grade 1 Compliant
This is a product that has fixed target specifications but are subject Ramtron International Corporation
to change pending char acterization results. 1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
Rev. 1.0
http://www.ramtron.com
Feb. 2011 Page 1 of 13
FM25L16B – Automotive Temp.
16Kb Serial 3V F-RAM Memory
Features
16K bit Ferroelectric Nonvolatile RAM
• Organized as 2,048 x 8 bits
• High Endurance 100 Trillion (10
13
) Read/Wr ites
• NoDelay™ Writes
• Advanced Hi gh-Reliability Fe rroelectric Process
Fast Serial Peripheral Interface - SPI
• Up to 15 MHz Frequency
• Direct Hardware Replacement for EEPROM
• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Sophisticated Writ e P r otection Scheme
• Hardware Protection
• Software P r otection
Low P ower Consumption
• Low Voltage Operation 3.0-3.6V
• 6 µA Standby Current (+85C)
Industry St andard Configuration
• Automotive Te mperature -40°C to +125°C
o Qualified to AEC Q100 Specification
• 8-pin “Green”/RoHS SOIC Package
Description
The FM25L16B is a 16-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.
The FM25L16B performs write operations at bus
speed. No write delays are incurred. Data is written to
the memory array immediately after each byte has
been transferred to the device. The next bus cycle
may commence without the need for data polling.
The FM25L16B is capable of supporting 10
13
read/write cycles, or 10 million times more write
cycles than EEPROM.
These capabilities make the FM25L16B ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection,
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause da ta lo ss.
The FM25L16B provides substantial benefits to users
of serial EEPROM as a hardware drop-in
replacement. The FM25L16B uses the high-speed
SPI bus, which enhances the high-speed write
capability of F-RAM technology. Device
specifications are guaranteed over an automotive
temperature range of -40°C to +125°C.
Pin Configuration
Pin Name Function
/CS Chip Select
/WP Write Protect
/HOLD Hold
SCK Serial Clock
SI Serial Data Input
SO Serial Data Output
VDD Supply Voltage
VSS Ground
Ordering Information
FM25L16B-GA “Green”/RoHS 8-pin SOIC,
Automotive Grad e 1
FM25L16B-GATR “Green”/RoHS 8-pin SOIC,
Automotive Grad e 1,
Tape & Reel
CS
SO
WP
VSS
VDD
HOLD
SCK
SI
1
2
3
4
8
7
6
5
FM25L16B - Automotive Temp.
Rev. 1 .0
Feb. 2011 Page 2 of 13
Instruction Decode
Clock Gener ator
Control Logic
Write Protect
Instruction Register
Address Register
Counter
256 x 64
FRAM Array
11
Data I/O Regist er
8
Nonvolatile Status
Register
3
WP
CS
HOLD
SCK
SOSI
Figure 1. Block Diagram
Pin Description s
Pin Name I/O Description
/CS Input Chip Select: This active low input activates the device. When high, the device enters
low-power standby mode, ignores other inputs, and all outputs are tri-stated. When
low, the device internally activates the SCK signal. A falling edge on /CS must occur
prior to every op-code.
SCK Input Serial Clock: All I/O activity is sync hronized to the serial clock. Inputs are latched on
the rising edge and outputs occur on the falling edge. Since the device is static, the
clock frequency may be any value between 0 and 15 MHz and may be interrupted at
any time.
/HOLD Input Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation
for another task. When /HOLD is low, the current operation is suspended. The device
ignores any transition on SCK or /CS. All transitions on /HOLD must occur while
SCK is lo w.
/WP Input Write P rotect: T his active low pin p revent s write oper ation s to the sta tu s regi ster. T his
is critical since other write protection features are controlled through the status
register. A complete explanation of write protection is provided on pages 6 and 7.
SI Input Serial Input: All data is input to the device on this pin. The pin is sampled on the
rising edge of SCK and is ignored at other times. It should always be driven to a valid
logic level to meet I
DD
specifications.
* SI may be connected to SO for a single pin data interface.
SO Output Serial Output: This is the data output pin. It is driven during a read and remains tri-
stated at all other times including when /HOLD is low. Data transitions are driven on
the falling edge of the serial clock.
* SO may be connected to SI for a single pin data interface.
VDD Supply Power Supply (3.0V to 3.6V)
VSS Supply Ground
FM25L16B - Automotive Temp .
Rev. 1 .0
Feb. 2011 Page 3 of 13
Overview
The FM25L16B is a serial F-RAM memory. The
memory array is logically organized as 2,048 x 8 and
is accessed using an industry standard Serial
Peripheral Interface or SPI bus. Functional operation
of the F-RAM is similar to serial EEPROMs. The
major difference betwee n the FM25L16B and a serial
EEPROM with the same pinout is the F-RAM’s
superior write perfor mance.
Memory Archit ectu re
When accessing the FM25L16B, the user addresses
2,048 locations of 8 data bits each. These data bits
are shifted serially. The addresses are accessed using
the SPI protocol, which includes a chip select (to
permit multiple devices on the bus), an op-code, and
a two-byte address. The upper 5 bits of the address
range are ‘don’t care’ values. The complete address
of 11-bits speci fies each byte address uniquely.
Most functions of the FM25L16B either are
controlled by the SPI interface or are handled
automatically by on-board circuitry. The access time
for memory operation is essentially zero, beyond the
time needed for the serial protocol. That is, the
memory is read o r written at the speed of the SP I bus.
Unlike an EEPROM, it is not necessary to poll the
device for a read y co ndition since writes occur at bus
speed. So, by the time a new bus transaction can be
shifted into the device, a write operation will be
complete. This is explained in more detail in the
interface section.
Users expect several obvious system benefits from
the FM25L16B due to its fast write cycle and high
endurance as compared with EEPROM. In addition
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to no ise during much of the cycle.
Note that the FM25L16B contains no power
management circuits other than a simple internal
power-on reset. It is the user’s responsibility to
ensure that V
DD
is within datasheet tolerances to
prevent incorrect operation. It is recommended
that the part is not powered down w ith chip select
active.
Serial Peripheral Interface – SPI Bus
The FM25L16B employs a Serial Peripheral
Interface (SPI) bus. It is specified to operate at speeds
up to 10 MHz. This high-speed serial bus provides
high performance serial communication to a host
microcontroller. Many common microcontrollers
have hardware SPI ports allowing a direct interface.
It is quite simple to emulate the port using ordinary
port pins for microcontrollers that do not. The
FM25L16B operates in SPI Mode 0 and 3.
The SPI interface uses a total of four pins: clock,
data-in, data-out, and chip select. A typical system
configuration uses one or more FM25L16B devices
with a microcontroller that has a dedicated SPI port,
as Figure 2 illustrates. Note that the clock, data-in,
and data-out pins are common among all devices.
The Chip Select and Hold pins must be driven
separately for each FM25L16B device.
For a microcontroller that has no dedicated SPI bus, a
general purpose port may be used. To reduce
hardware resources on the controller, it is possible to
connect the two data pins (SI, SO) together and tie
off (high) the Hold pin. Figure 3 shows a
configuration that uses only three pins.
Protocol Overview
The SPI interface is a synchronous serial interface
using clock and data pins. It is intended to support
multiple devices on the bus. Each device is activated
using a chip select. Once chip select is activated by
the bus master, t he FM25L16B will begin monitorin g
the clock and da ta line s. T he re lations hip b et ween t he
falling edge of /CS, the clock and data is dictated by
the SPI mode. The device will make a determination
of the SPI mode on the falling edge of each chip
select. While there are four such modes, the
FM25L16B supports Modes 0 and 3. Figure 4 shows
the required signal relationships for Modes 0 and 3.
For both modes, data is clocked into the FM25L16B
on the rising edge of SCK a nd data is expected on the
first rising edge after /CS goes active. If the clock
begins from a high state, it will fall prior to beginning
data transfer in order to create the first rising edge.
The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the device. After
/CS is activated the first byte transferred from the bus
master is the op-code. Following the op-code, any
addresses and data are then transferred. Note that the
WREN and WRDI op-codes are commands with no
subsequent data trans fer.
Important: The /CS must go inactive (high) after
an operation is co mplete and before a new op-code
can be issued. There is one valid op-code only per
active chip select.
FM25L16B - Automotive Temp .
Rev. 1 .0
Feb. 2011 Page 4 of 13
SPI
Microcontroller FM25L16B
SO SI SCK
CS HOLD
FM25L16B
SO SI SCK
CS HOLD
SCK
MOSI
MISO
SS1
SS2
HOLD1
HOLD2
MOSI : Master Out Slave In
MISO : Master In Slave Out
SS : Slave Select
Figure 2. Sy st em Configuration wit h SP I port
Microcontroller
FM25L16B
SO SI SCK
CS HOLD
P1.0
P1.1
P1.2
Figure 3. Sy st em Configuration w it hout SPI port
SPI Mode 0: CPOL=0, CPHA=0
01234567
SPI Mode 3: CPOL=1, CPHA=1
01234567
Figure 4. SPI Modes 0 & 3
FM25L16B - Automotive Temp .
Rev. 1 .0
Feb. 2011 Page 5 of 13
Data Transfer
All data transfers to and from the FM25L16B occur
in 8-bit groups. They are synchronized to the clock
signal (SCK), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of SCK. Outputs are driven from the falling
edge of SCK.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25L16B . They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the status
register. The third group includes commands for
memory transactions followed by a n address and one
or more bytes of data.
Table 1. Op-code Commands
Name Description Op-code
WREN
Set Write Enable Latch 0000
0110b
WRDI
Write Disable 0000
0100b
RDSR
Read Status Register 0000
0101b
WRSR
Write Stat us Register 0000
0001b
READ
Read Memor y Data 0000
0011b
WRITE
Write Memo ry Data 0000
0010b
WREN - Set Write Enable Latch
The FM25L16B will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for
write operations. These include writing the status
register and writing the me mory.
Sending the WREN op-code causes the internal
Write Enable Latch to b e set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the status
register has no effect. Completing any write
operation will automatically clear the write-enable
latch and prevent further writes without another
WREN command. Figure 5 below illustrates the
WREN command bus co nfiguration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the sta tus r egister and ve rifyi ng t hat W EL= 0. Fi gure
6 illustrates the WRDI command bus con figuration.
Figure 5. WREN Bus Configuration
Figure 6. WRDI Bus Configuration
FM25L16B - Automotive Temp .
Rev. 1 .0
Feb. 2011 Page 6 of 13
RDSR - Read Status Register
The RDSR command allows the bus master to verify
the contents of the Status Register. Reading Status
provides information about the current state of the
write protection features. Following the RDSR op-
code, the FM25L16B will return one byte with the
contents of the Status Register. The Status Register is
described in detail in a later sectio n.
WRSR – Write Status Reg ister
The WRSR command allows the user to select
certain write pro tection featur es by writing a b yte to
the Status Register. Prior to issuing a WRSR
command, the /WP pin must be high or inactive.
Note that on the FM25L16B, /WP only prevents
writing to the Sta tus Re gis ter, no t the me mor y arra y.
Prior to sending t he WRSR command, the user must
send a WREN command to enable writes. Note that
executing a WRSR command is a write operation
and therefore clears the W r ite Enable Latch. The bus
configuration of RDSR and WRSR are shown
below.
Figure 7. RDSR Bus Configuration
Figure 8. WRSR Bus Configuration
(WREN not shown)
Status Register & Write Protection
The write protection features of the FM25L16B are
multi-tiered. First, a WREN op-code must be issued
prior to any write oper ation. Ass uming that writes are
enabled using WREN, writes to memory are
controlled by the Status Register. As described
above, writes to the status register are performed
using the WRSR command and subject to the /WP
pin. The Status Register is organized as follows.
Table 2. Sta t us Register
Bit 7 6 5 4 3 2 1 0
Name WPEN 0 0 0 BP1 BP0 WEL 0
Bits 0 and 4-6 are fixed at 0 and cannot be modified.
Note that bit 0 (Ready in EEPROMs) is unnecessary
as the F-RAM writes in real-time and is never busy.
The WPEN, BP1 and BP0 control write protection
features. They are nonvolatile (shaded yellow). The
WEL flag indicates the state of the Write Enable
Latch. Attempting to directly write the WEL bit in
the status register has no effect on its state. This bit
is internally set and cleared via the WREN and
WRDI commands, respectively.
BP1 and BP0 are memory block write protection
bits. They specify p ortions of me mo ry that are writ e
protected as shown in the following table.
Table 3. Block Memory Write Protection
BP1 B P0 Pr otecte d Address Range
0 0 None
0 1 600h to 7FFh (upper ¼)
1 0 400h to 7FFh (upper ½)
1 1 000h to 7FFh (all)
FM25L16B - Automotive Temp .
Rev. 1 .0
Feb. 2011 Page 7 of 13
The BP1 and BP0 bits and the Write Enable Latch
are the only mechanisms that protect the memory
from writes. The remaining write protection features
protect inadvertent changes to the block protect bits.
The WPEN bit controls the effect of the hardware
/WP pin. When WPEN is low, the /WP pin is
ignored. When WPEN is high, the /WP pin controls
write access to the status register. Thus the Status
Register is write protected if WPEN=1 and /WP=0.
This sche me pro vides a write p ro tection mechanism,
which can prevent software from writing the
memory under any circumstances. This occurs if the
BP1 and BP0 are set to 1, the WPEN bit is set to 1,
and /WP is set to 0. This occurs because the block
protect bits prevent writing memory and the /WP
signal in hardware prevents altering the block
protect bits (if WPEN is high). Therefore in this
condition, hardware must be involved in allowing a
write oper ation. The follo wing table s ummarizes the
write protection conditions.
Table 4. Write Protection
WEL WPEN /WP Protected Blocks Unprotected Blocks St atus Register
0 X X Protected Protected Protected
1 0 X Protected Unprotected Unprotected
1 1 0 Protected Unprotected Protected
1 1 1 Protected Unprotected Unprotected
Memory Operation
The SPI interface, which is capable of a relatively
high clock frequency, highlights the fast write
capability of the F-RAM technology. Unlike SPI-bus
EEPROMs, the FM25L16B can perform sequential
writes at bus speed. No page register is needed and
any number of sequential writes ma y be performed.
Write Operation
All writes to the memory array begin with a WREN
op-code. The next op-code is the WRITE instruction.
This op-code is followed by a two-byte address
value. T he upper 5-bits of the address are ignored. In
total, the 11-bits specify the address of the first data
byte of the write op eratio n. Su bseq uent b ytes are d ata
and they are written sequentially. Addresses are
incremented internally as long as the bus master
continues to issue clocks. If the last address of 7FFh
is reached, the counter will roll over to 000h. Data is
written MSB first. A write operation is shown in
Figure 9.
Unlike EEPROMs, any number of bytes can be
written sequentially and each byte is written to
memory immediately after it is clocked in (after the
8
th
clock). The rising edge of /CS terminates a
WRITE op-code operation .
Read Operation
After the falling edge of /CS, the bus master can issue
a READ op-code. Following this instruction is a two-
byte address value. The upper 5-bits of the address
are ignored. In total, the 11-bits specify the address of
the first byte of the read operation. After the op-code
and address are complete, the SI line is ignored. The
bus master issues 8 clocks, with one bit read out for
each. Addresses are increme nted internally as long as
the bus master continues to issue clocks. If the last
address of 7FFh is reached, the counter will roll over
to 000h. Data is read MSB first. The rising edge of
/CS terminates a READ op-code operation. A read
operation is shown in Figure 10.
Hold
The /HOLD pin can be used to interrupt a serial
operation without aborting it. If the bus master pulls
the /HOLD pin low while SCK is low, the current
operation will pause. Taking the /HOLD pin high
while SCK is low will resume an operation. The
transitions of /HOLD must occur while SCK is low,
but the SCK pin can toggle during a hold state.
FM25L16B - Automotive Temp .
Rev. 1 .0
Feb. 2011 Page 8 of 13
Figure 9. Memory Write
(WREN not shown)
Figure 10. Memory Read
Endurance
The FM25L16B devices are capable of being
accessed at least 10
13
times, reads or writes. An F-
RAM memory operates with a read and restore
mechanism. Therefore, an endurance c ycle is applied
on a row basis for each access (read or write) to the
memory array. The F-RAM architecture is based on
an array of rows and columns. Rows are defined by
A10-A3 a nd column addresses by A2-A0. See Block
Diagram (pg 2) which shows the array as 256 rows of
64-bits each. The entire row is internally accessed
once whether a single byte or all eight b ytes are read
or written. Each b yte in the r ow is counted only once
in an endurance calculation. The table below shows
endurance calculations for 64-byte repeating loop,
which includes an op-code, a starting address, and a
sequential 64-byte data stream. This causes each byte
to experience one endurance cycle through the loop.
F-RAM read and write endurance is virtually
unlimited even at 10MHz clock rate.
Table 5. Time to Reach Endurance Limit for Repeating 64-byte Loop
SCK Freq
(MHz) Endurance
Cycles/sec. Endurance
Cycles/year Years to Reach
Limit
10 18,660 5.88 x 10
11
17.0
5 9,330 2.94 x 10
11
34.0
1 1,870 5.88 x 10
10
170.1
012345670123456 456701234567
op-c
ode
0000001 MSB
11-bit Add
r
ess
XX
X
XX109 3210
76543210
LSB MSB LSB
CS
SC
K
SI
SO Data
1
0 1 2 345670 1 2 345 456701234567
op-c
ode
00000010M
SB
11-bit Add
r
ess
X
XXXX10 321076543210
LSB MSB LSB
CS
SCK
SI
S
O
D
ata
9
6
FM25L16B - Automotive Temp .
Rev. 1 .0
Feb. 2011 Page 9 of 13
Electrical Specifications
Ab solute M aximum Ratings
Symbol Description Ratings
V
DD
Power Supply Voltage with resp ect to V
SS
-1.0V to +5.0V
V
IN
Voltage on any pin with respect to V
SS
-1.0V to +5.0V
and V
IN
< V
DD
+1.0V
T
STG
Storage Temperature -55°C to + 125 °C
T
LEAD
Lead Temperature (Soldering, 10 seconds) 260° C
V
ESD
Electrostatic Discharge Voltage
- Human Body Model
(AEC-Q100-002 Rev. E)
- Charged Device Model
(AEC-Q100-011 Rev. B)
- Machine Model
(AEC-Q100-003 Rev. E)
TBD
TBD
TBD
Package Moisture Sensitivity Level MSL-1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, a nd th e functi ona l operati on of the d evic e at thes e or an y other cond ition s ab ove those li sted in the op erat ional s ection of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (T
A
= -40° C to +125° C, V
DD
= 3.0V to 3.6V unless otherwise specified)
Symbol Parameter Min Typ Max Units Notes
V
DD
Power Supply Voltage 3.0 3.3 3.6 V
I
DD
VDD Supply Current
@ SCK = 1.0 MHz
@ SCK = 15.0 MHz
0.2
2.0
mA
mA
1
I
SB
Standby Current
@ +85°C
@ +125°C
-
-
6
20
µA
µA
2
I
LI
Input Leakage Current - ±1
µ
A 3
I
LO
Output Lea kage Current - ±1
µ
A 3
V
IH
Input High Voltage 0.75 V
DD
V
DD
+ 0.3 V
V
IL
Input Lo w Voltage -0.3 0.25 V
DD
V
V
OH
Output High Voltage
@ I
OH
= -2 mA V
DD
– 0.8 - V
V
OL
Output Low Voltage
@ I
OL
= 2 mA - 0.4 V
V
HYS
Input Hysteresis 0.05 V
DD
V 4
Notes
1.
SCK toggling between V
DD
-0. 3 V and V
SS
, other inputs V
SS
or V
DD
-0.3V.
2.
SCK = SI = /CS=V
DD
. All inputs V
SS
or V
DD
.
3.
V
SS
≤ V
IN
≤ V
DD
and V
SS
≤ V
OUT
≤ V
DD
.
4.
Characterized but not 100% tested in production. Applies only to /CS and SCK pins.
FM25L16B - Automotive Temp .
Rev. 1 .0
Feb. 2011 Page 10 of 13
AC Parameters (T
A
= -40° C to +125° C, V
DD
= 3.0V to 3.6V unless otherwise specified)
Symbol Parameter Min Max Units Notes
f
C
K
SCK Clock Frequency 0 15 MHz
t
CH
Clock High Time 30 ns 1
t
CL
Clock Low Time 30 ns 1
t
CSU
Chip Select Setup 10 ns
t
CSH
Chip Select Hold 10 ns
t
OD
Output Disable Time 20 ns 2
t
ODV
Output Data Valid Time 30 ns
t
OH
Output Hold Time 0 ns
t
D
Deselect Time 60 ns
t
R
Data In Rise Time 50 ns 2,3
t
F
Data In Fall Time 50 ns 2,3
t
SU
Data Setup Time 5 ns
t
H
Data Hold Time 5 ns
t
HS
/HOLD Setup Time 10 ns
t
HH
/HOLD Hold Time 10 ns
t
HZ
/HOLD Low to Hi-Z 20 ns 2
t
LZ
/HOLD High to Data Active 20 ns 2
Notes
1. t
CH
+ t
CL
= 1/f
CK
.
2. Characterized but not 100% tested in production.
3. Rise and fall times measured betwe en 10% and 90% of waveform.
Capacitance (T
A
= 25° C, f=1.0 MHz, V
DD
= 3.3V)
Symbol Parameter Min Max Units Notes
C
O
Output Capacitance (SO) - 8 pF 1
C
I
Input Capacitance - 6 pF 1
Notes
1. This parameter is periodically sampled and not 100% tested.
2. Slope measured at any point on V
DD
wav efo rm.
AC Test Conditions
Input Pulse Levels 10% and 90% of V
DD
Input and output timing levels 0.5 V
DD
Input rise and fall ti mes 5 ns Output Load Capacitance 30 pF
Power Cycle Timing
Power Cycle Timing (T
A
= -40° C to +125° C, V
DD
= 3.0V to 3.6V unless otherwise specified)
Symbol Parameter Min Max Units Notes
t
PU
V
DD
(min) to First Access Start 10 - ms
t
PD
Last Access Complete to V
DD
(min) 0 -
µ
s
t
VR
V
DD
Rise Time 30 -
µ
s/V 1
t
VF
V
DD
Fall Time 100 -
µ
s/V 1
Notes
1.
Slope measured at any point on V
DD
wav efo rm.
FM25L16B - Automotive Temp .
Rev. 1 .0
Feb. 2011 Page 11 of 13
Serial Data Bus Timing
/Hold Timing
CS
SCK
SO
HOLD tHS
tHH
tHZ tLZ
tHS
tHH
Data Retention (V
DD
= 3.0V to 3.6V)
Parameter Min Max Units Notes
Data Retention
@
T
A
= +55°C
@ T
A
= +105°C
@
T
A
= +125°C
17
10,000
1,000
-
-
-
Years
Hours
Hours
Note: Data retention qualification tests are accelerated tests and are performed such that all th ree conditions have been
applied: (1 ) 17 years at a temperatu re o f +55°C, (2) 10 ,000 hours a t +105°C, and (3) 1,000 hours at +125°C.
Typical Grade 1 Operating Profile
0
200
400
600
800
1000
1200
1400
1600
70 75 80 85 90 95 100 105 110 115 120 125
Temperature (°C)
Hours
Typ ical Grad e 1 Storage Prof ile
0
5000
10000
15000
20000
25000
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
Temperature (°C)
Hours
FM25L16B - Automotive Temp .
Rev. 1 .0
Feb. 2011 Page 12 of 13
Mechanical Drawing
8-pin SOIC (JEDEC Standard MS-012, variation AA)
Pin 1
3.90
±
0.10 6.00
±
0.20
4.90
±
0.10
0.10
0.25
1.35
1.75
0.33
0.51
1.27 0 .10 mm
0.25
0.50 45
°
0.40
1.27
0.19
0.25
0°- 8°
Recommended PCB Footprint
7.70
0.65
1.27
2.00
3.70
Refer to JEDEC MS-012 for complete dimensions and notes.
All dimen sions in millimeters.
SOIC Package Marking Scheme
Legend:
XXXXXX= part number, P= package t ype (G=SOIC) ,
T= temperature (A=Automotive, blank=ind.)
R=rev code, LLLLLLL= lot code
RIC= Ramtron Int’l Corp , YY=year , WW=work week
Example: FM25L16B, “Green” SOIC pac kage, Auto motive Temperature,
Rev A, Lot L3502G1, Year 2011, Work Week 04
FM25L16BGA
AL3502G1
RIC1104
XXXXXXPT
RLLLLLLL
RICYYWW
FM25L16B - Automotive Temp .
Rev. 1 .0
Feb. 2011 Page 13 of 13
Revision History
Revision
Date
Summary
1.0 2/18/2011 Initial Release
