Triple Differential Receiver with
300 Meter Adjustable Line Equalization
Data Sheet
AD8122
Rev. 0
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved.
FEATURES
Compensates cables up to 300 meters for wideband video
60 MHz equalized BW at 300 meters of UTP cable
120 MHz equalized BW at 150 meters of UTP cable
Fast time domain performance
70 ns settling time to 1% at 300 meters of UTP cable
7 ns rise/fall times with 2 V step at 300 meters of UTP cable
3 frequency response gain adjustment pins
High frequency peaking adjustment (VPEAK)
Output low-pass filter cutoff adjustment (VFI LTE R )
Broadband flat gain adjustment (VGAIN)
Selectable for UTP or coaxial compensation
DC output offset adjustment pin (VOFFSET)
Low output offset voltage: ±4 mV at G = 1
Compensates both RGB and YPbPr
2 on-chip comparators with hysteresis can be used
for common-mode sync pulse extraction
Available in 40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
Keyboard-video-mouse (KVM)
Digital signage
RGB video over UTP cables
Professional video projection and distribution
HD video
Security video
FUNCTIONAL BLOCK DIAGRAM
OUTR
GAINR
OUTG
GAING
OUTB
GAINB
VPEAK VFILTER VOFFSET VGAIN
–INCMP1
+INCMP1
–INCMP2
OUTCMP1
OUTCMP2
+INCMP2
AD8122
COAX/UTP
–INR
+INR
–ING
+ING
–INB
+INB
10780-001
Figure 1.
GENERAL DESCRIPTION
The AD8122 is a high speed, triple differential receiver and
equalizer that compensates for the transmission losses of UTP
cables up to 300 meters in length and coaxial cables up to
200 meters in length. Various gain stages are summed to best
approximate the inverse frequency response of the cable. Each
channel features a high impedance differential input with high
rejection of common-mode (CM) signals that is ideal for inter-
facing directly with the cable.
The AD8122 has two control inputs for optimal cable
compensation, one LPF control input, an input to select UTP or
coaxial cable, and an input to adjust the dc output offset. The cable
compensation inputs are used to compensate for different cable
lengths: the VPEAK input controls the amount of high frequency
peaking, and the VGAIN input adjusts the broadband flat gain to
compensate for the flat cable loss. The VFILTER input controls the
cutoff frequency of output low-pass filters on each channel.
The selection of UTP or coaxial cable compensation responses
is determined by the binary COAX/UTP input, which can be
left floating in UTP applications. The VOFFSET input allows the
dc voltage at the output to be adjusted, which can be useful in
dc-coupled systems.
For added flexibility, the gain of each channel can be set to 1
or 2 using the associated gain control pin.
The AD8122 is available in a 6 mm × 6 mm, 40-lead LFCSP
and is rated to operate over the extended temperature range
of −40°C to +85°C.
AD8122 Data Sheet
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
Maximum Power Dissipation ..................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 12
Adjustable Control Voltages ...................................................... 12
Differential Inputs ...................................................................... 12
Outputs ........................................................................................ 12
On-Chip Comparators .............................................................. 12
Input Single-Ended Voltage Range Considerations .............. 12
Applications Information .............................................................. 13
Basic Operation .......................................................................... 13
Input Overdrive Recovery and Protection .............................. 13
Comparator Applications .......................................................... 13
Sync Pulse Extraction Using Comparators ............................. 14
Using the VPEAK, VGAIN, VFILTER, and VOFFSET Inputs ................. 15
Using the COAX/UTP Selector ................................................ 15
Driving High Impedance Capacitive Loads ........................... 15
Driving 75 Ω Cable with the AD8122 ..................................... 15
Layout and Power Supply Decoupling Considerations ......... 15
Input Common-Mode Range ................................................... 15
Power-Down ............................................................................... 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
7/12—Revision 0: Initial Version
Data Sheet AD8122
Rev. 0 | Page 3 of 20
SPECIFICATIONS
TA = 25°C, VS = ±5 V, Category 5e UTP cable, input VCM = 0 V, VOFFSET = 0 V, V PEAK, VGAIN, and VFILTER are set to the recommended settings
shown in Figure 24, unless otherwise noted. For G = 2, RL = 150 Ω and VOUT = 2 V p-p; for G = 1, RL = 1 kΩ and VOUT = 1 V p-p.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC AND NOISE PERFORMANCE
−3 dB Large Signal Bandwidth AD8122 only, G = 1/G = 2 270/165 MHz
150 meters of cable, G = 1/G = 2 120/110 MHz
300 meters of cable, G = 1, G = 2 60 MHz
Slew Rate V
OUT
= 2 V p-p, AD8122 only, G = 1, G = 2 1000 V/µs
10% to 90% Rise/Fall Times V
OUT
= 2 V step, 150 meters of cable, G = 2 6 ns
V
OUT
= 2 V step, 300 meters of cable, G = 2 7 ns
V
OUT
= 1 V step, 150 meters of cable, G = 1 6 ns
V
OUT
= 1 V step, 300 meters of cable, G = 1 7 ns
Settling Time to 1% V
OUT
= 2 V step, 150 meters of cable, G = 2 70 ns
V
OUT
= 2 V step, 300 meters of cable, G = 2 70 ns
VOUT = 1 V step, 150 meters of cable, G = 1
ns
V
OUT
= 1 V step, 300 meters of cable, G = 1 70 ns
Integrated Output Voltage Noise 150 meters of cable, integrated to 160 MHz,
G = 1/G = 2
3.7/6.2 mV rms
300 meters of cable, integrated to 160 MHz,
G = 1/G = 2
17/27 mV rms
INPUT PERFORMANCE
Input Voltage Range Common mode, −IN
x
= +IN
x
±4.0 V
Maximum Differential Voltage Swing
|(+INx) − (−INx)|
V
Voltage Gain Error ΔV
OUT
/ΔV
IN
, V
GAIN
set for 0 meters of cable, G = 1 1.5 %
ΔV
OUT
/ΔV
IN
, V
GAIN
set for 0 meters of cable, G = 2 0.50 %
Channel-to-Channel Gain Matching G = 1, G = 2 0.15 %
Common-Mode Rejection (CMR) ΔV
OUT
/ΔV
IN, CM
DC, V
PEAK
= V
GAIN
= 0 V, G = 1/G = 2 −92/−87 dB
DC, 300 meters of cable, G = 1/G = 2 −89/−85 dB
1 MHz, 300 meters of cable, G = 1/G = 2 −63/−57 dB
50 MHz, 300 meters of cable, G = 1/G = 2 5/10 dB
100 MHz, 300 meters of cable, G = 1/G = 2 10/14 dB
Input Resistance Common mode 4.4 MΩ
Differential 3.7 MΩ
Input Capacitance Common mode 1.0 pF
Differential 0.5 pF
Input Bias Current 1.1 µA
ADJUSTMENT PINS
V
PEAK
Input Voltage Range Relative to ground 0 to 2 V
V
GAIN
Input Voltage Range Relative to ground 0 to 2 V
V
OFFSET
Input Current 1.1 µA
V
GAIN
Input Current −0.5 µA
V
PEAK
Input Current ±0.6 µA
V
FILTER
Input Current 0.5 µA
VOFFSET to OUTx Gain OUTx = OUTR, OUTG, OUTB, range limited by
output swing, V
GAIN
= 0 V, G = 1
1 V/V
OUTPUT CHARACTERISTICS
Output Voltage Swing G = 1, G = 2 −3.9 to +3.9 V
Output Offset Voltage RTO, V
PEAK
= V
GAIN
= V
FILTER
= V
OFFSET
= 0 V, G = 1/G = 2 ±4/±8 mV
RTO, 300 meters of cable, G = 1/G = 2 ±10/±30 mV
Output Offset Voltage Drift RTO, G = 1/G = 2 2.6/3.2 µV/°C
AD8122 Data Sheet
Rev. 0 | Page 4 of 20
Parameter Test Conditions/Comments Min Typ Max Unit
COMPARATORS
Output Voltage Level Low, V
OL
0.3 V
Output Voltage Level High, V
OH
3.3 V
Hysteresis, V
HYST
70 mV
Propagation Delay
Low to High, t
PD, LH
14 ns
High to Low, t
PD, HL
10 ns
Rise Time, t
RISE
8 ns
Fall Time, t
FAL L
7 ns
Output Resistance, V
OL
18 Ω
Output Resistance, V
OH
1 Ω
DIGITAL CONTROLS
COAX/UTP Pin
Input Voltage Level Low, V
IL
1.5 V
Input Voltage Level High, V
IH
3.5 V
Input Current, Low ±0.7 µA
Input Current, High 24 µA
PD Pin
Input Voltage Level Low, VIL
2.9
V
Input Voltage Level High, V
IH
3.2 V
Input Current, Low 1 µA
Input Current, High 1 µA
POWER SUPPLY
Operating Voltage Range ±4.5 ±5.5 V
Positive Quiescent Supply Current 120 mA
Negative Quiescent Supply Current 66 mA
Supply Current Drift, I
CC
210 µA/°C
Supply Current Drift, I
EE
−120 µA/°C
Positive Power Supply Rejection ΔV
OUT
/ΔV
SUPPLY
DC, RTO, 0 meters of cable, G = 1/G = 2 −72/−66 dB
DC, RTO, 300 meters of cable, G = 1/G = 2 −68/−62 dB
100 MHz, RTO, 300 meters of cable, G = 1/G = 2 5/8 dB
Negative Power Supply Rejection
ΔVOUT/ΔVSUPPLY
DC, RTO, 0 meters of cable, G = 1/G = 2 −88/−80 dB
DC, RTO, 300 meters of cable, G = 1/G = 2 −80/−74 dB
100 MHz, RTO, 300 meters of cable, G = 1/G = 2 18/14 dB
Positive Supply Current, Powered Down V
PEAK
= V
GAIN
= V
FI LT E R
= 0 V 3.4 mA
Negative Supply Current, Powered Down V
PEAK
= V
GAIN
= V
FI LT E R
= 0 V 0.4 mA
OPERATING TEMPERATURE RANGE −40 +85 °C
Data Sheet AD8122
Rev. 0 | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage 11 V
Power Dissipation
See Figure 2
Input Voltage (Any Input) V
S−
− 0.3 V to V
S+
+ 0.3 V
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, the device
soldered in a circuit board in still air. This value was measured
using a JEDEC standard 4-layer printed circuit board (PCB).
Table 3. Thermal Resistance
Package Type θ
JA
θ
JC
Unit
40-Lead LFCSP 39 1.3 °C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8122 package
is limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8122. Exceeding a junction temperature
of 175°C for an extended period can result in changes in the
silicon devices, potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS+ and VS−)
times the quiescent current (IS). The power dissipation due to
each load current is calculated by multiplying the load current
by the voltage difference between the associated power supply
and the output voltage. The total power dissipation due to load
currents is then obtained by taking the sum of the individual
power dissipations. RMS output voltages must be used when
dealing with ac signals.
Airflow reduces θJA. In addition, more metal directly in contact
with the package leads from metal traces, through holes, ground,
and power planes reduces θJA. The exposed pad on the underside
of the package must be soldered to a pad on the PCB surface that
is thermally connected to a solid plane (usually the ground plane)
to achieve the specified θJA.
Figure 2 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 40-lead LFCSP
(θJA = 39°C/W) on a JEDEC standard 4-layer board with the
exposed pad soldered to a pad that is thermally connected
to a PCB plane. θJA values are approximations.
0
1
2
3
4
5
6
–40 –20 020 40 60 80
MAXIMUM POWER DISSIPATION (W)
AMBIENT TEMPERATURE ( °C)
10780-003
Figure 2. Maximum Power Dissipation vs. Ambient Temperature
for a 4-Layer Board
ESD CAUTION
AD8122 Data Sheet
Rev. 0 | Page 6 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. TO ACHIEVE THE SPECIFIED THERMAL RESISTANCE, THE EXPOSED PAD
ON THE UNDERS IDE O F THE P ACKAGE MUS T BE S OLDE RE D TO A P AD
ON THE PCB S URFACE T HAT IS THERMALL Y CONNECT E D TO A S OLID
PLANE WITH A VOLTAGE BETWEEN VS+ AND VS–.
2. NC = NO I NTERNAL CONNECT ION.
1NC 2
+INCMP1 3
–INCMP1 4
OUTCMP1 5
VS+_CMP 6
VS–_CMP 7
OUTCMP2 8
–INCMP2 9
+INCMP2 10VS–
23 VOFFSET
24 DGND
25 VGAIN
26 VPEAK
27 VFILTER
28 PD
29 DVS+
30 COAX/UTP
22 DVS–
21 VS+
11GAINB12OUTB
13V
S+
15GAIN
G
17V
S+
16OUT
G
18V
S–
19GAIN
R
20OUT
R
14V
S–
33 AGND
34 +IN
G
35 –ING
36 AGND
37 +INB
38 –INB
39 AGND
40 NC
32 –INR
31 +INR
AD8122
10780-021
TOP VIEW
(No t t o Scal e)
1
2
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 40 NC No Internal Connection.
2 +IN
CMP1
Positive Input, Comparator 1.
3 −IN
CMP1
Negative Input, Comparator 1.
4
OUTCMP1
Output, Comparator 1.
5 V
S+_CMP
Positive Power Supply, Comparator. Connect to +5 V.
6 V
S−_CMP
Negative Power Supply, Comparator. Connect to −5 V.
7 OUT
CMP2
Output, Comparator 2.
8 −IN
CMP2
Negative Input, Comparator 2.
9
+INCMP2
Positive Input, Comparator 2.
10, 14, 18 V
S−
Negative Power Supply, Equalizer Sections. Connect to −5 V.
11 GAIN
B
Blue Channel Gain. Connect to OUT
B
for G = 1; connect to AGND for G = 2.
12 OUT
B
Output, Blue Channel.
13, 17, 21 V
S+
Positive Power Supply, Equalizer Sections. Connect to +5 V.
15 GAIN
G
Green Channel Gain. Connect to OUT
G
for G = 1; connect to AGND for G = 2.
16 OUT
G
Output, Green Channel.
19 GAIN
R
Red Channel Gain. Connect to OUT
R
for G = 1; connect to AGND for G = 2.
20 OUT
R
Output, Red Channel.
22 DV
S−
Negative Power Supply, Digital Control. Connect to −5 V.
23 V
OFFSET
Output Offset Control Voltage.
24 DGND Digital Ground Reference.
25 V
GAIN
Broadband Flat Gain Control Voltage.
26 V
PEAK
Equalizer High Frequency Boost Control Voltage.
27 V
FILTER
Low-Pass Filter Cutoff Frequency Adjustment Control Voltage.
28 PD Power-Down.
29 DV
S+
Positive Power Supply, Digital Control. Connect to +5 V.
30 COAX/UTP Cable Compensation Control Input. Connect this pin to Logic 1 for coaxial cable; connect this pin to
Logic 0 for UTP cable. This input can be left floating in UTP applications.
Data Sheet AD8122
Rev. 0 | Page 7 of 20
Pin No. Mnemonic Description
31 +IN
R
Positive Input, Red Channel.
32 −IN
R
Negative Input, Red Channel.
33, 36, 39 AGND Analog Ground Reference.
34 +IN
G
Positive Input, Green Channel.
35
−ING
Negative Input, Green Channel.
37 +IN
B
Positive Input, Blue Channel.
38 −IN
B
Negative Input, Blue Channel.
EP Exposed Pad. To achieve the specified thermal resistance, the exposed pad on the underside of the
package must be soldered to a pad on the PCB surface that is thermally connected to a solid plane
with voltage between V
S
+ and V
S
−.
AD8122 Data Sheet
Rev. 0 | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±5 V, Category 5e UTP cable, input VCM = 0 V, V OFFSET = 0 V, V PEAK, VGAIN, and VFILTER are set to the recommended settings
shown in Figure 24, unless otherwise noted. For G = 2, RL = 150 Ω and VOUT = 2 V p-p; for G = 1, RL = 1 kΩ and VOUT = 1 V p-p.
–18
–15
–12
–9
–6
–3
0
3
6
0.1 110 100
GAIN (d B)
FREQUENCY (MHz)
100m
150m
200m
250m
300m
10780-004
Figure 4. Equalized Frequency Response for Various UTP Cable Lengths, G = 1
–18
–15
–12
–9
–6
–3
0
3
6
0.1 110 100
GAIN (d B)
FREQUENCY (MHz)
100m
150m
200m
10780-005
Figure 5. Equalized Frequency Response for Various Coaxial Cable Lengths,
G = 1
–12
–9
–6
–3
0
3
10.1 10 100
GAIN (d B)
FREQUENCY (MHz)
VGAIN = 1.37V
VPEAK = 1. 86V
VFILTER = 2V
10780-006
VFILTER = 1. 7V
VFILTER = 0V
Figure 6. Equalized Frequency Response for Various VFILTER Levels,
300 m Cable Length, G = 1
–12
–9
–6
–3
0
3
6
9
12
0.1 110 100
GAIN (d B)
FREQUENCY (MHz)
100m
150m
200m
250m
300m
10780-007
Figure 7. Equalized Frequency Response for Various UTP Cable Lengths, G = 2
–12
–9
–6
–3
0
3
6
9
12
0.1 110 100
GAIN (d B)
FREQUENCY (MHz)
10780-008
100m
150m
200m
Figure 8. Equalized Frequency Response for Various Coaxial Cable Lengths,
G = 2
10.1 10 10010.1 10 100
–6
–3
0
3
6
9
12
GAIN (d B)
FREQUENCY (MHz)
V
GAIN
= 1.37V
V
PEAK
= 1.86V
10780-009
V
FILTER
= 2V
V
FILTER
= 1.7V
V
FILTER
= 0V
Figure 9. Equalized Frequency Response for Various VFILTER Levels,
300 m Cable Length, G = 2
Data Sheet AD8122
Rev. 0 | Page 9 of 20
40
50
60
70
80
90
100
110
120
130
140
100 120 140 160 180 200 220 240 260 280 300
–3dB BANDWIDTH (MHz )
CABLE LENG TH (m)
G = 1
G = 2
10780-010
Figure 10. Equalized −3 dB Bandwidth vs. Cable Length
0
5
10
15
20
25
30
050 100 150 200 250 300
INTEGRAT E D OUT P UT NOISE ( mV rms)
CABLE LENG TH (m)
G = 1
G = 2
10780-011
Figure 11. Integrated Output Noise (1 MHz to 160 MHz) vs. Cable Length
–120
–100
–80
–60
–40
–20
0
20
0.1 110 100
CROSSTALK (dB)
FREQUENCY (MHz)
150m
300m
10780-012
Figure 12. Crosstalk vs. Frequency for 300 m and 150 m Cable Lengths, G = 1
10
100
1000
10000
0.1 110 100
OUTPUT VOLTAGE NOISE (nV/√Hz)
FREQUENCY (MHz)
150m, G = 1
300m, G = 1
300m, G = 2
150m, G = 2
10780-013
Figure 13. Voltage Noise Density vs. Frequency for 300 m and 150 m
Cable Lengths, RTO
0
10
20
30
40
50
60
70
0
1
2
3
4
5
6
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
INTEGRATED OUTPUT NOISE
FOR 300m SETTINGS ( mV rms)
INTEGRATED OUTPUT NOISE
FOR 150m SETTINGS ( mV rms)
V
FILTER
(V)
300m, G = 2
150m, G = 2
150m, G = 1
300m, G = 1
10780-014
Figure 14. Integrated Output Noise (1 MHz to 160 MHz) vs. VFILTER
for 300 m and 150 m Cable Lengths
–120
–100
–80
–60
–40
–20
0
20
0.1 110 100
CROSSTALK (dB)
FREQUENCY (MHz)
150m
300m
10780-015
Figure 15. Crosstalk vs. Frequency for 300 m and 150 m Cable Lengths, G = 2
AD8122 Data Sheet
Rev. 0 | Page 10 of 20
–100
–80
–60
–40
–20
0
20
0.1 110 100
CMR (dB)
FREQUENCY (MHz)
300m
150m
ΔV
OUT
/ΔV
IN, CM
10780-016
Figure 16. Input Common-Mode Rejection vs. Frequency
for 300 m and 150 m Cable Lengths, G = 1
–70
–60
–50
–40
–30
–20
–10
0
10
20
0.1 110 100
PSR (dB)
FREQUENCY (MHz)
POSITIVE, 150m
POSITIVE, 300m
NEGATIVE, 150m
NEGATIVE, 300m
ΔV
OUT
/ΔV
SUPPLY
10780-017
Figure 17. Power Supply Rejection vs. Frequency
for 300 m and 150 m Cable Lengths, G = 1
–6
–4
–2
0
2
4
6
0100 200 300 400 500 600 700 800 900 1000
VOLTAGE (V)
TIME (n s)
INPUT
OUTPUT WITHOUT INPUT CLAMPS
OUTPUT WITH INPUT CLAMPS
10780-018
Figure 18. Overdrive Recovery, G = 1
–100
–80
–60
–40
–20
0
20
0.1 110 100
CMR (dB)
FREQUENCY (MHz)
300m
150m
ΔV
OUT
/ΔV
IN, CM
10780-019
Figure 19. Input Common-Mode Rejection vs. Frequency
for 300 m and 150 m Cable Lengths, G = 2
–70
–60
–50
–40
–30
–20
–10
0
10
20
0.1 110 100
PSR (dB)
FREQUENCY (MHz)
POSITIVE, 150m
NEGATIVE, 150m
NEGATIVE, 300m
ΔV
OUT
/ΔV
SUPPLY
10780-020
POSITIVE, 300m
Figure 20. Power Supply Rejection vs. Frequency
for 300 m and 150 m Cable Lengths, G = 2
–6
–4
–2
0
2
4
6
0100 200 300 400 500 600 700 800 900
1000
VOLTAGE (V)
TIME (n s)
INPUT × 2
OUTPUT
10780-121
Figure 21. Overdrive Recovery, G = 2
Data Sheet AD8122
Rev. 0 | Page 11 of 20
500mV/DIV
150m
300m
TIME (n s)
050 100 150 200 250 300 350 400 450
10780-122
Figure 22. Equalized Pulse Response for 300 m and 150 m Cable Lengths
(2 MHz), G = 1
–1.00
–0.75
–0.50
–0.25
0
0.25
0.50
0.75
1.00
–2
–1
0
1
2
–100 0100 200 300 400 500 600 700 800
V
OUT
(V)
SETTLING ERROR (%)
TIME (n s)
V
IN
– V
OUT
V
OUT
10780-123
Figure 23. Settling Time to 1%, 300 m Cable Length, G = 1
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
050 100 150 200 250 300
CONTROL VOLTAGE (V)
CABLE LENG TH (m)
V
PEAK
AND V
FILTER
V
GAIN
10780-124
Figure 24. Recommended Settings for UTP Cable
1V/DIV
150m
300m
TIME (n s)
050 100 150 200 250 300 350 400 450
10780-125
Figure 25. Equalized Pulse Response for 300 m and 150 m Cable Lengths
(2 MHz), G = 2
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
–2
–1
0
1
2
–100 0100 200 300 400 500 600 700 800
V
OUT
(V)
SETTLING ERROR (%)
TIME (n s)
2V
IN
– V
OUT
V
OUT
10780-126
Figure 26. Settling Time to 1%, 300 m Cable Length, G = 2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
CONTROL VOLTAGE (V)
CABLE LENG TH (m)
10780-127
020 40 60 80 100 120 140 160 180 200
V
GAIN
V
PEAK
AND V
FILTER
Figure 27. Recommended Settings for Coaxial Cable
AD8122 Data Sheet
Rev. 0 | Page 12 of 20
THEORY OF OPERATION
The AD8122 is a triple, wideband, low noise analog line equalizer
that compensates for losses in UTP cables up to 300 meters in
length and coaxial cables up to 200 meters in length. The 3-channel
architecture is targeted at high resolution RGB applications, but
can be used in HD YPbPr applications as well. The transfer func-
tion of the AD8122 can be pin selected for UTP or coaxial cable,
and the gain of each channel can be set to 1 or 2.
ADJUSTABLE CONTROL VOLTAGES
Four continuously adjustable control voltages, common to the
RGB channels, are available to the designer to provide compen-
sation for various cable lengths, as well as for variations in the
cable itself.
• The VPEAK pin is used to control the amount of high fre-
quency peaking. The VPEAK control is used to compensate
for frequency dependent losses and cable length dependent
losses that are present due to the skin effect of the cable.
• The VGAIN pin is used to adjust broadband gain to com-
pensate for low frequency flat losses present in the cable.
• The VFILTER pin is used to adjust the cutoff frequency of the
output low-pass filters.
• The VOFFSET pin is an output offset adjustment control that
allows the designer to shift the output dc level.
DIFFERENTIAL INPUTS
The AD8122 has high impedance differential inputs that make
termination simple and allow dc-coupled signals to be received
directly from the cable. The AD8122 inputs can also be used in a
single-ended fashion in coaxial cable applications. For differen-
tial systems that require a very wide input common-mode range,
the AD8143 high voltage, triple differential receiver can be placed
in front of the AD8122. For more information, see the Input
Common-Mode Range section.
OUTPUTS
The AD8122 has low impedance outputs that are capable of
driving a 150 Ω load. In systems where the AD8122 must drive
a high impedance capacitive load, it is recommended that a small
series resistor be placed between the output and the load to buffer
the capacitance. The resistor should not be so large as to reduce
the overall bandwidth to an unacceptable level. For more informa-
tion, see the Driving High Impedance Capacitive Loads section.
ON-CHIP COMPARATORS
Two on-chip comparators can be used for sync pulse extraction
in systems that use common-mode sync pulse encoding (see the
Sync Pulse Extraction Using Comparators section).
Each comparator can be used in a source-only cable termination
scheme by placing a resistor in series with the comparator output.
For more information, see the Comparator Applications section.
INPUT SINGLE-ENDED VOLTAGE RANGE
CONSIDERATIONS
When using the AD8122 as a receiver, it is important to ensure
that its single-ended input voltages stay within their specified
ranges. The received single-ended level for each input is calcu-
lated by adding the common-mode level of the driver, the single-
ended peak amplitude of the received signal, the amplitude of
any sync pulses, and other induced common-mode signals, such
as ground shifts between the driver and the AD8122 and pickup
from external sources, such as power lines and fluorescent lights.
For more information, see the Input Common-Mode Range
section.
Data Sheet AD8122
Rev. 0 | Page 13 of 20
APPLICATIONS INFORMATION
BASIC OPERATION
The AD8122 is easy to apply because it contains on chip all
components needed for cable loss compensation. Figure 30
shows a basic application circuit for common-mode sync pulse
extraction that is compatible with the common-mode sync pulse
encoding technique used in the AD8134, AD8142, AD8147,
and AD8148 triple differential drivers. If sync pulse extraction
is not required, the terminations can be single 100 Ω resistors,
and the comparator inputs can be left floating.
INPUT OVERDRIVE RECOVERY AND PROTECTION
Occasional large differential transients can occur on the cable
due to a number of causes, such as ESD and switching. When
operating the AD8122 at G = 1, a differential input that exceeds
+3.4 V or −3.4 V causes the output to “stick” at the associated
power supply rail (positive rail for positive overdrive, negative
rail for negative overdrive). The overdrive condition does not
occur in applications with G = 2.
The AD8122 recovers from the overdrive condition when the
magnitude of the differential input falls below 200 mV. Most
video signals return to 0 V nominal during the blanking intervals;
therefore, recovery from the overdrive condition in systems that
use these signals occurs during the first blanking interval after
the overdrive event has ended.
In systems with G = 1 and video signals that do not return to
0 V—for example, systems that include dc offsets—it is necessary
to prevent the overdrive condition from occurring. Figure 28 shows
a protection circuit that limits the differential input voltage to a
little over ±2 V. This circuit should be placed between the termina-
tion resistors and each AD8122 differential input.
49.9Ω
1
6
2
5
3
4
HN2D02FUTW1T1G
1
6
2
5
3
4
HN2D02FUTW1T1G
TERMINATION
RESISTORS
AD8122
INPUT
49.9Ω
10780-022
Figure 28. Required Input Protection for Applications with G = 1
COMPARATOR APPLICATIONS
The two on-chip comparators are most often used to extract
video sync pulses from the received common-mode voltages
(see the Sync Pulse Extraction Using Comparators section).
However, the comparators can also be used to recover sync
pulses in sync-on-color applications, to receive differential
digital information received on other channels such as the
fourth UTP pair, or as general-purpose comparators. Built-in
hysteresis helps to eliminate false triggers from noise.
An ideal source terminated transmission line has a source
resistance that exactly matches the characteristic impedance of
the line and a load impedance that is infinite. When the signal is
launched into the source termination, the initial value of the signal
is one-half the source value because the signal amplitude is divided
by 2 in the voltage divider formed by the source termination and
the transmission line. At the load, the signal experiences 100%
positive reflection due to the infinite load impedance and is
restored to its full value. This technique is commonly used in
PCB layouts that involve high speed digital logic.
The comparators are designed to drive source terminated
transmission lines and have output resistances of 18 Ω in the
low state and 1 Ω in the high state. Because the output resistances
are different for each state, a compromise must be made in select-
ing the external source termination resistor value to match the
transmission line impedance. The best approximation to a 50 Ω
match that can be achieved in this case is with an external resistor
value of approximately 41.2 Ω, which is available as a standard
1% value. See Figure 29 for an illustration of the source termina-
tion technique.
Impedance mismatches occur in both the high state and the low
state due to the differences in output resistances, resulting in a
reflection coefficient of approximately +8.4% (21.5 dB return
loss) in the low state, where the total source resistance is 59.2 Ω,
and −8.4% (21.5 dB return loss) in the high state, where the total
source resistance is 42.2 Ω. This source match is acceptable for
digital sync pulses.
Figure 29 shows how to apply source termination to the
comparators when driving a 50 Ω transmission line that is
high impedance at its receive end.
41.2
Ω
HIGH-Z
Z
0
= 50Ω
10780-023
Figure 29. Using a Comparator with Source Termination
AD8122 Data Sheet
Rev. 0 | Page 14 of 20
SYNC PULSE EXTRACTION USING COMPARATORS
The AD8122 is useful in many systems that transport computer
video signals, which typically comprise red, green, and blue video
signals, as well as separate horizontal and vertical sync signals
(RGBHV). Because the sync signals are separate and not embedded
in the color signals, it is advantageous to transmit them using a
simple scheme that encodes them on the three common-mode
voltages of the RGB signals. The AD8134, AD8142, AD8147,
and AD8148 triple differential drivers are natural complements
to the AD8122 because they perform the sync pulse encoding
with the necessary circuitry on chip.
The sync encoding equations are as follows:
[ ]
HV
K
VRed
CM
−= 2
(1)
[ ]
V2
2−= K
VGreen
CM
(2)
[ ]
HV
K
VBlue
CM
+= 2
(3)
where:
Red VCM, Green VCM, and Blue VCM are the transmitted common-
mode voltages of the respective color signals.
K is an adjustable gain constant that is set by the driver.
V and H are the vertical and horizontal sync pulses, respectively,
defined with a weight of −1 when the pulses are in their low states
and a weight of +1 when the pulses are in their high states.
For more information about the encoding scheme, see the data
sheets for the AD8134, AD8142, AD8147, and AD8148 drivers.
Figure 30 shows how the AD8122 comparators can be used to
extract the horizontal and vertical sync pulses that are encoded
on the RGB common-mode voltages by the drivers.
RED VIDEO OUTP UT
RED G AIN
RED
GREEN
BLUE
GRE E N V IDEO OUTP UT
GRE E N GAIN
BLUE V IDEO OUTP UT
BLUE GAIN
HSYNC OUTP UT
VSY NC OUTP UT
AD8122
4
11
12
15
16
19
20
7
49.9Ω
PO WER-DOWN CONTROL
CABLE S E LECT CONTROL
ANALOG
CONTROL
INPUTS
49.9Ω
49.9Ω
49.9Ω
49.9Ω
49.9Ω
1kΩ BLUE V
CM
RECEIVED
RED VIDEO
RECEIVED
GREEN VIDEO
RECEIVED
BLUE V IDEO
RED V
CM
GRE E N V
CM
1kΩ
475Ω
47pF 47pF
31
30
28
23
27
25
26
32
34
35
37
38
2
3
9
8
10780-024
V
OFFSET
V
GAIN
V
PEAK
V
FILTER
PD
COAX/UTP
1
2
Figure 30. Basic Application Circuit with Common-Mode Sync Pulse Extraction (Supplies and Input Protection Not Shown)
Data Sheet AD8122
Rev. 0 | Page 15 of 20
USING THE VPEAK, VGAIN, VFILTER, AND VOFFSET INPUTS
The VPEAK input is the main peaking control and is used to
compensate for the low-pass roll-off in the cable response.
The VGAIN input controls the broadband flat gain and is used
to compensate for the cable loss that is nominally flat.
The output of each channel contains an on-chip adjustable low-
pass filter to reduce high frequency noise. In most applications,
the filter cutoff frequency control, VFILTER, is connected directly
to the VPEAK voltage to provide the maximum bandwidth and
minimum noise for a given VPEAK setting. External low-pass
filters are generally not required.
The VOFFSET input is used to produce an offset at the AD8122
output. The output offset is equal to the voltage applied to the
VOFFSET input, limited by the output swing limits.
USING THE COAX/UTP SELECTOR
Connect the COAX/UTP input to Logic 1 for coaxial cable or
to Logic 0 for UTP cable (see Table 1 for the logic levels). This
input has an internal pull-down resistor and can, therefore, be
left floating in UTP applications.
DRIVING HIGH IMPEDANCE CAPACITIVE LOADS
In many applications that use RGB over UTP cable, delay correc-
tion is required to remove the skew that exists among the three
pairs used to carry the RGB signals. The AD8120 is ideally suited
to perform this skew correction and can be placed immediately
following the AD8122 in the receiver signal chain. The AD8120
has a high input impedance and a fixed gain of 2. When using
the AD8120 with the AD8122, configure the AD8122 for a gain
of 1 by connecting each video output (OUTR, OUTG, and OUTB)
to its respective gain pin (GAINR, GAING, and GAINB).
In systems where the AD8122 must drive a high impedance
capacitive load, a small series resistor must be placed between
each of the three AD8122 video outputs and the load to buffer
the input capacitance of the device being driven. The resistor
value must be small enough to preserve the required bandwidth.
DRIVING 75 Ω CABLE WITH THE AD8122
When the RGB outputs must drive a 75 Ω line instead of a high
impedance load, an additional gain of 2 is required to make up
for the double termination loss (75 Ω source and load termina-
tions). Each output of the AD8122 (OUTR, OUTG, or OUTB) is
easily configured for a gain of 2 by grounding its respective gain
pin (GAINR, GAING, or GAINB).
LAYOUT AND POWER SUPPLY DECOUPLING
CONSIDERATIONS
Standard high speed PCB layout practices should be adhered
to when designing with the AD8122. A solid ground plane is
required, and controlled impedance traces should be used when
interconnecting the high speed signals. Place source termination
resistors on all of the outputs as close as possible to the output pins.
The exposed pad on the underside of the AD8122 must be
soldered to a pad on the PCB surface that is thermally connected
to a solid plane (usually the ground plane) to achieve the specified
θJA. Use several thermal vias to make the connection between the
pad and the PCB planes.
Place high quality 0.1 μF power supply decoupling capacitors as
close as possible to all of the supply pins; use small surface-mount
ceramic capacitors. For bulk supply decoupling, tantalum capac-
itors are recommended.
INPUT COMMON-MODE RANGE
Most applications that use the AD8122 as a receiver use a driver
powered from ±5 V supplies. (Suggested drivers include the
AD8146, AD8147, AD8148, AD8133, and AD8134.) In such
applications, the common-mode voltage on the line is placed at
a nominal 0 V relative to the ground potential at the driver and
provides optimum immunity from any common-mode anoma-
lies picked up along the cable (including ground shifts between
the driver and receiver ends).
The AD8122 input voltage range of ±4 V typical is sufficient for
many of these applications. If a wider input range is required,
the AD8143 triple receiver (with an input common-mode range
of ±10.5 V on ±12 V supplies) can be placed in front of the
AD8122. Figure 31 shows this configuration for one channel.
100Ω
49.9Ω
1
2
3
RECEIVED
SIGNAL
+5V
ONE AD8122
INPUT
ONE AD8143 CHANNEL
POWER SUPPLIES = ±12V
–5V
HBAT-540C
10780-025
Figure 31. Optional Use of the AD8143 in Front of the AD8122
for Wide Input Common-Mode Range
The Schottky diodes are required to protect the AD8122 from
any AD8143 outputs that exceed the AD8122 input limits. The
49.9 Ω resistor limits the fault current and produces a pole at
approximately 800 MHz with the effective diode capacitance of
3 pF and the AD8122 input capacitance of 1 pF. The pole lowers
the response by only 0.07 dB at 100 MHz and, therefore, has a
negligible effect on the signal.
AD8122 Data Sheet
Rev. 0 | Page 16 of 20
When using a single 5 V supply on the driver side, the common-
mode voltage at the driver output is typically 2.5 V (in the case
of the AD8142 driver, the common-mode voltage at the output
is fixed at 1.5 V). The largest received differential video signal is
approximately 700 mV p-p, which adds 175 mVPEAK to each single-
ended side of the differential signal and results in a worst-case
peak voltage of 2.675 V or 1.675 V on an AD8122 single-ended
input (assuming that there is no ground shift between the driver
and receiver). Because these levels are within the AD8122 input
voltage swing limits, such a system works well as long as the
difference in ground potential between the driver and receiver
does not cause the input voltage swing to exceed these limits.
When used, common-mode sync signals are generally applied
with a peak deviation of 500 mV during the blanking intervals
(video signal = 0 V), increasing the common-mode level from
2.5 V to 3.0 V (1.5 V to 2.0 V in the case of the AD8142 driver).
These common-mode levels are below the upper input voltage
swing limit of 4 V and, therefore, leave a margin of 1 V or 2 V
for ground shifts between the driver and receiver. To increase
the common-mode range of the overall system, use one or both
of these techniques:
• Power the driver from dual supplies (output common-mode
voltage = 0 V).
• Place an AD8143 in front of the AD8122, as shown in
Figure 31.
These techniques can be combined or applied separately.
POWER-DOWN
The power-down feature can be used to reduce power consump-
tion when a particular device is not in use. When asserted, the
PD pin does not place the output in a high-Z state. The input
logic levels and supply current in power-down mode are listed
in Table 1.
Data Sheet AD8122
Rev. 0 | Page 17 of 20
OUTLINE DIMENSIONS
05-06-2011-A
COM P LI ANT TO JEDE C S TANDARDS M O-220-WJJD- 5.
0.50
BSC
BOTTOM VIEWTOP VIEW
PIN 1
INDICATOR
EXPOSED
PAD
PIN 1
INDICATOR
S
EATING
PLANE
0.05 M AX
0.02 NOM
0.20 RE F
COPLANARITY
0.08
0.30
0.25
0.18
6.10
6.00 SQ
5.90
FOR PROPER CONNECTIO N OF
THE EXPO S E D P AD, REFER T O
THE PIN CO NFIGURATIO N AND
FUNCT IO N DE SCRIP TIONS
SECTION OF T HIS DATA SHEET.
0.45
0.40
0.35
0.25 M IN
40
1
11
20
21
30
31
10
4.85
4.70 S Q
4.55
0.80
0.75
0.70
Figure 32. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
6 mm × 6 mm Body, Very Very Thin Quad
(CP-40-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD8122ACPZ −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-40-12
AD8122ACPZ-R7 −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-40-12
AD8122-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
AD8122 Data Sheet
Rev. 0 | Page 18 of 20
NOTES
Data Sheet AD8122
Rev. 0 | Page 19 of 20
NOTES
AD8122 Data Sheet
Rev. 0 | Page 20 of 20
NOTES
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10780-0-7/12(0)