1
LTC2420
20-Bit µPower
No Latency ∆Σ
TM
ADC in SO-8
■
Weight Scales
■
Direct Temperature Measurement
■
Gas Analyzers
■
Strain Gauge Transducers
■
Instrumentation
■
Data Acquisition
■
Industrial Process Control
■
4-Digit DVMs
No Latency ∆Σ is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
Total Unadjusted Error (3V Supply)
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
20-Bit ADC in SO-8 Package
■
8ppm INL, No Missing Codes at 20 Bits
■
4ppm Full-Scale Error
■
0.5ppm Offset
■
1.2ppm Noise
■
Digital Filter Settles in a Single Cycle. Each
Conversion Is Accurate, Even After an Input Step
■
Fast Mode: 16-Bit Noise, 12 Bits TUE at 100sps
■
Internal Oscillator—No External Components
Required
■
110dB Min, 50Hz/60Hz Notch Filter
■
Reference Input Voltage: 0.1V to V
CC
■
Live Zero—Extended Input Range Accommodates
12.5% Overrange and Underrange
■
Single Supply 2.7V to 5.5V Operation
■
Low Supply Current (200µA) and Auto Shutdown
■
Pin Compatible with 24-Bit LTC2400
The LTC
®
2420 is a micropower 20-bit A/D converter with
an integrated oscillator, 8ppm INL and 1.2ppm RMS
noise that operates from 2.7V to 5.5V. It uses delta-sigma
technology and provides a digital filter that settles in a
single cycle for multiplexed applications. Through a single
pin, the LTC2420 can be configured for better than 110dB
rejection at 50Hz or 60Hz ±2%, or it can be driven by an
external oscillator for a user-defined rejection frequency
in the range 1Hz to 800Hz. The internal oscillator requires
no external frequency setting components.
The converter accepts any external reference voltage from
0.1V to V
CC
. With its extended input conversion range of
–12.5% V
REF
to 112.5% V
REF
, the LTC2420 smoothly
resolves the offset and overrange problems of preceding
sensors or signal conditioning circuits.
The LTC2420 communicates through a flexible 3-wire
digital interface which is compatible with SPI and
MICROWIRE
TM
protocols.
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
V
CC
F
O
V
REF
SCK
V
IN
SDO
1
2
3
4
8
7
6
5
GND CS
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUT RANGE
–0.12V
REF
TO 1.12V
REF
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
3-WIRE
SPI INTERFACE
1µF
2.7V TO 5.5V
LTC2420
2420 TA01
V
CC
INPUT VOLTAGE (V)
0
ERROR (ppm)
2
6
10
2.0
2420 G01
–2
–6
0
4
8
–4
–8
–10 0.5 1.0 1.5 2.5
VCC = 3V
VREF = 2.5V
TA = –55°C, –45°C, 25°C, 90°C
2
LTC2420
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) 0.1V ≤ V
REF
≤ V
CC
, (Note 5) ●20 Bits
Integral Nonlinearity V
REF
= 2.5V (Note 6) ●4 10 ppm of V
REF
V
REF
= 5V (Note 6) ●8 20 ppm of V
REF
Integral Nonlinearity (Fast Mode) V
REF
= 5V, V
REF
= 2.5V, 100 Samples/Second, f
O
= 2.048MHz ●40 250 ppm of V
REF
Offset Error 2.5V ≤ V
REF
≤ V
CC
●0.5 10 ppm of V
REF
Offset Error (Fast Mode) 2.5V < V
REF
< 5V, 100 Samples/Second, f
O
= 2.048MHz 3 ppm of V
REF
Offset Error Drift 2.5V ≤ V
REF
≤ V
CC
0.04 ppm of V
REF
/°C
Full-Scale Error 2.5V ≤ V
REF
≤ V
CC
●4 10 ppm of V
REF
Full-Scale Error (Fast Mode) 2.5V < V
REF
< 5V, 100 Samples/Second, f
O
= 2.048MHz 10 ppm of V
REF
Full-Scale Error Drift 2.5V ≤ V
REF
≤ V
CC
0.04 ppm of V
REF
/°C
Total Unadjusted Error V
REF
= 2.5V 8 ppm of V
REF
V
REF
= 5V 16 ppm of V
REF
Output Noise V
IN
= 0V (Note 13) 6 µV
RMS
Output Noise (Fast Mode) V
REF
= 5V, 100 Samples/Second, f
O
= 2.048MHz 20 µV
RMS
Normal Mode Rejection 60Hz ±2% (Note 7) ●110 130 dB
Normal Mode Rejection 50Hz ±2% (Note 8) ●110 130 dB
Power Supply Rejection, DC V
REF
= 2.5V, V
IN
= 0V 100 dB
Power Supply Rejection, 60Hz ±2% V
REF
= 2.5V, V
IN
= 0V, (Notes 7, 15) 110 dB
Power Supply Rejection, 50Hz ±2% V
REF
= 2.5V, V
IN
= 0V, (Notes 8, 15) 110 dB
ORDER PART NUMBER
Consult factory for Military grade parts.
S8 PART MARKING
(Notes 1, 2)
Supply Voltage (V
CC
) to GND.......................–0.3V to 7V
Analog Input Voltage to GND ....... –0.3V to (V
CC
+ 0.3V)
Reference Input Voltage to GND .. –0.3V to (V
CC
+ 0.3V)
Digital Input Voltage to GND........ –0.3V to (V
CC
+ 0.3V)
Digital Output Voltage to GND ..... –0.3V to (V
CC
+ 0.3V)
Operating Temperature Range
LTC2420C ............................................... 0°C to 70°C
LTC2420I............................................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)..................300°C
T
JMAX
= 125°C, θ
JA
= 130°C/W
LTC2420CS8
LTC2420IS8
2420
2420I
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
ABSOLUTE MAXIMUM RATINGS
W
WW
U
PACKAGE/ORDER INFORMATION
UUW
CONVERTER CHARACTERISTICS
U
1
2
3
4
8
7
6
5
TOP VIEW
F
O
SCK
SDO
CS
V
CC
V
REF
V
IN
GND
S8 PACKAGE
8-LEAD PLASTIC SO
3
LTC2420
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
High Level Input Voltage 2.7V ≤ V
CC
≤ 5.5V ●2.5 V
CS, F
O
2.7V ≤ V
CC
≤ 3.3V 2.0 V
V
IL
Low Level Input Voltage 4.5V ≤ V
CC
≤ 5.5V ●0.8 V
CS, F
O
2.7V ≤ V
CC
≤ 5.5V 0.6 V
V
IH
High Level Input Voltage 2.7V ≤ V
CC
≤ 5.5V (Note 9) ●2.5 V
SCK 2.7V ≤ V
CC
≤ 3.3V (Note 9) 2.0 V
V
IL
Low Level Input Voltage 4.5V ≤ V
CC
≤ 5.5V (Note 9) ●0.8 V
SCK 2.7V ≤ V
CC
≤ 5.5V (Note 9) 0.6 V
I
IN
Digital Input Current 0V ≤ V
IN
≤ V
CC
●–10 10 µA
CS, F
O
I
IN
Digital Input Current 0V ≤ V
IN
≤ V
CC
(Note 9) ●–10 10 µA
SCK
C
IN
Digital Input Capacitance 10 pF
CS, F
O
C
IN
Digital Input Capacitance (Note 9) 10 pF
SCK
V
OH
High Level Output Voltage I
O
= –800µA●V
CC
– 0.5 V
SDO
V
OL
Low Level Output Voltage I
O
= 1.6mA ●0.4 V
SDO
V
OH
High Level Output Voltage I
O
= –800µA (Note 10) ●V
CC
– 0.5 V
SCK
V
OL
Low Level Output Voltage I
O
= 1.6mA (Note 10) ●0.4 V
SCK
I
OZ
High-Z Output Leakage ●–10 10 µA
SDO
DIGITAL I PUTS A D DIGITAL OUTPUTS
UU
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC
Supply Voltage ●2.7 5.5 V
I
CC
Supply Current
Conversion Mode CS = 0V (Note 12) ●200 300 µA
Sleep Mode CS = V
CC
(Note 12) ●20 30 µA
POWER REQUIRE E TS
WU
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
Input Voltage Range (Note 14) ●–0.125 • V
REF
1.125 • V
REF
V
V
REF
Reference Voltage Range ●0.1 V
CC
V
C
S(IN)
Input Sampling Capacitance 1 pF
C
S(REF)
Reference Sampling Capacitance 1.5 pF
I
IN(LEAK)
Input Leakage Current CS = V
CC
●–100 1 100 nA
I
REF(LEAK)
Reference Leakage Current V
REF
= 2.5V, CS = V
CC
●–100 1 100 nA
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
A ALOG I PUT A D REFERE CE
UU
U
U
4
LTC2420
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
f
EOSC
External Oscillator Frequency Range 20-Bit Effective Resolution ●2.56 307.2 kHz
12-Bit Effective Resolution ●2.56 2.048 MHz
t
HEO
External Oscillator High Period ●0.2 390 µs
t
LEO
External Oscillator Low Period ●0.2 390 µs
t
CONV
Conversion Time F
O
= 0V ●130.86 133.53 136.20 ms
F
O
= V
CC
●157.03 160.23 163.44 ms
External Oscillator (Note 11) ●20510/f
EOSC
(in kHz) ms
f
ISCK
Internal SCK Frequency Internal Oscillator (Note 10) 19.2 kHz
External Oscillator (Notes 10, 11) f
EOSC
/8 kHz
D
ISCK
Internal SCK Duty Cycle (Note 10) 45 55 %
f
ESCK
External SCK Frequency Range (Note 9) ●2000 kHz
t
LESCK
External SCK Low Period (Note 9) ●250 ns
t
HESCK
External SCK High Period (Note 9) ●250 ns
t
DOUT_ISCK
Internal SCK 24-Bit Data Output Time Internal Oscillator (Notes 10, 12) ●1.23 1.25 1.28 ms
External Oscillator (Notes 10, 11) ●192/f
EOSC
(in kHz) ms
t
DOUT_ESCK
External SCK 24-Bit Data Output Time (Note 9) ●24/f
ESCK
(in kHz) ms
t
1
CS ↓ to SDO Low Z ●0 150 ns
t2 CS ↑ to SDO High Z ●0 150 ns
t3 CS ↓ to SCK ↓(Note 10) ●0 150 ns
t4 CS ↓ to SCK ↑(Note 9) ●50 ns
t
KQMAX
SCK ↓ to SDO Valid ●200 ns
t
KQMIN
SDO Hold After SCK ↓(Note 5) ●15 ns
t
5
SCK Set-Up Before CS ↓●50 ns
t
6
SCK Hold After CS ↓●50 ns
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: All voltages are with respect to GND. VCC = 2.7 to 5.5V unless
otherwise specified. RSOURCE = 0Ω.
Note 4: Internal Conversion Clock source with the FO pin tied
to GND or to VCC or to external conversion clock source with
fEOSC = 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2%
(external oscillator).
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2%
(external oscillator).
Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is fESCK and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance CLOAD = 20pF.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
FO = 0V or FO = VCC.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: For reference voltage values VREF > 2.5V the extended input
of –0.125 • VREF to 1.125 • VREF is limited by the absolute maximum
rating of the Analog Input Voltage pin (Pin 3). For 2.5V < VREF ≤
0.267V + 0.89 • VCC the input voltage range is –0.3V to 1.125 • VREF.
For 0.267V + 0.89 • VCC < VREF ≤ VCC the input voltage range is –0.3V
to VCC + 0.3V.
Note 15: VCC (DC) = 4.1V, VCC (AC) = 2.8VP-P.
TI I G CHARACTERISTICS
UW
5
LTC2420
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Total Unadjusted Error (3V Supply) Negative Input Extended Total
Unadjusted Error (3V Supply)
INPUT VOLTAGE (V)
0
ERROR (ppm)
2
6
10
2.0
2420 G01
–2
–6
0
4
8
–4
–8
–10 0.5 1.0 1.5 2.5
V
CC
= 3V
V
REF
= 2.5V
T
A
= –55°C, –45°C, 25°C, 90°C
INPUT VOLTAGE (V)
0
ERROR (ppm)
2
6
10
2.0
2420 G02
–2
–6
0
4
8
–4
–8
–10 0.5 1.0 1.5 2.5
V
CC
= 3V
V
REF
= 2.5V
T
A
= –55°C, –45°C, 25°C, 90°C
INPUT VOLTAGE (V)
0
–10
–6
–2
2
–0.05 –0.10 –0.15 –0.20
2420 G03
–0.25
10
–0.30
ERROR (ppm)
6
–8
–4
0
8
4
VCC = 3V
VREF = 2.5V TA = 90°C
TA = 25°C
TA = –45°C
TA = –55°C
INL (3V Supply)
Positive Input Extended Total
Unadjusted Error (3V Supply)
INPUT VOLTAGE (V)
2.50
–10
–6
–2
2
2.55 2.60 2.65 2.70
2420 G04
2.75
10
2.80
ERROR (ppm)
6
–8
–4
0
8
4
V
CC
= 3V
V
REF
= 2.5V
T
A
= –55°C, –45°C, 25°C, 90°C
INPUT VOLTAGE (V)
0
ERROR (ppm)
2
6
10
4
2420 G05
–2
–6
0
4
8
–4
–8
–10 1235
V
CC
= 5V
V
REF
= 5V
T
A
= –55°C, –45°C, 25°C, 90°C
Total Unadjusted Error (5V Supply) INL (5V Supply)
INPUT VOLTAGE (V)
0
ERROR (ppm)
2
6
10
4
2420 G06
–2
–6
0
4
8
–4
–8
–10 1235
V
CC
= 5V
V
REF
= 5V
T
A
= –55°C, –45°C, 25°C, 90°C
Negative Input Extended Total
Unadjusted Error (5V Supply)
INPUT VOLTAGE (V)
0
–10
–6
–2
2
–0.05 –0.10 –0.15 –0.20
2420 G07
–0.25
10
–0.30
ERROR (ppm)
6
–8
–4
0
8
4
VCC = 5V
VREF = 5V TA = 90°C
TA = 25°C
TA = –55°C
TA = –45°C
Positive Input Extended Total
Unadjusted Error (5V Supply)
INPUT VOLTAGE (V)
5.00
–10
–6
–2
2
5.05 5.10 5.15 5.20
2420 G08
5.25
10
5.30
ERROR (ppm)
6
–8
–4
0
8
4
VCC = 5V
VREF = 5V
TA = –45°C
TA = –55°C
TA = 25°CTA = 90°C
Offset Error vs Reference Voltage
REFERENCE VOLTAGE (V)
0
OFFSET ERROR (ppm)
90
120
150
4
2420 G09
60
30
01235
V
CC
= 5V
T
A
= 25°C
6
LTC2420
TYPICAL PERFOR A CE CHARACTERISTICS
UW
RMS Noise vs Reference Voltage Offset Error vs V
CC
REFERENCE VOLTAGE (V)
0
0
RMS NOISE (ppm OF V
REF
)
10
20
30
40
50
60
1234
2420 G10
5
V
CC
= 5V
T
A
= 25°C
V
CC
(V)
2.7
–10
OFFSET ERROR (ppm)
–5
0
5
10
3.2 3.7 4.2 4.7
2420 G11
5.2 5.5
V
REF
= 2.5V
T
A
= 25°C
RMS Noise vs V
CC
V
CC
(V)
2.7
0
RMS NOISE (ppm)
2.5
5.0
7.5
10.0
3.2 3.7 4.2 4.7
2420 G12
5.2 5.5
V
REF
= 2.5V
T
A
= 25°C
Noise Histogram RMS Noise vs Code Out Offset Error vs Temperature
CODE OUT (HEX)
0 7FFFFF FFFFFF
0
RMS NOISE (ppm)
1.25
2.50
3.75
5.00
2420 G14
V
CC
= 5V
V
REF
= 5V
V
IN
= 0.3V TO 5.3V
T
A
= 25°C
TEMPERATURE (°C)
–55
–10
OFFSET ERROR (ppm)
–5
0
5
10
–30 –5 20 45
2420 G15
70 95 120
V
CC
= 5V
V
REF
= 5V
V
IN
= 0V
Full-Scale Error vs Temperature Full-Scale Error vs VCC
TEMPERATURE (°C)
–55
–10
FULL-SCALE ERROR (ppm)
–5
0
5
10
–30 –5 20 45
2420 G16
70 95 120
V
CC
= 5V
V
REF
= 5V
V
IN
= 5V
Full-Scale Error
vs Reference Voltage
REFERENCE VOLTAGE (V)
0
–150
FULL-SCALE ERROR (ppm)
–125
–100
–75
–50
–25
0
1234
2420 G17
5
V
CC
= 5V
V
IN
= V
REF
V
CC
(V)
2.7
–10
FULL-SCALE ERROR (ppm)
–5
0
5
10
3.2 3.7 4.2 4.7
2420 G18
5.2 5.5
V
REF
= 2.5V
V
IN
= 2.5V
T
A
= 25°C
OUTPUT CODE (ppm)
0
50
100
150
200
250
300
350
26
2420G13
–2 0 4
NUMBER OF READINGS
V
CC
= 5
V
REF
= 5
V
IN
= 0
7
LTC2420
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Conversion Current
vs Temperature Sleep Current vs Temperature Rejection vs Frequency at VCC
TEMPERATURE (°C)
–55
SUPPLY CURRENT (µA)
220
20
2420 G19
190
170
–30 –5 45
160
150
230
210
200
180
70 95 120
V
CC
= 5.5V
V
CC
= 4.1V
V
CC
= 2.7V
TEMPERATURE (°C)
–55
0
SUPPLY CURRENT (µA)
10
20
30
–30 –5 20 45
2420 G20
70 95 120
V
CC
= 2.7V
V
CC
= 5V
Rejection vs Frequency at VCC Rejection vs Frequency at VCC Rejection vs Frequency at VIN
Rejection vs Frequency at VIN Rejection vs Frequency at VIN
Rejection vs Frequency at VIN
FREQUENCY AT V
CC
(Hz)
1
REJECTION (dB)
–60
–40
–20
200
2420 G21
–80
–100
–120 50 100 150 250
V
CC
= 4.1V
V
IN
= 0V
T
A
= 25°C
F
O
= 0
FREQUENCY AT VCC (Hz)
15200
–120
REJECTION (dB)
–100
–80
–60
–40
0
15250 15300 15350 15400
2420 G22
15450 15500
–20
VCC = 4.1V
VIN = 0V
TA = 25°C
FO = 0
FREQUENCY AT V
CC
(Hz)
1
–120
REJECTION (dB)
–100
–80
–60
–40
–20
0
100 10k 1M
2420 G23
V
CC
= 4.1V
V
IN
= 0V
T
A
= 25°C
F
O
= 0
FREQUENCY AT V
IN
(Hz)
1
–120
REJECTION (dB)
–100
–80
–60
–40
–20
0
50 100 150 200
2420 G24
250
V
CC
= 5V
V
REF
= 5V
V
IN
= 2.5V
F
O
= 0
INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)
–12–8–404812
REJECTION (dB)
2420 G25
–60
–70
–80
–90
–100
–110
–120
–130
–140
FREQUENCY AT V
IN
(Hz)
15100
–120
REJECTION (dB)
–100
–80
–60
–40
–20
0
15200 15300 15400 15500
2420 G26
V
CC
= 5V
V
REF
= 5V
V
IN
= 2.5V
F
O
= 0
SAMPLE RATE = 15.36kHz ±2%
INPUT FREQUENCY
0
–60
–40
0
2420 F27
–80
–100
f
S
/2 f
S
–120
–140
–20
REJECTION (dB)
8
LTC2420
TYPICAL PERFOR A CE CHARACTERISTICS
UW
INL vs Output Rate INL vs Output Rate Resolution vs Output Rate
OUTPUT RATE (Hz)
0 7.5
RESOLUTION (BITS)
20
22
75
2420 G30
18
16 25 50 100
24 T
A
= 25°C
T
A
= 90°C
T
A
= –45°C
V
CC
= 5V
V
REF
= 5V
f
O
= EXTERNAL
V
CC
(Pin 1): Positive Supply Voltage. Bypass to GND
(Pin␣ 4) with a 10µF tantalum capacitor in parallel with
0.1µF ceramic capacitor as close to the part as possible.
V
REF
(Pin 2): Reference Input. The reference voltage range
is 0.1V to V
CC
.
V
IN
(Pin 3): Analog Input. The input voltage range is
–0.125 • V
REF
to 1.125 • V
REF
. For V
REF
> 2.5V the input
voltage range may be limited by the pin absolute maxi-
mum rating of –0.3V to V
CC
+ 0.3V.
GND (Pin 4): Ground. Shared pin for analog ground,
digital ground, reference ground and signal ground. Should
be connected directly to a ground plane through a mini-
mum length trace or it should be the single-point-ground
in a single point grounding system.
CS (Pin 5): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW on CS wakes up the ADC. A
LOW-to-HIGH transition on this pin disables the SDO
digital output. A LOW-to-HIGH transition on CS during the
Data Output transfer aborts the data transfer and starts a
new conversion.
SDO (Pin 6): Three-State Digital Output. During the data
output period this pin is used for serial data output. When
the chip select CS is HIGH (CS = V
CC
), the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin can be used as a conversion status out-
put. The conversion status can be observed by pulling CS
LOW.
SCK (Pin 7): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the data output
period. In External Serial Clock Operation mode, SCK is
used as digital input for the external serial interface. A
weak internal pull-up is automatically activated in Internal
Serial Clock Operation mode. The Serial Clock mode is
determined by the level applied to SCK at power up and the
falling edge of CS.
F
O
(Pin 8): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the F
O
pin is connected to V
CC
(F
O
= V
CC
), the
converter uses its internal oscillator and the digital filter’s
first null is located at 50Hz. When the F
O
pin is connected
to GND (F
O
= OV), the converter uses its internal oscillator
and the digital filter first null is located at 60Hz. When F
O
is driven by an external clock signal with a frequency f
EOSC
,
the converter uses this signal as its clock and the digital
filter first null is located at a frequency f
EOSC
/2560.
PIN FUNCTIONS
UU
U
OUTPUT RATE (Hz)
0
TUE RESOLUTION (BITS)
16
18
20
40
2420 G28
14
12
10 10 20 30 50 60 70 80 90 100
VCC = 5V
VREF = 5V
FO = EXTERNAL
TA = –45°C
TA = 25°C
TA = 90°C
OUTPUT RATE (Hz)
0
TUE RESOLUTION (BITS)
16
18
20
40
2420 G29
14
12
10 10 20 30 50 60 70 80 90 100
VCC = 3V
VREF = 2.5V
FO = EXTERNAL
TA = –45°C
TA = 25°CTA = 90°C
9
LTC2420
UU
W
FU CTIO AL BLOCK DIAGRA
TEST CIRCUITS
AUTOCALIBRATION
AND CONTROL
DAC
DECIMATING FIR
INTERNAL
OSCILLATOR
SERIAL
INTERFACE
ADC
∑
∫∫∫
GND
V
CC
V
IN
SDO
SCK
V
REF
CS
F
O
(INT/EXT)
2420 FD
3.4k
SDO
2420 TC01
Hi-Z TO V
OH
V
OL
TO V
OH
V
OH
TO Hi-Z
C
LOAD
= 20pF
3.4k
SDO
2420 TC02
Hi-Z TO V
OL
V
OH
TO V
OL
V
OL
TO Hi-Z
C
LOAD
= 20pF
V
CC
10
LTC2420
APPLICATIO S I FOR ATIO
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The LTC2420 is pin compatible with the LTC2400. The two
devices are designed to allow the user to incorporate
either device in the same design with no modifications.
While the LTC2420 output word length is 24 bits (as
opposed to the 32-bit output of the LTC2400), its output
clock timing can be identical to the LTC2400. As shown in
Figure 1, the LTC2420 data output is concluded on the
falling edge of the 24th serial clock (SCK). In order to
maintain drop-in compatibility with the LTC2400, it is
possible to clock the LTC2420 with an additional 8 serial
clock pulses. This results in 8 additional output bits which
are always logic HIGH.
Converter Operation Cycle
The LTC2420 is a low power, delta-sigma analog-to-
digital converter with an easy to use 3-wire serial interface.
Its operation is simple and made up of three states. The
converter operating cycle begins with the conversion,
followed by a low power sleep state and concluded with
the data output (see Figure 2). The 3-wire interface con-
sists of serial data output (SDO), a serial clock (SCK) and
a chip select (CS).
Initially, the LTC2420 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
While in this sleep state, power consumption is reduced by
an order of magnitude. The part remains in the sleep state
as long as CS is logic HIGH. The conversion result is held
indefinitely in a static shift register while the converter is
in the sleep state.
Once CS is pulled LOW, the device begins outputting the
conversion result. There is no latency in the conversion
result. The data output corresponds to the conversion just
performed. This result is shifted out on the serial data out
pin (SDO) under the control of the serial clock (SCK). Data
is updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK, see Figure 4.
The data output state is concluded once 24 bits are read
out of the ADC or when CS is brought HIGH. The device
automatically initiates a new conversion cycle and the
cycle repeats.
Through timing control of the CS and SCK pins, the
LTC2420 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require
program
ming configuration registers; moreover, they do
Figure 1. LTC2420 Compatible Timing with the LTC2400
CS
SCK
SDO
CONVERSION SLEEP
8 8 8 8 (OPTIONAL)
EOC = 1 EOC = 1
LAST 8 BITS ALWAYS 1
EOC = 0 DATA OUT
4 STATUS BITS 20 DATA BITS
DATA OUTPUT
2420 F01
CONVERSION
CONVERT
SLEEP
DATA OUTPUT
2420 F02
0
1 CS AND
SCK
Figure 2. LTC2420 State Transition Diagram
11
LTC2420
not disturb the cyclic operation described above. These
modes of operation are described in detail in the Serial
Interface Timing Modes section.
Conversion Clock
A major advantage delta-sigma converters offer over
conventional type converters is an on-chip digital filter
(commonly known as Sinc or Comb filter). For high
resolution, low frequency applications, this filter is typi-
cally designed to reject line frequencies of 50Hz or 60Hz
plus their harmonics. In order to reject these frequencies
in excess of 110dB, a highly accurate conversion clock is
required. The LTC2420 incorporates an on-chip highly
accurate oscillator. This eliminates the need for external
frequency setting components such as crystals or oscilla-
tors. Clocked by the on-chip oscillator, the LTC2420
rejects line frequencies (50Hz or 60Hz ±2%) a minimum
of 110dB.
Ease of Use
The LTC2420 data output has no latency, filter settling or
redundant data associated with the conversion cycle.
There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
an analog input voltage is easy.
The LTC2420 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation de-
scribed above. The advantage of continuous calibration is
extreme stability of offset and full-scale readings with re-
spect to time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2420 automatically enters an internal reset state
when the power supply voltage V
CC
drops below approxi-
mately 2.2V. This feature guarantees the integrity of the
conversion result and of the serial interface mode selec-
tion which is performed at the initial power-up. (See the
2-wire I/O sections in the Serial Interface Timing Modes
section.)
When the V
CC
voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with duration of approximately 0.5ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2420 starts a normal conversion cycle and
follows the normal succession of states described above.
The first conversion result following POR is accurate
within the specifications of the device.
Reference Voltage Range
The LTC2420 can accept a reference voltage from 0V to
V
CC
. The converter output noise is determined by the
thermal noise of the front-end circuits, and as such, its
value in microvolts is nearly constant with reference
voltage. A decrease in reference voltage will not signifi-
cantly improve the converter’s effective resolution. On the
other hand, a reduced reference voltage will improve the
overall converter INL performance. The recommended
range for the LTC2420 voltage reference is 100mV to V
CC
.
Input Voltage Range
The converter is able to accommodate system level offset
and gain errors as well as system level overrange situa-
tions due to its extended input range, see Figure 3. The
LTC2420 converts input signals within the extended input
range of –0.125 • V
REF
to 1.125 • V
REF
.
For large values of V
REF
, this range is limited by the
absolute maximum voltage range of – 0.3V to (V
CC
+ 0.3V).
Beyond this range, the input ESD protection devices begin
to turn on and the errors due to the input leakage current
increase rapidly.
Input signals applied to V
IN
may extend below ground by
–300mV and above V
CC
by 300mV. In order to limit any
APPLICATIO S I FOR ATIO
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2420 F03
V
CC
+ 0.3V
9/8V
REF
V
REF
1/2V
REF
–0.3V
–1/8V
REF
0
NORMAL
INPUT
RANGE
EXTENDED
INPUT
RANGE
ABSOLUTE
MAXIMUM
INPUT
RANGE
Figure 3. LTC2420 Input Range
12
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fault current, a resistor of up to 25k may be added in series
with the V
IN
pin without affecting the performance of the
device. In the physical layout, it is important to maintain
the parasitic capacitance of the connection between this
series resistance and the V
IN
pin as low as possible;
therefore, the resistor should be located as close as
practical to the V
IN
pin. The effect of the series resistance
on the converter accuracy can be evaluated from the
curves presented in the Analog Input/Reference Current
section. In addition, a series resistor will introduce a
temperature dependent offset error due to the input leak-
age current. A 1nA input leakage current will develop a
1ppm offset error on a 5k resistor if V
REF
= 5V. This error
has a very strong temperature dependency.
Output Data Format
The LTC2420 serial output data stream is 24 bits long. The
first 4 bits represent status information indicating the
sign, input range and conversion state. The next 20 bits are
the conversion result, MSB first.
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 21 (third output bit) is the conversion result sign indi-
cator (SIG). If V
IN
is >0, this bit is HIGH. If V
IN
is <0, this
bit is LOW. The sign bit changes state during the zero code.
Bit 20 (fourth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0␣ ≤␣V
IN
≤ V
REF
, this bit is LOW. If the input is outside the
normal input range, V
IN
> V
REF
or V
IN
< 0, this bit is HIGH.
The function of these bits is summarized in Table 1.
Table 1. LTC2420 Status Bits
Bit 23 Bit 22 Bit 21 Bit 20
Input Range EOC DMY SIG EXR
V
IN
> V
REF
0 011
0 < V
IN
≤ V
REF
0 010
V
IN
= 0
+
/0
–
0 0 1/0 0
V
IN
< 0 0 001
Bit 19 (fifth output bit) is the most significant bit (MSB).
Bits 19-0 are the 20-bit conversion result MSB first.
Bit 0 is the least significant bit (LSB).
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 4. Whenever CS is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 23 (EOC) can be captured on the first rising
edge of SCK. Bit 22 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 23rd SCK and may be latched on
Figure 4. Output Data Timing
MSBEXTSIG“0”
12345 192024
BIT 0BIT 19 BIT 4
LSB
20
BIT 20BIT 21BIT 22
SDO
SCK
CS
EOC
BIT 23
SLEEP DATA OUTPUT CONVERSION
2420 F04
Hi-Z
13
LTC2420
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Table 2. LTC2420 Output Data Format
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 … Bit 0
Input Voltage EOC DMY SIG EXR MSB LSB
V
IN
> 9/8 • V
REF
0 01100 0 11...1
9/8 • V
REF
0 01100 0 11...1
V
REF
+ 1LSB 0 01100 0 00...0
V
REF
0 01011 1 11...1
3/4V
REF
+ 1LSB 0 01011 0 00...0
3/4V
REF
0 01010 1 11...1
1/2V
REF
+ 1LSB 0 01010 0 00...0
1/2V
REF
0 01001 1 11...1
1/4V
REF
+ 1LSB 0 01001 0 00...0
1/4V
REF
0 01000 1 11...1
0
+
/0
–
0 01/0*000 0 00...0
–1LSB 0 0 0111 1 11...1
–1/8 • V
REF
0 00111 1 00...0
V
IN
< –1/8 • V
REF
0 00111 1 00...0
*The sign bit changes state during the 0 code.
the rising edge of the 24th SCK pulse. On the falling edge
of the 24th SCK pulse, SDO goes HIGH indicating a new
conversion cycle has been initiated. This bit serves as EOC
(Bit 23) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the V
IN
pin is maintained within
the –0.3V to (V
CC
+ 0.3V) absolute maximum operating
range, a conversion result is generated for any input value
from –0.125 • V
REF
to 1.125 • V
REF
.
For input voltages
greater than 1.125 • V
REF
, the conversion result is clamped
to the value corresponding to 1.125 • V
REF
. For input
voltages below –0.125 • V
REF
, the conversion result is
clamped to the value corresponding to –0.125 • V
REF
.
Frequency Rejection Selection (F
O
Pin Connection)
The LTC2420 internal oscillator provides better than 110dB
normal mode rejection at the line frequency and its har-
monics for 50Hz ±2% or 60Hz ±2%. For 60Hz rejection, F
O
(Pin 8) should be connected to GND (Pin 4) while for 50Hz
rejection the F
O
pin should be connected to V
CC
(Pin␣ 1).
The selection of 50Hz or 60Hz rejection can also be made
by driving F
O
to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2420 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the F
O
pin and turns off the internal oscillator. The
frequency f
EOSC
of the external signal must be at least
2560Hz (1Hz notch frequency) to be detected. The exter-
nal clock signal duty cycle is not significant as long as the
minimum and maximum specifications for the high and
low periods t
HEO
and t
LEO
are observed.
While operating with an external conversion clock of a
frequency f
EOSC
, the LTC2420 provides better than 110dB
normal mode rejection in a frequency range f
EOSC
/2560
±4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from f
EOSC
/2560
is shown in Figure 5.
14
LTC2420
APPLICATIO S I FOR ATIO
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INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)
–12–8–404812
REJECTION (dB)
2420 F05
–60
–70
–80
–90
–100
–110
–120
–130
–140
Figure 5. LTC2420 Normal Mode Rejection When
Using an External Oscillator of Frequency fEOSC
Whenever an external clock is not present at the F
O
pin, the
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2420
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
not be affected. If the change occurs during the data output
state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.
Table 3 summarizes the duration of each state as a
function of F
O
.
SERIAL INTERFACE
The LTC2420 transmits the conversion results and re-
ceives the start of conversion command through a syn-
chronous 3-wire interface. During the conversion and
sleep states, this interface can be used to assess the
converter status and during the data output state it is used
to read the conversion result.
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 7) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2420 creates its own serial clock by
dividing the internal conversion clock by 8. In the External
SCK mode of operation, the SCK pin is used as input. The
internal or external SCK mode is selected on power-up and
then reselected every time a HIGH-to-LOW transition is
detected at the CS pin. If SCK is HIGH or floating at power-
up or during this transition, the converter enters the inter-
nal SCK mode. If SCK is LOW at power-up or during this
transition, the converter enters the external SCK mode.
Table 3. LTC2420 State Duration
State Operating Mode Duration
CONVERT Internal Oscillator F
O
= LOW 133ms
(60Hz Rejection)
F
O
= HIGH 160ms
(50Hz Rejection)
External Oscillator F
O
= External Oscillator 20510/f
EOSC
s
with Frequency f
EOSC
kHz
(f
EOSC
/2560 Rejection)
SLEEP As Long As CS = HIGH Until CS = 0 and SCK
DATA OUTPUT Internal Serial Clock F
O
= LOW/HIGH As Long As CS = LOW But Not Longer Than 1.26ms
(Internal Oscillator) (24 SCK cycles)
F
O
= External Oscillator with As Long As CS = LOW But Not Longer Than 256/f
EOSC
ms
Frequency f
EOSC
kHz (24 SCK cycles)
External Serial Clock with As Long As CS = LOW But Not Longer Than 24/f
SCK
ms
Frequency f
SCK
kHz (24 SCK cycles)
15
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Serial Data Output (SDO)
The serial data output pin, SDO (Pin 6), drives the serial
data during the data output state. In addition, the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.
When CS (Pin 5) is HIGH, the SDO driver is switched to a
high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS is LOW.
Chip Select Input (CS)
The active LOW chip select, CS (Pin 5), is used to test the
conversion status and to enable the data output transfer as
described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2420 will abort any serial data
transfer in progress and start a new conversion cycle any-
time a LOW-to-HIGH transition is detected at the CS pin
after the converter has entered the data output state (i.e.,
after the first rising edge of SCK occurs while CS is LOW).
Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by FO. Tying a
capacitor to CS will reduce the output rate and power
dissipation by a factor proportional to the capacitor’s
value, see Figures 13 to 15.
SERIAL INTERFACE TIMING MODES
The LTC2420’s 3-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes of
operation. These include internal/external serial clock,
2- or 3-wire I/O, single cycle conversion and autostart. The
following sections describe each of these serial interface
timing modes in detail. In all these cases, the converter
can use the internal oscillator (F
O
= LOW or F
O
= HIGH) or
an external oscillator connected to the F
O
pin. Refer to
Table 4 for a summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 6.
The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin. EOC
= 1 while a conversion is in progress and EOC = 0 if the
device is in the sleep state. Independent of CS, the device
automatically enters the low power sleep state once the
conversion is complete.
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift regis-
ter. The device remains in the sleep state until the first
rising edge of SCK is seen while CS is LOW. Data is
shifted
out the SDO pin on each falling edge of SCK. This enables
Table 4. LTC2420 Interface Timing Modes
Conversion Data Connection
SCK Cycle Output and
Configuration Source Control Control Waveforms
External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 6, 7
External SCK, 2-Wire I/O External SCK SCK Figure 8
Internal SCK, Single Cycle Conversion Internal CS ↓CS ↓Figures 9, 10
Internal SCK, 2-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 11
Internal SCK, Autostart Conversion Internal C
EXT
Internal Figure 12
16
LTC2420
EOC
BIT 23
SDO
SCK
(EXTERNAL)
CS
V
CC
F
O
V
REF
SCK
V
IN
SDO
GND CS
V
REF
0.1V TO V
CC
V
IN
–0.12V
REF
TO 1.12V
REF
1µF
2.7V TO 5.5V
LTC2420
TEST EOC
MSB LSB
20
EXRSIG
BIT 0BIT 4BIT 19 BIT 18BIT 20BIT 21BIT 22
SLEEP DATA OUTPUT CONVERSION
2420 F06
CONVERSION
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
Hi-ZHi-ZHi-Z
V
CC
TEST EOCTEST EOC
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Figure 6. External Serial Clock, Single Cycle Operation
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result can be latched on
the 24th rising edge of SCK. On the 24th falling edge of
SCK, the device begins a new conversion. SDO goes HIGH
(EOC = 1) indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the
24th falling edge of SCK, see Figure 7. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion. This is useful for sys-
tems not requiring all 24 bits of output data, aborting an
invalid conversion cycle or synchronizing the start of a
conversion.
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 8. CS
may be permanently tied to ground (Pin 4), simplifying the
user interface or isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after V
CC
exceeds 2.2V. The level
applied to SCK at this time determines if SCK is internal or
external. SCK must be driven LOW prior to the end of POR
in order to enter the external serial clock timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and EOC
= 0 once the conversion enters the low power sleep state.
On the falling edge of EOC, the conversion result is loaded
17
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VCC FO
VREF SCK
VIN SDO
GND CS
VREF
0.1V TO VCC
VIN
–0.12VREF TO 1.12VREF
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
1µF
2.7V TO 5.5V
LTC2420
SDO
SCK
(EXTERNAL)
CS
DATA OUTPUT
CONVERSIONSLEEP SLEEP
TEST EOC TEST EOC
DATA OUTPUT
Hi-Z Hi-ZHi-Z
CONVERSION
2420 F07
MSBEXRSIG
BIT 8BIT 19 BIT 9BIT 20BIT 21BIT 22
EOC
BIT 23
BIT 0
EOC
Hi-Z
VCC
TEST EOC
EOC
BIT 23
SDO
SCK
(EXTERNAL)
CS
VCC FO
VREF SCK
VIN SDO
GND CS
VREF
0.1V TO VCC
VIN
–0.12VREF TO 1.12VREF
1µF
2.7V TO 5.5V
LTC2420
MSBEXRSIG
BIT 0
LSB20
BIT 4BIT 19 BIT 18BIT 20BIT 21BIT 22
SLEEP DATA OUTPUT CONVERSION
2420 F07
CONVERSION
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
VCC
Figure 7. External Serial Clock, Reduced Data Output Length
Figure 8. External Serial Clock, CS = 0 Operation
18
LTC2420
into an internal static shift register. The device remains in
the sleep state until the first rising edge of SCK. Data is
shifted out the SDO pin on each falling edge of SCK
enabling external circuitry to latch data on the rising edge
of SCK. EOC can be latched on the first rising edge of SCK.
On the 24th falling edge of SCK, SDO goes HIGH (EOC = 1)
indicating a new conversion has begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 9.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time t
EOCtest
after the falling edge of CS
(if EOC = 0) or t
EOCtest
after EOC goes LOW (if CS is LOW
during the falling edge of EOC). The value of t
EOCtest
is 23µs
if the device is using its internal oscillator (F
0
= logic LOW
or HIGH). If F
O
is driven by an external oscillator of
frequency f
EOSC
, then t
EOCtest
is 3.6/f
EOSC
. If CS is pulled
HIGH before time t
EOCtest
, the device remains in the sleep
state. The conversion result is held in the internal static
shift register.
If CS remains LOW longer than t
EOCtest
, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 24th
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
SDO
SCK
(INTERNAL)
CS
MSBEXRSIG
BIT 0
LSB
20
BIT 4 TEST EOC
BIT 19 BIT 18BIT 20BIT 21BIT 22
EOC
BIT 23
SLEEP DATA OUTPUT CONVERSIONCONVERSION
2420 F09
<t
EOCtest
V
CC
F
O
V
REF
SCK
V
IN
SDO
GND CS
V
REF
0.1V TO V
CC
V
IN
–0.12V
REF
TO 1.12V
REF
1µF
2.7V TO 5.5V
LTC2420
V
CC
10k
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
Hi-Z Hi-Z Hi-Z Hi-Z
V
CC
TEST EOC
Figure 9. Internal Serial Clock, Single Cycle Operation
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19
LTC2420
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 24th rising edge of SCK. After the
24th rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH, and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 24th rising edge of
SCK, see Figure 10. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 24 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2420’s internal pull-up at
pin SCK is disabled. Normally, SCK is not externally driven
if the device is in the internal SCK timing mode. However,
certain applications may require an external driver on SCK.
If this driver goes Hi-Z after outputting a LOW signal, the
LTC2420’s internal pull-up remains disabled. Hence, SCK
remains LOW. On the next falling edge of CS, the device is
switched to the external SCK timing mode. By adding an
external 10k pull-up resistor to SCK, this pin goes HIGH
once the external driver goes Hi-Z. On the next CS falling
edge, the device will remain in the internal SCK timing
mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0), SCK
will go LOW. Once CS goes HIGH (within the time period
defined above as t
EOCtest
), the internal pull-up is activated.
For a heavy capacitive load on the SCK pin, the internal
pull-up may not be adequate to return SCK to a HIGH level
before CS goes low again. This is not a concern under
normal conditions where CS remains LOW after detecting
EOC = 0. This situation is easily overcome by adding an
external 10k pull-up resistor to the SCK pin.
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SDO
SCK
(INTERNAL)
CS
>t
EOCtest
MSBEXRSIG
BIT 8
TEST EOCTEST EOC BIT 19 BIT 18BIT 20BIT 21BIT 22
EOC
BIT 23
EOC
BIT 0
SLEEP DATA OUTPUT
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
DATA OUTPUT
CONVERSIONCONVERSIONSLEEP
2420 F10
<t
EOCtest
V
CC
F
O
V
REF
SCK
V
IN
SDO
GND CS
V
REF
0.1V TO V
CC
V
IN
–0.12V
REF
TO 1.12V
REF
1µF
2.7V TO 5.5V
LTC2420
V
CC
10k
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
TEST EOC
Figure 10. Internal Serial Clock, Reduced Data Output Length
20
LTC2420
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 11. CS may be permanently tied to ground (Pin 4),
simplifying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after V
CC
exceeds 2.2V. An internal
weak pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
APPLICATIO S I FOR ATIO
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then immediately begins outputting data. The data output
cycle begins on the first rising edge of SCK and ends after
the 24th rising edge. Data is shifted out the SDO pin on
each falling edge of SCK. The internally generated serial
clock is output to the SCK pin. This signal may be used
to shift the conversion result into external circuitry. EOC
can be latched on the first rising edge of SCK and the last
bit of the conversion result can be latched on the 24th
rising edge of SCK. After the 24th rising edge, SDO goes
HIGH (EOC = 1) indicating a new conversion is in progress.
SCK remains HIGH during the conversion.
Internal Serial Clock, Autostart Conversion
This timing mode is identical to the internal serial clock,
2-wire I/O described above with one additional feature.
Instead of grounding CS, an external timing capacitor is
tied to CS.
While the conversion is in progress, the CS pin is held
HIGH by an internal weak pull-up. Once the conversion is
complete, the device enters the low power sleep state and
an internal 25nA current source begins discharging the
SDO
SCK
(INTERNAL)
CS
LSB
20
MSBEXRSIG
BIT 4 BIT 0BIT 19 BIT 18BIT 20BIT 21BIT 22
EOC
BIT 23
SLEEP
DATA OUTPUT CONVERSIONCONVERSION
2420 F11
V
CC
F
O
V
REF
SCK
V
IN
SDO
GND CS
V
REF
0.1V TO V
CC
V
IN
–0.12V
REF
TO 1.12V
REF
1µF
2.7V TO 5.5V
LTC2420
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
Figure 11. Internal Serial Clock, Continuous Operation
21
LTC2420
APPLICATIO S I FOR ATIO
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capacitor tied to CS, see Figure 12. The time the converter
spends in the sleep state is determined by the value of the
external timing capacitor, see Figures 13 and 14. Once the
voltage at CS falls below an internal threshold (≈1.4V), the
device automatically begins outputting data. The data
output cycle begins on the first rising edge of SCK and
ends on the 24th rising edge. Data is shifted out the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
After the 24th rising edge, CS is pulled HIGH and a new
conversion is immediately started. This is useful in appli-
cations requiring periodic monitoring and ultralow power.
Figure 15 shows the average supply current as a function
of capacitance on CS.
It should be noticed that the external capacitor discharge
current is kept very small in order to decrease the con-
verter power dissipation in the sleep state. In the autostart
mode the analog voltage on the CS pin cannot be observed
without disturbing the converter operation using a regular
oscilloscope probe. When using this configuration, it is
important to minimize the external leakage current at the
CS pin by using a low leakage external capacitor and
properly cleaning the PCB surface.
SDO
Hi-ZHi-Z
SCK
(INTERNAL)
CS
V
CC
GND
2420 F12
V
CC
F
O
V
REF
SCK
V
IN
SDO
GND
C
EXT
CS
V
REF
0.1V TO V
CC
V
IN
–0.12V
REF
TO 1.12V
REF
1µF
2.7V TO 5.5V
LTC2420
BIT 0
SIG
BIT 21BIT 22
SLEEP DATA OUTPUT CONVERSIONCONVERSION
EOC
BIT 23
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
Figure 12. Internal Serial Clock, Autostart Operation
CAPACITANCE ON CS (pF)
1
5
6
7
1000 10000
2420 F13
4
3
10 100 100000
2
1
0
t
SAMPLE
(SEC)
V
CC
= 5V
V
CC
= 3V
Figure 13. CS Capacitance vs fSAMPLE
22
LTC2420
APPLICATIO S I FOR ATIO
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The internal serial clock mode is selected every time the
voltage on the CS pin crosses an internal threshold volt-
age. An internal weak pull-up at the SCK pin is active while
CS is discharging; therefore, the internal serial clock
timing mode is automatically selected if SCK is floating. It
is important to ensure there are no external drivers pulling
SCK LOW while CS is discharging.
DIGITAL SIGNAL LEVELS
The LTC2420’s digital interface is easy to use. Its digital
inputs (F
O
, CS and SCK in External SCK mode of operation)
accept standard TTL/CMOS logic levels and the internal
hysteresis receivers can tolerate edge rates as slow as
100µs. However, some considerations are required to take
advantage of exceptional accuracy and low supply current.
CAPACITANCE ON CS (pF)
0
SAMPLE RATE (Hz)
3
4
5
1000 100000
2420 F14
2
1
010 100 10000
6
7
8
V
CC
= 5V
V
CC
= 3V
Figure 14. CS Capacitance vs Output Rate
CAPACITANCE ON CS (pF)
1
0
SUPPLY CURRENT (µA
RMS
)
50
100
150
200
250
300
10 100 1000 10000
2420 F15
100000
V
CC
= 5V
V
CC
= 3V
Figure 15. CS Capacitance vs Supply Current
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
In order to preserve the LTC2420’s accuracy, it is very
important to minimize the ground path impedance which
may appear in series with the input and/or reference signal
and to reduce the current which may flow through this path.
The GND pin should be connected to a low resistance
ground plane through a minimum length trace. The use of
multiple via holes is recommended to further reduce the
connection resistance. The LTC2420’s power supply cur-
rent flowing through the 0.01Ω resistance of the common
ground pin will develop a 2.5µV offset signal. For a refer-
ence voltage V
REF
= 2.5V, this represents a 1ppm offset
error.
In an alternative configuration, the GND pin of the converter
can be the single-point-ground in a single point grounding
system. The input signal ground, the reference signal
ground, the digital drivers ground (usually the digital
ground) and the power supply ground (the analog ground)
should be connected in a star configuration with the com-
mon point located as close to the GND pin as possible.
The power supply current during the conversion state
should be kept to a minimum. This is achieved by restrict-
ing the number of digital signal transitions occurring
during this period.
While a digital input signal is in the range 0.5V to
(V
CC
␣ –␣ 0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (F
O
, CS and SCK
in External SCK mode of operation) is within this range, the
LTC2420 power supply current may increase even if the
signal in question is at a valid logic level. For micropower
operation and in order to minimize the potential errors due
to additional ground pin current, it is recommended to
drive all digital input signals to full CMOS levels
[V
IL
< 0.4V and V
OH
> (V
CC
– 0.4V)].
Severe ground pin current disturbances can also occur
due to the undershoot of fast digital input signals. Under-
shoot and overshoot can occur because of the imped-
ance mismatch at the converter pin when the transition
time of an external control signal is less than twice the
23
LTC2420
propagation delay from the driver to LTC2420. For refer-
ence, on a regular FR-4 board, signal propagation veloc-
ity is approximately 183ps/inch for internal traces and
170ps/inch for surface traces. Thus, a driver generating
a control signal with a minimum transition time of 1ns
must be connected to the converter pin through a trace
shorter than 2.5 inches. This problem becomes particu-
larly difficult when shared control lines are used and
multiple reflections may occur. The solution is to care-
fully terminate all transmission lines close to their char-
acteristic impedance.
Parallel termination near the LTC2420 pin will eliminate
this problem but will increase the driver power dissipation.
A series resistor between 27Ω and 56Ω placed near the
driver or near the LTC2420 pin will also eliminate this
problem without additional power dissipation. The actual
resistor value depends upon the trace impedance and
connection topology.
Driving the Input and Reference
The analog input and reference of the typical delta-sigma
analog-to-digital converter are applied to a switched ca-
pacitor network. This network consists of capacitors switch-
ing between the analog input (V
IN
), ground (Pin 4) and the
reference (V
REF
). The result is small current spikes seen at
both V
IN
and V
REF
. A simplified input equivalent circuit is
shown in Figure 16.
The key to understanding the effects of this dynamic input
current is based on a simple first order RC time constant
model. Using the internal oscillator, the LTC2420’s inter-
nal switched capacitor network is clocked at 153,600Hz
corresponding to a 6.5µs sampling period. Fourteen time
constants are required each time a capacitor is switched in
order to achieve 1ppm settling accuracy.
Therefore, the equivalent time constant at V
IN
and V
REF
should be less than 6.5µs/14 = 460ns in order to achieve
1ppm accuracy.
Input Current (V
IN
)
If complete settling occurs on the input, conversion re-
sults will be uneffected by the dynamic input current. If the
settling is incomplete, it does not degrade the linearity
performance of the device. It simply results in an offset/
full-scale shift, see Figure 17. To simplify the analysis of
input dynamic current, two separate cases are assumed:
large capacitance at V
IN
(C
IN
> 0.01µF) and small capaci-
tance at V
IN
(C
IN
< 0.01µF).
If the total capacitance at V
IN
(see Figure 18) is small
(<0.01µF), relatively large external source resistances (up
to 80k for 20pF parasitic capacitance) can be tolerated
without any offset/full-scale error. Figures 19 and 20 show
a family of offset and full-scale error curves for various
small valued input capacitors (C
IN
< 0.01µF) as a function
of input source resistance.
APPLICATIO S I FOR ATIO
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V
REF
V
IN
V
CC
R
SW
5k
AVERAGE INPUT CURRENT:
I
IN
= 0.25(V
IN
– 0.5 • V
REF
)fC
EQ
I
REF(LEAK)
I
REF(LEAK)
V
CC
R
SW
5k
C
EQ
1pF (TYP)
R
SW
5k
I
IN(LEAK)
I
IN
2420 F16
I
IN(LEAK)
SWITCHING FREQUENCY
f = 153.6kHz FOR INTERNAL OSCILLATOR (f
O
= LOGIC LOW OR HIGH)
f = f
EOSC
FOR EXTERNAL OSCILLATORS
GND
Figure 16. LTC2420 Equivalent Analog Input Circuit
0
TUE
V
REF
/2
V
IN
2420 F17
V
REF
C
IN
2420 F18
INTPUT
SIGNAL
SOURCE
R
SOURCE
V
IN
LTC2420
C
PAR
≅20pF
Figure 17. Offset/Full-Scale Shift
Figure 18. An RC Network at VIN
24
LTC2420
APPLICATIO S I FOR ATIO
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For large input capacitor values (C
IN
> 0.01µF), the input
spikes are averaged by the capacitor into a DC current. The
gain shift becomes a linear function of input source
resistance independent of input capacitance, see Figures
21 and 22. The equivalent input impedance is 16.6MΩ.
This results in ±150nA of input dynamic current at the
extreme values of V
IN
(V
IN
= 0V and V
IN
= V
REF
, when
V
REF
= 5V). This corresponds to a 0.3ppm shift in offset
and full-scale readings for every 10Ω of input source
resistance.
In addition to the input current spikes, the input ESD
protection diodes have a temperature dependent leakage
current. This leakage current, nominally 1nA (±10nA
max), results in a fixed offset shift of 10µV for a 10k source
resistance.
R
SOURCE
(Ω)
1
OFFSET ERROR (ppm)
30
40
50
10k
2420 F19
20
10
010 100 1k 100k
V
CC
= 5V
V
REF
= 5V
V
IN
= 0V
T
A
= 25°C
C
IN
= 100pF
C
IN
= 1000pF
C
IN
= 0pF
C
IN
= 0.01µF
Figure 19. Offset vs RSOURCE (Small C)
Figure 20. Full-Scale Error vs RSOURCE (Small C)
Reference Current (V
REF
)
Similar to the analog input, the reference input has a
dynamic input current. This current has negligible effect
on the offset. However, the reference current at V
IN
= V
REF
is similar to the input current at full-scale. For large values
of reference capacitance (C
VREF
> 0.01µF), the full-scale
error shift is 0.03ppm/Ω of external reference resistance
independent of the capacitance at V
REF
, see Figure 23. If
the capacitance tied to V
REF
is small (C
VREF
< 0.01µF), an
input resistance of up to 80k (20pF parasitic capacitance
at V
REF
) may be tolerated, see Figure 24.
Unlike the analog input, the integral nonlinearity of the
device can be degraded with excessive external RC time
constants tied to the reference input. If the capacitance at
R
SOURCE
(Ω)
0
25
30
35
600 800
2420 F21
20
15
200 400 1000
10
5
0
OFFSET ERROR (ppm)
C
IN
= 22µF
C
IN
= 10µF
C
IN
= 1µF
C
IN
= 0.1µF
C
IN
= 0.01µF
C
IN
= 0.001µF
V
CC
= 5V
V
REF
= 5V
V
IN
= 0V
T
A
= 25°C
R
SOURCE
(Ω)
0
FULL-SCALE ERROR (ppm)
–20
–15
–10
600 1000
2420 F22
–25
–30
–35 200 400 800
–5
0
5
C
IN
= 22µF
C
IN
= 10µF
C
IN
= 1µF
C
IN
= 0.1µF
C
IN
= 0.01µF
C
IN
= 0.001µF
V
CC
= 5V
V
REF
= 5V
V
IN
= 0V
T
A
= 25°C
Figure 21. Offset vs RSOURCE (Large C)
Figure 22. Full-Scale Error vs RSOURCE (Large C)
RSOURCE (Ω)
1
–50
FULL-SCALE ERROR (ppm)
–40
–30
–20
–10
0
10
10 100 1k 10k
2420 F20
100k
VCC = 5V
VREF = 5V
VIN = 5V
TA = 25°C
CIN = 0.01µF
CIN = 100pF
CIN = 1000pF
CIN = 0pF
25
LTC2420
APPLICATIO S I FOR ATIO
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node V
REF
is small (C
VREF
< 0.01µF), the reference input
can tolerate large external resistances without reduction
in INL, see Figure 25. If the external capacitance is large
(C
VREF
> 0.01µF), the linearity will be degraded by
0.015ppm/Ω independent of capacitance at V
REF
, see
Figure 26.
In addition to the dynamic reference current, the V
REF
ESD
protection diodes have a temperature dependent leakage
current. This leakage current, nominally 1nA (±10nA max),
results in a fixed full-scale shift of 10µV for a 10k source
resistance.
ANTIALIASING
One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2420 significantly
simplifies antialiasing filter requirements.
The digital filter provides very high rejection except at
integer multiples of the modulator sampling frequency
(f
S
), see Figure 27. The modulator sampling frequency is
256 • F
O
, where F
O
is the notch frequency (typically 50Hz
or 60Hz). The bandwidth of signals not rejected by the
digital filter is narrow (≈0.2%) compared to the bandwidth
of the frequencies rejected.
RESISTANCE AT V
REF
(Ω)
0
40
50
60
600 800
2420 F23
30
20
200 400 1000
10
0
–10
FULL-SCALE ERROR (ppm)
C
VREF
= 22µF
C
VREF
= 10µF
C
VREF
= 1µF
C
VREF
= 0.1µF
C
VREF
= 0.01µF
C
VREF
= 0.001µF
V
CC
= 5V
V
REF
= 5V
V
IN
= 5V
T
A
= 25°C
RESISTANCE AT V
REF
(Ω)
1
300
400
500
1k 10k
2420 F24
200
100
10 100 100k
0
–100
–200
VOLTAGE
V
CC
= 5V
V
REF
= 5V
V
IN
= 5V
T
A
= 25°C
C
VREF
= 0.01µF
C
VREF
= 100pF
C
VREF
= 1000pF
C
VREF
= 0pF
RESISTANCE AT V
REF
(Ω)
1
30
40
50
1k 10k
2420 F25
20
10
10 100 100k
0
–10
–20
INL ERROR (ppm)
V
CC
= 5V
V
REF
= 5V
T
A
= 25°C
C
VREF
= 0.01µF
C
VREF
= 1000pF
C
VREF
= 0pF
C
VREF
= 100pF
RESISTANCE AT V
REF
(Ω)
0
6
8
10
600 800
2420 F26
4
2
–2
–4
–6
–8
–10 200 400 1000
0
INL ERROR (ppm)
C
VREF
= 22µF
C
VREF
= 10µF
C
VREF
= 1µF
C
VREF
= 0.1µF
C
VREF
= 0.01µF
C
VREF
= 0.001µF
V
CC
= 5V
V
REF
= 5V
T
A
= 25°C
Figure 23. Full-Scale Error vs RVREF (Large C)
Figure 24. Full-Scale Error vs RVREF (Small C)
Figure 25. INL Error vs RVREF (Small C)
Figure 26. INL Error vs RVREF (Large C)
26
LTC2420
APPLICATIO S I FOR ATIO
WUUU
As a result of the oversampling ratio (256) and the digital
filter, minimal (if any) antialias filtering is required in front
of the LTC2420. If passive RC components are placed in
front of the LTC2420 the input dynamic current should be
considered (see Input Current section). In cases where
large effective RC time constants are used, an external
buffer amplifier may be required to minimize the effects of
input dynamic current.
The modulator contained within the LTC2420 can handle
large-signal level perturbations without saturating. Signal
levels up to 40% of V
REF
do not saturate the analog modu-
lator. These signals are limited by the input ESD protection
to 300mV below ground and 300mV above V
CC
.
Operation at Higher Data Output Rates
The LTC2420 typically operates with an internal oscillator
of 153.6kHz. This corresponds to a notch frequency of
60Hz and an output rate of 7.5 samples/second. The
internal oscillator is enabled if the F
O
pin is logic LOW
(logic HIGH for a 50Hz notch). It is possible to drive the F
O
pin with an external oscillator for higher data output rates.
As shown in Figure 28, an external clock of 2.048MHz
applied to the F
O
pin results in a notch frequency of 800Hz
with a data output rate of 100 samples/second.
Figure 29 shows the total unadjusted error (Offset Error +
Full-Scale Error + INL + DNL) as a function of the output
data rate with a 5V reference. The relationship between the
output data rate (ODR) and the frequency applied to the F
O
pin (F
O
) is:
ODR = F
O
/20480
For output data rates up to 50 samples/second, the total
unadjusted error (TUE) is better than 16 bits, and better
than 12 bits at 100 samples/second. As shown in Figure
30, for output data rates of 100 samples/second, the TUE
is better than 15 bits for V
REF
below 2.5V. Figure 31 shows
an unaveraged total unadjusted error for the LTC2420 op-
erating at 100 samples/second with V
REF
= 2.5V. Figure 32
shows the same device operating with a 5V reference and
an output data rate of 7.5 samples/second.
At 100 samples/second, the LTC2420 can be used to
capture transient data. This is useful for monitoring set-
tling or auto gain ranging in a system. The LTC2420 can
monitor signals at an output rate of 100 samples/second.
INPUT FREQUENCY
0
–60
–40
0
2420 F27
–80
–100
f
S
/2 f
S
–120
–140
–20
REJECTION (dB)
Figure 27. Sinc4 Filter Rejection
F
O
SCK
SDO
CS
V
CC
V
REF
V
IN
GND
8
7
6
5
1
2
3
4
LTC2420
800Hz NOTCH (100 SAMPLES/SECOND)
60Hz NOTCH (7.5 SAMPLES/SECOND)
EXTERNAL 2.048MHz CLOCK SOURCE
INTERNAL 153.6kHz OSCILLATOR
2420 F28
Figure 28. Selectable 100 Samples/Second Turbo Mode
OUTPUT RATE (SAMPLES/SEC)
0
TOTAL UNADJUSTED ERROR (ppm)
96
128
160
12 BITS
13 BITS
14 BITS
16 BITS
2420 F29
64
32
050 100
192
224
256 V
REF
= 5V
150
Figure 29. Total Error vs Output Rate (VREF = 5V)
27
LTC2420
Figure 31. Total Unadjusted Error at
100 Samples/Second (No Averaging) Figure 32. Total Unadjusted Error at
7.5 Samples/Second (No Averaging)
Figure 30. Total Error vs VREF (Output Rate = 100sps)
APPLICATIO S I FOR ATIO
WUUU
REFERENCE VOLTAGE (V)
1.0
TOTAL UNADJUSTED ERROR (ppm)
128
192
5.0
2420 F30
64
02.0 3.0 4.0
1.5 2.5 3.5 4.5
256
96
160
32
224
OUTPUT RATE = 100sps 12 BITS
13 BITS
14 BITS
15 BITS
INPUT VOLTAGE (V)
0
–40
TOTAL UNADJUSTED ERROR (ppm)
–30
–25
–20
–15
–10
–5
2420 F31
0
5
10
–35
2.5
VCC = 5V
VREF = 2.5V
INPUT VOLTAGE (V)
0
TOTAL UNADJUSTED ERROR (ppm)
–2
0
2
5
2420 F32
–4
–6
–10
–8
6
4
V
CC
= 5V
V
REF
= 5V
After acquiring 100 samples/second data the F
O
pin may
be driven LOW enabling 60Hz rejection to 110dB and the
highest possible DC accuracy. The no latency architecture
of the LTC2420 allows consecutive readings (one at 100
samples/second the next at 7.5 samples/second) without
interaction between the two readings.
As shown in Figure 33, the LTC2420 can capture transient
data with 90dB of dynamic range (with a 300mV
P-P
input
signal at 2Hz). The exceptional DC performance of the
LTC2420 enables signals to be digitized independent of a
large DC offset. Figures 34a and 34b show the dynamic
performance with a 15Hz signal superimposed on a 2V DC
level. The same signal with no DC level is shown in Figures
34c and 34d.
28
LTC2420
33a. Digitized Waveform 33b. Output FFT
Figure 33. Transient Signal Acquisiton
34a. Digitized Waveform with 2V DC Offset 34b. FFT Waveform with 2V DC Offset
34c. Digitized Waveform with No Offset
Figure 34. Using the LTC2420’s High Accuracy Wide Dynamic Range to Digitize
a 300mVP-P 15Hz Waveform with a Large DC Offset (VCC = 5V, VREF = 5V)
34d. FFT Waveform with No Offset
APPLICATIO S I FOR ATIO
WUUU
TIME
ADC OUTPUT (NORMALIZED TO VOLTS)
0
0.05
0.10
–0.05
–0.10
–0.20
–0.15
0.20 500ms
0.15
f
IN
= 2Hz
2420 F33a
FREQUENCY (Hz)
MAGNITUDE (dB)
–60
–40
–20
0
–80
–100
–120
2Hz
100sps
0V OFFSET
2420 F33b
TIME
ADC OUTPUT (NORMALIZED TO VOLTS)
2.00
2.05
2.10
2420 F34a
1.95
1.90
1.80
1.85
2.20
2.15
V
IN
= 300mV
P-P
+ 2V DC
FREQUENCY (Hz)
MAGNITUDE (dB)
–60
–40
–20
0
2420 F34b
–80
–100
–120
15Hz
100sps
2V OFFSET
TIME
ADC OUTPUT (NORMALIZED TO VOLTS)
0.00
0.05
0.10
2420 F34c
–0.05
–0.10
–0.20
–0.15
0.20
0.15
V
IN
= 300mV
P-P
+ 0V DC
FREQUENCY (Hz)
MAGNITUDE (dB)
–60
–40
–20
0
2420 F34d
–80
–100
–120
15Hz
100sps
0V OFFSET
29
LTC2420
SYNCHRONIZATION OF MULTIPLE LTC2420s
Since the LTC2420’s absolute accuracy (total unadjusted
error) is 10ppm, applications utilizing multiple matched
ADCs are possible.
Simultaneous Sampling with Two LTC2420s
One such application is synchronizing multiple LTC2420s,
see Figure 35. The start of conversion is synchronized to
the rising edge of CS. In order to synchronize multiple
LTC2420s, CS is a common input to all the ADCs.
To prevent the converters from autostarting a new con-
version at the end of data output read, 23 or fewer SCK
clock signals are applied to the LTC2420 instead of 24 (the
24th falling edge would start a conversion). The exact
timing and frequency for the SCK signal is not critical
since it is only shifting out the data. In this case, two
LTC2420’s simultaneously start and end their conversion
cycles under the external control of CS.
TYPICAL APPLICATIO S
U
Increasing the Output Rate Using Multiple LTC2420s
A second application uses multiple LTC2420s to increase
the effective output rate by 4×, see Figure 36. In this case,
four LTC2420s are interleaved under the control of sepa-
rate CS signals. This increases the effective output rate
from 7.5Hz to 30Hz (up to a maximum of 400Hz). Addi-
tionally, the one-shot output spectrum is unfolded allow-
ing further digital signal processing of the conversion
results. SCK and SDO may be common to all four LTC2420s.
The four CS rising edges equally divide one LTC2420
conversion cycle (7.5Hz for 60Hz notch frequency). In
order to synchronize the start of conversion to CS, 23 or
less SCK clock pulses must be applied to each ADC.
Both the synchronous and 4× output rate applications use
the external serial clock and single cycle operation with
reduced data output length (see Serial Interface Timing
Modes section and Figure 7). An external oscillator clock
is applied commonly to the F
O
pin of each LTC2420 in
order to synchronize the sampling times. Both circuits
may be extended to include more LTC2420s.
23 OR LESS CLOCK CYCLES
CS
SCK1
SCK2
2420 F35
SDO1
SDO2
23 OR LESS CLOCK CYCLES
LTC2420
#1
V
CC
V
REF
V
IN
GND
F
O
SCK
SDO
CS
SCK2
SCK1
CS
SDO1
SDO2
LTC2420
#2
V
CC
V
REF
V
IN
GND
F
O
SCK
SDO
CS
µCONTROLLER
EXTERNAL OSCILLATOR
(153,600HZ)
V
REF
(0.1V TO V
CC
)
Figure 35. Synchronous Conversion—Extendable
30
LTC2420
TYPICAL APPLICATIO S
U
CS1
CS2
CS3
2420 F36
CS4
SCK
23 OR LESS
CLOCK PULSES
SDO
LTC2420
#1
VCC
VREF
VIN
GND
FO
SCK
SDO
CS
SCK
SDO
CS1
CS2
CS3
CS4
LTC2420
#2
VCC
VREF
VIN
GND
FO
SCK
SDO
CS
LTC2420
#3
VCC
VREF
VIN
GND
FO
SCK
SDO
CS
LTC2420
#4
VCC
VREF
VIN
GND
FO
SCK
SDO
CS
µCONTROLLER
EXTERNAL OSCILLATOR
(153,600HZ)
VREF
(0.1V TO VCC)
Figure 36. 4× Output Rate LTC2420 System
31
LTC2420
TYPICAL APPLICATIO S
U
Single-Chip Instrumentation Amplifier
for the LTC2420
The circuit in Figure 37 is a simple solution for processing
differential signals in pressure transducer, weigh scale or
strain gauge applications that can operate on a supply
voltage range of ±5V to ±15V. The circuit uses an LT
®
1920
single-chip instrumentation amplifier to perform a differ-
ential to single-ended conversion. The amplifier’s output
voltage is applied to the LTC2420’s input and converted to
a digital value with an overall accuracy exceeding 17 bits
(0.0008%). Key circuit performance results are shown in
Table 5.
The practical gain range for this topology as shown is from
5 to 100 because the LTC2420’s wide dynamic range
makes gains below 5 virtually unnecessary, whereas gains
up to 100 significantly reduce the input referred noise.
The optional passive RC lowpass filter between the
amplifier’s output and the LTC2420’s input attenuates
high frequency noise and its effects. Typically, the filter
reduces the magnitude of averaged noise by 30% and
improves resolution by 0.5 bit without compromising
linearity. Resistor R2 performs two functions: it isolates
C1 from the LTC2420’s input and limits the LTC2420’s
input current should its input voltage drop below –300mV
or swing above V
CC
+ 300mV.
The LT1920 is the choice for applications where low cost
is important. For applications where more precision is
required, the LT1167 is a pin-to-pin alternative choice with
a lower offset voltage, lower input bias current and higher
gain accuracy than the LT1920. The LT1920’s maximum
total input-referred offset (V
OST
) is 135µV for a gain of
100. At the same gain, the LT1167’s V
OST
is 63µV. At gains
of 10 or 100, the LT1920’s maximum gain error is 0.3%
and its maximum gain nonlinearity is 30ppm. At the same
gains, the LT1167’s maximum gain error is 0.1% and its
maximum gain nonlinearity is 15ppm. Table 6 summa-
rizes the performance of Figure 37’s circuit using the
LT1167.
Figure 37. The LT1920 is a Simple Solution That Converts a Differential Input
to a Ground Referred Single-Ended Signal for the LTC2420
V
S+
V
S–
7
2
1
8
34
6
V
IN+
V
IN–
R
G
R
G
**
DIFFERENTIAL
INPUT R
G
3
2
1
††
*OPTIONAL—SEE TEXT
**R
G
= 49.4k/(A
V
– 1): USE 5.49k FOR A
V
= 10; 499Ω FOR A
V
= 100
†
USE SHORT LEAD LENGTHS
†48
2420 F37
5
6
7
CHIP SELECT
SERIAL DATA OUT
SERIAL CLOCK
CS
SDO
SCK
0.1µF
0.1µF5V
R1*
47Ω
C1*
1µF
SINGLE POINT
“STAR” GROUND
R2*
10k
0.1µF
V
IN
V
REF
V
REFIN
V
CC
GND
LTC2420
F
O
LT1920
32
LTC2420
Table 6. Typical Performance of the LTC2420 ADC When Used with the
LT1167 Instrumentation Amplifiers in Figure 34’s Differential Digitizing Circuit
V
S
= ±5V V
S
= ±15V
PARAMETER A
V
= 10 A
V
= 100 A
V
= 10 A
V
= 100 TOTAL (UNITS)
Differential Input Voltage Range – 30 to 400 –3 to 40 –30 to 500 –3 to 50 mV
Zero Error –94 –1590 –110 –1470 µV
Maximum Input Current 0.5 nA
Nonlinearity ±4.1 ±4.4 ±4.1 ±3.7 ppm
Noise (Without Averaging) 1.4* 0.19* 1.5* 0.18* µV
RMS
Noise (Averaged 64 Readings) 0.18* 0.02* 0.19* 0.02* µV
RMS
Resolution (with Averaged Readings) 21.4 21.0 21.3 21.1 Bits
Overall Accuracy (Uncalibrated) 18.2 18.1 18.2 19.4 Bits
Common Mode Rejection Ratio ≥120 dB
Common Mode Range 2/–1.5** 2.2/–1.7** 11.5/–11** 11.7/–11.2** V
*Input referred noise for the respective gain. **Typical values based on single lab tested sample of each amplifier.
TYPICAL APPLICATIO S
U
Table 5. Typical Performance of the LTC2420 ADC When Used with the
LT1920 Instrumentation Amplifiers in Figure 34’s Differential Digitizing Circuit
V
S
= ±5V V
S
= ±15V
PARAMETER A
V
= 10 A
V
= 100 A
V
= 10 A
V
= 100 TOTAL (UNITS)
Differential Input Voltage Range – 30 to 400 –3 to 40 –30 to 500 –3 to 50 mV
Zero Error –160 –2650 –213 –2625 µV
Maximum Input Current 2.0 nA
Nonlinearity ±8.2 ±7.4 ±6.5 ±6.1 ppm
Noise (Without Averaging) 1.8* 0.25* 1.5* 0.27* µV
RMS
Noise (Averaged 64 Readings) 0.2* 0.03* 0.19* 0.03* µV
RMS
Resolution (with Averaged Readings) 21 20.6 21.3 20.5 Bits
Overall Accuracy (Uncalibrated) 17.2 17.3 17.5 18.2 Bits
Common Mode Rejection Ratio ≥120 dB
Common Mode Range 2/–1.5** 2.2/–1.7** 11.5/–11** 11.7/–11.2** V
*Input referred noise for the respective gain. **Typical values based on single lab tested sample of each amplifier.
33
LTC2420
TYPICAL APPLICATIO S
U
Using a Low Power Precision Reference
The circuit in Figure 38 shows the connections and by-
passing for an LT1461-2.5 as a 2.5V reference. The
LT1461 is a bandgap reference capable of 3ppm/°C tem-
perature stability yet consumes only 45µA of current. The
1k resistor between the reference and the ADC reduces the
transient load changes associated with sampling and
produces optimal results. This reference will not impact
the noise level of the LTC2420 if signals are less than 60%
full scale, and only marginally increases noise approach-
ing full scale. Even lower power references can be used if
only the lower end of the LTC2420 input range is required.
A Differential to Single-Ended Analog Front End
Figure 39 shows the LT1167 as a means of sensing
differential signals. The noise performance of the LT1167
is such that for gains less than 200, the noise floor of the
LTC2420 remains the dominant noise source. At the point
where the noise of the amplifier begins to dominate, the
input referred noise is essentially that of the instrumenta-
tion amplifier. The linearity of the instrumentation ampli-
fier does, however, degrade at higher gains. As a result, if
the full linearity of the LTC2420 is desired, gain in the
instrumentation amplifier should be limited to less than
100, possibly requiring averaging multiple samples to
extend the resolution below the noise floor. The noise level
of the LT1167 at gains greater than 100 is on the order of
50nV
RMS
, although, 1/f noise and temperature effects may
degrade this below 0.1Hz. The introduction of a filter
between the amplifier and the LTC2420 may improve
noise levels under some circumstances by reducing noise
bandwidth. Note that temperature offset drift effects enve-
lope detection in the input of the LT1167 if exposed to RFI,
thermocouple voltages in connectors, resistors and sol-
dered junctions can all compromise results, appearing as
drift or noise. Turbulent airflow over this circuitry should
be avoided.
+
LT1461-2.5
GND
IN
2420 F38
10µF
16V
TANT
TO
LTC2420
REF
OUT5V 1k
0.1µF
CER
+
–
+
LT1167
3.5k
×4
1
2
RG
5V
8
351µF
22Ω5k
1
10µF
2
3
AV =
RECOMMENDED RG: 500Ω, 0.1%
5ppm/°C
+ 1
49.4kΩ
RG
4
OPTIONAL
6
2428 F39
–5V
5V
LTC2420
Figure 38. Low Power Reference
Figure 39. A Differential to Single-Ended Analog Front End
34
LTC2420
TYPICAL APPLICATIO S
U
U1-A U1-B U1-C
U1-F
U1-E
TO LTC2420
F
O
PIN
U1-D
12
5pF
5k
1k
2N3904
10k
47k
1k
47k
10pF
100smps, F
O
= 2.048MHz
30smps, F
O
= 614.4kHz
U1: 74HC14 OR EQUIVALENT
270pF
345 6
12 13 HALT
11 10
9 8
2420 F40
Figure 40. 2.048MHz Oscillator for 100sps Output Rate
2.048MHz Oscillator for 100sps Output Ratio
The oscillator circuit shown in Figure 40 can be used to
drive the FO pin, boosting the conversion rate of the
LTC2420 for applications that do not require a notch at
50Hz or 60Hz. This oscillator is not sensitive to hysteresis
voltage of a Schmitt trigger device as are simpler
relaxation oscillators using the 74HC14 or similar de-
vices. The circuit can be tuned over a 3:1 range with only
one resistor and can be gated. The use of transmission
gates could be used to shift the frequency in order to
provide setable conversion rates.
35
LTC2420
PACKAGE I FOR ATIO
UU
W
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.016 – 0.050
(0.406 – 1.270)
0.010 – 0.020
(0.254 – 0.508)× 45°
0°– 8° TYP
0.008 – 0.010
(0.203 – 0.254)
SO8 1298
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
TYP
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
1234
0.150 – 0.157**
(3.810 – 3.988)
8765
0.189 – 0.197*
(4.801 – 5.004)
0.228 – 0.244
(5.791 – 6.197)
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
36
LTC2420
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1019 Precision Bandgap Voltage Reference, 2.5V, 5V 3ppm/°C Drift, 0.05% Max
LT1025 Micropower Thermocouple Cold Junction Compensator 0.5°C Initial Accuracy, 80µA Supply Current
LTC1043 Dual Precision Instrumentation Switched Capacitor Precise Charge, Balanced Switching, Low Power
Building Block
LTC1050 Precision Chopper Stabilized Op Amp No External Components 5µV Offset, 1.6µV
P-P
Noise
LT1236A-5 Precision Bandgap Voltage Reference, 5V 0.05% Max, 5ppm/°C Drift
LTC1391 8-Channel Multiplexer Low R
ON
: 45Ω, Low Charge Injection, Serial Interface
LT1460 Micropower Series Voltage Reference 0.075% Max, 10ppm/°C Max Drift, 2.5V, 5V and 10V Versions
LTC2400 24-Bit µPower, No Latency ∆Σ ADC in SO-8 4ppm INL, 10ppm TUE, 200µA, Pin Compatible with LTC2420
LTC2401/LTC2402 1-/2-Channel, 24-Bit No Latency ∆Σ ADCs 24 Bits in MSOP Package
LTC2404/LTC2408 4-/8-Channel, 24-Bit No Latency ∆Σ ADC 4ppm INL, 10ppm TUE, 200µA
LTC2410 24-Bit No Latency ∆Σ ADC with Differential Inputs 800nV Noise, Differential Reference, 2.7V to 5.5V Operation
LTC2411 24-Bit No Latency ∆Σ ADC with Differential Inputs/Reference 1.6µV Noise, Fully Differential, 10-Lead MSOP Package
LTC2413 24-Bit No Latency ∆Σ ADC Simultaneous 50Hz to 60Hz Rejection 0.16ppm Noise
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2420f LT/LCG 1000 4K • PRINTED IN USA
L INE AR TE CHNO LOGY CO RPORATIO N 2000
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear-tech.com
TYPICAL APPLICATIO
U
The circuit shown in Figure 41 enables pseudodifferential
measurements of several bridge transducers and abso-
lute temperature measurement. The LTC1391 is an
8-to-1 analog multiplexer.
Consecutive readings are performed on each side of the
bridge by selecting the appropriate channel on the
LTC1391. Each output is digitized and the results digitally
subtracted to obtain the pseudodifferential result. Several
bridge transducers may be digitized in this manner.
In order to measure absolute temperature with a thermo-
couple, cold junction compensation must be performed.
Channel 6 measures the output of the thermocouple while
channel 7 measures the output of the cold junction sensor
(diode, thermistor, etc.). This enables digital cold junc-
tion compensation of the thermocouple output. The tem-
perature measurement may then be used to compensate
the temperature effects of the bridge transducers.
CH1
CH0
THERMOCOUPLE
THERMISTOR
CH3 OUT
GND
LTC1391 LTC2420
2420 F41
V
REF
V
IN
GND
V
CC
V
CC
F
O
SCK
SDO
CS
CH4
CH5
CH6
CH7
CH2
Figure 41. Pseudodifferential Multichannel Bridge Digitizer
and Digital Cold Junction Compensation
