2003-2011 Microchip Technology Inc. DS21796L-page 1
93AA76A/B/C, 93LC76A/B/C,
93C76A/B/C
Device Selection Table
Features:
• Low-Power CMOS Technology
• ORG Pin to Select Word Size for ‘76C’ Version
• 1024 x 8-bit Organization ‘A’ Devices (no ORG)
• 512 x 16-bit Organization ‘B’ Devices (no ORG)
• Program Enable Pin to Write-Protect the Entire
Array (‘76C’ version only)
• Self-Timed Erase/Write Cycles (including
Auto-Erase)
• Automatic ERAL Before WRAL
• Power-On/Off Data Protection Circuitry
• Industry Standard 3-Wire Serial I/O
• Device Status Signal (Ready/Busy)
• Sequential Read Function
• 1,000,000 Erase/Write Cycles
• Data Retention > 200 Years
• Pb-free and RoHS Compliant
• Temperature Ranges Supported:
Pin Function Table
Description:
The Microchip Technology Inc. 93XX76A/B/C devices
are 8Kbit, low-voltage, serial Electrically Erasable
PROMs (EEPROM). Word-selectable devices such as
the 93XX76C are dependent upon external logic levels
driving the ORG pin to set word size. In the SOT-23
package, the 93XX76A devices provide dedicated 8-bit
memory organization, while the 93XX76B devices
provide dedicated 16-bit memory organization. A
Program Enable (PE) pin allows the user to write-protect
the entire memory array. Advanced CMOS technology
makes these devices ideal for low-power, nonvolatile
memory applications. The 93XX Series is available in
standard packages including 8-lead PDIP and SOIC,
and advanced packaging including 8-lead MSOP, 6-lead
SOT-23, 8-lead 2x3 DFN/TDFN and 8-lead TSSOP. All
packages are Pb-free (Matte Tin) finish.
Package Types (not to scale)
Part Number VCC Range ORG Pin PE Pin Word Size Temp Ranges Packages
93AA76A 1.8-5.5 No No 8-bit I OT, SN
93AA76B 1.8-5-5 No No 16-bit I OT, SN
93LC76A 2.5-5.5 No No 8-bit I, E OT, SN
93LC76B 2.5-5.5 No No 16-bit I, E OT, SN
93C76A 4.5-5.5 No No 8-bit I, E OT, SN
93C76B 4.5-5.5 No No 16-bit I, E OT, SN
93AA76C 1.8-5.5 Yes Yes 8- or 16-bit I P, SN, ST, MS, MC, MN
93LC76C 2.5-5.5 Yes Yes 8- or 16-bit I, E P, SN, ST, MS, MC, MN
93C76C 4.5-5.5 Yes Yes 8- or 16-bit I, E P, SN, ST, MS, MC, MN
- Industrial (I) -40°C to +85°C
- Automotive (E) -40°C to +125°C
Name Function
CS Chip Select
CLK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
VSS Ground
PE Program Enable – 93XX76C only
ORG Memory Configuration – 93XX76C only
VCC Power Supply
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
V
CC
PE*
ORG*
V
SS
PDIP/SOIC
(P, SN)
TSSOP/MSOP
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
V
CC
PE
ORG
V
SS
(ST, MS)
SOT-23
DO
V
SS
DI
1
2
3
6
5
4
V
CC
CS
CLK
(OT)
DFN/TDFN
CS
CLK
DI
DO
PE
ORG
VSS
VCC
8
7
6
5
1
2
3
4
(MC, MN)
*93XX76C only
8K Microwire Compatible Serial EEPROM
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796L-page 2 2003-2011 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins 4kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
All parameters apply over the specified
ranges unless otherwise noted.
Industrial (I): TA = -40°C to +85°C, VCC = +1.8V to 5.5V
Automotive (E): T
A = -40°C to +125°C, VCC = +2.5V to 5.5V
Param.
No. Symbol Parameter Min Typ Max Units Conditions
D1 VIH1
VIH2
High-level input voltage 2.0
0.7 VCC
—
—
VCC +1
VCC +1
V
V
VCC 2.7V
VCC < 2.7V
D2 VIL1
VIL2
Low-level input voltage -0.3
-0.3
—
—
0.8
0.2 VCC
V
V
VCC 2.7V
VCC < 2.7V
D3 VOL1
VOL2
Low-level output voltage —
—
—
—
0.4
0.2
V
V
IOL = 2.1 mA, VCC = 4.5V
IOL = 100 A, VCC = 2.5V
D4 VOH1
VOH2
High-level output voltage 2.4
VCC - 0.2
—
—
—
—
V
V
IOH = -400 A, VCC = 4.5V
IOH = -100 A, VCC = 2.5V
D5 ILI Input leakage current — — ±1 AVIN = VSS or VCC
D6 ILO Output leakage current — — ±1 AVOUT = VSS or VCC
D7 CIN,
COUT
Pin capacitance (all inputs/
outputs)
——7 pFVIN/VOUT = 0V (Note 1)
T
A = 25°C, FCLK = 1 MHz
D8 ICC write Write current —
—
—
500
3
—
mA
A
FCLK = 3 MHz, VCC = 5.5V
FCLK = 2 MHz, VCC = 2.5V
D9 ICC read Read current —
—
—
—
—
100
1
500
—
mA
A
A
FCLK = 3 MHz, VCC = 5.5V
FCLK = 2 MHz, VCC = 3.0V
FCLK = 2 MHz, VCC = 2.5V
D10 ICCS Standby current —
—
—
—
1
5
A
A
I – Temp
E – Temp
CLK = CS = 0V
ORG = DI = PE = VSS or VCC
(Note 2) (Note 3)
D11 VPOR VCC voltage detect
—
—
1.5
3.8
—
—
V
V
(Note 1)
93AA76A/B/C, 93LC76A/B/C
93C76A/B/C
Note 1: This parameter is periodically sampled and not 100% tested.
2: ORG and PE pins not available on ‘A’ or ‘B’ versions.
3: Ready/Busy status must be cleared from DO; see Section 3.4 “Data Out (DO)”.
2003-2011 Microchip Technology Inc. DS21796L-page 3
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
TABLE 1-2: AC CHARACTERISTICS
All parameters apply over the specified
ranges unless otherwise noted.
Industrial (I): TA = -40°C to +85°C, VCC = +1.8V to 5.5V
Automotive (E): T
A = -40°C to +125°C, VCC = +2.5V to 5.5V
Param.
No. Symbol Parameter Min Max Units Conditions
A1 FCLK Clock frequency — 3
2
1
MHz
MHz
MHz
4.5V VCC < 5.5V
2.5V VCC < 4.5V
1.8V VCC < 2.5V
A2 TCKH Clock high time 200
250
450
—ns
ns
ns
4.5V VCC < 5.5V
2.5V VCC < 4.5V
1.8V VCC < 2.5V
A3 TCKL Clock low time 100
200
450
—ns
ns
ns
4.5V VCC < 5.5V
2.5V VCC < 4.5V
1.8V VCC < 2.5V
A4 TCSS Chip Select setup time 50
100
250
—ns
ns
ns
4.5V VCC < 5.5V
2.5V VCC < 4.5V
1.8V VCC < 2.5V
A5 TCSH Chip Select hold time 0 — ns 1.8V VCC < 5.5V
A6 TCSL Chip Select low time 250 — ns 1.8V VCC < 5.5V
A7 TDIS Data input setup time 50
100
250
—ns
ns
ns
4.5V VCC < 5.5V
2.5V VCC < 4.5V
1.8V VCC < 2.5V
A8 TDIH Data input hold time 50
100
250
—ns
ns
ns
4.5V VCC < 5.5V
2.5V VCC < 4.5V
1.8V VCC < 2.5V
A9 TPD Data output delay time — 100
250
400
ns
ns
ns
4.5V VCC < 5.5V, CL = 100 pF
2.5V VCC < 4.5V, CL = 100 pF
1.8V VCC < 2.5V, CL = 100 pF
A10 TCZ Data output disable time — 100
200
ns
ns
4.5V VCC < 5.5V, (Note 1)
1.8V VCC < 4.5V, (Note 1)
A11 TSV Status valid time — 200
300
500
ns
ns
ns
4.5V VCC < 5.5V, CL = 100 pF
2.5V VCC < 4.5V, CL = 100 pF
1.8V VCC < 2.5V, CL = 100 pF
A12 TWC Program cycle time — 5 ms Erase/Write mode (AA and LC
versions)
A13 TWC — 2 ms Erase/Write mode
(93C versions)
A14 TEC — 6 ms ERAL mode, 4.5V VCC 5.5V
A15 TWL — 15 ms WRAL mode, 4.5V VCC 5.5V
A16 — Endurance 1M — cycles 25°C, VCC = 5.0V, (Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This application is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which may be obtained from Microchip’s web
site at www.microchip.com.
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796L-page 4 2003-2011 Microchip Technology Inc.
FIGURE 1-1: SYNCHRONOUS DATA TIMING
TABLE 1-3: INSTRUCTION SET FOR X16 ORGANIZATION (93XX76B OR 93XX76C WITH ORG = 1)
TABLE 1-4: INSTRUCTION SET FOR X8 ORGANIZATION (93XX76A OR 93XX76C WITH ORG = 0)
Instruction SB Opcode Address Data In Data Out Req. CLK
Cycles
READ 1 10 X A8A7A6A5A4A3A2A1A0 — D15-D0 29
EWEN 1 00 11xxxxxxxx —High-Z 13
ERASE 1 11 X A8A7A6A5A4A3A2A1A0 — (RDY/
BSY)13
ERAL 1 00 10XXXXXXXX — (RDY/BSY)13
WRITE 1 01 X A8A7A6A5A4A3A2A1A0 D15-D0 (RDY/
BSY)29
WRAL 1 00 01xxxxxxxx D15-D0 (RDY/BSY)29
EWDS 1 00 00xxxxxxxx —High-Z 13
Instruction SB Opcode Address Data In Data Out Req. CLK
Cycles
READ 1 10 X A9A8A7A6A5A4A3A2A1A0 — D7-D0 22
EWEN 1 00 11x x xxxxxxx — High-Z 14
ERASE 1 11 X A9A8A7A6A5A4A3A2A1A0 — (RDY/
BSY)14
ERAL 1 00 10x x xxxxxxx — (RDY/BSY)14
WRITE 1 01 X A9A8A7A6A5A4A3A2A1A0 D7-D0 (RDY/
BSY)22
WRAL 1 00 01x x xxxxxxx D7-D0 (RDY/BSY)22
EWDS 1 00 00x x xxxxxxx — High-Z 14
CS VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
CLK
DI
DO
(Read)
DO
(Program)
TCSS
TDIS
TCKH TCKL
TDIH
TPD
TCSH
TPD
TCZ
Status Valid
TSV
TCZ
Note: TSV is relative to CS.
2003-2011 Microchip Technology Inc. DS21796L-page 5
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
2.0 FUNCTIONAL DESCRIPTION
When the ORG pin (93XX76C) is connected to VCC,
the (x16) organization is selected. When it is connected
to ground, the (x8) organization is selected. Instruc-
tions, addresses and write data are clocked into the DI
pin on the rising edge of the clock (CLK). The DO pin is
normally held in a High-Z state except when reading
data from the device, or when checking the Ready/
Busy status during a programming operation. The
Ready/Busy status can be verified during an Erase/
Write operation by polling the DO pin; DO low indicates
that programming is still in progress, while DO high
indicates the device is ready. DO will enter the High-Z
state on the falling edge of CS.
2.1 Start Condition
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device
operation (Read, Write, Erase, EWEN, EWDS, ERAL
or WRAL). As soon as CS is high, the device is no
longer in Standby mode.
An instruction following a Start condition will only be
executed if the required opcode, address and data bits
for any particular instruction are clocked in.
2.2 Data In/Data Out (DI/DO)
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation if A0 is a logic high-
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of the
driver, the higher the voltage at the Data Out pin. In
order to limit this current, a resistor should be
connected between DI and DO.
2.3 Data Protection
All modes of operation are inhibited when VCC is below
a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices
or 3.8V for ‘93C’ devices.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
After power-up the device is automatically in the EWDS
mode. Therefore, an EWEN instruction must be
performed before the initial ERASE or WRITE instruction
can be executed.
Block Diagram
Note: When preparing to transmit an instruction,
either the CLK or DI signal levels must be
at a logic low as CS is toggled active high.
Note: For added protection, an EWDS command
should be performed after every write
operation and an external 10 k pull-down
protection resistor should be added to the
CS pin.
Note: To prevent accidental writes to the array in
the 93XX76C devices, set the PE pin to a
logic low.
Memory
Array
Data Register
Mode
Decode
Logic
Clock
Register
Address
Decoder
Address
Counter
Output
Buffer
DO
DI
ORG*
CS
CLK
VCC VSS
*ORG and PE inputs are not available on
PE*
A/B devices.
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796L-page 6 2003-2011 Microchip Technology Inc.
2.4 Erase
The ERASE instruction forces all data bits of the
specified address to the logical ‘1’ state. The rising
edge of CLK before the last address bit initiates the
write cycle.
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
FIGURE 2-1: ERASE TIMING
2.5 Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle
is identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed. The
rising edge of CLK before the last data bit initiates the
write cycle. Clocking of the CLK pin is not necessary
after the device has entered the ERAL cycle.
The DO pin indicates the Ready/Busy status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL).
VCC must be 4.5V for proper operation of ERAL.
FIGURE 2-2: ERAL TIMING
Note: After the Erase cycle is complete, issuing
a Start bit and then taking CS low will clear
the Ready/Busy status from DO.
CS
CLK
DI
DO
TCSL
Check Status
111ANAN-1 AN-2 ••• A0
TSV TCZ
Busy Ready
High-Z
TWC
High-Z
Note: After the ERAL command is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
CS
CLK
DI
DO
TCSL
Check Status
100 10x
••• x
TSV TCZ
Busy Ready
High-Z
TEC
High-Z
2003-2011 Microchip Technology Inc. DS21796L-page 7
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
2.6 Erase/Write Disable and Enable
(EWDS/EWEN)
The 93XX76A/B/C powers up in the Erase/Write
Disable (EWDS) state. All programming modes must be
preceded by an Erase/Write Enable (EWEN) instruction.
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or VCC is removed from the device.
To protect against accidental data disturbance, the
EWDS instruction can be used to disable all erase/write
functions and should follow all programming opera-
tions. Execution of a READ instruction is independent of
both the EWEN and EWDS instructions.
FIGURE 2-3: EWDS TIMING
FIGURE 2-4: EWEN TIMING
2.7 Read
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit (If ORG pin is low or A-version
devices) or 16-bit (If ORG pin is high or B-version
devices) output string.
The output data bits will toggle on the rising edge of the
CLK and are stable after the specified time delay (TPD).
Sequential read is possible when CS is held high. The
memory data will automatically cycle to the next register
and output sequentially.
FIGURE 2-5: READ TIMING
CS
CLK
DI 100 00x ••• x
TCSL
1x
CS
CLK
DI 00 1 1x
TCSL
•••
CS
CLK
DI
DO
110
AN••• A0
High-Z 0Dx ••• D0 Dx ••• D0 •••
Dx D0
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796L-page 8 2003-2011 Microchip Technology Inc.
2.8 Write
The WRITE instruction is followed by 8 bits (if ORG is
low or A-version devices) or 16 bits (if ORG pin is high
or B-version devices) of data which are written into the
specified address. The self-timed auto-erase and
programming cycle is initiated by the rising edge of CLK
on the last data bit.
The DO pin indicates the Ready/Busy status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been written with
the data specified and the device is ready for another
instruction.
FIGURE 2-6: WRITE TIMING
Note: The write sequence requires a logic high
signal on the PE pin prior to the rising
edge of the last data bit.
Note: After the Write cycle is complete, issuing a
Start bit and then taking CS low will clear
the Ready/Busy status from DO.
CS
CLK
DI
DO
101AN••• A0 Dx ••• D0
Busy Ready High-Z
High-Z
TWC
TCSL
TCZ
TSV
2003-2011 Microchip Technology Inc. DS21796L-page 9
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
2.9 Write All (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
The self-timed auto-erase and programming cycle is
initiated by the rising edge of CLK on the last data bit.
Clocking of the CLK pin is not necessary after the
device has entered the WRAL cycle. The WRAL
command includes an automatic ERAL cycle for the
device, so the WRAL instruction does not require an
ERAL instruction. However, the chip must be in the
EWEN status.
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
VCC must be 4.5V for proper operation of WRAL.
FIGURE 2-7: WRAL TIMING
Note: The write sequence requires a logic high
signal on the PE pin prior to the rising
edge of the last data bit.
Note: After the Write All cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
CS
CLK
DI
DO
HIGH-Z
10001 x
••• xDx ••• D0
High-Z Busy Ready
TWL
TCSL
TSV TCZ
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796L-page 10 2003-2011 Microchip Technology Inc.
3.0 PIN DESCRIPTIONS
TABLE 3-1: PIN DESCRIPTIONS
3.1 Chip Select (CS)
A high level selects the device; a low level deselects
the device and forces it into Standby mode. However, a
programming cycle that is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into Standby mode as soon as the
programming cycle is completed.
CS must be low for 250 ns minimum (T
CSL) between
consecutive instructions. If CS is low, the internal
control logic is held in a Reset status.
3.2 Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93XX series
device. Opcodes, address and data bits are clocked in
on the positive edge of CLK. Data bits are also clocked
out on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low-level) and can be continued
anytime with respect to Clock High Time (T
CKH) and
Clock Low Time (TCKL). This gives the controlling
master freedom in preparing opcode, address and
data.
CLK is a “don’t care” if CS is low (device deselected). If
CS is high, but the Start condition has not been
detected (DI = 0), any number of clock cycles can be
received by the device without changing its status (i.e.,
waiting for a Start condition).
CLK cycles are not required during the self-timed write
(i.e., auto erase/write) cycle.
After detection of a Start condition the specified number
of clock cycles (respectively, low-to-high transitions of
CLK) must be provided. These clock cycles are
required to clock in all required opcode, address and
data bits before an instruction is executed. CLK and DI
then become “don’t care” inputs waiting for a new Start
condition to be detected.
3.3 Data In (DI)
Data In (DI) is used to clock in a Start bit, opcode,
address and data synchronously with the CLK input.
3.4 Data Out (DO)
Data Out (DO) is used in the Read mode to output data
synchronously with the CLK input (TPD after the
positive edge of CLK).
This pin also provides Ready/Busy status information
during erase and write cycles. Ready/Busy status infor-
mation is available on the DO pin if CS is brought high
after being low for minimum Chip Select Low Time
(T
CSL) and an erase or write operation has been
initiated.
The Status signal is not available on DO, if CS is held
low during the entire erase or write cycle. In this case,
DO is in the High-Z mode. If status is checked after the
erase/write cycle, the data line will be high to indicate
the device is ready.
3.5 Organization (ORG)
When the ORG pin is connected to VCC or Logic HI, the
(x16) memory organization is selected. When the ORG
pin is tied to VSS or Logic LO, the (x8) memory
organization is selected. For proper operation, ORG
must be tied to a valid logic level.
93XX76A devices are always (x8) organization and
93XX76B devices are always (x16) organization.
Name PDIP SOIC TSSOP MSOP DFN(1) TDFN(1) SOT-23 Function
CS 1 1 1 1 1 1 5 Chip Select
CLK 2 2 2 2 2 2 4 Serial Clock
DI 3 3 3 3 3 3 3 Data In
DO 4 4 4 4 4 4 1 Data Out
VSS 5555552Ground
ORG 6 6 6 6 6 6 — Organization/93XX76C
only
PE 7 7 7 7 7 7 — Program Enable/
93XX76C only
VCC 8 8 8 8 8 8 6 Power Supply
Note 1: The exposed pad on the DFN/TDFN package may be connected to VSS or left floating.
Note: After a programming cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
2003-2011 Microchip Technology Inc. DS21796L-page 11
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
3.6 Program Enable (PE)
This pin allows the user to enable or disable the ability
to write data to the memory array. If the PE pin is tied
to VCC, the device can be programmed. If the PE pin is
tied to VSS, programming will be inhibited. This pin
cannot be floated – it must be tied to VCC or VSS. PE is
not available on 93XX76A or 93XX76B. On those
devices, programming is always enabled.
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796L-page 12 2003-2011 Microchip Technology Inc.
4.0 PACKAGING INFORMATION
4.1 Package Marking Information
Example:
6-Lead SOT-23
8-Lead MSOP (150 mil) Example:
XXXXXXT
YWWNNN
3L76CI
5281L7
XXNN 4EL7
T/XXXNNN
XXXXXXXX
YYWW
8-Lead PDIP
8-Lead SOIC
XXXXYYWW
XXXXXXXT
NNN
XXXX
TYWW
8-Lead TSSOP
NNN
I/P 1L7
93LC76C
0528
Example:
Example:
SN 0528
93LC76CI
1L7
1L7
L76C
I528
Example:
8-Lead 2x3 DFN Example:
3B4
528
L7
XXX
YWW
NN
3
e
3
e
8-Lead 2x3 TDFN Example:
EB4
528
L7
XXX
YWW
NN
2003-2011 Microchip Technology Inc. DS21796L-page 13
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
Part Number
1st Line Marking Codes
TSSOP MSOP
SOT-23 DFN TDFN
I Temp. E Temp. I Temp. E Temp. I Temp. E Temp.
93AA76A — —4BNN—————
93AA76B — — 4LNN — — — — —
93AA76C A76C 3A76CT — — 3B1 — EB1 —
93LC76A — — 4ENN 4FNN — — — —
93LC76B — — 4PNN 4RNN — — — —
93LC76C L76C 3L76CT — — 3B4 3B5 EB4 EB5
93C76A — — 4HNN 4JNN — — — —
93C76B — — 4TNN 4UNN — — — —
93C76C C76C 3C76CT — — 3B7 3B8 EB7 EB8
Note: T = Temperature grade (I, E)
NN = Alphanumeric traceability code
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note: For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796L-page 14 2003-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2011 Microchip Technology Inc. DS21796L-page 15
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796L-page 16 2003-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2011 Microchip Technology Inc. DS21796L-page 17
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
b
E
4
N
E1
PIN1IDBY
LASER MARK
D
123
e
e1
A
A1
A2 c
L
L1
φ
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796L-page 18 2003-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2011 Microchip Technology Inc. DS21796L-page 19
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
!"##$% !
N
E1
NOTE 1
D
123
A
A1
A2
L
b1
b
e
E
eB
c
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796L-page 20 2003-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2011 Microchip Technology Inc. DS21796L-page 21
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796L-page 22 2003-2011 Microchip Technology Inc.
"&'()#$%!*
2003-2011 Microchip Technology Inc. DS21796L-page 23
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
++,"-(-$%
D
N
E
E1
NOTE 1
12
b
e
c
A
A1
A2
L1 L
φ
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796L-page 24 2003-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2011 Microchip Technology Inc. DS21796L-page 25
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
.',/0*"11#()$% .
D
N
E
NOTE 1
12
EXPOSED PAD
NOTE 1
21
D2
K
L
E2
N
e
b
A3 A1
A
NOTE 2
BOTTOM VIEW
TOP VIEW
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796L-page 26 2003-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2011 Microchip Technology Inc. DS21796L-page 27
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796L-page 28 2003-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2011 Microchip Technology Inc. DS21796L-page 29
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
.',/0"11#(23$% .
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796L-page 30 2003-2011 Microchip Technology Inc.
APPENDIX A: REVISION HISTORY
Revision A (05/2003)
Initial Release.
Revision B (07/2003)
Revision C (12/2003)
Corrections to Section 1.0, Electrical Characteristics.
Section 4.1, 6-Lead SOT-23 package to OT.
Revision D (02/2004)
Corrections to Device Selection Table, Table 1-1, Table
1-2, Section 2.4, Section 2.5, Section 2.8 and Section
2.9. Added note to Figure 2-7.
Revision E (03/2005)
Added DFN package.
Revision F (04/2005)
Added notes throughout.
Revision G (09/2006)
Revised note in Sections 2.8 and 2.9. Replaced DFN
package drawing.
Revision H (11/2006)
Updated Package Drawings.
Revision J (10/2007)
Revised Device Selection Table; Revised Pin Function
Table; Revised Package Types; Revised Table 3-1;
Replaced Package Drawings; Revised Product ID
System.
Revision K (5/2008)
Revised Figures 2-1, 2-2, 2-6 and 2-7; Revised
Package Marking Information; Replaced Package
Drawings.
Revision L (01/2012)
Added TDFN package.
2003-2011 Microchip Technology Inc. DS21796L-page 31
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Development Systems Information Line
Customers should contact their distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796L-page 32 2003-2011 Microchip Technology Inc.
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO: Technical Publications Manager
RE: Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS21796L93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
2003-2011 Microchip Technology Inc. DS21796L-page 33
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office..
Device: 93AA76A: 8K 1.8V Microwire Serial EEPROM (x8)
93AA76B: 8K 1.8V Microwire Serial EEPROM (x16)
93AA76C: 8K 1.8V Microwire Serial EEPROM w/ORG
93LC76A: 8K 2.5V Microwire Serial EEPROM (x8)
93LC76B: 8K 2.5V Microwire Serial EEPROM (x16)
93LC76C: 8K 2.5V Microwire Serial EEPROM w/ORG
93C76A: 8K 5.0V Microwire Serial EEPROM (x8)
93C76B: 8K 5.0V Microwire Serial EEPROM (x16)
93C76C: 8K 5.0V Microwire Serial EEPROM w/ORG
Tape & Reel: Blank = Standard pinout
T = Tape & Reel
Temperature Range: I = -40°C to +85°C
E = -40°C to +125°C
Package: MS = Plastic MSOP (Micro Small outline), 8-lead
OT = Plastic SOT-23, 6-lead (Tape & Reel only)
P = Plastic DIP (300 mil body), 8-lead
SN = Plastic SOIC (3.90 mm body), 8-lead
ST = Plastic TSSOP (4.4 mm body), 8-lead
MC = Plastic DFN (2x3x0.90 mm body), 8-lead
MNY(1) = Plastic TDFN (2x3x0.75 mm body), 8-lead
(Tape & Reel only)
Examples:
a) 93AA76C-I/P: 8K, 1024x8 or 512x16 Serial
EEPROM, PDIP package, 1.8V
b) 93AA76AT-I/OT: 8K, 1024x8 Serial EEPROM,
SOT-23 package, tape and reel, 1.8V
c) 93AA76CT-I/MS: 8K, 1024x8 or 512x16 Serial
EEPROM, MSOP package, tape and reel, 1.8V
a) 93LC76C-I/ST: 8K, 1024x8 or 512x16 Serial
EEPROM, TSSOP package, 2.5V
b) 93LC76BT-I/OT: 8K, 512x16 Serial EEPROM,
SOT-23 package, tape and reel, 2.5V
c) 93LC76CT-E/MNY: 8K, 1024x8 or 512x16
Serial EEPROM, Automotive Temp, TDFN
package
a) 93C76C-I/MS: 8K, 1024x8 or 512x16 Serial
EEPROM, MSOP package, 5.0V
b) 93C76AT-I/OT: 8K, 1024x8 Serial EEPROM,
SOT-23 package, tape and reel, 5.0V
c) 93C76BX-I/SN: 8K, 512x16 Serial EEPROM,
rotated SOIC package, 5.0V
PART NO. X/XX
Package
Temperature
Range
Device
X
Lead Finish
X
Tape & Reel
Note 1: “Y” indicates a Nickel Palladium Gold (NiPdAu) finish.
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796L-page 34 2003-2011 Microchip Technology Inc.
NOTES:
2003-2011 Microchip Technology Inc. DS21796L-page 35
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-957-1
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21796L-page 36 2003-2011 Microchip Technology Inc.
AMERICAS
Corporate Office
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Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
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Web Address:
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Worldwide Sales and Service
11/29/11
