TOSHIBA TENTATIVE TC74VHCT373AF/AFW/AFT TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74VHCT373AF, TC74VHCT373AFW, TC74VHCT373AFT OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT The TC74VHCT373A is an advanced high speed CMOS OCTAL LATCH with 3-STATE OUTP abricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. is 8-bit D-type latch is controlled by a latch enable input (LE) and a output enable input (OE). When the OF input is high, the eight outputs are in a high impedance state. The input voltage are compatible with TTL output voltage. This device may be used as a level converter for interfacing 3.3V to 5V system. Input protection and output circuit ensure that 0 to 5.5V can be applied to the input and output*! pins without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and input/output voltages such as battery back up, hot board insertion, etc. *1; output in off-state FEATURES : e High Speed soe veensacceononenssenereceasceesene toa = 7.7ns(typ.) at Voc =5V e Low Power Dissipation-----+++++------ loc = 4A(Max.) at Ta = 25C Compatible with TTL outputs ---- Vi, = 0.8V (Max.) Vin = 2.0V (Min.) e Power Down Protection is provided on all inputs and outputs. e Balanced Propagation Delays---- totH=toHt LOW Noiige --vsseessesetsscerecevesseseeenes Votp = 1.6V (Max.) e Pin and Function Compatible with the 74 series (74AC /HC /F/ALS/LS etc.) 373 type. F (SOP20-P-300- 1.27) Weight : 0.229 (TYP.) <> 1 Weight : 0.089 (TYP.) a 20 & aa 1 1 FW (SOL20-P-300-1.27) Weight : 0.46g (TYP.) FT (TSSOP20-P-0044-0.65) PIN ASSIGNMENT (TOP VIEW) OE 1 20 Qo 2 19 po 3 18 D1 4 17 Qi 5 16 Q2 6 15 D2 7 14 D3 8 13 Q3 9 12 GND 10 11 Vee Q7 07 D6 Q6 Qs DS D4 Q4 LE TRUTH TABLE INPUTS = OUTPUT OE | LE D H x xX zZ L L 4 Qn L H L L L H H H X : Dont Care Z : High Impedance Qn : Q outputs are latched at the time when the LE input is taken to a low logic level. IEC LOGIC SYMBOL 1 11 OE LE EN c1 D D1 D2 D3 D4 D5 D6 D7 @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in genera! can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the res . produ observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within s a recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor nsibility of the buyer, when utilizing TOSHIBA products, to cified operating ra es as set forth in the most liability Handbook. 96100 1EBA2 313 1997-01-30 1/6 TOSHIBA TC74VHCT373AF/AFW/AFT SYSTEM DIAGRAM ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL VALUE UNIT Supply Voltage Range Vec 0.5~7.0 Vv DC Input Voltage Vin 0.5~7.0 Vv 0.5~7.0 (Note 1) DC Output Voltage Vour =0.5~VEC+0.5 (Note 2) Vv Input Diode Current bik 20 mA Output Diode Current lox +20 (Note 3) mA DC Output Current lour 25 mA DC Vce/Ground Current lec +75 mA Power Dissipation Po 180 mw Storage Temperature Tstg 65~150 C (Note 1) Output in Off-State (Note 2) High or Low State. Ioy7z absolute maximum rating must be observed. (Note 3) VouT<GND, VouT>Vcc RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL VALUE UNIT Supply Voltage Vee 4.5~5.5 Vv Input Voltage Vin 0~5.5 Vv 0~5.5 (Note 4) Output Voltage Vout O=VCC (Note 5) V Operating Temperature Topr 40~85 C Input Rise and Fall Time dt/dV 0~20 ns/V (Note 4) Output in Off-State (Note 5) High or Low State 3 The products described in this document are subject to foreign exchange and foreign trade control laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intetlectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 314 1997-01-30 2/6 TOSHIBA TC74VHCT373AF/AFW/AFT DC ELECTRICAL CHARACTERISTICS Ta=25C Ta= 40~85C PARAMETER SYMBOL CONDITON : : UNIT Vec(V) | MIN. | TYP. | MAX.] MIN. | MAX. High - Level ~ _ _ _ input Voltage Vin 4.5~5.5] 2.0 2.0 Vv Low - Level ~ _ _ input Voltage Vi 4.5~5.5 0.8 08 | v High - Level Vou Vine lon= ~SO0vA | 45 1440] 450| | 440] V Output Voltage VnorVi. [loo=-8mA | a5 [394] | | 3.80] Low - Level Vin= lo. = 50 nA 4.5 - 0.0 | 0.1 - 0.1 Output Voltage Vou Vv 9 VinorVic [lop =8mA 45 ~ - 1036] | 0.44 3-State Output Vin = Vin Or Vic _ ~ |+ |+ Off - State Current loz Vout = Vc or GND 5-5 40.25 $2.50 Input Leakage Current lin Vin = 5.5V or GND O~5.5) _ +014) 1.0 uA . lee Vin = Vcc or GND 5.5 ad _ 4.0 _ 40.0 Quiescent Supply : Current lecn PER INPUT =: Vin=3.4V 5.5 _ _ 1as | - 1.50 | mA OTHER INPUT : Vcc or GND Cutput Leakage loo | Vout =5.5V 0 - |- |os | | 50 | za TIMING REQUIREMENTS (Input t= tr=3ns) Ta = 25C Ta = -40-85C PARAMETER symeot | TEST CONDITION 2 Cunt Vee TYP. LIMIT LIMIT Minimum Ans Width twH) 5040.5] 6.5 8.5 Minimum Set-up Time ts 5.00.5 - 1.5 15 ns Minimum Hold Time th 5.0+0.5 _ 3.5 3.5 315 1997-01-30 3/6 TOSHIBA TC74VHCT373AF/AFW/AFT AC ELECTRICAL CHARACTERISTICS ( Input t, = t=3ns) TEST CONDITION = 25 = 40~85 PARAMETER SYMBOL CONDITIO Ta = 25C fa = 40 85C nr Vec(V) | CL (pF) | MIN. | TYP. | MAX. | MIN. | MAX. Propagation Delay Time tot 5.0+0.5 15 _ 77 12.3 1.0 | 13.5 (LE-Q) toHL ~ 50 _ 8.5 | 13.3 | 1.0 | 14.5 Propagation Delay Time tot 5.0+0.5 15 _ 5.1 8.5 1.0 9.5 (D-Q) tox oT 50 _ 5.9 9.5 1.0 10.5 3-State Output Enable Time tozt RL=1koQ 15.040. 15 6.3 10.9 1.0} 12.5 State Output Enable Ti tozi 040.5;.5 [71 }119 {10 1135) 3-State Output Disable Time pe RL=1kQ 15.0+0.5| 50 _ 88 | 11.2 | 1.0 | 12.0 p! Output to Output Skew fost (Note 6)|5.0+0.5| 50 - - 10 | 1.0 Input Capacitance Cin _ 4 10 - 10 Output Capacitance Cout 6 _ _ pF Power Dissipation Capacitance Cpp (Note 7) _ 25 - _ _ (Note 6) Parameter guaranteed by design. tos. = Itotum tortin |, tosts = Itonim ~ toxin! (Note 7) Cpp is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: lecfope) =C po Vee fin tlec/ 8 ( per latch ) And the total Cpp when n pes. of Latch operate can be gained by the following equation : Ceo (total) =14+11-n NOISE CHARACTERISTICS (Input t, = t; = 3ns) PARAMETER SYMBOL TEST ce a = ee x UNIT agnor Dyn amic Vor Vor C, = 50pF 5.0 1.2 1.6 Vv Winimam'Dynamic Vo, | Wow C, = 50pF 5.0 =12 ~1.6 V Minimum igh level | vuo | cesar | 50 | - | 20 | v Maximumtow level [vio | c=soer | so | - | oa | v 316 1997-01-30 4/6