X24C45
1
Serial AUTOSTORE™ NOVRAM
© Xicor, Inc. 1991, 1995, 1996 Patents Pending Characteristics subject to change without notice
3833-1.5 2/24/99 T3/C3/D0 NS
DESCRIPTION
The Xicor X24C45 is a serial 256 bit NOVRAM featuring
a static RAM configured 16 x 16, overlaid bit-by-bit with
a nonvolatile E2PROM array. The X24C45 is fabricated
with Xicor’s Advanced CMOS Floating Gate technology.
The Xicor NOVRAM design allows data to be transferred
between the two memory arrays by means of software
commands or external hardware inputs. A store opera-
tion (RAM data to E2PROM) is completed in 5ms or less
and a recall operation (E2PROM data to RAM) is com-
pleted in 2µs or less.
The X24C45 also includes the AUTOSTORE feature, a
user selectable feature that automatically performs a
store operation when VCC falls below a preset threshold.
Xicor NOVRAMs are designed for unlimited write opera-
tions to RAM, either from the host or recalls from E2PROM
and a minimum 1,000,000 store operations. Inherent data
retention is specified to be greater than 100 years.
FEATURES
•AUTOSTORE™ NOVRAM
—Automatically Performs a Store Operation
Upon Loss of VCC
•Single 5 Volt Supply
•Ideal for use with Single Chip Microcomputers
—Minimum I/O Interface
—Serial Port Compatible (COPS™, 8051)
—Easily Interfaced to Microcontroller Ports
•Software and Hardware Control of Nonvolatile
Functions
•Auto Recall on Power-Up
•TTL and CMOS Compatible
•Low Power Dissipation
—Active Current: 10mA
—Standby Current: 50µA
•8-Lead PDIP and 8-Lead SOIC Packages
•High Reliability
—Store Cycles: 1,000,000
—Data Retention: 100 Years
256 Bit X24C45 16 x 16 Bit
3833 FHD F01
FUNCTIONAL DIAGRAM
NONVOLATILE
E2PROM
CONTROL
LOGIC
COLUMN
DECODE
ROW
DECODE
4-BIT
COUNTER
INSTRUCTION
DECODE
INSTRUCTION
REGISTER
CE (1)
DI (3)
SK (2) DO (4)
RECALL (6)
AS (7)
STATIC
RAM
256-BIT
RECALL
STORE
AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc.
COPS is a trademark of National Semiconductor Corp.
APPLICATION NOTES
AVAILABLE
AN3 • AN7 • AN8 • AN15 • AN16 • AN25 • AN29
• AN30 • AN35 • AN36 • AN39 • AN56 • AN69
2
X24C45
PIN CONFIGURATIONPIN DESCRIPTIONS
Chip Enable (CE)
The Chip Enable input must be HIGH to enable all read/
write operations. CE must remain HIGH following a
Read or Write command until the data transfer is com-
plete. CE LOW places the X24C45 in the low power
standby mode and resets the instruction register. There-
fore, CE must be brought LOW after the completion of an
operation in order to reset the instruction register in
preparation for the next command.
Serial Clock (SK)
The Serial Clock input is used to clock all data into and
out of the device.
Data In (DI)
Data In is the serial data input.
Data Out (DO)
Data Out is the serial data output. It is in the high
impedance state except during data output cycles in
response to a READ instruction.
AUTOSTORE Output (AS)
AS is an open drain output which, when asserted indi-
cates VCC has fallen below the AUTOSTORE threshold
(VASTH). AS may be wire-ORed with multiple open drain
outputs and used as an interrupt input to a microcontroller
or as an input to a low power reset circuit.
RECALL
RECALL LOW will initiate an internal transfer of data
from E2PROM to the RAM array.
PIN NAMES
Symbol Description
CE Chip Enable
SK Serial Clock
DI Serial Data In
DO Serial Data Out
RECALL Recall Input
AS AUTOSTORE Output
VCC +5V
VSS Ground 3833 PGM T01
3833 FHD F02.1
CE
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
AS
RECALL
VSS
X24C45
DIP/SOIC
X24C45
3
DEVICE OPERATION
The X24C45 contains an 8-bit instruction register. It is
accessed via the DI input, with data being clocked in on
the rising edge of SK. CE must be HIGH during the entire
data transfer operation.
Table 1. contains a list of the instructions and their
operation codes. The most significant bit (MSB) of all
instructions is a logic one (HIGH), bits 6 through 3 are
either RAM address bits (A) or don’t cares (X) and bits
2 through 0 are the operation codes. The X24C45
requires the instruction to be shifted in with the MSB first.
After CE is HIGH, the X24C45 will not begin to interpret
the data stream until a logic “1” has been shifted in on DI.
Therefore, CE may be brought HIGH with SK running
and DI LOW. DI must then go HIGH to indicate the start
condition of an instruction before the X24C45 will begin
any action.
In addition, the SK clock is totally static. The user can
completely stop the clock and data shifting will be
stopped. Restarting the clock will resume shifting of
data.
RCL and RECALL
Either a software RCL instruction or a LOW on the
RECALL input will initiate a transfer of E2PROM data
into RAM. This software or hardware recall operation
sets an internal “previous recall” latch. This latch is reset
upon power-up and must be intentionally set by the user
to enable any write or store operations. Although a recall
operation is performed upon power-up, the previous
recall latch is not set by this operation.
WRDS and WREN
Internally the X24C45 contains a “write enable” latch. This
latch must be set for either writes to the RAM or store
operations to the E2PROM. The WREN instruction sets
the latch and the WRDS instruction resets the latch,
disabling both RAM writes and E2PROM stores, effec-
tively protecting the nonvolatile data from corruption. The
write enable latch is automatically reset on power-up.
STO
The software STO instruction will initiate a transfer of
data from RAM to E2PROM. In order to safeguard
against unwanted store operations, the following condi-
tions must be true:
• STO instruction issued.
• The internal “write enable” latch must be set
(WREN instruction issued).
• The “previous recall” latch must be set (either a
software or hardware recall operation).
Once the store cycle is initiated, all other device func-
tions are inhibited. Upon completion of the store cycle,
the write enable latch is reset. Refer to Figure 4 for a
state diagram description of enabling/disabling condi-
tions for store operations.
TABLE 1. INSTRUCTION SET
Instruction Format, I2 I1 I0Operation
WRDS (Figure 3) 1XXXX000 Reset Write Enable Latch (Disables Writes and Stores)
STO (Figure 3) 1XXXX001 Store RAM Data in E2PROM
ENAS 1XXXX010 Enable AUTOSTORE Feature
WRITE (Figure 2) 1AAAA011 Write Data into RAM Address AAAA
WREN (Figure 3) 1XXXX100 Set Write Enable Latch (Enables Writes and Stores)
RCL (Figure 3) 1XXXX101 Recall E2PROM Data into RAM
READ (Figure 1) 1AAAA11X Read Data from RAM Address AAAA 3833 PGM T11
X = Don’t Care
A = Address
4
X24C45
WRITE
The WRITE instruction contains the 4-bit address of the
word to be written. The write instruction is immediately
followed by the 16-bit word to be written. CE must
remain HIGH during the entire operation. CE must go
LOW before the next rising edge of SK. If CE is brought
LOW prematurely (after the instruction but before 16 bits
of data are transferred), the instruction register will be
reset and the data that was shifted-in will be written to
RAM.
If CE is kept HIGH for more than 24 SK clock cycles (8-bit
instruction plus 16-bit data), the data already shifted-in will
be overwritten.
READ
The READ instruction contains the 4-bit address of the
word to be accessed. Unlike the other six instructions, I0
of the instruction word is a “don’t care”. This provides two
advantages. In a design that ties both DI and DO
together, the absence of an eighth bit in the instruction
allows the host time to convert an I/O line from an output
to an input. Secondly, it allows for valid data output
during the ninth SK clock cycle.
D0, the first bit output during a read operation, is trun-
cated. That is, it is internally clocked by the falling edge
of the eighth SK clock; whereas, all succeeding bits are
clocked by the rising edge of SK (refer to Read Cycle
Diagram).
LOW POWER MODE
When CE is LOW, non-critical internal devices are
powered-down, placing the device in the standby power
mode, thereby minimizing power consumption.
AUTOSTORE Feature
The AUTOSTORE instruction (ENAS) sets the
“AUTOSTORE enable” latch, allowing the X24C45 to
automatically perform a store operation when VCC falls
below the AUTOSTORE threshold (VASTH).
WRITE PROTECTION
The X24C45 provides two software write protection
mechanisms to prevent inadvertent stores of unknown
data.
Power-Up Condition
Upon power-up the “write enable” and “AUTOSTORE
enable” latches are in the reset state, disabling any store
operation.
Unknown Data Store
The “previous recall” latch must be set after power-up.
It may be set only by performing a software or hardware
recall operation, which assures that data in all RAM
locations is valid.
SYSTEM CONSIDERATIONS
Power-Up Recall
The X24C45 performs a power-up recall that transfers
the E2PROM contents to the RAM array. Although the
data may be read from the RAM array, this recall does
not set the “previous recall” latch. During this power-up
recall operation, all commands are ignored. Therefore,
the host should delay any operations with the X24C45 a
minimum of tPUR after VCC is stable.
X24C45
5
Figure 1. RAM Read
3833 FHD F09.1
Figure 2. RAM Write
3833 FHD F10.1
Figure 3. Non-Data Operations
3833 FHD F11.1
1
CE
2345678
1A 1AAA 1X*
SK
DI
9 101112222324
D1D2D3D14 D15 D0
D13
DO HIGH Z
*Bit 8 of Read Instructions is Don’t Care
D0
1
CE
2345678
1A 1AAA 1
SK
DI
9 101121222324
D0D1D2D12 D13 D14 D15
0
1
CE
2345678
1X I
2
XXX I
1I0
SK
DI
6
X24C45
Figure 4. X24C45 State Diagram
POWER
ON
STORE
ENABLED
RAM READ
OR WRITE
RAM
READ
ENABLED
RAM
READ
ENABLED
RAM
READ & WRITE
ENABLED
WREN
COMMAND
RAM READ
RAM READ
POWER-UP
RECALL
RCL COMMAND
OR RECALL
STO OR
WRDS CMD
RAM
READ & WRITE
ENABLED
STORE ENABLED
AUTOSTORE
ENABLED
RAM READ
OR WRITE ENAS COMMAND
WREN
COMMAND
STO OR
WRDS CMD
POWER
OFF
AUTOSTORE
POWER DOWN
3833 FHD F12.1
X24C45
7
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to VSS .......................................–1V to +7V
D.C. Output Current .............................................5mA
Lead Temperature
(Soldering, 10 seconds).............................. 300°C
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C +70°C
Industrial –40°C +85°C
Military –55°C +125°C
3833 PGM T02.1
Supply Voltage Limits
X24C45 5V ±10%
3833 PGM T03.1
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol Parameter Max. Units Test Conditions
COUT(2) Output Capacitance 8 pF VOUT = 0V
CIN(2) Input Capacitance 6 pF VIN = 0V
3833 PGM T06.1
ENDURANCE AND DATA RETENTION
Parameter Min. Units
Endurance 100,000 Data Changes Per Bit
Store Cycles 1,000,000 Store Cycles
Data Retention 100 Years 3833 PGM T05
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol Parameter Min. Max. Units Test Conditions
lCC1 VCC Supply Current 10 mA SK = 0.4V/2.4V Levels @ 1MHz,
(TTL Inputs) DO = Open, All Other Inputs = VIH
ICC2 VCC Supply Current 2 mA All Inputs = VIH, CE = VIL
(During AUTOSTORE) DO = Open, VCC = 4.3V
ISB1 VCC Standby Current 1 mA DO = Open, CE = VIL,
(TTL Inputs) All Other Inputs = VIH
ISB2 VCC Standby Current 50 µA DO = Open, CE = VSS
(CMOS Inputs) All Other Inputs = VCC – 0.3V
ILI Input Load Current 10 µA VIN = VSS to VCC
ILO Output Leakage Current 10 µA VOUT = VSS to VCC
VlL(1) Input LOW Voltage –1 0.8 V
VIH(1) Input HIGH Voltage 2 VCC + 1 V
VOL Output LOW Voltage 0.4 V IOL = 4.2mA
VOH Output HIGH Voltage 2.4 V IOH = –2mA
VOL(AS) Output LOW Voltage (AS) 0.4 V IOL (AS) = 1mA 3833 PGM T04.3
8
X24C45
A.C. CONDITIONS OF TEST
Input Pulse Levels 0V to 3V
Input Rise and
Fall Times 10ns
Input and Output
Timing Levels 1.5V 3833 PGM T07.1
EQUIVALENT A.C. LOAD CIRCUIT
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
POWER-UP TIMING
Symbol Parameter Max. Units
tPUR(4) Power-up to Read Operation 200 µs
tPUW(4) Power-up to Write or Store Operation 5 ms 3833 PGM T09
Notes: (3) SK rise and fall times must be less than 50ns.
(4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters
are periodically sampled and not 100% tested.
3833 FHD F03
5V
919Ω
497Ω
OUTPUT
100pF
Read and Write Cycle Limits
Symbol Parameter Min. Max. Units
FSK(3) SK Frequency 1 MHz
tSKH SK Positive Pulse Width 400 ns
tSKL SK Negative Pulse Width 400 ns
tDS Data Setup Time 400 ns
tDH Data Hold Time 80 ns
tPD1 SK to Data Bit 0 Valid 375 ns
tPD SK to Data Valid 375 ns
tZChip Enable to Output High Z 1 µs
tCES Chip Enable Setup 800 ns
tCEH Chip Enable Hold 350 ns
tCDS Chip Deselect 800 ns
3833 PGM T08.1
X24C45
9
Write Cycle
3833 FHD F04
Read Cycle
3833 FHD F05
SK X12n
CE
DI
SK CYCLE #
tCES
tSKH
1/FSK tSKL
tCEH tCDS
tDH
tDS
SK
678910 n
D0 D1 Dn
HIGH Z HIGH Z
CE
DI
DO
DON’T CARE
SK CYCLE #
12 I1
tPD1
tPD
tZ
VIH
10
X24C45
NONVOLATILE OPERATIONS
Previous
Software Write Enable Recall Latch
Operation RECALL Instruction Latch State State
Hardware Recall 0 NOP(5) XX
Software Recall 1 RCL X X
Software Store 1 STO SET SET
3833 PGM T10
ARRAY RECALL LIMITS
Symbol Parameter Min. Max. Units
tRCC Recall Cycle Time 2 µs
tRCP Recall Pulse Width(6) 500 ns
tRCZ Recall to Output in High Z 500 ns
3833 PGM T11
Recall Timing
3833 FHD F06
Notes: (5) NOP designates when the X24C45 is not currently executing an instruction.
(6) Recall rise time must be <10µs.
(7) Typical values are for TA = 25°C and nominal supply voltage.
tRCC
tRCP
tRCZ HIGH Z
RECALL
DO
SOFTWARE STORE CYCLE LIMITS
Symbol Parameter Min. Typ.(7) Max. Units
tST Store Time After Clock 8 of STO Command 2 5 ms
3833 PGM T12.1
X24C45
11
AUTOSTORE Cycle Limits
Symbol Parameter Min. Max. Units
tASTO AUTOSTORE Cycle Time 5 ms
VASTH AUTOSTORE Threshold Voltage 4.0 4.3 V
VASEND AUTOSTORE Cycle End Voltage 3.5 V
3833 PGM T13.1
AUTOSTORE Cycle Timing Diagrams
3833 FHD F08
SYMBOL TABLE
AS
tPUR tASTO tPUR
0V
VASTH
VCC
1
2
3
4
5VCC
VOLTS (V)
TIME (ms)
VASTH
VASEND
AUTOSTORE CYCLE IN PROGRESS
tASTO
STORE TIME
WAVEFORM INPUTS OUTPUTS
Must be
steady Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
12
X24C45
PACKAGING INFORMATION
0.020 (0.51)
0.016 (0.41)
0.150 (3.81)
0.125 (3.18)
0.325 (8.25)
0.300 (7.62)
0.110 (2.79)
0.090 (2.29)
0.430 (10.92)
0.360 (9.14)
0.300
(7.62) REF.
PIN 1 INDEX
0.140 (3.56)
0.130 (3.30)
0.020 (0.51)
0.015 (0.38)
3926 FHD F01
PIN 1
SEATING
PLANE
0.062 (1.57)
0.058 (1.47)
0.255 (6.47)
0.245 (6.22)
0.060 (1.52)
0.020 (0.51)
TYP. 0.010 (0.25)
0°
15°
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.092 (2.34)
DIA. NOM.
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.015 (0.38)
MAX.
X24C45
13
PACKAGING INFORMATION
0.150 (3.80)
0.158 (4.00) 0.228 (5.80)
0.244 (6.20)
0.014 (0.35)
0.019 (0.49)
PIN 1
PIN 1 INDEX
0.010 (0.25)
0.020 (0.50)
0.050 (1.27)
0.188 (4.78)
0.197 (5.00)
0.004 (0.19)
0.010 (0.25)
0.053 (1.35)
0.069 (1.75)
(4X) 7°
0.016 (0.410)
0.037 (0.937)
0.0075 (0.19)
0.010 (0.25)
0° – 8°
X 45°
3926 FHD F22.1
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.250"
0.050" TYPICAL
0.050"
TYPICAL
0.030"
TYPICAL
8 PLACES
FOOTPRINT
14
X24C45
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
US. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976.
Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use as critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its satety or effectiveness.
ORDERING INFORMATION
Device
X24C45 P T -V
VCC Limits
Blank = 5V ±10%
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
Package
P = 8-Lead Plastic DIP
S = 8-Lead SOIC
