APA2059 2.4W Stereo Fully Differential Audio Power Amplifier With Stereo Class AB Cap-free Headphone Driver and LDO Features General Description * * The APA2059 is a stereo fully differential audio power amplifier with stereo Class-AB cap-free headphone driver * * * * * * * * * * * Meeting VISTATM Requirement Fully Differential Power Amplifier with and LDO available in a TQFN5X5-32 pins package. The built-in gain setting at power amplifier can minimize Excellent RF Rectification Immunity No Output Capacitor Required for Head the external component counts. For the flexible application, the gain can be set to 4-steps, 10, 12, 15.6, and 21.6dB by Phone Driver Integrated LDO (Low Dropout Regulator) for Audio Codec (4.75V) gain control pins (GAIN0 and GAIN1). The power amplifier's fully differential architecture provides high PSRR, in- Adjustable Gain Setting for Power Amplifier creased immunity to noise and RF rectification. AV=-1.5V/V Fixed Gain Setting for Headphone The APA2059 power amplifiers are capable of driving Driver 2.4W at VDD=5V into 4 speaker, the cap-free headphone drivers can provide 180mW at HV DD =3.3V into16 Fast Start-up Time headphones, and the LDO has a maximum 120mA (4.75V) driver current for audio codec. The APA2059 pro- Integrated De-Pop Circuitry High PSRR (Power Supply Rejection Ratio) vides thermal and over-current protections. The cap-free headphone driver eliminates the DC block- Thermal and Over-Current Protections Less External Components Required ing capacitors at outputs and saves the PCB space. The integration of fully differential power amplifier, cap-free Space Saving Package - TQFN5x5-32 headphone driver, and LDO is a best solution for VISTATM requirement and it can lower the total BOM costs. Lead Free and Green Devices Available (RoHS Compliant) Applications Common Mode Rejection Ratio (dB) * * * +0 LCD Monitor Notebook Portable DVD Simplified Application Circuit Audio Codec Stereo Speakers -10 -20 -30 -40 VDD=5.0V RL=4 AV=10dB Vin=0.2VPP Ci=0.47F Input Short AMP Mode -50 -60 -70 -80 -90 -100 20 100 1k 10k 20k Frequency (Hz) Stereo Headphone LDO (Low Drop -Out Regulator) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 1 www.anpec.com.tw APA2059 Ordering and Marking Information Package Code QB : TQFN5x5-32 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APA2059 Assembly Material Handling Code Temperature Range Package Code APA2059 QB : APA2059 XXXXX XXXXX - Date Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). 17 HVDD 18 PVDD 20 ROUTP 19 ROUTN 22 HP_EN 21 PGND 24 BIAS 23 AMP_EN Pin Configuration LDO_EN 25 16 HP_LO RIN_H 26 15 HP_RO 14 HVSS LIN_H 27 GND 28 13 CVSS TQFN5x5-32 (Top View) LDOUT 29 12 CPN 11 CGND VDD 30 PVDD 8 LOUTN 7 PGND 5 RINP_A 2 LOUTP 6 9 NC LINP_A 3 GAIN1 32 LINN_A 4 10 CPP RINN_A 1 GAIN0 31 =Thermal-Pad (connected the Thermal-Pad to GND plane for better heat dissipation) Absolute Maximum Ratings Symbol VDD HVDD VSS (Note 1) Parameter Rating Supply Voltage (VDD to GND, PVDD to PGND) -0.3 to 6 Supply Voltage (HVDD to GND) -0.3 to 6 Supply Voltage (HVSS, CVSS to GND) -6 to +0.3 Input Voltage (RINN_A, RINP_A, LINN_A, LINP_A to GND) Input Voltage (RIN_H, LIN_H to GND) -0.3 to VDD+0.3 V VSS-0.3 to HVDD+0.3 Input Voltage (GAIN0, GAIN1, LDO_EN, AMP_EN, HP_EN to GND) Input Voltage (PGND, CGND to GND) Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 Unit -0.3 to VDD+0.3 -0.3 to +0.3 2 www.anpec.com.tw APA2059 Absolute Maximum Ratings (Cont.) Symbol TJ Parameter Rating Maximum Junction Temperature Unit 150 TSTG Storage Temperature Range TSDR Maximum Lead Soldering Temperature, 10 Seconds PD (Note 1) -65 to +150 C 260 Power Dissipation Internally Limited W Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol JA JC Parameter Thermal Resistance -Junction to Ambient Typical Value (Note 2) TQFN5X5-32 Thermal Resistance -Junction to Case (Note 3) TQFN5X5-32 40 8 Unit C/W C/W Note 2: Please refer to " Layout Recommendation", the Thermal-Pad on the bottom of the IC should soldered directly to the PCB's Thermal-Pad area that with several thermal vias connect to the ground plan, and the PCB is a 2-layer, 5-inch square area with 2oz copper thickness. Note 3: The case temperature is measured at the center of the Thermal-Pad on the underside of the TQFN5X5-32 package. Recommended Operating Conditions Symbol Parameter Range VDD Supply Voltage 4.5 ~ 5.5 HVDD Supply Voltage 3.0 ~ 5.5 VIH High Level Input Voltage GAIN0, GAIN1, LDO_EN, AMP_EN, HP_EN 2 ~ VDD VIL Low Level Input Voltage GAIN0, GAIN1, LDO_EN, AMP_EN, HP_EN 0 ~ 0.5 VIC Common Mode Input Voltage ILDOUT For Power Amplifier 0.5 ~ VDD-0.5 For Headphone Amplifier HVSS ~ HVDD Output Current (LDOUT) 0 ~ 200 TA Ambient Temperature Range -40 ~ 85 TJ Junction Temperature Range -40 ~ 125 COUT LDO Output Capacitor (MLCC type) 1 ~ 100 RL Speaker Resistance 4~ RL Headphone Resistance 16 ~ Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 3 Unit V mA C F www.anpec.com.tw APA2059 Electrical Characteristics o Refer to the typical application circuits. VDD=5V, HVDD=3.3V, Gnd=0V, TA=25 C (unless otherwise noted) Symbol IDD(HVDD) Parameter Supply Current IDD(VDD) IAMP(HVDD) Power Amplifier Supply Current IAMP(VDD) IHP(HVDD) Headphone Driver Supply Current IHP(VDD) ILDO(HVDD) LDO Supply Current ILDO(VDD) ISD(HVDD) Shutdown Current ISD(VDD) II Input Current APA2059 Test Conditions VAMP_EN =VHP_EN=VLDO_EN=5V Min. Typ. Max. HVDD - 2.5 5 VDD - 9 18 VAMP_EN=5V, VHP_EN=VLDO_EN=0V HVDD - 0.1 0.2 VDD - 4.5 11 VHP_EN=5, VAMP_EN=VLDO_EN=0V HVDD - 2.5 5 VDD - 6 12 VLDO_EN=5V, VAMP_EN =VHP_EN=0V HVDD - 0.1 0.2 VDD - 0.4 0.65 HVDD - - 2 VDD - - 5 GAIN0, GAIN1, LDO_EN, AMP_EN, HP_EN - - 1 CB=0.47F - 25 - AV=10dB - 76 - AV=12dB - 60 - AV=15.6dB - 40 - AV=21.6dB 17 20 - VGAIN0=VGAIN1=0V. 9.5 10 10.5 VGAIN0=0V, VGAIN1=VDD. 11.5 12 12.5 VGAIN0=VDD, VGAIN1=0V. 15.1 15.6 16.1 VGAIN0=VGAIN1=VDD. 21.1 21.6 22.1 - 5 20 1.9 1.3 - 1 - 2.4 1.5 - - 0.07 0.05 - - -110 -110 - VAMP_EN =VHP_EN=VLDO_EN=0V Unit mA A SPEAKER MODE, AV =10dB TSTART-UP Ri Start-Up Time from Shutdown Input Resistor AV Closed-Loop Gain VOS Output Offset Voltage PO Output Power THD+N Crosstalk Total Harmonic Distortion Plus Noise Channel Separation RL = 8 THD+N=1%, fin=1kHz RL=4 RL=8 THD+N=10%, fin=1 kHz RL=4 RL=8 fin=1kHz RL=4, PO=1.4W RL=8, PO=0.9W fin=1kHz RL=4, Po=200mW RL=8, Po=130mW Power Supply Rejection Ratio fin=217Hz, Vrr=0.2Vrms,RL=8 - -75 - CMRR Common Mode Rejection Ratio fin=1kHz, Vin=0.2Vrms.,RL=8 fin=20~20kHz With A-weighting Filter RL=4, PO=1.4W, RL=8, PO=0.9W, fin=20~20kHz,With A-weighting Filter RL=8 - -65 - - 100 100 - - 22 - Signal-to-Noise Ratio Vn Noise Output Voltage Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 4 k dB mV W PSRR S/N ms % dB Vrms www.anpec.com.tw APA2059 Electrical Characteristics (Cont.) o Refer to the typical application circuits. VDD=5V, HVDD=3.3V, Gnd=0V, TA=25 C (unless otherwise noted) Symbol Parameter APA2059 Test Conditions Min. Typ. Unit Max. HEADPHONE MODE, AV = -1.5V/V, CPF=CPO=1F(X5R TYPE) TSTART-UP Start-Up Time from Shutdown Ri Input Resistor AV Closed-Loop Gain VOS Output Offset Voltage PO VO THD+N Crosstalk PSRR Output Power Output Swing Voltage Total Harmonic Distortion Plus Noise Channel Separation Power Supply Rejection Ratio S/N Signal-to-Noise Ratio Vn Noise Output Voltage CB=0.47F RL = 32 THD+N=1%, fin=1kHz RL=16 RL=32 THD+N=10%, fin=1kHz RL=16 RL=32 THD+N=1%, fin=1kHz RL=320 RL=10k THD+N=10%, fin=1kHz RL=320 RL=10k fin=1kHz RL=16, PO=125mW RL=32, PO=88mW RL=320, VO=1.5V RL=10k, VO=1.6V fin=1kHz RL=16, PO=16mW RL=32, PO=12mW RL=320, VO=0.22V RL=10k, VO=0.22V fin=217Hz,Vrr=0.2Vrms RL=32 fin=20~20kHz, With A-weighting Filter RL=16, PO=125mW RL=32, PO=88mW RL=320, VO=1.5V RL= 10k, VO=1.6V fin=20~20kHz, With A-weighting Filter RL=32 - 10 - 17 20 - k -1.45 -1.5 -1.55 V/V - 1 5 mV 140 120 - 100 - 150 180 160 1.8 2.0 2.1 - - 2.45 2.6 - - - - - mW V 0. 03 0. 02 0. 005 0. 004 -82 -82 -77 -77 -80 99 100 100 100 - 15 ms - % - - dB - - Vrms LDO (LOW DROP-OUT REGULATOR) VDD Supply Voltage 4.9 5.0 5.5 V IO Output Current - - 120 mA VO Output Voltage IO=1mA 4.65 4.75 4.85 V Line Regulation IO=1mA, VDD=5.0V to 5.5V - 3 10 mV Load Regulation IO=1mA to 120mA - 0.06 0.2 mV/mA VDROP Dropout Voltage IO=120mA 80 100 mV PSRR Power Supply Rejection Ratio IO=1mA,fin=120Hz,Vrr=0.2Vrms - -50 - dB - 50 - k RDIS Discharge Resistor Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 5 www.anpec.com.tw APA2059 Electrical Characteristics (Cont.) o Refer to the typical application circuits. VDD=5V, HVDD=3.3V, Gnd=0V, TA=25 C (unless otherwise noted) Symbol Parameter APA2059 Test Conditions Min. Typ. Unit Max. CHARGE PUMP, CPF=CPO=1F(X5R type) FOSC Oscillator Frequency - 450 - kHz REQ Equivalent Resistance - 10 - CVss Negative Output Voltage -5.1 -5 -4.9 V RDIS Discharge Resistor - 5 - k Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 No load 6 www.anpec.com.tw APA2059 Typical Operating Characteristics (TA = +25C, unless otherwise noted.) THD+N vs. Frequency THD+N vs. Output Power 1 PO=0.14W PO=0.7W 0.1 THD+N (%) THD+N (%) 10 R =4 L fin=1kHz Ci=0.47F AV=10dB BW<22kHz 1 AMP Mode VDD=4.5V 0.1 0.01 VDD=5.0V RL=4 Ci=0.47F AV=10dB BW<22kHz AMP Mode 0.001 20 100 VDD=5.0V VDD=5.5V 0.01 10m 100m 1 PO=1.4W 5 Output Power (W) Common Mode Rejection Ratio (dB) Crosstalk (dB) +0 -60 -80 Right to Left -100 Left to Right -120 20 100 1k -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 10k 20k VDD=5.0V RL=4 AV=10dB Vin=0.2VPP Ci=0.47F Input Short AMP Mode 20 100 Frequency (Hz) THD+N vs. Frequency 0.1 VDD=4.5V 0.1 100m 1 5 Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 PO=0.09W PO=0.45W 0.01 VDD=5.0V RL=8 AV=10dB Ci=0.47F BW<22kHz AMP Mode 0.001 20 100 VDD=5.0V VDD=5.5V 0.01 10m 10k 20k 1 RL=8 fin=1kHz Ci=0.1F AV=10dB BW<22kHz AMP Mode THD+N (%) THD+N (%) 1 1k Frequency (Hz) THD+N vs. Output Power 10 10k 20k CMRR vs. Frequency Crosstalk vs. Frequency +0 TT TTTTT VDD=5.0V RL=4 -20 A =10dB V Ci=0.47F -40 PO=200mW AMP Mode -140 1k Frequency (Hz) PO=0.9W 1k 10k 20k Frequency (Hz) 7 www.anpec.com.tw APA2059 Typical Operating Characteristics (Cont.) (TA = +25C, unless otherwise noted.) CMRR vs. Frequency +0 Common Mode Rejection Ratio (dB) -60 -80 Right to Left -100 Left to Right -120 -140 VDD=5.0V RL=8 AV=10dB -20 Vin=0.2VPP -30 Ci=0.47F Input Short -40 AMP Mode -10 -50 -60 -70 -80 -90 -100 20 100 1k 10k 20k 20 100 +22 +200 +21 +180 Phase VDD=5.0V RL=8 AV=10dB Ci=0.47F AMP Mode +7 10 100 1k 10k 200k Gain (dB) Gain (dB) +9 +220 Phase (deg) Gain +8 +220 +20 +180 Phase +160 +19 +140 +18 VDD=5.0V RL=8 AV=21.6dB Ci=0.47F AMP Mode 10 100 Output Noise Voltage vs. Frequency Output Noise Voltage (Vrms) 10k 200k +140 Crosstalk vs. Frequency Crosstalk (dB) 10 VDD=5.0V RL=8 AV=10dB Cin=0.47F A-Wighting AMP Mode 100 1k +0 Left channel 20 +160 Frequency (Hz) Right channel 1 +200 Gain Frequency (Hz) 50 10k 20k Frequency Response Frequency Response +11 +10 1k Frequency (Hz) Frequency (Hz) Phase (deg) Crosstalk (dB) Crosstalk vs. Frequency +0 TTTTTTT VDD=5.0V R =8 -20 A L=10dB V Ci=0.47F -40 PO=130mW AMP Mode VDD=5.0V HVDD=3.3V -20 R =4(AMP) L RL=10k(HP) -40 PO=200mW(AMP) AMP(active) mode -60 HP mode -80 Left(AMP) to Right(HP) -100 Right(AMP) to Right(HP) -120 -140 1k 10k 20k 20 100 Right(AMP) to Left(HP) 1k 10k 20k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 Left(AMP) to Left(HP) 8 www.anpec.com.tw APA2059 Typical Operating Characteristics (Cont.) (TA = +25C, unless otherwise noted.) THD+N vs. Output Voltage 10 10 0.1 THD+N (%) VDD=5.0V HVDD=3.3V fin=1kHz Ci=1F BW<22kHz In Phase HP Mode 1 THD+N (%) THD+N vs. Output Power RL=16 RL=32 0.01 VDD=5.0V HVDD=3.3V RL=16 fin=1kHz Ci=1F 1 BW<22kHz HP Mode In Phase 0.1 Mono RL=320 RL=10k 0.001 0 500m 1 1.5 2 2.5 0.01 3 10m 100m THD+N vs. Frequency Crosstalk vs. Frequency 1 -20 PO=13mW -40 Crosstalk (dB) THD+N (%) 0.1 +0 VDD=5.0V HVDD=3.3V RL=16 Ci=1F BW<22kHz HP Mode PO=63mW PO=125mW 0.01 500m Output Power (W) Output Voltage (Vrms) VDD=5.0V HVDD=3.3V RL=16 PO=16mW Ci=1F HP Mode -60 Right to Left -80 Left to Right -100 -120 0.001 -140 20 100 1k 20 10k 20k 100 1 VDD=5.0V HVDD=3.3V RL=32 fin=1kHz Ci=1F 1 BW<22kHz HP Mode In Phase THD+N (%) THD+N (%) 10k 20k THD+N vs. Frequency THD+N vs. Output Power 10 0.1 1k Frequency (Hz) Frequency (Hz) Mono 0.1 VDD=5.0V HVDD=3.3V RL=32 Ci=1F BW<22kHz HP Mode PO=9mW PO=88mW 0.01 PO=44mW 0.01 10m 100m 0.001 300m Output Power (mW) Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 20 100 1k 10k 20k Frequency (Hz) 9 www.anpec.com.tw APA2059 Typical Operating Characteristics (Cont.) (TA = +25C, unless otherwise noted.) Output Noise Voltage vs. Frequency Crosstalk vs. Frequency 50 VDD=5.0V HVDD=3.3V -20 R =32 L PO=12mW -40 Ci=1F HP Mode Output Noise Voltage (Vrms) Crosstalk (dB) +0 Right channel 10 -60 Right to Left -80 Left to Right -100 -120 -140 Left channel 20 100 1k VDD=5.0V HDD=3.3V RL=32 Ci=1F A-Weighting HP Mode 1 10k 20k 20 100 Frequency (Hz) +220 Gain +0 T +200 +2 +180 Phase VDD=5.0V HVDD=3.3V RL=32 Ci=1F HP Mode +0 10 100 -40 Crosstalk (dB) +3 Phase (deg) Gain (dB) -20 +1 -60 Left(HP) to Right(AMP) -80 Right(HP) to Left(AMP) Right(HP) to Right(AMP) Left(HP) to Left(AMP) -120 10k 200k T =5.0V VDD HVDD=3.3V RL=8(AMP) RL=16(HP) PO=16mW(HP) AMP Mode HP(active) Mode -100 +160 1k -140 +140 20 100 Frequency (Hz) THD+N vs. Frequency 10k 20k Crosstalk vs. Frequency +0 VDD=5.0V HVDD=3.3V RL=320 Ci=1F BW<22kHz HP Mode Crosstalk (dB) THD+N (%) 1k Frequency (Hz) 1 0.1 10k 20k Crosstalk vs. Frequency Frequency Response +4 1k Frequency (Hz) VO=0.15V 0.01 VDD=5.0V HVDD=3.3V -20 R =320 L VO=0.22Vrms -40 Ci=1F HP Mode -60 Right to Left -80 Left to Right -100 VO=0.75V -120 VO=1.5V 0.001 20 100 1k -140 10k 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 20 100 1k 10k 20k Frequency (Hz) 10 www.anpec.com.tw APA2059 Typical Operating Characteristics (Cont.) (TA = +25C, unless otherwise noted.) THD+N vs. Frequency 1 Crosstalk vs. Frequency +0 VDD=5.0V HVDD=3.3V RL=10k Ci=1F BW<22kHz HP Mode -20 -40 Crosstalk (dB) THD+N (%) 0.1 VO=0.16V 0.01 VDD=5.0V HVDD=3.3V RL=10k VO=0.22Vrms Ci=1F HP Mode -60 Right to Left -80 Left to Right -100 VO=1.6V -120 VO=0.8V 0.001 20 100 1k -140 10k 20k 20 100 1k 10k 20k Frequency (Hz) Frequency (Hz) Output Noise Voltage vs. Frequency Frequency Response 50 +4 +220 Left channel 1 Gain (dB) Right channel 10 VDD=5.0V HDD=3.3V RL=10k Ci=1F A-Weighting HP Mode 20 +200 +2 +180 Phase VDD=5.0V HVDD=3.3V RL=10k Ci=0.47F HP Mode +1 100 1k +0 10k 20k 10 100 Phase (deg) Output Noise Voltage (Vrms) Gain +3 +160 1k 10k 200k +140 Frequency (Hz) Frequency (Hz) AMP Attenuation vs. Frequency HP Attenuation vs. Frequency +0 -20 AMP Attenuation (dB) -30 -40 -50 VDD=5.0V RL=8 AV=10dB Ci=0.47F VO=2Vrms (AMP enable) AMP Mode (disable) -10 -20 HP Attenuation (dB) -10 -60 -70 -80 Left channel -90 Right channel -30 -40 -50 VDD=5.0V HVDD=3.3V RL=32 Ci=1F VO=1Vrms (HP enable) HP Mode (disable) -60 -70 -80 -90 -100 Right channel -110 -110 Left channel -120 -120 -100 20 100 1k 10k 20k Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 20 100 1k 10k 20k Frequency (Hz) Frequency (Hz) 11 www.anpec.com.tw APA2059 Typical Operating Characteristics (Cont.) (TA = +25C, unless otherwise noted.) HP Attenuation vs. Frequency PSRR vs. Frequency -20 TT +0 -10 AMP Attenuation (dB) -20 -30 -40 -50 Power Supply Rejection Ratio (dB) VDD=5.0V HVDD=3.3V RL=10k Ci=1F VO=1Vrms (HP enable) HP Mode (disable) -60 Right channel -70 -80 Left channel -90 -100 -110 -120 20 100 1k -30 -40 -50 VDD=5.0V RL=8 AV=10dB Ci=0.47F Vrr=0.2Vrms AMP Mode -60 -70 -80 -90 -100 -110 -120 10k 20k T Vrr:Ripple Voltage on VDD 20 100 PSRR vs. Frequency PSRR vs. Frequency VDD=5.0V HVDD=3.3V RL=32 Ci=1F Vrr=0.2Vrms HP Mode -30 -40 -50 -60 -70 -80 -90 -100 -110 Vrr:Ripple Voltage on HVDD -120 20 100 1k -40 -50 -60 -70 -80 -90 -100 -110 -120 10k 20k VDD=5.0V HVDD=3.3V RL=10k Ci=1F Vrr=0.2Vrms HP Mode -30 Vrr:Ripple Voltage on HVDD 20 100 PSRR vs. Frequency VDD=5.0V IO=10mA Vrr=0.2Vrms LDO Mode LDO Mode 4.79 Output Voltage (Volt) Power Supply Rejection Ratio (dB) 4.80 -30 -40 -50 -60 -70 -80 10k 20k LDO Output Voltage vs. Supply Voltage +0 -20 1k Frequency (Hz) Frequency (Hz) -10 10k 20k -20 Power Supply Rejection Ratio (dB) Power Supply Rejection Ratio (dB) -20 1k Frequency (Hz) Frequency (Hz) 4.78 4.76 IO=10mA 4.75 4.74 IO=60mA IO=120mA 4.73 4.71 Vrr:Ripple Voltage on VDD 20 100 1k 4.70 5 10k 20k Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 5.1 5.2 5.3 5.4 5.5 Supply Voltage (Volt) Frequency (Hz) 12 www.anpec.com.tw APA2059 Typical Operating Characteristics (Cont.) (TA = +25C, unless otherwise noted.) Power Dissipation vs. Output Power 1.0 1.8 0.9 1.6 0.8 1.4 Power Dissipation (W) Power Dissipation (W) Power Dissipation vs. Output Power 2.0 VDD=5.5V 1.2 VDD=5.0V 1.0 VDD=4.5V 0.8 0.6 RL=4 fin=1kHz Mono AMP Mode 0.4 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 0.7 0.6 VDD=5.5V 0.5 VDD=5.0V 0.4 VDD=4.5V 0.3 0.1 0.0 0.0 3.0 0.5 Output Power vs. Supply Voltage Power Dissipation vs. Output Power 3.0 300 RL=4 AV=10dB fin=1kHz Mono AMP Mode 2.8 2.6 RL=16 Output Power (W) Power Dissipation (mW) 250 200 150 RL=32 100 0 0 VDD=5.0V HVDD=3.3V fin=1kHz Mono HP Mode 25 50 75 100 125 150 175 2.4 THD+N=10% 2.2 2.0 1.8 THD+N=1% 1.6 1.4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 200 Output Power (mW) Supply Voltage (V) Output Power vs. Supply Voltage Output Power (W) 1.8 Supply Current vs. Output Power 0.8 RL=8 AV=10dB fin=1kHz Mono AMP Mode VDD=5.5V 0.7 Supply Current (A) 2.0 1.0 Output Power (W) Output Power (W) 50 RL=8 fin=1kHz Mono AMP Mode 1.5 2.0 0.2 1.6 THD+N=10% 1.4 1.2 THD+N=1% VDD=5.0V VDD=4.5V 0.6 0.5 0.4 0.3 RL=4 AV=10dB fin=1kHz Mono AMP Mode 0.2 1.0 0.1 0.8 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 0.0 0.0 5.3 5.4 5.5 Supply Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 0.5 1.0 1.5 2.0 2.5 3.0 Output Power (W) 13 www.anpec.com.tw APA2059 Typical Operating Characteristics (Cont.) (TA = +25C, unless otherwise noted.) Output Power vs. Load Resistance Supply Current vs. Output Power 2.6 0.50 VDD=5.5V 2.2 VDD=5.0V 0.35 Output Power (W) Supply Current (A) 0.40 VDD=4.5V 0.30 0.25 0.20 0.15 RL=8 AV=10dB fin=1kHz Mono AMP Mode 0.10 0.05 0.00 0.0 0.5 1.0 Output Power (W) 1.5 2.0 1.8 1.6 250 1.2 1.0 0.8 THD+N=1% 0.6 0.4 2.0 4 8 12 16 20 24 28 32 Load Resistance () 11 VDD=5.0V HVDD=3.3V fin=1kHz Mono HP Mode 10 Supply Current (mA) 200 THD+N=10% 1.4 Output Power vs. Load Resistance Output Power (W) VDD=5.0V AV=10dB fin=1kHz Mono AMP Mode 2.4 0.45 150 THD+N=10% 100 THD+N=1% 50 Supply Current (IVDD) vs. Supply Voltage (VDD) HVDD=3.3V No Load 9 8 AMP,HP enable (IHVDD=2.2mA) 7 6 AMP enable (IHVDD=0.1mA) HP enable (IHVDD=2.2mA) 5 0 10 100 4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 1000 Load Resistance () 3.0 Supply Current (mA) 2.5 Supply Voltage(V) Supply Current (IHVDD) vs. Supply Voltage (HVDD) VDD=5.0V No Load 2.0 1.5 AMP,HP enable (IVDD=9.3mA) HP enable (IVDD=5.0mA) 1.0 0.5 0.0 3.3 AMP enable (IVDD=4.9mA) 3.4 3.5 3.6 Supply Voltage(V) Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 14 www.anpec.com.tw APA2059 Operating Waveforms Power On Power Off VDD VDD 1 1 2 2 VROUT VROUT 3 3 VHP_RO VHP_RO CH1: VDD, 2V/Div, DC CH2: VROUT, 20mV/Div, DC CH3: VHP_RO, 20mV/Div, DC CH1: VDD, 2V/Div, DC TIME: 5ms/Div TIME: 20ms/Div CH2: VROUT, 20mV/Div, DC CH3: VHP_RO, 20mV/Div, DC Speaker Disable Speaker Enable VAMP_EN VAMP_EN 1 1 VOUTP VOUTP 2 2 CH1: VAMP_EN, 2V/Div, DC CH1: VAMP_EN, 2V/Div, DC CH2: VOUTP, 1V/Div, AC CH2: VOUTP, 1V/Div, AC TIME: 1ms/Div TIME: 5ms/Div Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 15 www.anpec.com.tw APA2059 Operating Waveforms (Cont.) Headphone Disable Headphone Enable VHP_EN VHP_EN 1 1 VHP_RO VHP_RO 2 2 CH1: VHP_EN, 2V/Div, DC CH1: VHP_EN, 2V/Div, DC CH2: VHP_LO, 1V/Div, AC CH2: VHP_LO, 1V/Div, AC TIME: 5ms/Div TIME: 1ms/Div LDO Power On LDO Power Off VDD V DD 1 1 VLDOUT VLDOUT 2 2 IO=120mA IO=120mA CH1: VDD, 2V/Div, DC CH1: VDD, 2V/Div, DC CH2: VLDOUT, 2V/Div, DC CH2: VLDOUT, 2V/Div, DC TIME: 10ms/Div TIME: 20ms/Div Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 16 www.anpec.com.tw APA2059 Operating Waveforms (Cont.) LDO Enable LDO Disable VLDO_EN VLDO_EN 1 1 VLDOUT VLDOUT 2 2 IO=120mA CH1: VLDO_EN, 2V/Div, DC CH1: VLDO_EN, 2V/Div, DC CH2: VLDOUT, 2V/Div, DC CH2: VLDOUT, 2V/Div, DC TIME: 200s/Div TIME: 1ms/Div IO=120mA LDO Line Transient LDO Load Transient ILDOUT V DD 1 1 2 2 V LDOUT VLDOUT CH1: ILDOUT, 50mA/Div, DC CH2: VLDOUT, 5mV/Div, DC VLDOUT Offset = 4.75V TIME: 200s/Div CH1: VDD, 200mV/Div, DC VDD Offset = 5.0V CH2: VLDOUT, 5mV/Div, DC VLDOUT Offset = 4.75V TIME: 200s/Div Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 17 www.anpec.com.tw APA2059 Operating Waveforms (Cont.) GSM Power Supply Rejection vs. Frequency GSM Power Supply Rejection vs. Time 1 AMP Output Voltage (dBV) -50 V ROUT 2 V HP_RO 3 CH1: VDD, 500mV/Div, DC VDD Offset = 5.0V CH2: VROUT , 20mV / Div, DC -100 -150 +0 Supply Voltage (dBV) +0 VDD -50 -100 -150 0 400 800 1.2k 1.6k 2k Frequency (Hz) CH3: VHP_RO , 20mV / Div, DC TIME: 2ms/Div +0 -50 HP Output Voltage (dBV) -100 -150 +0 Supply Voltage (dBV) GSM Power Supply Rejection vs. Frequency -50 -100 -150 0 400 800 1.2k 1.6k 2k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 18 www.anpec.com.tw APA2059 Pin Description PIN I/O/P FUNCTION NO. NAME 1 RINN_A I The inverting input pin of right channel power amplifier. 2 RINP_A I The non-inverting input pin of right channel power amplifier. 3 LINP_A I The non-inverting input pin of left channel power amplifier. 4 LINN_A I The inverting input pin of left channel power amplifier. 5,21 PGND P Power amplifier's ground. 6 LOUTP O The positive output pin of left channel power amplifier. 7 LOUTN O The negative output pin of left channel power amplifier. 8,18 PVDD P Power amplifier's supply voltage pin, connect this pin to VDD. 9 NC - No Connection. 10 CPP I/O 11 CGND P 12 CPN I/O Charge pump flying capacitor negative connection. 13 CVSS O Charge pump output pin, connect this pin to the HVSS. 14 HVSS P Headphone driver's negative supply voltage pin, connect this pin to CVSS. 15 HP_RO O The output pin of right channel headphone driver. 16 HP_LO O The output pin of left channel headphone driver. 17 HVDD P Headphone driver's positive supply voltage pin. 19 ROUTN O The negative output pin of right channel power amplifier. 20 ROUTP O The positive output pin of right channel power amplifier. 22 HP_EN I Headphone drivers enable input pin; High=Enable. 23 AMP_EN I Power amplifiers enable input pin; High=Enable. 24 BIAS P Bias voltage for power amplifiers. 25 LDO_EN I LDO (Low Drop-Out Regulator) enables input pin; High=Enable. 26 RIN_H I The input pin of right channel headphone driver. 27 LIN_H I The input pin of left channel headphone driver. 28 GND P Control block's ground, connect this pin to CGND and PGND. 29 LDOUT O LDO (Low Drop-Out Regulator)'s output pin. 30 VDD P Control block and LDO supply voltage pin, connect this pin to PVDD. 31 GAIN0 I Control pin for internal gain setting, MSB, Bit 1. 32 GAIN1 I Control pin for internal gain setting, LSB, Bit 0. Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 Charge pump flying capacitor positive connection. Charge pump's ground. 19 www.anpec.com.tw APA2059 Block Diagram 240k LOUTP LINN_A LINP_A LOUTN GAIN1 PVDD Gain Control GAIN0 PGND ROUTN RINP_A RINN_A ROUTP 30k 20k - LIN_H HP_LO + HVDD GND HVSS + HP_RO 20k RIN_H VDD PVDD LDO Charge Pump 30k AMP_EN CPP HP_EN Control LDO_EN CPN BIAS Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 VDD LDOUT 20 CVSS CGND www.anpec.com.tw APA2059 Typical Application Circuit Differential input mode VDD Regulator Output CO2 CO1 CS3 Ci5* 1F Gnd 1F Gain Control (Amplifier) Ci1 RINN_A 0.47F Ci2 RINP_A 0.47F Ci3 LINP_A 0.47F Ci4 LINN_A 0.47F Right Channel Input Signal (Amplifier) Left Channel Input Signal (Amplifier) 25 LDO_EN 26 RIN_H 27 LIN_H 28 GND 29 LDOUT 1 CB 24 BIAS 2 23 AMP_EN 3 22 HP_EN 4 21 PGND APA2059 Gnd 20 ROUTP LOUTP 6 19 ROUTN LOUTN 7 18 PVDD PVDD 8 17 HVDD VDD Gnd Power Amplifier Enable Headphone Driver Enable 0.47F PGND 5 Gnd 30 VDD 31 GAIN0 32 GAIN1 0.1F 2.2F Headphone Driver Input Signals Regulator Enable Ci6* 1F VDD HVDD CPO 1F HP_LO 16 HP_RO 15 CS5 0.1F Gnd Headphone Jack 1F HVSS 14 0.1F 10F CVSS 13 CPF CPN 12 CPP 10 CS1 CS2 CGND 11 NC 9 CS4 2.2F VSS Gnd Tip Sleeve Ring Single-ended input mode VDD Regulator Output CO2 CO1 Ci5* 1F Gnd 1F Gain Control (Amplifier) Ci1 Right Channel GndC Input Signal i2 (Amplifier) C Left i3 Channel Ci4 Input Signal (Amplifier) Gnd Gnd 26 RIN_H 27 LIN_H 28 GND 29 LDOUT 30 VDD 31 GAIN0 32 GAIN1 0.1F 2.2F 25 LDO_EN CS3 RINN_A 1 Headphone Driver Input Signals Regulator Enable Ci6* 1F 24 BIAS 0.47F CB Gnd Power Amplifier Enable Headphone Driver Enable 0.47F 23 AMP_EN RINP_A 2 0.47F LINP_A 3 22 HP_EN 0.47F LINN_A 4 21 PGND APA2059 0.47F PGND 5 LOUTP 6 19 ROUTN LOUTN 7 18 PVDD PVDD 8 17 HVDD VDD Gnd 20 ROUTP VDD HVDD CPO 1F HP_LO 16 HP_RO 15 HVSS 14 VSS Gnd Note *If using MLCC type capacitor for low frequency performance, 3.3F is recommended. Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 Tip Sleeve 21 CS5 0.1F Gnd Headphone Jack 1F CPN 12 CPF CVSS 13 0.1F 10F CGND 11 CS1 CPP 10 CS2 NC 9 CS4 2.2F Ring www.anpec.com.tw APA2059 Function Description Fully Differential Amplifier The Cap-free headphone drivers use a charge pump to The APA2059's power amplifier is a fully differential amplifier with differential inputs and outputs. The fully invert the positive power supply (VDD) to the negative power supply (VSS) (see Figure 1). The headphone amplifiers differential amplifier has some advantages versus traditional amplifier. Firstly, don't need the input coupling ca- operate at this bipolar power supply, and the outputs reference refers to the ground. This feature eliminates the pacitors because the common-mode feedback will compensate the input bias. The inputs can be biased from output capacitor that using in conventional single-ended headphone amplifiers. In addition, the power supply rail 0.5V to VDD-0.5V, and the outputs are still biased at midsupply voltage of the power amplifier. If the inputs are for Cap-free headphone drivers has almost 1.5X compare to the single power supply rail headphone drivers. biased out of the input range, the coupling capacitors are required. Secondly, the fully differential amplifier has out- Thermal Protection The thermal protection circuit limits the junction temperature of the APA2059. When the junction tempera- standing immunity against supply voltage ripple (217Hz) caused by GSM RF transmitters' signal, which is better ture exceeds TJ = +150oC, a thermal sensor turns off the amplifier, allowing the devices to cool. The thermal sen- than the typical audio amplifier. Gain Setting Function For the convenient uses, the APA2059's power amplifiers provide four gain setting options by GAIN0 and GAIN1 sor allows the amplifier to start-up after the junction temperature down about 125 oC. The thermal protection is designed with a 25 o C hysteresis to lower the average TJ during continuous thermal overload conditions, increas- pins. ing lifetime of the ICs. GAIN0 GAIN1 AV(dB) Ri(k) Rf(k) 0 0 10 76 240 Over-Current Protection (OCP) 0 1 12 60 240 * The power amplifier monitors the output buffers'current. 1 0 15.6 40 240 1 1 21.6 20 240 When the over-current occurs, the output buffers'current will be reduced and limited to a fold-back current level. The power amplifier will go back to normal operation until the over-current current situation has been removed. In Headphone Mode Operation VOUT Conventional Headphone Driver HVDD addition, if the over-current period is long enough and the IC's junction temperature reaches the thermal protection HVDD/2 threshold, the IC enters thermal protection mode. * The LDO regulator provides a current-limit circuitry, which monitors and controls P-channel MOS's gate Gnd voltage, limiting the output current to 0.4A. For reliable operation, the device should not be operated in current- HVDD VOUT limit for extended period time. When the output voltage drops below 0.6V, which is caused by the over load or short circuit, the internal short circuit current-limit circuitry limits the output current down to 250mA. The short circuit Gnd current-limit is used to reduce the power dissipation during short circuit condition. The short circuit current-limit Cap-free Headphone Driver VSS has a blanking time feature after the under-voltage lockout threshold is reached, therefore, it will avoid the output Figure 1: The Cap-Free Headphone Driver's Operation Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 causing short circuit current-limit protection during startup; the blanking time is about 600s. 22 www.anpec.com.tw APA2059 Function Description (Cont.) Over-Current Protection (OCP) (Cont.) * The charge pump monitors the output voltage (V SS ). In addition, it has an over-voltage protection to avoid overcurrent occuring on headphone driver's output. When the output voltage (VSS) is greater than -2V, the charge pump will turn off the charge pump's output. The charge pump's output will turn on again if the situation has been removed. Typical under voltage protection threshold is -2V with 0.5V hysteresis. Low Drop-Out (LDO) Regulator The LDO regulator's output provides maximum 120mA drive capacity for external audio codec. A 2.2F decoupling capacitor with 0.1f capacitor (filtering the high frequency noise) is recommended at LDO regulator`s output. The LDO regulator has built-in under-voltage lockout circuits to keep the output shutting off until internal circuitry is operating properly. The under-voltage lockout function initiates a soft-start process after input voltage exceeds its rising under-voltage lockout threshold during power on. The internal soft-start circuit controls the rise rate of the output voltage and limits the current surge during startup. Approximate 20s delay time after the VDD is over the under-voltage lockout threshold; the LDO regulator's output voltage starts the soft-start. The typical soft-start interval is about 130s and the under-voltage lockout threshold is 2.5V with 0.15V hysteresis. Enable Mode The APA2059 provides the independent enable control functions and allows user disable any main circuit blocks when not in using, and these can save the power consumption. In addition, if either the power amplifier or the headphone driver is disabled, the released time will happen immediately when enable the power amplifier or the headphone driver. However, if both the power amplifier and the headphone driver are disabled at the same time, the released time will be the TSTART-UP Time when enable one of them. Disable all blocks ( V AMP_EN=VHP_EN= VLDO_EN=0V), The APA2059 enters the shutdown mode, and only consumption 5A(Max.) at VDD supply current and 2A(Max.) at HVDD supply current. Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 23 www.anpec.com.tw APA2059 Application Information Windows VistaTM Premium Mobile Requirement Device Type Requirement Value Full Scale Output voltage THD+N Analog Line Output Jack (RL=10k) Line output cross-talk Noise level during system activity Full Scale Output voltage Analog Headphone Output Jack (RL=320) THD+N Analog Headphone Output Jack (RL=32) THD+N Headphone output cross-talk Noise level during system activity Full Scale Output voltage Headphone output cross-talk Noise level during system activity 0.707Vrms -65dBFS 20Hz~20kHz -50dB, 20Hz~15kHz -80dBFS A-weighting 0.707Vrms -65dBFS 100Hz~20kHz -50 dB 100Hz~15kHz -80dBFS A-weighting 0.3Vrms -45dBFS 100Hz~20kHz -50dB 100Hz~15kHz -80dBFS A-weighting APA2059 typical performance 2.3Vrms -70dB 20Hz~20kHz -70dB 20Hz~20kHz -100dBFS A-weighting 2.3Vrms -78dB 100Hz~20kHz -75 dB 100Hz~15kHz -100dBFS A-weighting 2.0Vrms -68dB 100Hz~20kHz -70 dB 100Hz~15kHz -100dBFS A-weighting Input Capacitor (Ci) leakage tantalum or ceramic capacitor is the best choice. In the typical application, an input capacitor, Ci, is required When polarized capacitors are used, the positive side of the capacitors should face the amplifiers' inputs in most to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the applications because the DC level of the amplifiers' inputs are held at VDD/2. Please note that it is important to minimum input impedance Ri form a high-pass filter with the corner frequency is determined in the following equation: fC(highpass ) = 1 2 R iC i confirm the capacitor polarity in the application. Power Supply Decoupling Capacitor, Cs (1) The APA2059 is a high-performance CMOS audio ampli- The value of Ci must be considered carefully because it directly affects the low frequency performance of the circuit. fier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) to be Consider the example where Ri is 20k and the specification calls for a flat bass response down to 40Hz. The as low as possible. Power supply decoupling also prevents the oscillations caused by long lead length between equation is reconfigured below : 1 Ci = 2 R i fc the amplifier and the speaker. The optimum decoupling is achieved by using two different types of capacitors that target on different types of (2) When input resistance varation is considered, the value of Ci is 0.2F. Therefore, a value in the range from 0.22F noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low to 1.0F would be chosen. A further consideration for this capacitor is the leakage path from the input source through equivalent-series-resistance (ESR) ceramic capacitor, (0.1F typically) placed as close as possible to the device the input network (Ri + Rf, Ci) to the load. VDD lead works best. This leakage current creates a DC offset voltage at the For filtering lower frequency noise signals, a large aluminum electrolytic capacitor of 10F or greater placed near input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a lowCopyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 the audio power amplifier is recommended. 24 www.anpec.com.tw APA2059 Application Information (Cont.) Charge Pump Flying Capacitor (CPF) 2. The output traces should be short, wide ( >50mil), and The flying capacitor affects the load transient of the charge pump. If the capacitor's value is too small, it will degrade symmetric. 3. The input trace should be short and symmetric. the charge pump's current driver capability and the performance of headphone amplifier. Increasing the flying 4. The power trace width should greater than 50 mil. 5. The TQFN5x5-32 thermal pad should be soldered on PCB, and the ground plane needs solded mask (to capacitor's value will improve the load transient of charge pump. Recommend using the low ESR ceramic capaci- avoid short circuit) except the thermal pad area. tors (X5R type is recommended) above 1f. Charge Pump Output Capacitor (CPO) The output capacitor's value affects the power ripple directly at VSS. Increasing the value of output capacitor will reduce the power ripple. The ESR of output capacitor affects the load transient of VSS. Low ESR and greater than 1f ceramic capacitor (X5R type is recommended) is recommendation. Layout Recommendation ThermalVia diameter 0.3mm X 9 1.15mm 0.25mm 3.6mm 4.1mm 0.5mm 3.6mm Solder Mask to Prevent Short Circuit TQFN5X5-32 Land Pattern Recommendation Ground plane for ThermalP AD Figure 5. TQFN5X5-32 Land Pattern Recommendation 1. All components should be placed close to the APA2059. For example, the input capacitor (Ci) should be close to APA2059's input pins to avoid causing noise coupling to APA2059's high impedance inputs; the decoupling capacitor (CS ) should be placed by the APA2059's power pin to decouple the power rail noise. Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 25 www.anpec.com.tw APA2059 Package Information TQFN5x5-32 D b E A D2 A1 A3 L K E2 Pin 1 Corner e S Y M B O L TQFN5x5-32 MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF b 0.18 0.30 0.007 0.012 D 4.90 5.10 0.193 0.201 D2 3.10 3.50 0.122 0.138 E 4.90 5.10 0.193 0.201 E2 3.10 3.50 0.122 0.138 e 0.50 BSC L 0.35 K 0.20 Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 0.020 BSC 0.014 0.45 0.018 0.008 26 www.anpec.com.tw APA2059 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TQFN5x5-32 A H 330.02.00 50 MIN. P0 P1 4.00.10 T1 C 12.4+2.00 13.0+0.50 -0.00 -0.20 8.00.10 P2 D0 2.00.10 1.5+0.10 -0.00 d D 1.5 MIN. 20.2 MIN. W E1 12.00.30 1.750.10 F 5.50.10 D1 T A0 B0 K0 1.5 MIN. 0.6+0.00 -0.40 5.300.20 5.300.20 1.300.20 (mm) Devices Per Unit Package Type Unit Quantity TQFN5x5-32 Tape & Reel 2500 Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 27 www.anpec.com.tw APA2059 Taping Direction Information TQFN5x5-32 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 28 www.anpec.com.tw APA2059 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 C 150 C 60-120 seconds 150 C 200 C 60-120 seconds 3 C/second max. 3C/second max. 183 C 60-150 seconds 217 C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 C/second max. 6 C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process - Classification Temperatures (Tc) 3 Package Thickness <2.5 mm Volume mm <350 235 C Volume mm 350 220 C 2.5 mm 220 C 220 C 3 Table 2. Pb-free Process - Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm - 2.5 mm 2.5 mm Volume mm <350 260 C 260 C 250 C 3 Volume mm 350-2000 260 C 250 C 245 C 3 Volume mm >2000 260 C 245 C 245 C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 29 Description 5 Sec, 245C 1000 Hrs, Bias @ Tj=125C 168 Hrs, 100%RH, 2atm, 121C 500 Cycles, -65C~150C VHBM2KV VMM200V 10ms, 1tr100mA www.anpec.com.tw APA2059 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.5 - Feb., 2010 30 www.anpec.com.tw