Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
2.4W Stereo Fully Differential Audio Power Amplifier With Stereo Class AB
Cap-free Headphone Driver and LDO
APA2059
FeaturesGeneral Description
Applications
• LCD Monitor
• Notebook
• Portable DVD
• Meeting VISTATM Requirement
• Fully Differential Power Amplifier with
Excellent RF Rectification Immunity
• No Output Capacitor Required for Head
Phone Driver
• Integrated LDO (Low Dropout Regulator) for
Audio Codec (4.75V)
• Adjustable Gain Setting for Power Amplifier
• AV=-1.5V/V Fixed Gain Setting for Headphone
Driver
• Fast Start-up Time
• Integrated De-Pop Circuitry
• High PSRR (Power Supply Rejection Ratio)
• Thermal and Over-Current Protections
• Less External Components Required
• Space Saving Package
– TQFN5x5-32
• Lead Free and Green Devices Available
(RoHS Compliant)
Simplified Application Circuit
The APA2059 is a stereo fully differential audio power
amplifier with stereo Class-AB cap-free headphone driver
and LDO available in a TQFN5X5-32 pins package.
The built-in gain setting at power amplifier can minimize
the external component counts. For the flexible application,
the gain can be set to 4-steps, 10, 12, 15.6, and 21.6dB by
gain control pins (GAIN0 and GAIN1). The power amplifier’s
fully differential architecture provides high PSRR, in-
creased immunity to noise and RF rectification.
The APA2059 power amplifiers are capable of driving
2.4W at VDD=5V into 4Ω speaker, the cap-free headphone
drivers can provide 180mW at HVDD=3.3V into16Ω
headphones, and the LDO has a maximum 120mA
(4.75V) driver current for audio codec. The APA2059 pro-
vides thermal and over-current protections.
The cap-free headphone driver eliminates the DC block-
ing capacitors at outputs and saves the PCB space. The
integration of fully differential power amplifier, cap-free
headphone driver, and LDO is a best solution for VISTATM
requirement and it can lower the total BOM costs.
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k100 1k 10k
Common Mode Rejection Ratio (dB)
Frequency (Hz)
VDD=5.0V
RL=4Ω
AV=10dB
Vin=0.2VPP
Ci=0.47µF
Input Short
AMP Mode
Audio
Codec
Stereo
Speakers
Stereo
Headphone
LDO (Low Drop
-Out Regulator)
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw2
APA2059
Pin Configuration
Absolute Maximum Ratings (Note 1)
Symbol
Parameter Rating Unit
VDD Supply Voltage (VDD to GND, PVDD to PGND) -0.3 to 6
HVDD Supply Voltage (HVDD to GND) -0.3 to 6
VSS Supply Voltage (HVSS, CVSS to GND) -6 to +0.3
Input Voltage (RINN_A, RINP_A, LINN_A, LINP_A to GND) -0.3 to VDD+0.3
Input Voltage (RIN_H, LIN_H to GND) VSS-0.3 to HVDD+0.3
Input Voltage (GAIN0, GAIN1, LDO_EN, AMP_EN, HP_EN to GND) -0.3 to VDD+0.3
Input Voltage (PGND, CGND to GND) -0.3 to +0.3
V
Ordering and Marking Information
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
LOUTP 6
RINN_A 1
RINP_A 2
LINP_A 3
LINN_A 4
PGND 5
LOUTN 7
PVDD 8
LDO_EN 25
RIN_H 26
LIN_H 27
GND 28
LDOUT 29
VDD 30
GAIN0 31
GAIN1 32
16 HP_LO
15 HP_RO
14 HVSS
13 CVSS
12 CPN
11 CGND
10 CPP
9 NC
17 HVDD
18 PVDD
19 ROUTN
20 ROUTP
21 PGND
22 HP_EN
23 AMP_EN
24 BIAS
=Thermal-Pad (connected the Thermal-Pad to GND plane for better heat dissipation)
TQFN5x5-32
(Top View)
APA2059
Handling Code
Temperature Range
Package Code
XXXXX - Date Code
Assembly Material
APA2059 QB : APA2059
XXXXX
Package Code
QB : TQFN5x5-32
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw3
APA2059
Recommended Operating Conditions
Symbol Parameter Range Unit
VDD Supply Voltage 4.5 ~ 5.5
HVDD Supply Voltage 3.0 ~ 5.5
VIH
High Level Input Voltage
GAIN0, GAIN1, LDO_EN, AMP_EN, HP_EN
2 ~ VDD
VIL
Low Level Input Voltage
GAIN0, GAIN1, LDO_EN, AMP_EN, HP_EN
0 ~ 0.5
For Power Amplifier 0.5 ~ VDD-0.5
VIC Common Mode Input Voltage
For Headphone Amplifier HVSS ~ HVDD
V
ILDOUT Output Current (LDOUT) 0 ~ 200 mA
TA Ambient Temperature Range -40 ~ 85
TJ Junction Temperature Range -40 ~ 125 οC
COUT LDO Output Capacitor (MLCC type) 1 ~ 100 µF
RL Speaker Resistance 4 ~
RL Headphone Resistance 16 ~ Ω
Thermal Characteristics
Symbol
Parameter Typical Value Unit
θJA Thermal Resistance -Junction to Ambient (Note 2) TQFN5X5-32
40 οC/W
θJC Thermal Resistance -Junction to Case (Note 3) TQFN5X5-32
8 οC/W
Note 2: Please refer to “ Layout Recommendation”, the Thermal-Pad on the bottom of the IC should soldered directly to the PCB’s
Thermal-Pad area that with several thermal vias connect to the ground plan, and the PCB is a 2-layer, 5-inch square area with
2oz copper thickness.
Note 3: The case temperature is measured at the center of the Thermal-Pad on the underside of the TQFN5X5-32 package.
Absolute Maximum Ratings (Cont.) (Note 1)
Symbol
Parameter Rating Unit
TJ Maximum Junction Temperature 150
TSTG Storage Temperature Range -65 to +150
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260
οC
PD Power Dissipation Internally Limited W
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw4
APA2059
Electrical Characteristics
Refer to the typical application circuits. VDD=5V, HVDD=3.3V, Gnd=0V, TA=25oC (unless otherwise noted)
APA2059
Symbol
Parameter Test Conditions Min.
Typ.
Max.
Unit
IDD(HVDD) HVDD
- 2.5 5
IDD(VDD) Supply Current VAMP_EN =VHP_EN=VLDO_EN=5V VDD - 9 18
IAMP(HVDD)
HVDD
- 0.1 0.2
IAMP(VDD) Power Amplifier Supply Current VAMP_EN=5V,
VHP_EN=VLDO_EN=0V VDD - 4.5 11
IHP(HVDD) HVDD
- 2.5 5
IHP(VDD) Headphone Driver Supply Current VHP_EN=5,
VAMP_EN=VLDO_EN=0V VDD - 6 12
ILDO(HVDD) HVDD
- 0.1 0.2
ILDO(VDD) LDO Supply Current VLDO_EN=5V,
VAMP_EN =VHP_EN=0V VDD - 0.4 0.65
mA
ISD(HVDD) HVDD - - 2
ISD(VDD) Shutdown Current VAMP_EN =VHP_EN=VLDO_EN=0V VDD - - 5
II Input Current GAIN0, GAIN1, LDO_EN, AMP_EN,
HP_EN - - 1
µA
SPEAKER MODE, AV =10dB
TSTART-UP Start-Up Time from Shutdown CB=0.47µF - 25 - ms
AV=10dB - 76 -
AV=12dB - 60 -
AV=15.6dB - 40 -
Ri Input Resistor
AV=21.6dB 17 20 -
kΩ
VGAIN0=VGAIN1=0V. 9.5 10 10.5
VGAIN0=0V, VGAIN1=VDD. 11.5
12 12.5
VGAIN0=VDD, VGAIN1=0V. 15.1
15.6
16.1
AV Closed-Loop Gain
VGAIN0=VGAIN1=VDD. 21.1
21.6
22.1
dB
VOS Output Offset Voltage RL = 8Ω - 5 20 mV
THD+N=1%, fin=1kHz
RL=4Ω
RL=8Ω
1
1.9
1.3 -
PO Output Power THD+N=10%, fin=1 kHz
RL=4Ω
RL=8Ω -
2.4
1.5 -
W
THD+N
Total Harmonic Distortion Plus
Noise
fin=1kHz
RL=4Ω, PO=1.4W
RL=8Ω, PO=0.9W -
0.07
0.05
- %
Crosstalk
Channel Separation fin=1kHz
RL=4Ω, Po=200mW
RL=8Ω, Po=130mW -
-110
-110
-
PSRR Power Supply Rejection Ratio fin=217Hz, Vrr=0.2Vrms,RL=8Ω - -75 -
CMRR Common Mode Rejection Ratio fin=1kHz, Vin=0.2Vrms.,RL=8Ω - -65 -
S / N Signal-to-Noise Ratio fin=20~20kHz With A-weighting Filter
RL=4Ω, PO=1.4W,
RL=8Ω, PO=0.9W, -
100
100
-
dB
Vn Noise Output Voltage fin=20~20kHz,With A-weighting Filter
RL=8Ω - 22 - µVrms
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw5
APA2059
Electrical Characteristics (Cont.)
APA2059
Symbol Parameter Test Conditions Min.
Typ. Max.
Unit
HEADPHONE MODE, AV = -1.5V/V, CPF=CPO=1µF(X5R TYPE)
TSTART-UP Start-Up Time from Shutdown CB=0.47µF - 10 - ms
Ri Input Resistor 17 20 - kΩ
AV Closed-Loop Gain -1.45
-1.5 -1.55 V/V
VOS Output Offset Voltage RL = 32Ω - 1 5 mV
THD+N=1%, fin=1kHz
RL=16Ω
RL=32Ω
100
140
120 -
PO Output Power THD+N=10%, fin=1kHz
RL=16Ω
RL=32Ω
150
180
160 -
mW
THD+N=1%, fin=1kHz
RL=320Ω
RL=10kΩ
1.8
2.0
2.1 -
VO Output Swing Voltage THD+N=10%, fin=1kHz
RL=320Ω
RL=10kΩ -
2.45
2.6 -
V
THD+N Total Harmonic Distortion Plus
Noise
fin=1kHz
RL=16Ω, PO=125mW
RL=32Ω, PO=88mW
RL=320Ω, VO=1.5V
RL=10kΩ, VO=1.6V
-
0. 03
0. 02
0. 005
0. 004
- %
Crosstalk Channel Separation
fin=1kHz
RL=16Ω, PO=16mW
RL=32Ω, PO=12mW
RL=320Ω, VO=0.22V
RL=10kΩ, VO=0.22V
-
-82
-82
-77
-77
-
PSRR Power Supply Rejection Ratio fin=217Hz,Vrr=0.2Vrms
RL=32Ω - -80 -
S/N Signal-to-Noise Ratio
fin=20~20kHz, With A-weighting Filter
RL=16Ω, PO=125mW
RL=32Ω, PO=88mW
RL=320Ω, VO=1.5V
RL= 10kΩ, VO=1.6V
-
99
100
100
100
-
dB
Vn Noise Output Voltage fin=20~20kHz, With A-weighting Filter
RL=32Ω - 15 - µVrms
LDO (LOW DROP-OUT REGULATOR)
VDD Supply Voltage 4.9 5.0 5.5 V
IO Output Current - - 120 mA
VO Output Voltage IO=1mA 4.65 4.75 4.85 V
Line Regulation IO=1mA, VDD=5.0V to 5.5V - 3 10 mV
Load Regulation IO=1mA to 120mA - 0.06 0.2 mV/mA
VDROP Dropout Voltage IO=120mA 80 100 mV
PSRR Power Supply Rejection Ratio
IO=1mA,fin=120Hz,Vrr=0.2Vrms - -50 - dB
RDIS Discharge Resistor - 50 - kΩ
Refer to the typical application circuits. VDD=5V, HVDD=3.3V, Gnd=0V, TA=25oC (unless otherwise noted)
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw6
APA2059
Electrical Characteristics (Cont.)
APA2059
Symbol Parameter Test Conditions Min.
Typ. Max.
Unit
CHARGE PUMP, CPF=CPO=1µF(X5R type)
FOSC Oscillator Frequency - 450 - kHz
REQ Equivalent Resistance - 10 - Ω
CVss Negative Output Voltage No load -5.1 -5 -4.9 V
RDIS Discharge Resistor - 5 - kΩ
Refer to the typical application circuits. VDD=5V, HVDD=3.3V, Gnd=0V, TA=25oC (unless otherwise noted)
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw7
APA2059
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
0.01
10
0.1
1
10m 5100m 1
THD+N (%)
Output Power (W)
THD+N vs. Output Power
VDD=4.5V
VDD=5.0V
VDD=5.5V
RL=4Ω
fin=1kHz
Ci=0.47µF
AV=10dB
BW<22kHz
AMP Mode
0.001
1
0.01
0.1
20 20k100 1k 10k
THD+N vs. Frequency
Frequency (Hz)
VDD=5.0V
RL=4Ω
Ci=0.47µF
AV=10dB
BW<22kHz
AMP Mode
THD+N (%)
PO=0.14W
PO=0.7W
PO=1.4W
-140
+0
-120
-100
-80
-60
-40
-20
20 20k100 1k 10k
TT TTTTTTT Crosstalk vs. Frequency
Crosstalk (dB)
Frequency (Hz)
Left to Right
Right to Left
VDD=5.0V
RL=4Ω
AV=10dB
Ci=0.47µF
PO=200mW
AMP Mode
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k100 1k 10k
CMRR vs. Frequency
Common Mode Rejection Ratio (dB)
Frequency (Hz)
VDD=5.0V
RL=4Ω
AV=10dB
Vin=0.2VPP
Ci=0.47µF
Input Short
AMP Mode
0.01
10
0.1
1
10m 5100m 1
THD+N (%)
Output Power (W)
THD+N vs. Output Power
VDD=4.5V
VDD=5.0V
VDD=5.5V
RL=8Ω
fin=1kHz
Ci=0.1µF
AV=10dB
BW<22kHz
AMP Mode
0.001
1
0.01
0.1
20 20k100 1k 10k
THD+N vs. Frequency
Frequency (Hz)
THD+N (%)
VDD=5.0V
RL=8Ω
AV=10dB
Ci=0.47µF
BW<22kHz
AMP Mode
PO=0.09W
PO=0.45W
PO=0.9W
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw8
APA2059
Typical Operating Characteristics (Cont.)
(TA = +25°C, unless otherwise noted.)
-140
+0
-120
-100
-80
-60
-40
-20
20 20k100 1k 10k
TTT TTTTT
Crosstalk vs. Frequency
Crosstalk (dB)
Frequency (Hz)
Left to Right
Right to Left
VDD=5.0V
RL=8Ω
AV=10dB
Ci=0.47µF
PO=130mW
AMP Mode
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k100 1k 10k
CMRR vs. Frequency
Common Mode Rejection Ratio (dB)
Frequency (Hz)
VDD=5.0V
RL=8Ω
AV=10dB
Vin=0.2VPP
Ci=0.47µF
Input Short
AMP Mode
+140
+220
+160
+180
+200
+7
+11
+8
+9
+10
10 200k100 1k 10k
Frequency Response
Frequency (Hz)
Gain (dB)
Phase (deg)
VDD=5.0V
RL=8Ω
AV=10dB
Ci=0.47µF
AMP Mode
Gain
Phase
+140
+220
+160
+180
+200
+18
+22
+19
+20
+21
10 200k100 1k 10k
Frequency Response
Frequency (Hz)
Gain (dB)
Phase (deg)
VDD=5.0V
RL=8Ω
AV=21.6dB
Ci=0.47µF
AMP Mode
Gain
Phase
20 20k100 1k 10k
Output Noise Voltage vs.
Frequency
Output Noise Voltage (Vrms)
Frequency (Hz)
VDD=5.0V
RL=8Ω
AV=10dB
Cin=0.47µF
A-Wighting
AMP Mode
Left channel
Right channel
50µ
10µ
1µ-140
+0
-120
-100
-80
-60
-40
-20
20 20k100 1k 10k
Crosstalk vs. Frequency
Crosstalk (dB)
Frequency (Hz)
Right(AMP) to Right(HP)
VDD=5.0V
HVDD=3.3V
RL=4Ω(AMP)
RL=10kΩ(HP)
PO=200mW(AMP)
AMP(active) mode
HP mode
Left(AMP) to Right(HP)
Left(AMP) to Left(HP) Right(AMP) to Left(HP)
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw9
APA2059
Typical Operating Characteristics (Cont.)
(TA = +25°C, unless otherwise noted.)
0.01
10
0.1
1
10m 500m100m
THD+N (%)
Output Power (W)
THD+N vs. Output Power
In Phase Mono
VDD=5.0V
HVDD=3.3V
RL=16Ω
fin=1kHz
Ci=1µF
BW<22kHz
HP Mode
0.001
1
0.01
0.1
20 20k100 1k 10k
THD+N vs. Frequency
Frequency (Hz)
THD+N (%)
PO=13mW
PO=63mW
PO=125mW
VDD=5.0V
HVDD=3.3V
RL=16Ω
Ci=1µF
BW<22kHz
HP Mode
0.001
10
0.01
0.1
1
0 3500m 11.5 22.5
THD+N (%)
Output Voltage (Vrms)
RL=32Ω
RL=16Ω
THD+N vs. Output Voltage
VDD=5.0V
HVDD=3.3V
fin=1kHz
Ci=1µF
BW<22kHz
In Phase
HP Mode
RL=320Ω
RL=10kΩ
-140
+0
-120
-100
-80
-60
-40
-20
20 20k100 1k 10k
Crosstalk vs. Frequency
Crosstalk (dB)
Frequency (Hz)
VDD=5.0V
HVDD=3.3V
RL=16Ω
PO=16mW
Ci=1µF
HP Mode
Left to Right
Right to Left
0.01
10
0.1
1
10m 300m100m
THD+N (%)
Output Power (mW)
THD+N vs. Output Power
Mono
In Phase
VDD=5.0V
HVDD=3.3V
RL=32Ω
fin=1kHz
Ci=1µF
BW<22kHz
HP Mode
0.001
1
0.01
0.1
20 20k100 1k 10k
THD+N vs. Frequency
Frequency (Hz)
THD+N (%)
PO=9mW
PO=44mW
PO=88mW
VDD=5.0V
HVDD=3.3V
RL=32Ω
Ci=1µF
BW<22kHz
HP Mode
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw10
APA2059
Typical Operating Characteristics (Cont.)
(TA = +25°C, unless otherwise noted.)
-140
+0
-120
-100
-80
-60
-40
-20
20 20k100 1k 10k
Crosstalk vs. Frequency
Crosstalk (dB)
Frequency (Hz)
Left to Right
Right to Left
VDD=5.0V
HVDD=3.3V
RL=32Ω
PO=12mW
Ci=1µF
HP Mode
20 20k100 1k 10k
Output Noise Voltage vs.
Frequency
Output Noise Voltage (Vrms)
Frequency (Hz)
VDD=5.0V
HDD=3.3V
RL=32Ω
Ci=1µF
A-Weighting
HP Mode
Left channel
Right channel
50µ
10µ
1µ
+140
+220
+160
+180
+200
+0
+4
+1
+2
+3
10 200k100 1k 10k
Frequency Response
Frequency (Hz)
Gain (dB)
Phase (deg)
Gain
Phase
VDD=5.0V
HVDD=3.3V
RL=32Ω
Ci=1µF
HP Mode -140
+0
-120
-100
-80
-60
-40
-20
20 20k100 1k 10k
T T
Crosstalk vs. Frequency
Crosstalk (dB)
Frequency (Hz)
VDD=5.0V
HVDD=3.3V
RL=8Ω(AMP)
RL=16Ω(HP)
PO=16mW(HP)
AMP Mode
HP(active) Mode
Right(HP) to Left(AMP)
Left(HP) to Right(AMP)
Right(HP) to Right(AMP)
Left(HP) to Left(AMP)
0.001
1
0.01
0.1
20 20k100 1k 10k
THD+N vs. Frequency
Frequency (Hz)
THD+N (%)
VO=0.15V
VO=1.5V
VO=0.75V
VDD=5.0V
HVDD=3.3V
RL=320Ω
Ci=1µF
BW<22kHz
HP Mode
-140
+0
-120
-100
-80
-60
-40
-20
20 20k100 1k 10k
Crosstalk vs. Frequency
Crosstalk (dB)
Frequency (Hz)
Left to Right
Right to Left
VDD=5.0V
HVDD=3.3V
RL=320Ω
VO=0.22Vrms
Ci=1µF
HP Mode
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw11
APA2059
Typical Operating Characteristics (Cont.)
(TA = +25°C, unless otherwise noted.)
0.001
1
0.01
0.1
20 20k100 1k 10k
THD+N vs. Frequency
Frequency (Hz)
THD+N (%)
VO=0.16V
VO=1.6V
VO=0.8V
VDD=5.0V
HVDD=3.3V
RL=10kΩ
Ci=1µF
BW<22kHz
HP Mode
Crosstalk vs. Frequency
-140
+0
-120
-100
-80
-60
-40
-20
20 20k100 1k 10k
Crosstalk (dB)
Frequency (Hz)
Left to Right
Right to Left
VDD=5.0V
HVDD=3.3V
RL=10kΩ
VO=0.22Vrms
Ci=1µF
HP Mode
20 20k100 1k 10k
Output Noise Voltage vs.
Frequency
Output Noise Voltage (Vrms)
Frequency (Hz)
Left channel
Right channel
VDD=5.0V
HDD=3.3V
RL=10kΩ
Ci=1µF
A-Weighting
HP Mode
50µ
10µ
1µ+140
+220
+160
+180
+200
+0
+4
+1
+2
+3
10 200k100 1k 10k
Frequency Response
Frequency (Hz)
Gain (dB)
Phase (deg)
VDD=5.0V
HVDD=3.3V
RL=10kΩ
Ci=0.47µF
HP Mode
Gain
Phase
-120
-10
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
20 20k100 1k 10k
AMP Attenuation vs. Frequency
Frequency (Hz)
AMP Attenuation (dB)
VDD=5.0V
RL=8Ω
AV=10dB
Ci=0.47µF
VO=2Vrms (AMP enable)
AMP Mode (disable)
Left channel
Right channel
-120
+0
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k100 1k 10k
HP Attenuation vs. Frequency
Frequency (Hz)
HP Attenuation (dB)
VDD=5.0V
HVDD=3.3V
RL=32Ω
Ci=1µF
VO=1Vrms (HP enable)
HP Mode (disable)
Left channel
Right channel
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw12
APA2059
Typical Operating Characteristics (Cont.)
(TA = +25°C, unless otherwise noted.)
-120
+0
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k100 1k 10k
HP Attenuation vs. Frequency
Frequency (Hz)
AMP Attenuation (dB)
VDD=5.0V
HVDD=3.3V
RL=10kΩ
Ci=1µF
VO=1Vrms (HP enable)
HP Mode (disable)
Left channel
Right channel
-120
-20
-110
-100
-90
-80
-70
-60
-50
-40
-30
20 20k100 1k 10k
TT T
Frequency (Hz)
VDD=5.0V
RL=8Ω
AV=10dB
Ci=0.47µF
Vrr=0.2Vrms
AMP Mode
PSRR vs. Frequency
Power Supply Rejection Ratio (dB)
Vrr:Ripple Voltage on VDD
-80
+0
-70
-60
-50
-40
-30
-20
-10
20 20k100 1k 10k
Frequency (Hz)
PSRR vs. Frequency
Power Supply Rejection Ratio (dB)
VDD=5.0V
IO=10mA
Vrr=0.2Vrms
LDO Mode
Vrr:Ripple Voltage on VDD
IO=60mA IO=120mA
IO=10mA
LDO Output Voltage vs. Supply Voltage
Supply Voltage (Volt)
Output Voltage (Volt)
4.70
4.71
4.73
4.74
4.75
4.76
4.78
4.79
4.80
55.1 5.2 5.3 5.4 5.5
LDO Mode
-120
-20
-110
-100
-90
-80
-70
-60
-50
-40
-30
20 20k100 1k 10k
Frequency (Hz)
PSRR vs. Frequency
Power Supply Rejection Ratio (dB)
Vrr:Ripple Voltage on HVDD
VDD=5.0V
HVDD=3.3V
RL=32Ω
Ci=1µF
Vrr=0.2Vrms
HP Mode
-120
-20
-110
-100
-90
-80
-70
-60
-50
-40
-30
20 20k100 1k 10k
Power Supply Rejection Ratio (dB)
VDD=5.0V
HVDD=3.3V
RL=10kΩ
Ci=1µF
Vrr=0.2Vrms
HP Mode
Vrr:Ripple Voltage on HVDD
PSRR vs. Frequency
Frequency (Hz)
Copyright ANPEC Electronics Corp.
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APA2059
Typical Operating Characteristics (Cont.)
(TA = +25°C, unless otherwise noted.)
0
50
100
150
200
250
300
025 50 75 100 125 150 175 200
Power Dissipation vs. Output Power
Power Dissipation (mW)
Output Power (mW)
VDD=5.0V
HVDD=3.3V
fin=1kHz
Mono
HP Mode
RL=32Ω
RL=16Ω
Output Power vs. Supply Voltage
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
Output Power (W)
Supply Voltage (V)
RL=4Ω
AV=10dB
fin=1kHz
Mono
AMP Mode
THD+N=10%
THD+N=1%
Supply Current vs. Output Power
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Output Power (W)
Supply Current (A)
RL=4Ω
AV=10dB
fin=1kHz
Mono
AMP Mode
VDD=4.5V
VDD=5.0V
VDD=5.5V
Output Power vs. Supply Voltage
0.8
1.0
1.2
1.4
1.6
1.8
2.0
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
Output Power (W)
Supply Voltage (V)
THD+N=10%
THD+N=1%
RL=8Ω
AV=10dB
fin=1kHz
Mono
AMP Mode
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Power Dissipation vs. Output Power
Power Dissipation (W)
Output Power (W)
RL=4Ω
fin=1kHz
Mono
AMP Mode
VDD=4.5V
VDD=5.0V
VDD=5.5V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.0 0.5 1.0 1.5 2.0
Output Power (W)
Power Dissipation (W)
VDD=4.5V
VDD=5.0V
VDD=5.5V
RL=8Ω
fin=1kHz
Mono
AMP Mode
Power Dissipation vs. Output Power
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw14
APA2059
Typical Operating Characteristics (Cont.)
(TA = +25°C, unless otherwise noted.)
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.0 0.5 1.0 1.5 2.0
VDD=4.5V
VDD=5.0V
VDD=5.5V
0.50 Supply Current vs. Output Power
Supply Current (A)
Output Power (W)
RL=8Ω
AV=10dB
fin=1kHz
Mono
AMP Mode 0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
4 8 12 16 20 24 28 32
Output Power vs. Load Resistance
Output Power (W)
Load Resistance (Ω)
THD+N=10%
THD+N=1%
VDD=5.0V
AV=10dB
fin=1kHz
Mono
AMP Mode
0
50
100
150
200
250
10 100 1000
Output Power vs. Load Resistance
Output Power (W)
Load Resistance (Ω)
THD+N=10%
THD+N=1%
VDD=5.0V
HVDD=3.3V
fin=1kHz
Mono
HP Mode
4
5
6
7
8
9
10
11
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
Supply Current (IVDD) vs. Supply
Voltage (VDD)
Supply Current (mA)
Supply Voltage(V)
HVDD=3.3V
No Load
AMP,HP enable
(IHVDD=2.2mA)
AMP enable
(IHVDD=0.1mA)
HP enable
(IHVDD=2.2mA)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.3 3.4 3.5 3.6
Supply Voltage(V)
Supply Current (mA)
Supply Current (IHVDD) vs. Supply
Voltage (HVDD)
VDD=5.0V
No Load
AMP,HP enable
(IVDD=9.3mA)
AMP enable
(IVDD=4.9mA)
HP enable
(IVDD=5.0mA)
Copyright ANPEC Electronics Corp.
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APA2059
Operating Waveforms
Power On
CH1: VDD, 2V/Div, DC
CH2: VROUT, 20mV/Div, DC
TIME: 5ms/Div
CH3: VHP_RO, 20mV/Div, DC
1
2
3
VDD
VROUT
VHP_RO
Power Off
CH2: VROUT, 20mV/Div, DC
TIME: 20ms/Div
CH3: VHP_RO, 20mV/Div, DC
CH1: VDD, 2V/Div, DC
1
2
3
VDD
VHP_RO
VROUT
Speaker Enable
1
2
CH2: VOUTP, 1V/Div, AC
TIME: 5ms/Div
CH1: VAMP_EN, 2V/Div, DC
VAMP_EN
VOUTP
Speaker Disable
1
2
TIME: 1ms/Div
CH1: VAMP_EN, 2V/Div, DC
CH2: VOUTP, 1V/Div, AC
VOUTP
VAMP_EN
Copyright ANPEC Electronics Corp.
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APA2059
Operating Waveforms (Cont.)
Headphone Enable
1
2
TIME: 5ms/Div
CH1: VHP_EN, 2V/Div, DC
CH2: VHP_LO, 1V/Div, AC
VHP_RO
VHP_EN
Headphone Disable
1
2
TIME: 1ms/Div
CH1: VHP_EN, 2V/Div, DC
CH2: VHP_LO, 1V/Div, AC
VHP_EN
VHP_RO
LDO Power On
1
2
VLDOUT
VDD
TIME: 10ms/Div
CH1: VDD, 2V/Div, DC
CH2: VLDOUT, 2V/Div, DC
IO=120mA
LDO Power Off
1
2
VLDOUT
VDD
TIME: 20ms/Div
CH1: VDD, 2V/Div, DC
CH2: VLDOUT, 2V/Div, DC
IO=120mA
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw17
APA2059
Operating Waveforms (Cont.)
1
2
VDD
VLDOUT
LDO Line Transient
TIME: 200µs/Div
CH1: VDD, 200mV/Div, DC
CH2: VLDOUT, 5mV/Div, DC
VDD Offset = 5.0V
VLDOUT Offset = 4.75V TIME: 200µs/Div
CH1: ILDOUT, 50mA/Div, DC
CH2: VLDOUT, 5mV/Div, DC
VLDOUT Offset = 4.75V
LDO Load Transient
1
2VLDOUT
ILDOUT
LDO Enable
1
2
VLDOUT
VLDO_EN
TIME: 200µs/Div
CH1: VLDO_EN, 2V/Div, DC
CH2: VLDOUT, 2V/Div, DC
IO=120mA
TIME: 1ms/Div
CH1: VLDO_EN, 2V/Div, DC
CH2: VLDOUT, 2V/Div, DC
IO=120mA
LDO Disable
1
2
VLDO_EN
VLDOUT
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw18
APA2059
Operating Waveforms (Cont.)
GSM Power Supply Rejection vs. TimeGSM Power Supply Rejection vs. Frequency
GSM Power Supply Rejection vs. Frequency
-150
+0
-100
-50
02k400 800 1.2k 1.6k
-150
+0
-100
-50
Supply Voltage (dBV)
HP Output Voltage (dBV)
Frequency (Hz)
1
2
3
VDD
VROUT
VHP_RO
CH1: VDD, 500mV/Div, DC
CH2: VROUT , 20mV / Div, DC
TIME: 2ms/Div
VDD Offset = 5.0V
CH3: VHP_RO , 20mV / Div, DC
+0
-100
-50
-150
-100
-50
02k
400 800 1.2k 1.6k
-150
+0
Frequency (Hz)
Supply Voltage (dBV)
AMP Output Voltage (dBV)
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw19
APA2059
Pin Description
PIN
NO. NAME I/O/P
FUNCTION
1 RINN_A I The inverting input pin of right channel power amplifier.
2 RINP_A I The non-inverting input pin of right channel power amplifier.
3 LINP_A I The non-inverting input pin of left channel power amplifier.
4 LINN_A I The inverting input pin of left channel power amplifier.
5,21 PGND P Power amplifier’s ground.
6 LOUTP O The positive output pin of left channel power amplifier.
7 LOUTN O The negative output pin of left channel power amplifier.
8,18 PVDD P Power amplifier’s supply voltage pin, connect this pin to VDD.
9 NC - No Connection.
10 CPP I/O Charge pump flying capacitor positive connection.
11 CGND P Charge pump’s ground.
12 CPN I/O Charge pump flying capacitor negative connection.
13 CVSS O Charge pump output pin, connect this pin to the HVSS.
14 HVSS P Headphone driver’s negative supply voltage pin, connect this pin to CVSS.
15 HP_RO O The output pin of right channel headphone driver.
16 HP_LO O The output pin of left channel headphone driver.
17 HVDD P Headphone driver’s positive supply voltage pin.
19 ROUTN O
The negative output pin of right channel power amplifier.
20 ROUTP O
The positive output pin of right channel power amplifier.
22 HP_EN I Headphone drivers enable input pin; High=Enable.
23
AMP_EN I Power amplifiers enable input pin; High=Enable.
24 BIAS P Bias voltage for power amplifiers.
25 LDO_EN I LDO (Low Drop-Out Regulator) enables input pin; High=Enable.
26 RIN_H I The input pin of right channel headphone driver.
27 LIN_H I The input pin of left channel headphone driver.
28 GND P Control block’s ground, connect this pin to CGND and PGND.
29 LDOUT O LDO (Low Drop-Out Regulator)’s output pin.
30 VDD P Control block and LDO supply voltage pin, connect this pin to PVDD.
31 GAIN0 I Control pin for internal gain setting, MSB, Bit 1.
32 GAIN1 I Control pin for internal gain setting, LSB, Bit 0.
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw20
APA2059
Block Diagram
LOUTP
LINP_A
LINN_A
RINP_A
RINN_A
Gain
Control
GAIN0
LOUTN
ROUTN
ROUTP
Control
GAIN1
+
+
-
-
Charge
Pump
LDO
LIN_H
RIN_H
HP_LO
HP_RO
AMP_EN
HP_EN
LDO_EN
BIAS VDD
CPP
CPN
CGNDCVSS
LDOUT
PVDD
PGND
HVDD
HVSS
GND
PVDD
VDD
240kΩ
30kΩ
20kΩ
20kΩ
30kΩ
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw21
APA2059
Typical Application Circuit
Differential input mode
Single-ended input mode
Note *：If using MLCC type capacitor for low
frequency performance, 3.3µF is recommended.
RINN_A 1
RINP_A 2
LINP_A 3
LINN_A 4
PGND 5
LOUTP 6
LOUTN 7
PVDD 8
25 LDO_EN
26 RIN_H
27 LIN_H
28 GND
29 LDOUT
30 VDD
31 GAIN0
32 GAIN1
HP_LO 16
HP_RO 15
HVSS 14
CVSS 13
CPN 12
CGND 11
CPP 10
17 HVDD
18 PVDD
19 ROUTN
20 ROUTP
21 PGND
22 HP_EN
23 AMP_EN
24 BIAS
VDD
0.1µF10µF
2.2µF
1µF1µF
Ring
Headphone
Jack
Sleeve
Tip
HVDD
VDD
Gnd
Headphone
Driver Enable
Power
Amplifier
Enable
Gnd
Gnd
Regulator
Enable
0.47µF0.47µF
0.47µF
0.47µF
0.47µF
Right
Channel
Input Signal
(Amplifier)
Left
Channel
Input Signal
(Amplifier)
Gain
Control
(Amplifier)
1µFGnd
VDD
0.1µF2.2µF
1µF1µF
Headphone
Driver Input
Signals
APA2059
Ci1
Ci2
Ci3
Ci4
Ci5*Ci6*
CB
CS1
CS2
CS4
CPF
CPO
CS3CO1
CO2 Regulator Output
Gnd
Gnd
CS5
0.1µF
Gnd
Gnd
VSS
NC 9
RINN_A 1
RINP_A 2
LINP_A 3
LINN_A 4
PGND 5
LOUTP 6
LOUTN 7
PVDD 8
25 LDO_EN
26 RIN_H
27 LIN_H
28 GND
29 LDOUT
30 VDD
31 GAIN0
32 GAIN1
HP_LO 16
HP_RO 15
HVSS 14
CVSS 13
CPN 12
CGND 11
CPP 10
NC 9
17 HVDD
18 PVDD
19 ROUTN
20 ROUTP
21 PGND
22 HP_EN
23 AMP_EN
24 BIAS
VDD
0.1µF10µF
2.2µF
1µF1µF
Ring
Headphone
Jack
Sleeve
Tip
HVDD
VDD
Gnd
Headphone
Driver Enable
Power
Amplifier
Enable
Gnd
Gnd
Regulator
Enable
0.47µF0.47µF
0.47µF
0.47µF
0.47µF
Right
Channel
Input Signal
(Amplifier)
Left
Channel
Input Signal
(Amplifier)
Gain
Control
(Amplifier)
1µFGnd
VDD
0.1µF2.2µF
1µF1µF
Headphone
Driver Input
Signals
APA2059
Ci1
Ci2
Ci3
Ci4
Ci5*Ci6*
CB
CS1
CS2
CS4
CPF
CPO
CS3CO1
CO2 Regulator Output
Gnd
Gnd
CS5
0.1µF
VSS
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw22
APA2059
GAIN0 GAIN1
AV(dB) Ri(kΩ) Rf(kΩ)
0 0 10 76 240
0 1 12 60 240
1 0 15.6 40 240
1 1 21.6 20 240
Function Description
Figure 1: The Cap-Free Headphone Driver’s Operation
Fully Differential Amplifier
Gain Setting Function
Headphone Mode Operation
Thermal Protection
Over-Current Protection (OCP)
The APA2059’s power amplifier is a fully differential
amplifier with differential inputs and outputs. The fully
differential amplifier has some advantages versus tradi-
tional amplifier. Firstly, don’t need the input coupling ca-
pacitors because the common-mode feedback will com-
pensate the input bias. The inputs can be biased from
0.5V to VDD-0.5V, and the outputs are still biased at mid-
supply voltage of the power amplifier. If the inputs are
biased out of the input range, the coupling capacitors are
required. Secondly, the fully differential amplifier has out-
standing immunity against supply voltage ripple (217Hz)
caused by GSM RF transmitters’ signal, which is better
than the typical audio amplifier.
For the convenient uses, the APA2059’s power amplifiers
provide four gain setting options by GAIN0 and GAIN1
pins.
The Cap-free headphone drivers use a charge pump to
invert the positive power supply (VDD) to the negative power
supply (VSS) (see Figure 1). The headphone amplifiers
operate at this bipolar power supply, and the outputs ref-
erence refers to the ground. This feature eliminates the
output capacitor that using in conventional single-ended
headphone amplifiers. In addition, the power supply rail
for Cap-free headphone drivers has almost 1.5X com-
pare to the single power supply rail headphone drivers.
The thermal protection circuit limits the junction tem-
perature of the APA2059. When the junction tempera-
ture exceeds TJ = +150oC, a thermal sensor turns off the
amplifier, allowing the devices to cool. The thermal sen-
sor allows the amplifier to start-up after the junction tem-
perature down about 125 oC. The thermal protection is
designed with a 25 o C hysteresis to lower the average TJ
during continuous thermal overload conditions, increas-
ing lifetime of the ICs.
• The power amplifier monitors the output buffers’ current.
When the over-current occurs, the output buffers’ current
will be reduced and limited to a fold-back current level.
The power amplifier will go back to normal operation until
the over-current current situation has been removed. In
addition, if the over-current period is long enough and the
IC’s junction temperature reaches the thermal protection
threshold, the IC enters thermal protection mode.
• The LDO regulator provides a current-limit circuitry,
which monitors and controls P-channel MOS’s gate
voltage, limiting the output current to 0.4A. For reliable
operation, the device should not be operated in current-
limit for extended period time. When the output voltage
drops below 0.6V, which is caused by the over load or
short circuit, the internal short circuit current-limit circuitry
limits the output current down to 250mA. The short circuit
current-limit is used to reduce the power dissipation dur-
ing short circuit condition. The short circuit current-limit
has a blanking time feature after the under-voltage lock-
out threshold is reached, therefore, it will avoid the output
causing short circuit current-limit protection during start-
up; the blanking time is about 600µs.
Gnd
VOUT
HVDD
VSS
Gnd
VOUT
Conventional Headphone Driver
Cap-free Headphone Driver
HVDD
HVDD/2
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw23
APA2059
Function Description (Cont.)
Over-Current Protection (OCP) (Cont.)
Enable Mode
• The charge pump monitors the output voltage (VSS). In
addition, it has an over-voltage protection to avoid over-
current occuring on headphone driver’s output. When the
output voltage (VSS) is greater than –2V, the charge pump
will turn off the charge pump’s output. The charge pump’s
output will turn on again if the situation has been removed.
Typical under voltage protection threshold is -2V with
0.5V hysteresis.
Low Drop-Out (LDO) Regulator
The LDO regulator’s output provides maximum 120mA
drive capacity for external audio codec. A 2.2µF decoupling
capacitor with 0.1µf capacitor (filtering the high frequency
noise) is recommended at LDO regulator‘s output. The
LDO regulator has built-in under-voltage lockout circuits
to keep the output shutting off until internal circuitry is
operating properly. The under-voltage lockout function ini-
tiates a soft-start process after input voltage exceeds its
rising under-voltage lockout threshold during power on.
The internal soft-start circuit controls the rise rate of the
output voltage and limits the current surge during start-
up. Approximate 20µs delay time after the VDD is over the
under-voltage lockout threshold; the LDO regulator’s out-
put voltage starts the soft-start. The typical soft-start inter-
val is about 130µs and the under-voltage lockout thresh-
old is 2.5V with 0.15V hysteresis.
The APA2059 provides the independent enable control
functions and allows user disable any main circuit blocks
when not in using, and these can save the power
consumption. In addition, if either the power amplifier or
the headphone driver is disabled, the released time will
happen immediately when enable the power amplifier or
the headphone driver. However, if both the power ampli-
fier and the headphone driver are disabled at the same
time, the released time will be the TSTART-UP Time when
enable one of them. Disable all blocks ( V AMP_EN=VHP_EN=
VLDO_EN=0V), The APA2059 enters the shutdown mode,
and only consumption 5µA(Max.) at VDD supply current and
2µA(Max.) at HVDD supply current.
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw24
APA2059
Device Type Requirement Value APA2059 typical performance
Full Scale Output voltage ≥0.707Vrms 2.3Vrms
THD+N ≤-65dBFS
20Hz~20kHz -70dB
20Hz~20kHz
Line output cross-talk ≤-50dB,
20Hz~15kHz -70dB
20Hz~20kHz
Analog Line Output Jack
(RL=10kΩ)
Noise level during system
activity ≤-80dBFS
A-weighting -100dBFS A-weighting
Full Scale Output voltage ≥0.707Vrms 2.3Vrms
THD+N ≤-65dBFS
100Hz~20kHz -78dB
100Hz~20kHz
Headphone output
cross-talk ≤-50 dB
100Hz~15kHz -75 dB
100Hz~15kHz
Analog Headphone Output
Jack
(RL=320Ω) Noise level during system
activity ≤-80dBFS
A-weighting -100dBFS
A-weighting
Full Scale Output voltage ≥0.3Vrms 2.0Vrms
THD+N ≤-45dBFS
100Hz~20kHz -68dB
100Hz~20kHz
Headphone output
cross-talk ≤-50dB
100Hz~15kHz -70 dB
100Hz~15kHz
Analog Headphone Output
Jack
(RL=32Ω) Noise level during system
activity ≤-80dBFS
A-weighting -100dBFS A-weighting
Application Information
Input Capacitor (Ci)
ii
)C(highpass CR21
fπ
=(1)
ci
ifR21
Cπ
=(2)
In the typical application, an input capacitor, Ci, is required
to allow the amplifier to bias the input signal to the proper
DC level for optimum operation. In this case, Ci and the
minimum input impedance Ri form a high-pass filter with
the corner frequency is determined in the following
equation:
The value of Ci must be considered carefully because it
directly affects the low frequency performance of the circuit.
Consider the example where Ri is 20kΩ and the specifi-
cation calls for a flat bass response down to 40Hz. The
equation is reconfigured below :
When input resistance varation is considered, the value
of Ci is 0.2µF. Therefore, a value in the range from 0.22µF
to 1.0µF would be chosen. A further consideration for this
capacitor is the leakage path from the input source through
the input network (Ri + Rf, Ci) to the load.
leakage tantalum or ceramic capacitor is the best choice.
When polarized capacitors are used, the positive side of
the capacitors should face the amplifiers’ inputs in most
applications because the DC level of the amplifiers’ in-
puts are held at VDD/2. Please note that it is important to
confirm the capacitor polarity in the application.
Windows VistaTM Premium Mobile Requirement
This leakage current creates a DC offset voltage at the
input to the amplifier that reduces useful headroom, es-
pecially in high gain applications. For this reason, a low-
Power Supply Decoupling Capacitor, Cs
The APA2059 is a high-performance CMOS audio ampli-
fier that requires adequate power supply decoupling to
ensure the output total harmonic distortion (THD) to be
as low as possible. Power supply decoupling also pre-
vents the oscillations caused by long lead length between
the amplifier and the speaker.
The optimum decoupling is achieved by using two differ-
ent types of capacitors that target on different types of
noise on the power supply leads. For higher frequency
transients, spikes, or digital hash on the line, a good low
equivalent-series-resistance (ESR) ceramic capacitor,
(0.1µF typically) placed as close as possible to the device
VDD lead works best.
For filtering lower frequency noise signals, a large alumi-
num electrolytic capacitor of 10µF or greater placed near
the audio power amplifier is recommended.
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw25
APA2059
2. The output traces should be short, wide ( >50mil), and
symmetric.
3. The input trace should be short and symmetric.
4. The power trace width should greater than 50 mil.
5. The TQFN5x5-32 thermal pad should be soldered on
PCB, and the ground plane needs solded mask (to
avoid short circuit) except the thermal pad area.
Application Information (Cont.)
Charge Pump Output Capacitor (CPO)
Layout Recommendation
Figure 5. TQFN5X5-32 Land Pattern Recommendation
The output capacitor’s value affects the power ripple di-
rectly at VSS. Increasing the value of output capacitor will
reduce the power ripple. The ESR of output capacitor af-
fects the load transient of VSS. Low ESR and greater than
1µf ceramic capacitor (X5R type is recommended) is
recommendation.
Charge Pump Flying Capacitor (CPF)
The flying capacitor affects the load transient of the charge
pump. If the capacitor’s value is too small, it will degrade
the charge pump’s current driver capability and the per-
formance of headphone amplifier. Increasing the flying
capacitor’s value will improve the load transient of charge
pump. Recommend using the low ESR ceramic capaci-
tors (X5R type is recommended) above 1µf.
1. All components should be placed close to the APA2059.
For example, the input capacitor (Ci) should be close
to APA2059’s input pins to avoid causing noise cou-
pling to APA2059’s high impedance inputs; the
decoupling capacitor (CS) should be placed by the
APA2059’s power pin to decouple the power rail noise.
0.5mm
0.25mm 1.15mm
3.6mm
3.6mm
4.1mm
ThermalVia
diameter
0.3mm X 9
Ground
plane for
ThermalP
AD
Solder Mask
to Prevent
Short Circuit TQFN5X5-32 Land Pattern
Recommendation
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw26
APA2059
Package Information
TQFN5x5-32 D
E
A
b
A1
A3
D2
E2
Pin 1
Corner
e
LK
0.70
0.138
0.028
0.002
0.50 BSC 0.020 BSC
0.20 0.008
K
4.90 5.10 0.193 0.201
4.90 5.10 0.193 0.201
S
Y
M
B
O
LMIN. MAX.
0.80
0.00
0.18 0.30
3.10 3.50
0.05
3.10
A
A1
b
D
D2
E
E2
e
L
MILLIMETERS
A3 0.20 REF
0.35 0.45
3.50
0.008 REF
MIN. MAX.
INCHES
0.031
0.000
0.007 0.012
0.122 0.138
0.122
0.014 0.018
TQFN5x5-32
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw27
APA2059
Application
A H T1 C d D W E1 F
330.0±2.00
50 MIN.
12.4+2.00
-
0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.10
P0 P1 P2 D0 D1 T A0 B0 K0
TQFN5x5-32
4.0±0.10
8.0±0.10
2.0±0.10
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
5.30±0.20
5.30±0.20
1.30±0.20
(mm)
Carrier Tape & Reel Dimensions
Package Type Unit Quantity
TQFN5x5-32 Tape & Reel 2500
Devices Per Unit
A
E1
A
B
W
F
T
P0
OD0
BA0
P2
K0
B0
SECTION B-B
SECTION A-A
OD1
P1
H
T1
A
d
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw28
APA2059
Taping Direction Information
TQFN5x5-32
Classification Profile
USER DIRECTION OF FEED
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw29
APA2059
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Average ramp-up rate
(Tsmax to TP) 3 °C/second max. 3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL) 183 °C
60-150 seconds 217 °C
60-150 seconds
Peak package body Temperature
(Tp)* See Classification Temp in table 1 See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc) 20** seconds 30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max. 6 °C/second max.
Time 25°C to peak temperature 6 minutes max. 8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Classification Reflow Profiles
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
350-2000 Volume mm3
>2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C
Reliability Test Program
Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ Tj=125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA
Copyright ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010 www.anpec.com.tw30
APA2059
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
