ADC0820-N
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ADC0820-N 8-Bit High Speed µP Compatible A/D Converter with Track/Hold Function
Check for Samples: ADC0820-N
1FEATURES KEY SPECIFICATIONS
2• Built-In Track-and-Hold Function • Resolution: 8 Bits
• No Missing Codes • Conversion Time
• No External Clocking – 2.5 µs Max (RD Mode)
• Single Supply—5 VDC – 1.5 µs Max (WR-RD Mode)
• Easy Interface to All Microprocessors, or • Low Power: 75 mW Max
Operates Stand-Alone • Total Unadjusted Error: ±½ LSB and ± 1 LSB
• Latched TRI-STATE Output DESCRIPTION
• Logic Inputs and Outputs Meet Both MOS and By using a half-flash conversion technique, the 8-bit
T2L Voltage Level Specifications ADC0820-N CMOS A/D offers a 1.5 µs conversion
• Operates Ratiometrically or with any time and dissipates only 75 mW of power. The half-
Reference Value Equal to or Less than VCC flash technique consists of 32 comparators, a most
• 0V to 5V Analog Input Voltage Range with significant 4-bit ADC and a least significant 4-bit
Single 5V Supply ADC.
• No Zero or Full-Scale Adjust Required The input to the ADC0820-N is tracked and held by
• Overflow Output Available for Cascading the input sampling circuitry eliminating the need for
an external sample-and-hold for signals moving at
• 0.3 in. Standard Width 20-Pin PDIP less than 100 mV/µs.
• 20-Pin PLCC For ease of interface to microprocessors, the
• 20-Pin SOIC ADC0820-N has been designed to appear as a
memory location or I/O port without the need for
external interfacing logic.
Connection and Functional Diagrams
Figure 1. CDIP, PDIP, Figure 2. PLCC Package
and SOIC Packages (Top View)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1999–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Figure 3. Functional Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)(3)
Supply Voltage (VCC) 10V
Logic Control Inputs −0.2V to VCC +0.2V
Voltage at Other Inputs and Output −0.2V to VCC +0.2V
Storage Temperature Range −65°C to +150°C
Package Dissipation at TA= 25°C 875 mW
Input Current at Any Pin(4) 1 mA
Package Input Current(4) 4 mA
ESD Susceptibility(5) 900V
PDIP Package 260°C
CDIP Package 300°C
Lead Temp. (Soldering, 10 sec.) Vapor Phase (60 sec.) 215°C
SOIC Package Infrared (15 sec.) 220°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not
apply when operating the device beyond its specified operating conditions.
(2) All voltages are measured with respect to the GND pin, unless otherwise specified.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(4) When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V−or VIN > V+) the absolute value of current at that pin
should be limited to 1 mA or less. The 4 mA package input current limits the number of pins that can exceed the power supply
boundaries with a 1 mA current limit to four.
(5) Human body model, 100 pF discharged through a 1.5 kΩresistor.
Operating Ratings(1)(2)
ADC0820CCJ, ADC0820CIWM −40°C≤TA≤+85°C
Temperature Range (TMIN≤TA≤TMAX)ADC0820BCN, ADC0820CCN, ADC0820BCV, 0°C≤TA≤70°C
ADC0820BCWM, ADC0820CCWM
VCC Range 4.5V to 8V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not
apply when operating the device beyond its specified operating conditions.
(2) All voltages are measured with respect to the GND pin, unless otherwise specified.
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Converter Characteristics
The following specifications apply for RD mode (pin 7 = 0), VCC = 5V, VREF(+) = 5V,and VREF(−) = GND unless otherwise
specified. Boldface limits apply from TMIN to TMAX; all other limits TA= Tj= 25°C. ADC0820BCN, ADC0820CCN,
ADC0820CCJ ADC0820BCV, ADC0820BCWM, Limit
ADC0820CCWM, ADC0820CIWM
Parameter Conditions Units
Tested Design Tested Design
Typ(1) Typ(1)
Limit(2) Limit(3) Limit (2) Limit(3)
Resolution 888Bits
ADC0820BCN, BCWM ±½ ±½ LSB
ADC0820CCJ ±1 LSB
Total Unadjusted
Error(4) ADC0820CCN, CCWM, CIWM ±1 ±1 LSB
ADC0820CCMSA ±1 ±1 LSB
Minimum Reference 2.3 1.00 2.3 1.2 kΩ
Resistance
Maximum Reference 2.3 62.3 5.3 6kΩ
Resistance
Maximum VREF(+) VCC VCC VCC V
Input Voltage
Minimum VREF(−)GND GND GND V
Input Voltage
Minimum VREF(+) VREF(−)VREF(−)VREF(−)V
Input Voltage
Maximum VREF(−)VREF(+) VREF(+) VREF(+) V
Input Voltage
Maximum VIN Input VCC+0.1 VCC+0.1 VCC+0.1 V
Voltage
Minimum VIN Input GND−0.1 GND−0.1 GND−0.1 V
Voltage CS =VCC
Maximum Analog
Input Leakage VIN=VCC 30.3 3µA
Current VIN=GND −3−0.3 −3µA
Power Supply VCC=5V±5% ±1/16 ±¼ ±1/16 ±¼ ±¼ LSB
Sensitivity
(1) Typicals are at 25°C and represent most likely parametric norm.
(2) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).
(3) Design limits are specified but not 100% tested. These limits are not used to calculate outgoing quality levels.
(4) Total unadjusted error includes offset, full-scale, and linearity errors.
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DC Electrical Characteristics
The following specifications apply for VCC = 5V, unless otherwise specified. Boldface limits apply from TMIN to TMAX; all
other limits TA= TJ= 25°C. ADC0820BCN, ADC0820CCN,
ADC0820CCJ ADC0820BCV, ADC0820BCWM, Limit
ADC0820CCWM, ADC0820CIWM
Parameter Conditions Units
Tested Design Tested Design
Typ(1) Typ(1)
Limit(2) Limit(3) Limit(2) Limit(3)
CS , WR , RD 2.0 2.0 2.0 V
VIN(1), Logical “1” VCC=5.25V
Input Voltage Mode 3.5 3.5 3.5 V
CS , WR , RD 0.8 0.8 0.8 V
VIN(0), Logical “0” VCC=4.75V
Input Voltage Mode 1.5 1.5 1.5 V
VIN(1)=5V; CS , RD 0.005 10.005 1µA
IIN(1), Logical “1” VIN(1)=5V; WR 0.1 30.1 0.3 3µA
Input Current VIN(1)=5V; Mode 50 200 50 170 200 µA
IIN(0), Logical “0” VIN(0)=0V; CS, RD, WR, Mode −0.005 −1−0.005 −1µA
Input Current VCC=4.75V, IOUT=−360 µA; 2.4 2.8 2.4 V
DB0–DB7, OFL , INT
VOUT(1), Logical “1”
Output Voltage VCC=4.75V, IOUT=−10 µA; 4.5 4.6 4.5 V
DB0–DB7, OFL , INT
VOUT(0), Logical “0” VCC=4.75V, IOUT=1.6 mA; 0.4 0.34 0.4 V
Output Voltage DB0–DB7, OFL , INT , RDY
VOUT=5V; DB0–DB7, RDY 0.1 30.1 0.3 3µA
IOUT, TRI-STATE
Output Current VOUT=0V; DB0–DB7, RDY −0.1 −3−0.1 −0.3 −3µA
VOUT=0V; DB0–DB7, OFL −12 −6−12 −7.2 −6mA
ISOURCE, Output
Source Current INT −9−4.0 −9−5.3 −4.0 mA
ISINK, Output Sink VOUT=5V; DB0–DB7, OFL , 14 714 8.4 7mA
Current INT , RDY
ICC, Supply Current CS =WR =RD =0 7.5 15 7.5 13 15 mA
(1) Typicals are at 25°C and represent most likely parametric norm.
(2) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).
(3) Design limits are specified but not 100% tested. These limits are not used to calculate outgoing quality levels.
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AC Electrical Characteristics
The following specifications apply for VCC = 5V, tr= tf= 20 ns, VREF(+) = 5V, VREF(−) = 0V and TA= 25°C unless otherwise
specified. Tested Design
Parameter Conditions Typ(1) Units
Limit(2) Limit(3)
tCRD, Conversion Time for RD Mode Pin 7 = 0 (Figure 4) 1.6 2.5 µs
tACC0, Access Time (Delay from Falling Pin 7 = 0 (Figure 4) tCRD + 20 tCRD + 50 ns
Edge of RD to Output Valid)
tCWR-RD, Conversion Time for WR-RD Pin 7 = VCC; tWR = 600 ns, tRD=600 ns 1.52 µs
Mode (Figure 5 &Figure 6)
Min Pin 7 = VCC (Figure 5 &Figure 6) 600 ns
tWR, Write Time Max Figure 11(4) 50 µs
Pin 7 = VCC (Figure 5 &Figure 6 &
tRD, Read Time Min 600 ns
Figure 12)(4)
Pin 7 = VCC, tRD < tI, CL= 15pF (Figure 5) 190 280 ns
tACC1, Access Time (Delay from Falling
Edge of RD to Output Valid) CL= 100 pF 210 320 ns
Pin 7 = VCC, tRD > tI, CL= 15pF (Figure 6) 70 120 ns
tACC2, Access Time (Delay from Falling
Edge of RD to Output Valid) CL=100 pF 90 150 ns
tACC3, Access Time (Delay from Rising RPULLUP = 1k and CL= 15 pF 30 ns
Edge of RDY to Output Valid) Pin 7 = VCC, CL= 50pF (Figure 6 &
tI, Internal Comparison Time 800 1300 ns
Figure 7)
t1H, t0H, TRI-STATE Control (Delay from RL= 1k, CL= 10 pF 100 200 ns
Rising Edge of RD to Hi-Z State) Pin 7 = VCC, CL= 50 pF tRD > tI(Figure 6) tIns
tINTL, Delay from Rising Edge of WR to
Falling Edge of INT tRD < tI(Figure 5) tRD+200 tRD+290 ns
tINTH, Delay from Rising Edge of RD to CL= 50pF (Figure 4 &Figure 5 &Figure 6)125 225 ns
Rising Edge of INT
tINTHWR, Delay from Rising Edge of WR to CL = 50pF (Figure 7)175 270 ns
Rising Edge of INT
tRDY, Delay from CS to RDY CL= 50 pF, Pin 7 = 0 (Figure 4) 50 100 ns
tID, Delay from INT to Output Valid See Figure 7 20 50 ns
tRI, Delay from RD to INT Pin 7 = VCC, tRD<tIFigure 5 200 290 ns
tP, Delay from End of Conversion to Next (Figure 4 &Figure 5 &Figure 6 &Figure 7 500 ns
Conversion & Figure 13)(4)
Slew Rate, Tracking 0.1 V/µs
CVIN, Analog Input Capacitance 45 pF
COUT, Logic Output Capacitance 5 pF
CIN, Logic Input Capacitance 5 pF
(1) Typicals are at 25°C and represent most likely parametric norm.
(2) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).
(3) Design limits are specified but not 100% tested. These limits are not used to calculate outgoing quality levels.
(4) Accuracy may degrade if tWR or tRD is shorter than the minimum value specified. See Figure 11 and Figure 12 graphs.
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TRI-STATE Test Circuits and Waveforms
tr=20 ns t1H Circuit t1H Waveform
tr=20 ns t0H Circuit t0H Waveform
Timing Diagrams
Note: On power-up the state of INT can be high or low.
Figure 4. RD Mode (Pin 7 is Low)
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Figure 5. WR-RD Mode (Pin 7 is High and tRD<tI)
Figure 6. WR-RD Mode (Pin 7 is High and tRD>tI)
Figure 7. WR-RD Mode (Pin 7 is High)
Stand-Alone Operation
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Typical Performance Characteristics
Logic Input Threshold Voltage Conversion Time (RD Mode)
vs. Supply Voltage vs. Temperature
Figure 8. Figure 9.
Power Supply Current vs.
Temperature (not including reference ladder) Accuracy vs. tWR
Figure 10. Figure 11.
Accuracy vs. tRD Accuracy vs. tp
Figure 12. Figure 13.
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Typical Performance Characteristics (continued)
Accuracy vs.
VREF [VREF=VREF(+)-VREF(-)] tI, Internal Time Delay vs. Temperature
Figure 14. Figure 15.
Output Current vs. Temperature
Figure 16.
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PIN DESCRIPTIONS
Pin Name Function
1 VIN Analog input; range =GND≤VIN≤VCC
2 DB0 TRI-STATE data output—bit 0 (LSB)
3 DB1 TRI-STATE data output—bit 1
4 DB2 TRI-STATE data output—bit 2
5 DB3 TRI-STATE data output—bit 3
WR: With CS low, the conversion is started on the falling edge of WR. Approximately 800 ns
(the preset internal time out, tI) after the WR rising edge, the result of the conversion will be
WR-RD Mode strobed into the output latch, provided that RD does not occur prior to this time out (See
Figure 5 &Figure 6).
6 WR / RDY RDY: This is an open drain output (no internal pull-up device). RDY will go low after the falling
RD Mode edge of CS; RDY will go TRI-STATE when the result of the conversion is strobed into the
output latch. It is used to simplify the interface to a microprocessor system (See Figure 4).
Mode: Mode selection input—it is internally tied to GND through a 50 µA current source.
7 Mode RD Mode: When mode is low
WR-RD Mode: When mode is high
With CS low, the TRI-STATE data outputs (DB0-DB7) will be activated when RD goes low
(See Figure 7). RD can also be used to increase the speed of the converter by reading data
WR-RD Mode prior to the preset internal time out (tI,∼800 ns). If this is done, the data result transferred to
output latch is latched after the falling edge of the RD (See Figure 5 &Figure 6).
8 RD With CS low, the conversion will start with RD going low, also RD will enable the TRI-STATE
RD Mode data outputs at the completion of the conversion. RDY going TRI-STATE and INT going low
indicates the completion of the conversion (See Figure 4).
INT going low indicates that the conversion is completed and the data result is in the output
latch. INT will go low, ∼800 ns (the preset internal time out, tI) after the rising edge of WR (See
WR-RD Mode Figure 6); or INT will go low after the falling edge of RD , if RD goes low prior to the 800 ns
9 INT time out (See Figure 5). INT is reset by the rising edge of RD or CS (See Figure 5 &Figure 6).
INT going low indicates that the conversion is completed and the data result is in the output
RD Mode latch. INT is reset by the rising edge of RD or CS (See Figure 4).
10 GND Ground
11 VREF(−) The bottom of resistor ladder, voltage range: GND≤VREF(−)≤VREF(+)(1)
12 VREF(+) The top of resistor ladder, voltage range: VREF(−)≤VREF(+)≤VCC(1)
13 CS CS must be low in order for the RD or WR to be recognized by the converter.
14 DB4 TRI-STATE data output—bit 4
15 DB5 TRI-STATE data output—bit 5
16 DB6 TRI-STATE data output—bit 6
17 DB7 TRI-STATE data output—bit 7 (MSB)
Overflow output—If the analog input is higher than the VREF(+), OFL will be low at the end of conversion. It can
18 OFL be used to cascade 2 or more devices to have more resolution (9, 10-bit). This output is always active and does
not go into TRI-STATE as DB0–DB7 do.
19 NC No connection
20 VCC Power supply voltage
(1) When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V−or VIN > V+) the absolute value of current at that pin
should be limited to 1 mA or less. The 4 mA package input current limits the number of pins that can exceed the power supply
boundaries with a 1 mA current limit to four.
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FUNCTIONAL DESCRIPTION
GENERAL OPERATION
The ADC0820-N uses two 4-bit flash A/D converters to make an 8-bit measurement (Figure 3). Each flash ADC
is made up of 15 comparators which compare the unknown input to a reference ladder to get a 4-bit result. To
take a full 8-bit reading, one flash conversion is done to provide the 4 most significant data bits (via the MS flash
ADC). Driven by the 4 MSBs, an internal DAC recreates an analog approximation of the input voltage. This
analog signal is then subtracted from the input, and the difference voltage is converted by a second 4-bit flash
ADC (the LS ADC), providing the 4 least significant bits of the output data word.
The internal DAC is actually a subsection of the MS flash converter. This is accomplished by using the same
resistor ladder for the A/D as well as for generating the DAC signal. The DAC output is actually the tap on the
resistor ladder which most closely approximates the analog input. In addition, the “sampled-data” comparators
used in the ADC0820-N provide the ability to compare the magnitudes of several analog signals simultaneously,
without using input summing amplifiers. This is especially useful in the LS flash ADC, where the signal to be
converted is an analog difference.
THE SAMPLED-DATA COMPARATOR
Each comparator in the ADC0820-N consists of a CMOS inverter with a capacitively coupled input (Figure 17
Figure 18). Analog switches connect the two comparator inputs to the input capacitor (C) and also connect the
inverter's input and output. This device in effect now has one differential input pair. A comparison requires two
cycles, one for zeroing the comparator, and another for making the comparison.
In the first cycle, one input switch and the inverter's feedback switch (Figure 17) are closed. In this interval, C is
charged to the connected input (V1) less the inverter's bias voltage (VB, approximately 1.2V). In the second cycle
(Figure 18), these two switches are opened and the other (V2) input's switch is closed. The input capacitor now
subtracts its stored voltage from the second input and the difference is amplified by the inverter's open loop gain.
The inverter's input (VB′) becomes
(1)
and the output will go high or low depending on the sign of VB′−VB.
The actual circuitry used in the ADC0820-N is a simple but important expansion of the basic comparator
described above. By adding a second capacitor and another set of switches to the input (Figure 19), the scheme
can be expanded to make dual differential comparisons. In this circuit, the feedback switch and one input switch
on each capacitor (Z switches) are closed in the zeroing cycle. A comparison is then made by connecting the
second input on each capacitor and opening all of the other switches (S switches). The change in voltage at the
inverter's input, as a result of the change in charge on each input capacitor, will now depend on both input signal
differences.
• VO= VB
• V on C = V1−VB
• CS= stray input node capacitor
• VB= inverter input bias voltage
Zeroing Phase
Figure 17. Sampled-Data Comparator
Compare Phase
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Figure 18. Sampled-Data Comparator Figure 19. ADC0820-N Comparator (from MS Flash
ADC)
ARCHITECTURE
In the ADC0820-N, one bank of 15 comparators is used in each 4-bit flash A/D converter (Figure 25). The MS
(most significant) flash ADC also has one additional comparator to detect input overrange. These two sets of
comparators operate alternately, with one group in its zeroing cycle while the other is comparing.
When a typical conversion is started, the WR line is brought low. At this instant the MS comparators go from
zeroing to comparison mode (Figure 24). When WR is returned high after at least 600 ns, the output from the
first set of comparators (the first flash) is decoded and latched. At this point the two 4-bit converters change
modes and the LS (least significant) flash ADC enters its compare cycle. No less than 600 ns later, the RD line
may be pulled low to latch the lower 4 data bits and finish the 8-bit conversion. When RD goes low, the flash
A/Ds change state once again in preparation for the next conversion.
Figure 24 also outlines how the converter's interface timing relates to its analog input (VIN). In WR-RD mode, VIN
is measured while WR is low. In RD mode, sampling occurs during the first 800 ns of RD. Because of the input
connections to the ADC0820-N's LS and MS comparators, the converter has the ability to sample VIN at one
instant (see Inherent Sample-Hold), despite the fact that two separate 4-bit conversions are being done. More
specifically, when WR is low the MS flash is in compare mode (connected to VIN), and the LS flash is in zero
mode (also connected to VIN). Therefore both flash ADCs sample VIN at the same time.
DIGITAL INTERFACE
The ADC0820-N has two basic interface modes which are selected by strapping the MODE pin high or low.
RD Mode
With the MODE pin grounded, the converter is set to Read mode. In this configuration, a complete conversion is
done by pulling RD low until output data appears. An INT line is provided which goes low at the end of the
conversion as well as a RDY output which can be used to signal a processor that the converter is busy or can
also serve as a system Transfer Acknowledge signal.
Figure 20. RD Mode (Pin 7 is Low)
When in RD mode, the comparator phases are internally triggered. At the falling edge of RD, the MS flash
converter goes from zero to compare mode and the LS ADC's comparators enter their zero cycle. After 800 ns,
data from the MS flash is latched and the LS flash ADC enters compare mode. Following another 800 ns, the
lower 4 bits are recovered.
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WR then RD Mode
With the MODE pin tied high, the A/D will be set up for the WR-RD mode. Here, a conversion is started with the
WR input; however, there are two options for reading the output data which relate to interface timing. If an
interrupt driven scheme is desired, the user can wait for INT to go low before reading the conversion result
(Figure 22). INT will typically go low 800 ns after WR's rising edge. However, if a shorter conversion time is
desired, the processor need not wait for INT and can exercise a read after only 600 ns (Figure 21). If this is
done, INT will immediately go low and data will appear at the outputs.
Figure 21. WR-RD Mode (Pin 7 is High and tRD<tI) Figure 22. WR-RD Mode (Pin 7 is High and tRD>tI)
Stand-Alone
For stand-alone operation in WR-RD mode, CS and RD can be tied low and a conversion can be started with
WR. Data will be valid approximately 800 ns following WR's rising edge.
Figure 23. WR-RD Mode (Pin 7 is High) Stand-Alone Operation
Note: MS means most significant
LS means least significant
Figure 24. Operating Sequence (WR-RD Mode)
OTHER INTERFACE CONSIDERATIONS
In order to maintain conversion accuracy, WR has a maximum width spec of 50 µs. When the MS flash ADC's
sampled-data comparators (see The Sampled-Data Comparator) are in comparison mode (WR is low), the input
capacitors (C, Figure 19) must hold their charge. Switch leakage and inverter bias current can cause errors if the
comparator is left in this phase for too long.
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Since the MS flash ADC enters its zeroing phase at the end of a conversion (see Architecture), a new conversion
cannot be started until this phase is complete. The minimum spec for this time (tP, see Figure 4 &Figure 5 &
Figure 6 &Figure 7) is 500 ns.
Detailed Block Diagram
Figure 25.
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Analog Considerations
REFERENCE AND INPUT
The two VREF inputs of the ADC0820-N are fully differential and define the zero to full-scale input range of the A
to D converter. This allows the designer to easily vary the span of the analog input since this range will be
equivalent to the voltage difference between VIN(+) and VIN(−). By reducing VREF(VREF = VREF(+) −VREF(−)) to
less than 5V, the sensitivity of the converter can be increased (i.e., if VREF = 2V then 1 LSB = 7.8 mV). The
input/reference arrangement also facilitates ratiometric operation and in many cases the chip power supply can
be used for transducer power as well as the VREF source.
This reference flexibility lets the input span not only be varied but also offset from zero. The voltage at VREF(−)
sets the input level which produces a digital output of all zeroes. Though VIN is not itself differential, the reference
design affords nearly differential-input capability for most measurement applications. Figure 26 shows some of
the configurations that are possible.
INPUT CURRENT
Due to the unique conversion techniques employed by the ADC0820-N, the analog input behaves somewhat
differently than in conventional devices. The A/D's sampled-data comparators take varying amounts of input
current depending on which cycle the conversion is in.
The equivalent input circuit of the ADC0820-N is shown in Figure 27. When a conversion starts (WR low, WR-RD
mode), all input switches close, connecting VIN to thirty-one 1 pF capacitors. Although the two 4-bit flash circuits
are not both in their compare cycle at the same time, VIN still sees all input capacitors at once. This is because
the MS flash converter is connected to the input during its compare interval and the LS flash is connected to the
input during its zeroing phase (see Architecture). In other words, the LS ADC uses VIN as its zero-phase input.
The input capacitors must charge to the input voltage through the on resistance of the analog switches (about 5
kΩto 10 kΩ). In addition, about 12 pF of input stray capacitance must also be charged. For large source
resistances, the analog input can be modeled as an RC network as shown in Figure 28. As RSincreases, it will
take longer for the input capacitance to charge.
In RD mode, the input switches are closed for approximately 800 ns at the start of the conversion. In WR-RD
mode, the time that the switches are closed to allow this charging is the time that WR is low. Since other factors
force this time to be at least 600 ns, input time constants of 100 ns can be accommodated without special
consideration. Typical total input capacitance values of 45 pF allow RSto be 1.5 kΩwithout lengthening WR to
give VIN more time to settle.
External Reference 2.5V Full-Scale Power Supply as Reference Input Not Referred to GND
Figure 26. Analog Input Options
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SNAS529C –JUNE 1999–REVISED MARCH 2013
www.ti.com
Figure 27. ADC0820-N Input Circuit
Figure 28. Analog Input, RC Network Model
INPUT FILTERING
It should be made clear that transients in the analog input signal, caused by charging current flowing into VIN, will
not degrade the A/D's performance in most cases. In effect the ADC0820-n does not “look” at the input when
these transients occur. The comparators' outputs are not latched while WR is low, so at least 600 ns will be
provided to charge the ADC's input capacitance. It is therefore not necessary to filter out these transients by
putting an external cap on the VIN terminal.
INHERENT SAMPLE-HOLD
Another benefit of the ADC0820-N's input mechanism is its ability to measure a variety of high speed signals
without the help of an external sample-and-hold. In a conventional SAR type converter, regardless of its speed,
the input must remain at least ½ LSB stable throughout the conversion process if full accuracy is to be
maintained. Consequently, for many high speed signals, this signal must be externally sampled, and held
stationary during the conversion.
Sampled-data comparators, by nature of their input switching, already accomplish this function to a large degree
(see The Sampled Data Comparator). Although the conversion time for the ADC0820-N is 1.5 µs, the time
through which VIN must be ½ LSB stable is much smaller. Since the MS flash ADC uses VIN as its “compare”
input and the LS ADC uses VIN as its “zero” input, the ADC0820-N only “samples” VIN when WR is low (see
Architecture and Input Current). Even though the two flashes are not done simultaneously, the analog signal is
measured at one instant. The value of VIN approximately 100 ns after the rising edge of WR (100 ns due to
internal logic prop delay) will be the measured value.
Input signals with slew rates typically below 100 mV/µs can be converted without error. However, because of the
input time constants, and charge injection through the opened comparator input switches, faster signals may
cause errors. Still, the ADC0820-N's loss in accuracy for a given increase in signal slope is far less than what
would be witnessed in a conventional successive approximation device. An SAR type converter with a
conversion time as fast as 1 µs would still not be able to measure a 5V 1 kHz sine wave without the aid of an
external sample-and-hold. The ADC0820-N, with no such help, can typically measure 5V, 7 kHz waveforms.
16 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC0820-N
ADC0820-N
www.ti.com
SNAS529C –JUNE 1999–REVISED MARCH 2013
Typical Applications
Figure 29. 8-Bit Resolution Configuration
Figure 30. 9-Bit Resolution Configuration
• VIN=3 kHz max ± 4VP
• No track-and-hold needed
• Low power consumption
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: ADC0820-N
ADC0820-N
www.ti.com
SNAS529C –JUNE 1999–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision B (March 2013) to Revision C Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 20
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: ADC0820-N
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ADC0820BCWMX/NOPB ACTIVE SOIC DW 20 1000 Green (RoHS
& no Sb/Br) SN | CU SN Level-3-260C-168 HR -40 to 85 ADC0820
BCWM
ADC0820CCN/NOPB ACTIVE PDIP NFH 20 18 Green (RoHS
& no Sb/Br) SN Level-1-NA-UNLIM -40 to 85 ADC0820CCN
ADC0820CCN/PB NRND PDIP NFH 20 18 TBD Call TI Call TI ADC0820CCN
ADC0820CCWM NRND SOIC DW 20 36 TBD Call TI Call TI -40 to 85 ADC0820
CCWM
ADC0820CCWM/NOPB ACTIVE SOIC DW 20 36 Green (RoHS
& no Sb/Br) SN | CU SN Level-3-260C-168 HR -40 to 85 ADC0820
CCWM
ADC0820CCWMX/NOPB ACTIVE SOIC DW 20 1000 Green (RoHS
& no Sb/Br) SN | CU SN Level-3-260C-168 HR -40 to 85 ADC0820
CCWM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 2
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADC0820BCWMX/NOPB SOIC DW 20 1000 330.0 24.4 10.9 13.3 3.25 12.0 24.0 Q1
ADC0820CCWMX/NOPB SOIC DW 20 1000 330.0 24.4 10.9 13.3 3.25 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADC0820BCWMX/NOPB SOIC DW 20 1000 367.0 367.0 45.0
ADC0820CCWMX/NOPB SOIC DW 20 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 2
MECHANICAL DATA
N0020A
www.ti.com
N20A (Rev G)
NFH0020A
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